JP2009081684A - Flicker reduction device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a flicker reduction device that reduces a residual flicker with a simple circuit configuration even if a subject moves. <P>SOLUTION: When an image pickup device is driven by an NTSC system and receives a flicker of light caused by lighting at a power-supply frequency of 50 Hz, a switch 16 selects output of a divider 14 when a subject is motionless while selecting output of a flicker gain generation circuit 19 when a subject is moving on the basis of the result of a motion detection circuit 15. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a flicker reducing apparatus that reduces a periodic change (hereinafter referred to as flicker) in an output signal of an image sensor caused by illumination by an AC power source.

  In general, the broadcasting system is set so that the frame or field frequency forming the screen is matched with the commercial power supply frequency. For example, the NTSC system adopted in an area where the commercial power frequency is 60 Hz has a field frequency of approximately 60 Hz, and the PAL system adopted in an area where the commercial power frequency is 50 Hz has a field frequency of 50 Hz. There are many cases. However, in some regions such as the East Japan region, the frequency (50 Hz) of the commercial power supply and the field frequency (60 Hz) may be different. In such an area, a general fluorescent lamp that is lit by an AC power supply repeats blinking at a predetermined cycle. Therefore, when incident light is converted into an electrical signal by an image sensor and read out, the charge accumulation time depends on the position of the pixel to be read. In the case of using image sensors having different values, the sum of the amounts of light incident within the accumulation time of each pixel is different even within the same screen (field or frame), so that a bright portion and a dark portion are generated at a specific cycle. . Such a phenomenon is line flicker. In addition, when using an image sensor in which the accumulation time of each pixel is the same in the same screen, brightness and darkness is generated for each screen, which is called field flicker or frame flicker.

  This will be described with reference to FIG. In FIG. 8, (A) represents the image sensor output, the broken line is the output when there is no flicker, and the solid line represents the output affected by the flicker. (B) represents the light emission cycle of a fluorescent lamp using a power frequency of 50 Hz.

  As shown in FIG. 8, a general fluorescent lamp that is lit with an AC power supply of 50 Hz repeats light emission at 100 Hz rectified to 50 Hz, and therefore, a bright portion and a dark portion are generated at a cycle of 100 Hz even within the same screen. For example, in the NTSC system, since the horizontal scanning (hereinafter referred to as a line) frequency is 15.75 KHz, light and dark are repeated every 1/100 sec = 157.5 lines. Further, since the common multiple of the field period (1/60 sec) and the lighting blinking period (1/100 sec) is 1/20 sec, the same light / dark pattern is obtained every 1/20 sec, that is, almost every three fields. Such a phenomenon is flicker. However, since the flicker frequency is sufficiently slower than the line frequency, there is no difference in the effect within the line, and the effect appears uniformly within each line as shown in the figure.

  With regard to such a flicker correction method, paying attention to the fact that the same bright and dark pattern is generally obtained every three fields, the division value between the average of the three fields and the current output is used as a correction gain, and the current output is multiplied. A method for correcting flicker components is known.

  FIG. 9 is an explanatory diagram showing a general schematic diagram of a correction method in which the image pickup device output is a signal input and flicker is reduced therefrom.

Signal input Y is input to the line averaging circuit 110 performs the averaging processing of the effective signal period in line units to calculate the line average value y ^0. The delay unit 1200 is composed of a plurality of memories capable of holding a line average value for one screen, and outputs each delayed by one field period. The delayed one field period in the memory 1 is y ^−1. The memory 2 further delayed by one field period is defined as y-2. Each line average value y ⁰ , y ⁻¹ , y ⁻² is obtained by calculating an average value of the line average values for three fields by the average value calculation circuit 130, and calculating the average value of the line average values y ⁰ by the divider 140. By dividing, the difference ratio of the current line average value y ^{0 to} the three field average value is obtained. This is used as a flicker correction signal, and the signal delayed by the delay unit 200 corresponding to the operation processing period is multiplied by the multiplier 210 to obtain an output Y ′ in which the level fluctuation component due to flicker is corrected. Is.

  However, in the flicker correction with the configuration of FIG. 9, since the gain is calculated for each line, even if the movement of the subject is a part of the line, it is affected by the gain correction even to a part where there is no movement.

  10A and 10B are schematic diagrams for explaining the influence of gain correction. FIG. 10A shows a correction input screen, and FIG. 10B shows a correction output screen. For example, when a circular object shown in the screen of FIG. 10A moves from a position 91 indicated by a dotted line to a position 92 indicated by a solid line, the influence affects the correction gain to be calculated. In response to the movement of the movement range line, that is, the entire hatched portion 93 shown in FIG. 10B, the level fluctuation occurs in units of lines, causing a side effect of the flicker correction operation.

  In order to improve this, there is a proposal of an apparatus for providing a motion detection means to switch the correction gain (see, for example, Patent Document 1).

(Conventional example 1)
FIG. 11 is a schematic diagram of a flicker reduction apparatus that uses an image sensor output as a signal input and reduces the influence on a subject change.

In FIG. 11, an input Y transmitted from an imaging unit or the like is input to the line averaging circuit 110. The line average circuit 110 calculates an average line value y ⁰ by performing an average process on the effective signal section on a line basis based on the input signal Y.

The delay unit 1200 is composed of a plurality of memories 1200a and 1200b capable of holding a line average value for one field, and each outputs a delayed one field period. The line average value delayed by one field period in the memory 1200a is y ^−1, and the line average value delayed by one field period in the memory 1200b is y ⁻² . The line average values y ⁰ , y ⁻¹ , and y ⁻² are input to the average value calculation circuit 130.

  The average value calculation circuit 130 calculates an average value of line average values for three fields from the current field to two fields before. The average value output from the average value calculation circuit 130 is input to the divider 140.

The divider 140 divides the average value output from the average value calculation circuit 130 by the current line average value y ⁰ to obtain the difference ratio of the current line average value y ^{0 to} the three field average value, This is the current flicker correction signal z ⁰ .

The delay unit 1210 is composed of a plurality of memories 1210a, 1210b, and 1210c capable of holding a flicker correction signal for one field, and outputs the delayed signals by one field period. The flicker correction signal delayed by one field period in the memory 1210a is z ⁻¹ , the flicker correction signal delayed by one field period in the memory 1210b is z ^−2, and the flicker correction signal delayed by one field period in the memory 1210 is z ^{−. 3}

The motion detection circuit 150 detects a difference between the line average values y ⁰ and y ⁻¹ to detect motion around one field and generates a detection signal. As the detection signal, the current flicker correction signal z ⁰ from the divider 140 is selected when the subject is stationary, and when the subject is moving, there is no movement effect from the memory 1210c and the flicker phase is the same. The switch 160 is controlled so as to select the flicker correction signal z ^-3 three fields before which is substantially in phase.

  The correction signal output from the switch 160 is input to the multiplier 210. The multiplier 210 multiplies the original signal output from the delay unit 200 with a delay corresponding to the calculation processing period by the correction signal, and outputs an output Y ′ in which the level fluctuation component due to flicker is corrected.

(Conventional example 2)
FIG. 12 shows a configuration of another example of a conventional flicker reducing apparatus. The flicker reduction apparatus shown in FIG. 12 uses the image sensor output as a signal input to reduce the influence on the subject change.

In FIG. 12, an input Y transmitted from an imaging unit or the like is input to the line averaging circuit 110. The line average circuit 110 calculates an average line value y ⁰ by performing an average process on the effective signal section on a line basis based on the input signal Y. The calculated line average value y ⁰ is input to the delay unit 1200, the average value calculation circuit 130, and the divider 140.

The delay unit 1200 is composed of a plurality of memories 1200a and 1200b capable of holding a line average value for one field, and each outputs a delayed one field period. The line average value delayed by one field period in the memory 1200a is y ^−1, and the line average value delayed by one field period in the memory 1200b is y ⁻² . The line average values y ⁰ , y ⁻¹ , and y ⁻² are input to the average value calculation circuit 130.

  The average value calculation circuit 130 calculates an average value of line average values for three fields from the current field to two fields before based on the input line average value.

The divider 140 divides the average value output from the average value calculation circuit 130 by the current line average value y ⁰ to obtain the difference ratio of the current line average value y ^{0 to} the three-field average value. A signal output from the divider 140 is a current flicker correction signal z ⁰ .

The delay unit 1220 includes a plurality of memories 1220a to 1220f that can hold a flicker correction signal for one field, and outputs the delayed signals by a period of one field. A flicker correction signal one field period delay memory 1220a and z ^-1, the flicker correction signal further one field period delayed by the memory 1220b and z ^-2, the flicker correction signal further one field period delayed by the memory 1220c z ^{- 3} , the flicker correction signal delayed by one field period in the memory 1220 d is set to z ⁻⁴ , the flicker correction signal further delayed by one field period in the memory 1220 e is set to z ^−5, and the flicker correction delayed by one field period in the memory 1220 f ^{Let the} signal be z- ⁶ .

Based on the current flicker correction signal z ⁰ , the flicker correction signal z ⁻³ before 3 fields whose flicker phase is substantially the same, and the flicker correction signal z ⁻⁶ before 6 fields, The error component included in the flicker correction gain in the same region of a plurality of fields is removed or a large variation is suppressed. Note that the smoothing circuit 170 is constituted by, for example, a median filter.

On the other hand, the motion detection circuit 150 detects a difference between the line average values y ⁰ and y ⁻¹ , detects a motion around one field, and generates a detection signal. As the detection signal, when the subject is stationary, the current flicker correction signal z ⁰ from the divider 140 is selected, and when the subject has a motion, the influence of the motion from the smoothing circuit 170 is reduced. The switch 160 is controlled so as to select the flicker correction signal. A signal output from the switch 160 is a flicker correction signal. The flicker correction signal is input to the multiplier 210.

  The multiplier 210 multiplies the flicker correction signal by the original signal delayed by the delay unit 200 corresponding to the arithmetic processing period, and outputs an output Y ′ in which the level fluctuation component due to flicker is corrected.

(Conventional example 3)
FIG. 13 shows a configuration of another example of a conventional flicker reducing apparatus. The flicker reduction apparatus shown in FIG. 13 uses the image sensor output as a signal input to reduce the influence on the subject change.

In FIG. 13, a signal Y transmitted from an imaging unit or the like is input to the line averaging circuit 110. The line average circuit 110 calculates an average line value y ⁰ by performing an average process on the effective signal section in units of lines. The calculated line average value y ⁰ is input to the delay unit 1200, the average value calculation circuit 130, and the divider 140.

The delay unit 1200 is composed of a plurality of memories 1200a and 1200b capable of holding a line average value for one field, and each outputs a delayed one field period. The line average value delayed by one field period in the memory 1200a is y ^−1, and the line average value delayed by one field period in the memory 1200b is y ⁻² . The line average values y ⁰ , y ⁻¹ , and y ⁻² are input to the average value calculation circuit 130.

  The average value calculation circuit 130 calculates an average value of line average values for three fields from the current field to two fields before. The calculated average value is input to the divider 140.

The divider 140 divides the average value output from the average value calculation circuit 130 by the current line average value y ⁰ to obtain the difference ratio of the current line average value y ^{0 to} the three-field average value. The difference ratio calculated by the divider 140 is set as a flicker component signal. The calculated flicker component signal is input to the flicker component extraction circuit 180.

  The flicker component extraction circuit 180 converts the frequency of the flicker component signal and extracts only the frequency band that is the component of flicker. The extracted frequency band information is input to the flicker gain generation circuit 190. Note that the flicker component extraction circuit 180 is constituted by, for example, a Fourier transform circuit.

  The flicker gain generation circuit 190 generates a sine wave from the flicker component (frequency domain) extracted by the flicker component extraction circuit 180 by superimposing a trigonometric function. The generated sine wave is output as a flicker correction signal. Note that the flicker gain generation circuit 190 is composed of, for example, an inverse Fourier transform circuit, and generates a flicker correction gain that excludes error components and fluctuation components caused by the subject.

  The multiplier 210 multiplies the flicker correction signal by the original signal delayed by the delay unit 200 corresponding to the arithmetic processing period, and outputs an output Y ′ in which the level fluctuation component due to flicker is corrected.

(Conventional example 4)
FIG. 14 shows a configuration of another example of a conventional flicker reducing apparatus. The flicker reduction apparatus shown in FIG. 14 uses an image sensor output as a signal input, and reduces the influence on a subject change (see Patent Document 2).

14, the signal Y transmitted from an imaging unit is input to the line accumulation block 111, calculates the line integration value s ⁰ performs integration processing of the useful signal period in units of lines. The calculated line integration value s ⁰ is input to the delay unit 1200, the average value calculation block 131, and the difference calculation block 141.

The delay unit 1200 is composed of a plurality of memories 1200a and 1200b capable of holding a line integrated value for one field, and outputs the delayed one field period. The line integrated value delayed by one field period in the memory 1200a is s ^−1, and the line integrated value delayed by one field period in the memory 1200b is s ⁻² . The line integration values s ⁻¹ and s ⁻² are input to the average value calculation block 131, and the line integration value s ⁻¹ is further input to the difference calculation block 141.

The average value calculation block 131 calculates an average value of line integrated values for three fields from the current field to two fields before based on the line integrated values s ⁰ , s ⁻¹ , and s ⁻² . The calculated average value is input to the normalization block 131.

The difference calculation block 141 calculates a difference between the line integrated values s ⁰ and s ⁻¹ , and extracts a level difference due to the influence of flicker assuming that there is no change in the subject. The extracted level difference is input to the normalization block 142.

  The flicker component is affected by the input signal level. The normalization block 142 normalizes the level difference extracted by the difference calculation block 141 by dividing the level difference by the integrated average value of the average value calculation block 131 to generate a flicker component signal. The generated flicker component signal is input to the DFT block 181.

  A DFT (discrete Fourier transform) block 181 performs frequency conversion of the flicker component signal by discrete Fourier transform, and extracts only a frequency band that is a component of flicker. The extracted frequency band information is input to the flicker gain generation block 191.

  The flicker gain generation block 191 generates a sine wave from the flicker component (frequency domain) extracted by the DFT block 181 by superimposing a trigonometric function. The flicker gain generation block 191 outputs the sine wave as a flicker correction signal. Note that the flicker gain generation block 191 is composed of, for example, an inverse Fourier transform circuit, and generates a flicker correction gain that excludes error components and fluctuation components caused by the subject.

The multiplier 210 multiplies the flicker correction signal by the original signal delayed by the delay unit 200 corresponding to the calculation processing period, and outputs an output Y ′ in which the level fluctuation component due to flicker is corrected.
Japanese Patent No. 3506900 JP 2004-222228 A

  However, the following problems may occur in the above-described conventional configuration.

(Problem 1)
The configuration in FIG. 11 corrects flicker by switching between the current flicker correction gain and the flicker correction gain before a multiple of 3 fields when motion of the subject is detected. In such a configuration, there is a problem that a large amount of memory is required to cope with the case where the movement is continuous, resulting in an increase in cost.

  Further, the flicker phase three fields before is actually slightly shifted. 15A and 15B are explanatory diagrams of phase shift, in which FIG. 15A shows an image sensor output driven by the NTSC system, and FIG. 15B shows a light emission cycle of a fluorescent lamp using a power supply frequency of 50 Hz. . In general, it is assumed that the flicker phase returns to the original in a period of three fields, but actually, a phase shift of 50 μsec remains between the three fields as shown in the figure. Accordingly, since the deviation increases with the past, the actual correction effect is lost.

  Further, if the update of the memory of the delay unit 1210 is stopped when detecting the motion and the flicker correction signal held is used, an increase in the memory can be avoided, but the problem of the phase shift of 50 μsec between the three fields remains. End up.

(Problem 2)
In the configuration shown in FIG. 11, when the movement of the subject is detected, the current flicker correction gain and the flicker correction gain before the multiple field of 3 are smoothed by the smoothing circuit 170 to correct the flicker. This is a configuration for gain. Similarly to the problem (Problem 1), since the phase shift of 50 μsec remains between the three fields, the effect of movement is eliminated as smoothing is performed, but the correction gain output by the phase shift However, the deviation from the current flicker phase becomes large. Therefore, there arises a problem that the actual correction effect is lost.

(Problem 3)
The configuration shown in FIGS. 12 and 13 is a configuration in which a sine wave synchronized with the flicker to be affected is generated and used as a flicker correction gain. In such a configuration, since correction is performed with a sine waveform, it is difficult to be affected by disturbance due to changes in the subject, but a portion different from the actual flicker waveform characteristic remains as remaining flicker.

  16A and 16B are explanatory diagrams of the characteristic difference. FIG. 16A is a light emission characteristic of the fluorescent lamp, FIG. 16B is a generated flicker correction gain, and FIG. 16C is a characteristic difference obtained by superimposing (a) and (b). (D) represents the difference. The light emission characteristics of fluorescent lamps are not sine curves as shown in FIG. 16 (a) due to the rectification performance of the AC power supply or the deterioration of the fluorescent material. As shown in FIG. 16D, a remaining flicker component is generated. Although the level of the remaining flicker component is small, the frequency becomes twice that of the original flicker, and the screen remains affected.

  An object of the present invention is to provide a flicker reduction apparatus with a small remaining flicker with a simple circuit configuration even when a subject moves.

  A first flicker reduction apparatus of the present invention is a flicker reduction apparatus that reduces flicker in the output of an image sensor having different accumulation times in units of pixels, and calculates an average value of effective signal sections of the image sensor output for each horizontal period. First average value calculating means for calculating, a plurality of cascaded storage means for holding the output of the first average value calculating means in units of one field or one frame, and the first average value calculating means The second average value calculating means for calculating the average value of the output of the plurality of storage means corresponding to the same horizontal cycle position as the output; the output of the first average value calculating means; First flicker gain calculating means for extracting an image level fluctuation component caused by flicker from a ratio to the output of the second average value calculating means, and flicker frequency from the output of the first flicker gain calculating means. A second flicker gain calculating means for extracting a component and generating a sine waveform synchronized with the flicker frequency; a motion detecting means for detecting a movement of a subject from an output change of the first average value calculating means; Gain selection means for selecting the output of the first flicker gain calculation means and the output of the second flicker gain calculation means from the result of the detection means, and the gain selection means for canceling the influence of flicker Multiplication means for multiplying the output of the image sensor by the output of the image sensor, and the gain selection means, when the image sensor is driven by the NTSC system and receives flicker due to illumination with a power frequency of 50 Hz, Based on this, when the subject is stationary, the output of the first flicker gain calculating means is selected, and when the subject is moving, the second flicker gain calculation means is selected. And selects the output of the flicker gain calculation means.

  A second flicker reduction apparatus of the present invention is a flicker reduction apparatus that reduces flicker in the output of an image sensor having different accumulation times in units of pixels, and calculates an average value of effective signal intervals of the image sensor output for each horizontal period. First average value calculating means for calculating, a plurality of cascaded storage means for holding the output of the first average value calculating means in units of one field or one frame, and the first average value calculating means The second average value calculating means for calculating the average value of the output of the plurality of storage means corresponding to the same horizontal cycle position as the output; the output of the first average value calculating means; First flicker gain calculating means for extracting an image level fluctuation component caused by flicker from a ratio to the output of the second average value calculating means, and flicker frequency from the output of the first flicker gain calculating means. A second flicker gain calculating means for extracting a component and generating a sine waveform synchronized with the flicker frequency; a motion detecting means for detecting a movement of a subject from an output change of the first average value calculating means; Gain selecting means for selecting the output of the first flicker gain calculating means and the output of the second flicker gain calculating means from the result of the detecting means, and the gain selecting means for canceling the influence of flicker The gain selecting means updates the plurality of storage means when the image sensor is driven in the NTSC system and receives flicker due to illumination with a power supply frequency of 60 Hz. Update the time until the field period and flicker period again coincide with each other at the time divided into three parts, Based on the results, but when the subject is stationary selects the output of the second flicker gain calculation unit, when the subject moves to control so as not to output the correction gain.

  A third flicker reducing apparatus of the present invention is a flicker reducing apparatus for reducing flicker in an output of an image sensor having different accumulation times in units of pixels, and calculates an average value of effective signal sections of the image sensor output for each horizontal period. First average value calculating means for calculating, a plurality of cascaded storage means for holding the output of the first average value calculating means in units of one field or one frame, and the first average value calculating means The second average value calculating means for calculating the average value of the output of the plurality of storage means corresponding to the same horizontal cycle position as the output; the output of the first average value calculating means; First flicker gain calculating means for extracting an image level fluctuation component caused by flicker from a ratio to the output of the second average value calculating means, and flicker frequency from the output of the first flicker gain calculating means. A second flicker gain calculating means for extracting a component and generating a sine waveform synchronized with the flicker frequency; a motion detecting means for detecting a movement of a subject from an output change of the first average value calculating means; Gain selecting means for selecting the output of the first flicker gain calculating means and the output of the second flicker gain calculating means from the result of the detecting means, and the gain selecting means for canceling the influence of flicker Multiplication means for multiplying the output of the image sensor by the output of the image sensor, and the gain selection means, when the image sensor is driven by the PAL method and receives flicker due to illumination with a power supply frequency of 60 Hz, Based on this, when the subject is stationary, the output of the first flicker gain calculating means is selected, and when the subject is moving, the second flicker gain calculation means is selected. And selects the output of the flicker gain calculation means.

  A fourth flicker reducing apparatus according to the present invention is a flicker reducing apparatus that reduces flicker in the output of an image sensor having different accumulation times in units of pixels, and calculates an average value of effective signal intervals of the image sensor output for each horizontal period. First average value calculating means for calculating, a plurality of cascaded storage means for holding the output of the first average value calculating means in units of one field or one frame, and the first average value calculating means The second average value calculating means for calculating the average value of the output of the plurality of storage means corresponding to the same horizontal cycle position as the output; the output of the first average value calculating means; First flicker gain calculating means for extracting an image level fluctuation component caused by flicker from a ratio to the output of the second average value calculating means, and flicker frequency from the output of the first flicker gain calculating means. A second flicker gain calculating means for extracting a component and generating a sine waveform synchronized with the flicker frequency; a motion detecting means for detecting a movement of a subject from an output change of the first average value calculating means; Gain selecting means for selecting the output of the first flicker gain calculating means and the output of the second flicker gain calculating means from the result of the detecting means, and the gain selecting means for canceling the influence of flicker Multiplication means for multiplying the output of the image sensor by the output of the image sensor, and frequency discrimination means for detecting the frequency of flicker. The gain selection means comprises: When the result is 50 Hz, based on the result of the motion detection means, when the subject is stationary, the first flicker gain calculation is performed. When the subject is moving, control is performed so that the output of the second flicker gain calculating means is selected, and the imaging device is driven by the NTSC system and the frequency discriminating means is discriminated. When the result is 60 Hz, the output of the second flicker gain calculation unit is selected when the subject is stationary based on the result of the motion detection unit, and the correction gain is output when the subject is moving. It controls to not.

  According to the present invention, it is possible to provide a flicker reducing device with a small remaining flicker with a simple circuit configuration even when a subject moves.

  The flicker reduction apparatus of the present invention can take the following aspects based on the above configuration.

  That is, the flicker reducing apparatus of the present invention further includes a frequency discriminating unit that detects a flicker frequency, and the gain selecting unit is switched based on a discrimination result of the frequency discriminating unit and a driving method of the image sensor. It can be configured to be controlled.

(Embodiment 1)
FIG. 1 is a block diagram showing a configuration example of a flicker reducing apparatus according to Embodiment 1 of the present invention. In the present embodiment, it is assumed that an imaging element driven by the NTSC system is affected by a general fluorescent lamp that is lit by an AC power supply of 50 Hz. As shown in FIG. 1, the flicker reducing apparatus according to the present embodiment includes a line average circuit 11 (first average value calculation means), a multiplier 14 (first flicker gain calculation means), and a motion detection circuit 15 (motion). Detection means), switch 16 (gain selection means), flicker component extraction circuit 18 (second flicker gain calculation means), flicker gain generation circuit 19 (second flicker gain calculation means), delay unit 20, multiplier 21 ( Multiplication means), a delay device 120, and an average value calculation circuit 130 (second average value calculation means).

The line average circuit 11 is a circuit that calculates an average value y ⁰ of an effective signal section of one line period of the signal Y transmitted from the imaging unit or the like.

The delay device 120 is a delay device including a memory 120a and a memory 120b (storage means) connected in cascade. The memories 120a and 120b can hold a line average value for one field, and output each line with a delay of one field period. The memory 120a delayed by one field period is y ⁻¹ , and the memory 120b further delayed by one field period is y ⁻² .

The average value calculation circuit 130 calculates the average value of the output y ⁰ of the line average circuit 11, the output y ^{−1 of} the memory 120a, and the output y ⁻² of the memory 120b. That is, the average of the line average values at the same line position for every three fields is calculated, and a reference value that eliminates the influence of flicker is created.

Divider 14, the average value output from the average value calculation circuit 130 of the current is divided by the line average value y ^0, the current for the line average value of the same line position of the three fields of line average value y ⁰ Find the difference ratio. The obtained difference ratio is set as a first flicker correction gain.

The motion detection circuit 15 compares the difference between the line average values y ⁰ and y ⁻¹ with the threshold value, and detects the motion of the subject before and after one field.

  The flicker component extraction circuit 18 converts the frequency of the first flicker correction gain generated by the divider 14 and extracts only the frequency region that is the flicker component.

  The flicker gain generation circuit 19 generates a sine wave synchronized with the flicker frequency by superimposing trigonometric functions based on the flicker component (frequency domain) extracted by the flicker component extraction circuit 18. The generated sine wave is set as a second flicker correction gain.

  The switch 16 is either one of the first flicker correction gain output from the divider 14 and the second flicker correction gain output from the flicker gain generation circuit 19 based on the detection result of the motion detection circuit 15. Select. The selected flicker correction gain is set as the final correction gain (correction signal).

  The delay unit 20 adjusts a delay corresponding to the input signal Y until a correction gain is generated.

  The multiplier 21 multiplies the Y signal time-adjusted by the delay unit 20 by a flicker correction gain, thereby outputting a correction output Y ′ in which fluctuation due to flicker is reduced.

  The operation will be described below.

When the signal Y (image signal) output from the imaging means such as a CCD image sensor is input to the flicker reduction apparatus shown in FIG. 1, it is input to the line averaging circuit 11 and the delay unit 20. The line average circuit 11 calculates an average value y ⁰ of effective signal sections of one line period of the input signal Y. The calculated average value y ⁰ is input to the average value calculation circuit 130, the divider 14, the motion detection circuit 15, and the memory 120 a in the delay unit 120. The memory 120a holds the input average value y ⁰ and outputs the average value y ⁻¹ after one field period. The signal y ⁻¹ output from the memory 120a is input to the average value calculation circuit 130 and the memory 120b. The memory 120b holds the input average value y ⁻¹ and outputs the average value y ⁻² after one field period (that is, after two field periods from y ⁰ ). The average value y ⁻² output from the memory 120 b is input to the average value calculation circuit 130. That is, average values y ⁰ , y ⁻¹ , and y ⁻² are input to average value calculation circuit 130.

The average value calculation circuit 130 calculates the average of the line average values at the same line position for every three fields, based on the input average values y ⁰ , y ⁻¹ , y ⁻² . The average value calculated by the average value calculation circuit 130 is input to the divider 14. The divider 14 divides the output of the average value calculation circuit 130 by the average value y ⁰ output from the line average circuit 11 to obtain a first flicker correction gain. The first flicker correction gain output from the divider 14 is input to one input terminal of the switch 16 and the flicker component extraction circuit 18.

  The flicker component extraction circuit 18 converts the frequency of the first flicker correction gain output from the divider 14 and extracts only the frequency region that is a flicker component. The flicker component extracted by the flicker component extraction circuit 18 is input to the flicker gain generation circuit 19. The flicker gain generation circuit 19 generates a second flicker correction gain based on the input flicker component (frequency domain). The second flicker correction gain generated by the flicker gain generation circuit 19 is input to the other input terminal of the switch 16.

On the other hand, the motion detection circuit 15 compares the difference between the input average values y ⁰ and y ⁻¹ with the threshold value, and detects the motion of the image (subject) before and after one field. For example, the difference between the average values y ⁰ and y ⁻¹ is low when the subject is stationary, and the difference between the average values y ⁰ and y ⁻¹ is high when the subject is moving. The motion detection circuit 15 outputs a value “1” as a detection signal if the difference is higher than the threshold value, and outputs a value “0” as the detection signal if the difference is lower than the threshold value. The output detection signal is input to the switch 16.

  The switch 16 selects the first flicker correction gain output from the divider 14 having a small remaining flicker component when the detection signal of the value “0” is input (when the subject is stationary). Also, when a detection signal of value “1” is input (when detecting the movement of the subject), the second flicker correction gain output from the flicker gain generation circuit 19 where the gain fluctuation due to the movement does not affect the correction gain is obtained. select. That is, one of the first flicker correction gain and the second flicker correction gain is output from the switch 16 as a final correction signal. The correction signal output from the switch 16 is input to the multiplier 21.

  Multiplier 21 multiplies the Y signal time-adjusted by delay device 20 and the correction signal. The multiplier 21 outputs a signal Y ′ obtained by reducing the fluctuation due to flicker from the signal Y output from the delay unit 20.

  As described above, according to the present embodiment, when 50 Hz flicker is received in the NTSC system, flicker correction is performed based on the first flicker correction gain generated by the divider 14 when the subject is stationary. Since the flicker correction is performed based on the second flicker correction gain of the sine wave output from the flicker gain generation circuit 19 when the subject is moving, it is hardly affected by the movement of the subject and the remaining flicker is A flicker reduction apparatus with few components can be realized.

(Embodiment 2)
FIG. 2 is a diagram showing a relationship between an image sensor output driven by the PAL method and 60 Hz flicker. FIG. 2A shows the output waveform of the image sensor, the broken line is the output waveform when there is no flicker, and the solid line shows the output waveform affected by the flicker. FIG. 2B shows a waveform for explaining the light emission period of a fluorescent lamp using a power frequency of 60 Hz.

  In the case of the PAL system, as shown in FIG. 2, the flicker phase period matches when the output of the image sensor is 5 fields. If the field frequency and the power supply frequency are ideal, the NTSC system as shown in FIG. 15 does not cause a shift such as 50 Hz period flicker. Based on this, the configuration of the second embodiment will be described.

  FIG. 3 shows a block diagram of a configuration example of a PAL system 60 Hz period flicker reduction apparatus according to Embodiment 2 of the present invention. The flicker reduction apparatus in FIG. 3 includes a delay unit 121 instead of the delay unit 120 of the flicker reduction apparatus according to Embodiment 1, and includes an average value calculation circuit 131 instead of the average value calculation circuit 130.

The delay device 121 includes a memory 121a, a memory 121b, a memory 121c, and a memory 121d (storage means) connected in cascade. Each of the memories 121a to 121d can hold a line average value for one field, and outputs it with a delay of one field period. The average value delayed by one field period in the memory 121a is y ⁻¹ , the average value delayed by one field period in the memory 121b is y ⁻² , the average value delayed by one field period in the memory 121c is y ⁻³ , and the memory The average value delayed by one field period at 121d is y- ⁴ .

The average value calculation circuit 131 (second average value calculation means) outputs the output y ⁰ of the line average circuit 11, the output y ⁻¹ of the memory 121a, the output y ⁻² of the memory 121b, and the output y ^{− of the} memory 121c. ³ and the output y ^{-4 of the} memory 121d are calculated. The average of the line average values at the same line position for every five fields is calculated, and a reference value that eliminates the influence of flicker is created.

  Since the other configuration is the same as that of the flicker reduction apparatus according to the first embodiment, the same components are denoted by the same reference numerals, and redundant description is omitted.

  The operation will be described below.

When the signal Y (image signal) output from the imaging means such as a CCD image sensor is input to the flicker reduction apparatus shown in FIG. 1, it is input to the line averaging circuit 11 and the delay unit 20. The line average circuit 11 calculates an average value y ⁰ of effective signal sections of one line period of the input signal Y. The calculated average value y ⁰ is input to the memory 121 a in the average value calculation circuit 131, the divider 14, the motion detection circuit 15, and the delay device 121. The memory 121a holds the input average value y ⁰ and outputs the average value y ⁻¹ after one field period. The signal y ⁻¹ output from the memory 121a is input to the average value calculation circuit 131 and the memory 121b. The memory 121b holds the input average value y ⁻¹ and outputs the average value y ⁻² after one field period (that is, after two field periods from y ⁰ ). The average value y ⁻² output from the memory 121b is input to the average value calculation circuit 131 and the memory 121c. Memory 121c holds the average value y ^-2 inputted, outputs the average value y ^-3 after one field period (i.e. from y ⁰ 3 after field period) to. The average value y ^-3 output from the memory 121c is input to the average value calculation circuit 131 and the memory 121d. Memory 121d holds the average value y ^-3 inputted, outputs the average value y ^-4 after one field period (i.e. from y ⁰ 4 after field period) to. The average value y ^-4 output from the memory 121d is input to the average value calculation circuit 131. That is, average values y ⁰ , y ⁻¹ , y ⁻² , y ⁻³ , and y ⁻⁴ are input to the average value calculation circuit 131.

The average value calculation circuit 131 calculates the average of the line average values at the same line position for every five fields based on the input average values y ⁰ , y ⁻¹ , y ⁻² , y ⁻³ , y ^−4. . The average value calculated by the average value calculation circuit 131 is input to the divider 14. Subsequent operations are the same as those described in the first embodiment, and are therefore omitted.

  As described above, according to the present embodiment, when 60 Hz flicker is received by the PAL method, flicker correction is performed based on the first flicker correction gain generated by the divider 14 when the subject is stationary. Since the flicker correction is performed based on the second flicker correction gain of the sine wave output from the flicker gain generation circuit 19 when the subject is moving, it is hardly affected by the movement of the subject and the remaining flicker is A flicker reduction apparatus with few components can be realized.

  However, when affected by 50 Hz flicker in the PAL system, the phase of the field period and the flicker period coincide with each other and cannot be corrected with the conventional configuration.

(Embodiment 3)
FIG. 4 is a diagram showing the relationship between the image sensor output driven by the NTSC system and 60 Hz flicker. FIG. 4A shows the output waveform of the image pickup device, the broken line is the output waveform when there is no flicker, and the solid line shows the output waveform when affected by the flicker. FIG. 4B shows a waveform for explaining the light emission cycle of a fluorescent lamp using a power frequency of 60 Hz.

Although it seems that the NTSC field period (60 Hz) and the phase of the 60 Hz flicker phase period substantially match, if the field frequency and the power supply frequency are ideal, strictly speaking, as shown in FIG. A deviation of .67 μsec has occurred. Therefore, the period until the field period and flicker period again match is
Flicker cycle 8.33 ms / deviation 16.67 μsec≈500 fields (Formula 1)
It appears on the screen as light and darkness that moves very slowly. Based on this, the configuration of the third embodiment will be described.

  FIG. 5 shows a block diagram of a configuration example of an NTSC 60 Hz period flicker reduction apparatus according to Embodiment 3 of the present invention. The flicker reduction apparatus in FIG. 5 includes a delay unit 122 instead of the delay unit 120 of the flicker reduction apparatus according to the first embodiment.

  The delay device 122 includes a memory 122a, a memory 122b, a memory 122c, and a memory 122d (storage means). Each of the memories 122a to 122d can hold a line average value for one field. The memory 122a is updated at a period of one field period, and the memory 122b, the memory 122c, and the memory 122d are updated at every 1/3 phase of the period in which the phase of the field period and the flicker period again match. That is, it is updated every 1 / 3≈167 fields of the cycle of (Equation 1).

The average value delayed by one field period in the memory 122a is y ⁻¹ , the average value delayed by 167 field periods in the memory 122b is y ^−1p , the average value delayed by 334 field periods in the memory 122c is y ^−2p , and the memory 122d ^Let y ^{-3p be} the average value delayed by 500 field periods.

Average value calculation circuit 130, the output y ^-1P memory 121b, the output of the memory 121c y ^-2p, and intended for calculating the average value of the output y ^-3P memory 121d, a line average of the line position of the three fields Calculate the average of the values and create a reference value that eliminates the effects of flicker.

The divider 14 divides the output of the average value calculation circuit 130 by the line average value y ^-1p of the memory 1 output, thereby maintaining the currently held line average value y ^{-1p with} respect to the line average value of the same line position for three fields. Is obtained as a first flicker correction gain.

The motion detection circuit 15 compares the difference between the current line average value y ⁰ and the line average value y ⁻¹ before one field period with the threshold value, and detects the motion of the subject around one field.

  Since the other configuration is the same as that of the flicker reduction apparatus according to the first embodiment, the same components are denoted by the same reference numerals, and redundant description is omitted.

  In the case of receiving 60 Hz flicker in the NTSC system, since the light and dark movement due to flicker is very slow, the memory update period for calculating the reference value by the average value calculation circuit 130 is set to every 167 fields, but the field frequency or power supply frequency is When the value deviates from the ideal value, the period until the field period and flicker period again coincide with each other, so that the reference value calculated by the average value calculation circuit 130 also shifts. Therefore, since the gain value is updated only for every 167 fields in the first flicker correction gain with this configuration, if it is used as it is for the correction gain, it cannot be used because the temporal level change is noticeable. Therefore, the flicker component extraction circuit 18 extracts only the flicker component included in the first flicker correction gain, and the flicker gain generation circuit 19 generates the second flicker correction gain, which is mainly used.

  Further, since the gain value is updated only for every 167 fields, the movement of the subject is not reflected in the first flicker correction gain for that period, or the influence continues, so that the second flicker correction gain to be generated is also reflected. As a result, the correction gain has an opposite phase and may increase the brightness due to flicker.

  For this reason, the control of the switch 16 selects the second flicker correction gain output from the flicker gain generation circuit 19 so that the gain fluctuation caused by the movement does not directly affect the correction gain when the subject is stationary, and controls the movement of the subject. If detected, the value “1” is selected so as not to perform gain correction.

  As described above, according to the present embodiment, when 60 Hz flicker is received in the NTSC system, flicker correction processing is performed based on the first flicker correction gain output from the flicker gain generation circuit 19 when the subject is stationary. By performing the above-described processing so that the flicker correction processing is not performed when the subject is moving, it is possible to realize a flicker reducing apparatus that is hardly affected by the motion of the subject.

(Embodiment 4)
FIG. 6 shows a block diagram of a configuration example of the flicker reduction apparatus according to Embodiment 4 of the present invention. The flicker reducing apparatus in FIG. 6 includes a power frequency discriminating circuit 22 added to the flicker reducing apparatus according to the third embodiment, and includes a four-terminal switch 23 instead of the three-terminal switch 16.

  The power frequency discriminating circuit 22 (frequency discriminating means) discriminates whether the flicker component extracted by the flicker component extracting circuit 18 is 100 Hz or 120 Hz. If neither of these is true, it is determined that there is no flicker component. The determination result in the power supply frequency determination circuit 22 is input to the delay unit 123 and the switch 23.

The delay unit 123 includes a memory 123a, a memory 123b, a memory 123c, a memory 123d, a memory 123e, and a memory 123f (storage means). Each of the memories 123a to 123f can hold a line average value for one field. The memory 123a is updated in one field cycle. The memory 123b, the memory 123c, and the memory 123d are switched according to the determination result of the power supply frequency determination circuit 22 so that the memory 123b, the memory 123c, and the memory 123d are updated in one field cycle in the case of 50 Hz flicker and updated in 167 field cycles in the case of 60 Hz flicker. The memory 123e and the memory 123f are updated in one field period only when the PAL method is 60 Hz flicker, and are not used in other cases. The average value delayed by one field period in the memory 123a is y ⁻¹ , the average value delayed in the memory 123b is y ^−1p , the average value delayed in the memory ^123c is y ^−2p, and the average value delayed in the memory 123d is and y ^-3P, an average value which is delayed by memory 123e and ^y -4p, an average value which is delayed by memory 123f and y ^-5p.

The average value calculation circuit 133 (second average value calculation means) creates a reference value that eliminates the influence of flicker. When operating in the NTSC system, the average value of the output y ^-1p of the memory 123b, the output y ^{-2p of} the memory ^123c , and the output y ^{-3p of} the memory 123d is calculated, and the line average value at the same line position every three fields The average of is calculated. When operating in the PAL system, the output y ^{-1p of the} memory 123b, the output y ^{-2p of} the memory ^123c , the output y ^{-3p of} the memory 123d, the output y ^{-4p of} the memory ^123e , and the output y ^{-5p of} the memory ^123f And the average of the line average values at the same line position every five fields is calculated.

  The switch 23 detects the first flicker correction gain output from the divider 14 and the second flicker output from the flicker gain generation circuit 19 from the detection result of the motion detection circuit 15 and the result of the power supply frequency discrimination circuit 22. Either one of the correction gain and the gain (value “1”) when correction is not performed is selected. The selected correction gain is used as a final correction signal.

  Since other configurations are the same as those of the flicker reduction apparatus according to Embodiments 1 and 3, the same components are denoted by the same reference numerals, and redundant description is omitted.

  The control of the switch 23 is switched as shown in Table 1 according to the detection result of the motion detection circuit 15 and the determination result in the power supply frequency determination circuit 22.

  As shown in Table 1, the first flicker correction gain of the divider 14 having a small remaining flicker component is selected when the subject is stationary when the NTSC system drive is 50 Hz flicker or the PAL system drive is 60 Hz flicker. To do. On the other hand, when the movement of the subject is detected, the second flicker correction gain of the flicker gain generation circuit 19 in which the gain fluctuation due to the movement does not affect the correction gain is selected.

  Further, in the case of 60 Hz flicker in the NTSC system drive, when the subject is stationary, the second flicker correction gain of the flicker gain generation circuit 19 that does not directly affect the correction gain is selected. On the other hand, when the movement of the subject is detected, a gain (value “1”) for which gain correction is not performed is selected to prevent side effects due to overcorrection.

  In the case of NTSC drive (50 Hz, 60 Hz), only the memories 123a, 123b, 123c, 123d in the delay unit 123 are operated, and the average value calculation circuit 133 is for three fields output from the memories 123b, 123c, 123d. The average of the average values of is calculated. Since the subsequent operations are described in the first embodiment, they are omitted. In the case of PAL driving, the memories 123a to 123f in the delay unit 123 are operated, and the average value calculation circuit 133 calculates the average of the average values for the five fields of the memories 123b, 123c, 123d, 123e, and 123f. Subsequent operations are described in the third embodiment, and are therefore omitted.

  As described above, according to the present embodiment, the movement of the subject is detected, the power supply frequency of the device on which the flicker reduction device is mounted is detected, and the correction gain is selected based on the detection result. Accordingly, it is possible to provide a flicker reducing apparatus that is hardly affected by the movement of the subject and has a small amount of remaining flicker components.

  A configuration in which means for automatically discriminating NTSC / PAL is further added to the configuration shown in FIG. FIG. 7 shows a configuration in which a synchronization frequency detector 24 is added to the configuration shown in FIG. The synchronization frequency detector 24 detects the synchronization frequency of the input signal Y, counts the number of lines per frame, and determines whether the signal Y is based on the NTSC system or the PAL system. The NTSC system has 525 lines per frame, whereas the PAL system has 625 lines per frame (excluding PAL-M). The synchronization frequency detection unit 24 determines whether the input signal Y is NTSC or PAL based on the difference in horizontal synchronization frequency. The detection result in the synchronization frequency detection unit 24 is input to the delay unit 123 and the switch 23.

  The delay device 123 operates the memories 123a to 123d when the detection result in the synchronization frequency detection unit 24 is the NTSC system. When the detection result in the synchronization frequency detection unit 24 is the PAL method, the memories 123a to 123f are operated.

  Further, the switch 23 does not correct the first flicker correction gain and the second flicker correction gain based on the detection result in the synchronization frequency detection unit 24 and the detection result in the motion detection circuit 15 (value “1”). Select one of the following. Combinations of detection results and selection contents are shown in (Table 1). Subsequent operations are the same as those of the fourth embodiment, and thus are omitted.

  The present invention has an advantage of a large flicker reduction effect, and can be used as a flicker reduction device in the field of imaging devices.

Block diagram of flicker reduction apparatus according to Embodiment 1 Waveform diagram for explaining flicker in the PAL system Block diagram of flicker reduction apparatus according to Embodiment 2 Waveform diagram for explaining flicker in NTSC system Block diagram of flicker reduction apparatus according to Embodiment 3 Block diagram of flicker reduction apparatus according to Embodiment 4 Block diagram showing a modification of the fourth embodiment Waveform diagram for explaining flicker Block diagram of a conventional flicker reduction device Schematic diagram for explaining problems in a conventional flicker reduction device Block diagram of flicker reduction device of conventional example 1 Block diagram of flicker reduction device of conventional example 2 Block diagram of flicker reduction device of Conventional Example 3 Block diagram of flicker reduction device of conventional example 4 Waveform diagram showing signal waveform in conventional flicker reduction device Waveform diagram showing signal waveform in conventional flicker reduction device

Explanation of symbols

11 Line averaging circuit 14 Divider 15 Motion detection circuit 16, 23 Switch 18 Flicker component extraction circuit 19 Flicker gain generation circuit 20 Delay device 21 Multiplier 120 Delay device 120a, 120b Memory 121 Delay device 121a, 121b, 121c, 121d Memory 122 Delay device 122a, 122b, 122c, 122d Memory 123 Delay device 123a, 123b, 123c, 123d, 123e, 123f Memory 130, 131, 133 Average value calculation circuit

Claims (5)

A flicker reduction device that reduces flicker at the output of an image sensor with different accumulation times in units of pixels,
First average value calculating means for calculating an average value of an effective signal section of the image sensor output for each horizontal period;
A plurality of cascaded storage means for holding the output of the first average value calculating means in units of one field or one frame;
A second average value calculating means for calculating an average value of the output of the first average value calculating means and the retained values of the plurality of storage means corresponding to the output and the same horizontal cycle position;
First flicker gain calculating means for extracting an image level variation component caused by flicker from a ratio between an output of the first average value calculating means and an output of the second average value calculating means;
Second flicker gain calculating means for extracting a flicker frequency component from the output of the first flicker gain calculating means and generating a sine waveform synchronized with the flicker frequency;
Movement detecting means for detecting movement of a subject from an output change of the first average value calculating means;
A gain selecting means for selecting an output of the first flicker gain calculating means and an output of the second flicker gain calculating means from the result of the motion detecting means;
Multiplication means for multiplying the output of the gain selection means by the output of the image sensor so as to cancel the influence of flicker,
The gain selection means includes
When the imaging device is driven by the NTSC system and receives flicker due to illumination with a power frequency of 50 Hz,
Based on the result of the motion detection means, the output of the first flicker gain calculation means is selected when the subject is stationary, and the output of the second flicker gain calculation means is selected when the subject is moving. Select a flicker reduction device. A flicker reduction device that reduces flicker at the output of an image sensor with different accumulation times in units of pixels,
First average value calculating means for calculating an average value of an effective signal section of the image sensor output for each horizontal period;
A plurality of cascaded storage means for holding the output of the first average value calculating means in units of one field or one frame;
A second average value calculating means for calculating an average value of the output of the first average value calculating means and the retained values of the plurality of storage means corresponding to the output and the same horizontal cycle position;
First flicker gain calculating means for extracting an image level variation component caused by flicker from a ratio between an output of the first average value calculating means and an output of the second average value calculating means;
Second flicker gain calculating means for extracting a flicker frequency component from the output of the first flicker gain calculating means and generating a sine waveform synchronized with the flicker frequency;
Movement detecting means for detecting movement of a subject from an output change of the first average value calculating means;
A gain selecting means for selecting an output of the first flicker gain calculating means and an output of the second flicker gain calculating means from the result of the motion detecting means;
Multiplication means for multiplying the output of the gain selection means by the output of the image sensor so as to cancel the influence of flicker,
The gain selection means includes
When the image sensor is driven by the NTSC system and receives flicker due to illumination with a power frequency of 60 Hz,
The update of the plurality of storage means is performed at a time obtained by equally dividing the period until the field period and flicker period again coincide with each other into three parts,
Based on the result of the motion detection means, the output of the second flicker gain calculation means is selected when the subject is stationary, and control is performed so as not to output the correction gain when the subject is moving. Flicker reduction apparatus. A flicker reduction device that reduces flicker at the output of an image sensor with different accumulation times in units of pixels,
First average value calculating means for calculating an average value of an effective signal section of the image sensor output for each horizontal period;
A plurality of cascaded storage means for holding the output of the first average value calculating means in units of one field or one frame;
A second average value calculating means for calculating an average value of the output of the first average value calculating means and the retained values of the plurality of storage means corresponding to the output and the same horizontal cycle position;
First flicker gain calculating means for extracting an image level variation component caused by flicker from a ratio between an output of the first average value calculating means and an output of the second average value calculating means;
Second flicker gain calculating means for extracting a flicker frequency component from the output of the first flicker gain calculating means and generating a sine waveform synchronized with the flicker frequency;
Movement detecting means for detecting movement of a subject from an output change of the first average value calculating means;
A gain selecting means for selecting an output of the first flicker gain calculating means and an output of the second flicker gain calculating means from the result of the motion detecting means;
Multiplication means for multiplying the output of the gain selection means by the output of the image sensor so as to cancel the influence of flicker,
The gain selection means includes
When the image sensor is driven by the PAL method and receives flicker due to illumination with a power supply frequency of 60 Hz,
Based on the result of the motion detection means, the output of the first flicker gain calculation means is selected when the subject is stationary, and the output of the second flicker gain calculation means is selected when the subject is moving. Flicker reduction device. A frequency discrimination means for detecting the flicker frequency;
The flicker reduction apparatus according to claim 1, wherein the gain selection unit is controlled to be switched based on a determination result of the frequency determination unit and a driving method of the imaging element. A flicker reduction device that reduces flicker at the output of an image sensor with different accumulation times in units of pixels,
First average value calculating means for calculating an average value of an effective signal section of the image sensor output for each horizontal period;
A plurality of cascaded storage means for holding the output of the first average value calculating means in units of one field or one frame;
A second average value calculating means for calculating an average value of the output of the first average value calculating means and the retained values of the plurality of storage means corresponding to the output and the same horizontal cycle position;
First flicker gain calculating means for extracting an image level variation component caused by flicker from a ratio between an output of the first average value calculating means and an output of the second average value calculating means;
Second flicker gain calculating means for extracting a flicker frequency component from the output of the first flicker gain calculating means and generating a sine waveform synchronized with the flicker frequency;
Movement detecting means for detecting movement of a subject from an output change of the first average value calculating means;
A gain selecting means for selecting an output of the first flicker gain calculating means and an output of the second flicker gain calculating means from the result of the motion detecting means;
Multiplication means for multiplying the output of the gain selection means by the output of the image sensor so as to cancel the influence of flicker;
Frequency discriminating means for detecting flicker frequency,
The gain selection means includes
When the imaging element is driven in the NTSC system and the discrimination result of the frequency discrimination means is 50 Hz, the first flicker gain is obtained when the subject is stationary based on the result of the motion detection means. Select the output of the calculation means, and when the subject is moving, control to select the output of the second flicker gain calculation means,
When the image sensor is driven by the NTSC system and the discrimination result of the frequency discrimination means is 60 Hz, the second flicker gain is obtained when the subject is stationary based on the result of the motion detection means. A flicker reduction device that selects an output of a calculation means and controls not to output a correction gain when the subject is moving.

Images