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JP2008517475A - Substrate having electric contact and method of manufacturing the same - Google Patents

Substrate having electric contact and method of manufacturing the same Download PDF

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Publication number
JP2008517475A
JP2008517475A JP2007537448A JP2007537448A JP2008517475A JP 2008517475 A JP2008517475 A JP 2008517475A JP 2007537448 A JP2007537448 A JP 2007537448A JP 2007537448 A JP2007537448 A JP 2007537448A JP 2008517475 A JP2008517475 A JP 2008517475A
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Prior art keywords
substrate
contact pad
pad
contact pads
contact
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JP2007537448A
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Japanese (ja)
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ヴァン ヴェーン ニコラス
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Koninklijke Philips NV
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Koninklijke Philips NV
Koninklijke Philips Electronics NV
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    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
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Abstract

第１金属接点パッド（１３ａ〜１３ｄ）を有する第１基板（１０）を提供するものであり、第１接点パッド（１３ａ〜１３ｄ）は第２基板（２０）上の第２接点パッド（２３ａ〜２３ｄ）とはんだ付けされるものである。本発明によれば、前記第１基板の第１表面に対する、前記第１接点パッド（１３ａ〜１３ｄ）の最大平面伸張長さ（Ｄｉｎ）が２０μｍを超えないようにする。このように、第１基板（１０）及び第２基板（２０）が互いにはんだ付けされると、０またはほぼ０のスタンドオフ距離Ｘｉｎを達成することができる。この方法は例えば、「アンダーバンプメタライゼーション（ＵＢＭ）」及び、「はんだ浸漬バンピング（ＩＳＢ）」が、前記第１基板（１０）の製造に用いられるフリップチップ技術に適用することができる。Provided is a first substrate (10) having first metal contact pads (13a-13d), wherein the first contact pads (13a-13d) are second contact pads (23a-23) on a second substrate (20). 23d) and soldered. According to the present invention, the maximum planar extension length (Din) of the first contact pads (13a to 13d) relative to the first surface of the first substrate does not exceed 20 μm. Thus, when the first substrate (10) and the second substrate (20) are soldered together, a standoff distance Xin of 0 or nearly 0 can be achieved. This method can be applied, for example, to the flip chip technology in which "under bump metallization (UBM)" and "solder immersion bumping (ISB)" are used for the production of the first substrate (10).

Description

本発明は、絶縁領域によって互いに分離された複数の第１金属接点パッドを有する第１表面を具える基板であって、これら第１接点パッドは、他の基板の第２表面上の第２接点パッドにはんだ付けされるべきものであり、前記基板上の前記第１接点パッドとこれに対応する前記他の基板上の第２接点パッドとが互いに対向するようになっている当該基板に関する。   The present invention is a substrate comprising a first surface having a plurality of first metal contact pads separated from one another by an insulating region, wherein the first contact pads are second contacts on the second surface of the other substrate. The present invention relates to a substrate to be soldered to a pad, wherein the first contact pad on the substrate and the corresponding second contact pad on the other substrate face each other.

本発明は更に、第１金属接点パッドを有する第１表面を具えた第１基板と、第２金属接点パッドを有する第２表面を具えた第２基板とが設けられた電子デバイスであって、前記第１接点パッドと前記第２接点パッドとが互いにはんだ付けされており、第１基板上の第１接点パッドと、これに対応する第２基板上の第２接点パッドとが互いに対向している当該電子デバイスに関する。   The invention further relates to an electronic device provided with a first substrate comprising a first surface having a first metal contact pad and a second substrate comprising a second surface having a second metal contact pad, The first contact pad and the second contact pad are soldered to each other, and the first contact pad on the first substrate and the corresponding second contact pad on the second substrate face each other. The electronic device concerned.

本発明は更に、このような基板を製造する方法に関する。   The invention further relates to a method of manufacturing such a substrate.

前記基板は、当該技術において幅広く用いられている。例えば、電子回路を有するダイは、良く知られている「フリップチップ技術」によって、「サポート」基板にダイを接続するための接点パッドをも有している。   The substrate is widely used in the art. For example, a die with electronic circuitry also has contact pads for connecting the die to a "support" substrate by the well known "flip chip technology".

「フリップチップ」という語は、「フェースダウン」方法によって直接、基板、ボード又は担体上に実装（装着）することができる電気素子または半導体デバイスを意味する。電気接続が、チップの表面上に形成された導電性バンプによって達成されるので、この実装処理が従来から「フェースダウン」と称されている。実装に際し、チップは、バンプが目的位置に正確に配置されている基板、ボード又は担体上で裏返しに（フリップ）される。それ故、このチップを「フリップチップ」と称している。フリップチップはワイヤボンドを必要としないので、対応する従来のワイヤボンドを用いる場合よりも、基板上に占めるスペースが少なくて足りる。   The term "flip chip" means an electrical element or semiconductor device that can be mounted (mounted) directly on a substrate, board or carrier by a "face down" method. This mounting process is conventionally referred to as "face-down" because electrical connections are achieved by conductive bumps formed on the surface of the chip. During mounting, the chip is flipped over on a substrate, board or carrier on which the bumps are precisely located at the desired position. Therefore, this chip is called "flip chip". Because flip chips do not require wire bonds, they occupy less space on the substrate than with corresponding conventional wire bonds.

フリップチップは、伝統的な半導体パッケージとは構造的に異なるものであり、従って、必要とするアセンブリ処理もまた、従来の半導体アセンブリとは異なっている。フリップチップのアセンブリは、主たる３つの工程、すなわち、１）チップのバンピング工程、２）バンピングされたチップを基板又はボードへ「フェースダウン」で取り付ける工程、３）チップと基板又はボードとの間の隙間を、機械的に保護する非導電性材料で充填する処理であるアンダーフィル工程より成る。バンピング、取り付け及びアンダーフィルの工程で使用される材料及び技術を種々に異ならせると、フリップチップは、種々に異なる配列となる。   Flip chips are structurally different from traditional semiconductor packages, so the assembly process required is also different from conventional semiconductor assemblies. The flip chip assembly consists of three main steps: 1) bumping the chip, 2) attaching the bumped chip "face down" to the substrate or board, 3) between the chip and the substrate or board It comprises an underfilling process which is a process of filling the gap with a nonconductive material that protects mechanically. The different materials and techniques used in the bumping, attachment and underfill processes result in different arrangements of flip chips.

フリップチップのバンピング処理を行うための、多くの既知の処理のうちの１つには、
スパッタリング、めっき、印刷、又はこれらに類似する処理により接着パッド上に、いわゆる「アンダーバンプメタライゼーション（ＵＢＭ）」の金属化体を配置する処理が含まれるものである。これらを組み合わせることも可能であること勿論である。ＵＢＭは、はんだのぬれ性（湿潤性）が良好な無電解ＮｉＡｕをもって構成するのが好ましいが、他の物質の組み合わせを適用することもできる。より高い温度に用いられる他の例は、無電解ＮｉＰｄＡｕである。ＵＢＭ処理によれば、接着パッド上の表面安定化酸化物層が除去され、はんだのぬれ領域が規定される。次に、適切な方法、例えば蒸着、電気めっき、スクリーン印刷またはディスペンシングによりＵＢＭ上にはんだを堆積することができる。 One of the many known processes for bumping flip chips is:
Included is the process of disposing a so-called "under bump metallization (UBM)" metallization on the bond pad by a process such as sputtering, plating, printing, or the like. It is of course possible to combine these. The UBM is preferably constructed with electroless NiAu, which has good solder wettability (wettability), but other combinations of materials can be applied. Another example used for higher temperatures is electroless NiPdAu. The UBM process removes the surface stabilizing oxide layer on the bond pad and defines the wetted area of the solder. The solder can then be deposited on the UBM by any suitable method, such as evaporation, electroplating, screen printing or dispensing.

ウエハバンピングを廉価に達成するために、はんだペーストのステンシル印刷が実行されており、フリップチップはんだ付けに大きく貢献している。費用効果以外の点では、無鉛合金を含む他のはんだペーストを用いることができる。しかしながら、入手しうるはんだペースト及びステンシルの幾何学的形状が原因で、現在この処理は、多量生産の場合２００μｍまで、試験的には１５０μｍまでのピッチに制限されている。   In order to achieve wafer bumping at low cost, stencil printing of solder paste is being performed, which greatly contributes to flip chip soldering. Other than cost effectiveness, other solder pastes can be used, including lead free alloys. However, due to the available solder paste and stencil geometry, this process is currently limited to pitches up to 200 μm for high volume production, and up to 150 μm for trial.

更なる他の方法は、いわゆる「はんだ浸漬バンピング（ＩＳＢ）」であり、この方法は電気めっきに代わる廉価な代替例として用いることができる。ＩＳＢは、通常は１００μｍから極めて微細なピッチの４０μｍまでの寸法を有するパッドに対して用いることができる。ＩＳＢでは、ウエハが液体はんだに浸され、ＵＢＭが湿潤され、小さいはんだキャップがＵＢＭ上に形成される。はんだキャップの高さは、パッドの寸法に著しく依存する。液体はんだの表面上に有機液体を配置することにより、はんだの酸化を防止し、湿潤性を向上させる。はんだ付けの後、残留物を容易に取り除くことができる。処理自体は、ウエハの寸法を制限するものではない。単体のダイを処理することも、同様に可能である。処理はまた、無鉛はんだの要求に適合するように変更することもできる。ＰｂＳｎ６３、ＳｎＢｉ４２、ＳｎＡｇ３．５、ＳｎＣｕ０．７のような他のはんだ材料を用いることもできる。   Yet another method is the so-called "solder immersion bumping (ISB)", which can be used as an inexpensive alternative to electroplating. ISB can be used for pads that typically have dimensions from 100 μm to very fine pitches of 40 μm. In ISB, the wafer is immersed in liquid solder, the UBM is wetted, and a small solder cap is formed on the UBM. The height of the solder cap is highly dependent on the size of the pad. Placing the organic liquid on the surface of the liquid solder prevents oxidation of the solder and improves wettability. After soldering, the residue can be easily removed. The process itself does not limit the size of the wafer. It is also possible to process a single die. The process can also be modified to meet the requirements of lead free solders. Other solder materials such as PbSn63, SnBi42, SnAg3.5, SnCu0.7 can also be used.

はんだバンピングのこの処理全体は一般に、ウエハのレベルで実行される。次に、はんだがバンピングされたウエハを個々のフリップチップに切断し、はんだを溶かすのに十分高い温度をアセンブリに与えることによって、これらフリップチップをボードまたは基板に装着し、これにより、相互接続を達成する。この目的のために、サーモードボンダ、すなわち選択して配置する手段が使用される。サーモードボンダの配置ヘッドは、リフロー処理を達成するのに充分な熱を提供することを目的として、フリップチップデバイスにエネルギーを供給するために用いられる。低融点の軟質はんだのはんだ浸漬バンピングと急速なサーモードボンディングとの組み合わせを、スマートタグ接着技術に代わるものとすることができる。   This entire process of solder bumping is generally performed at the wafer level. These flip chips are then attached to a board or substrate by cutting the bumped wafers into individual flip chips and providing the assembly with a temperature high enough to melt the solder, thereby interconnecting Achieve. For this purpose, a thermobonder, ie a means for selective placement, is used. The placement head of the thermal bonder is used to provide energy to the flip chip device in order to provide sufficient heat to accomplish the reflow process. The combination of low melting point soft solder solder immersion bumping and rapid thermode bonding can be an alternative to smart tag bonding technology.

最後に、フリップチップデバイスに、アンダーフィル処理を行う。この処理は、しばしばフリップチップのエッジに沿うニードルディスペンシング処理によって達成される。この場合、毛管作用により、空間が満たされるまで、ディスペンシングされたアンダーフィル材料を内部へ吸引する。次に、熱硬化を実行して、不変的な結合を形成する。   Finally, the flip chip device is underfilled. This process is often accomplished by a needle dispensing process along the edge of the flip chip. In this case, the dispensed underfill material is drawn internally by capillary action until the space is filled. Next, heat curing is performed to form a permanent bond.

本明細書において使用されている「基板」という用語は、フリップチップ技術における基板を意味するだけでなく、電子回路を含むダイをも含むことに留意しなければならない。チップ製造に関する、「基板」と「ダイ」との相違は、本発明にとっては問題とならないものである。用語「基板」が、そのチップに関連する意味において必要である場合は常に、これに代えて、用語「サポート基板」が用いられるものである。更にまた、対応する処理を使用する場合に、通常「アンダーバンプメタライゼーション」と称されていることは、本明細書では一般的な表現で、「金属接点パッド」と称することを考慮すべきである。この一般的な表現を用いる理由は、本発明が、フリップチップ技術にも、ＵＢＭ又はＩＳＢの処理にも限定されないた為である。   It should be noted that the term "substrate" as used herein not only refers to a substrate in flip chip technology, but also includes dies that contain electronic circuitry. The difference between "substrate" and "die" in chip manufacture is not a problem for the present invention. Whenever the term "substrate" is required in the sense associated with the chip, the term "support substrate" is used instead. Furthermore, when using the corresponding process, what is usually referred to as "under bump metallization" should be considered in general terms herein to be referred to as "metal contact pad". is there. The reason for using this general expression is that the present invention is not limited to flip chip technology, nor to the processing of UBM or ISB.

図１ａは、従来技術である基板４０の断面を示し、図１ｂは、これに対応する頂面図を示す。（第１）基板４０は、より大きい電子回路の一部でもよく、この場合、図１ａ及び１ｂは、通常は、これらの一部を多数含むこのような電子回路の切り取り部のみを示す。   FIG. 1a shows a cross section of a prior art substrate 40 and FIG. 1b shows a corresponding top view. The (first) substrate 40 may be part of a larger electronic circuit, in which case FIGS. 1a and 1b only show the cutout of such electronic circuit, which usually contains a large number of these parts.

前記基板４０は、その第１表面上に第１金属接着パッド４１を具えている。この基板４０上には第１絶縁層４２が配置され、しかもこの第１絶縁層４２は第１金属接着パッド４１の境界域を覆い、これにより、円柱状の溝を第１接着パッド４１の上面上に形成している。第１金属接着パッド４１上には、第１接点パッド４３が配置され、この第１接点パッドは前記第１絶縁層４２から突出している。円柱状の溝のために、第１接点パッド４３は、隆起したエッジを有する。最後に、第１接点パッド４３上に、はんだバンプ４４が形成されている。はんだバンプ４４の高さＨｐｒは、第１接点パッド４３の直径Ｄｐｒに依存し、代表的にこの直径Ｄｐｒの約０．３倍である。図１ａ及び１ｂに示されている構成は通常、中間生成体である。本例では、この構成が、電子回路を有するダイの一部であると仮定している。   The substrate 40 comprises a first metal bond pad 41 on its first surface. A first insulating layer 42 is disposed on the substrate 40, and the first insulating layer 42 covers the boundary area of the first metal bonding pad 41, thereby forming a cylindrical groove on the upper surface of the first bonding pad 41. Formed on. A first contact pad 43 is disposed on the first metal bonding pad 41, and the first contact pad protrudes from the first insulating layer 42. Due to the cylindrical groove, the first contact pad 43 has a raised edge. Finally, solder bumps 44 are formed on the first contact pads 43. The height Hpr of the solder bump 44 depends on the diameter Dpr of the first contact pad 43, and is typically about 0.3 times this diameter Dpr. The configurations shown in FIGS. 1a and 1b are usually intermediates. In this example, it is assumed that this configuration is part of a die with electronic circuitry.

電子デバイス６０を完成するために、このダイが、サポート基板上にフリップチップ装着されている。この従来技術であるサポート基板の一部を、図２に示す。この図２は、図１ａの部分と、これと同一の鏡像反転させた部分とが、互いにはんだ付けされた構造を示す。鏡像反転された前記部分は他の（第２）基板５０を有し、この基板５０はその第２表面上に第２金属接着パッド５１を有する。基板５０の下には第２絶縁層５２が配置され、この第２絶縁層もまた、第２金属接着パッド５１の境界域を覆い、これにより、円柱状の溝を第２接着パッド５１の下面上に形成する。第２金属接着パッド５１の下には、第２接点パッド５３が配置され、この第２接点パッド自体は前記第２絶縁層５２から突出している。円柱状の溝のために、第２接点パッド５３は、隆起したエッジを有する。鏡像反転された部分では別のはんだバンプ４４が省略されている。その理由は、はんだが既に第１接点パッド４３上に存在している為である。両部分が互いにはんだ付けされると、第１接点パッド４３及び第２接点パッド５３は、はんだの表面張力によって互いに吸引される。図２は、２つの部分が接合されることにより、いわゆるスタンドオフ距離Ｘｐｒ、すなわち接点パッド４３及び５３間の距離が得られることを示している。このスタンドオフ距離Ｘｐｒも、第１接点パッド４３の直径Ｄｐｒに依存し、このスタンドオフ距離は前記直径Ｄｐｒの約０．１５倍である。本例では、第１接点パッド４３及び第２接点パッド５３の直径は同一であると仮定している。直径が異なる場合には、他の結果が得られること勿論である。   To complete the electronic device 60, the die is flip chip mounted on a support substrate. A portion of this prior art support substrate is shown in FIG. This FIG. 2 shows the structure of FIG. 1a and the same mirror-inverted part soldered together. The mirror-inverted portion has another (second) substrate 50, which has a second metal bond pad 51 on its second surface. A second insulating layer 52 is disposed under the substrate 50, and the second insulating layer also covers the boundary area of the second metal bonding pad 51, thereby forming a cylindrical groove on the lower surface of the second bonding pad 51. Form on. A second contact pad 53 is disposed under the second metal adhesive pad 51, and the second contact pad itself protrudes from the second insulating layer 52. Due to the cylindrical groove, the second contact pad 53 has a raised edge. Another solder bump 44 is omitted in the mirror-inverted part. The reason is that the solder is already present on the first contact pad 43. When both parts are soldered to each other, the first contact pad 43 and the second contact pad 53 are attracted to each other by the surface tension of the solder. FIG. 2 shows that by joining the two parts a so-called standoff distance Xpr, ie the distance between the contact pads 43 and 53, is obtained. The standoff distance Xpr also depends on the diameter Dpr of the first contact pad 43, and the standoff distance is about 0.15 times the diameter Dpr. In this example, it is assumed that the diameters of the first contact pad 43 and the second contact pad 53 are the same. Of course, other results can be obtained if the diameters are different.

電子デバイスの寸法を最小化する傾向に合わせて、前記スタンドオフ距離Ｘｐｒを最小化する努力も払われている。しかし、接点パッドはある寸法を有さなければならないので、スタンドオフ距離もまた、ある寸法を有する。   Efforts have also been made to minimize the standoff distance Xpr in keeping with the trend of minimizing the size of the electronic device. However, since the contact pads must have certain dimensions, the standoff distance also has certain dimensions.

発明の目的及び概要OBJECT AND SUMMARY OF THE INVENTION

本発明の目的は、スタンドオフ距離を０又はほぼ０とする解法策を提供することにある。   An object of the present invention is to provide a solution in which the standoff distance is zero or almost zero.

この目的は、前記第１表面に対する前記第１接点パッドの最大平面伸張長さが２０μｍを超えないようにした前述した種類の基板によって達成される。驚いたことに、第１接点パッドの寸法が０である場合（この場合は勿論無意味である）だけでなく、ある値、すなわち２０μｍを超えない場合においても、スタンドオフ距離を０又はほぼ０とすることができることを確かめた。図５の線図は、上述した効果を示す。この線図は、旧来の研究による、はんだバンプの高さＨｐｒ（一点鎖線）と、スタンドオフ距離Ｘｐｒ（破線）とをパッドの直径Ｄの関数として示す。この線図から容易に理解しうるように、はんだバンプの高さＨｐｒは、パッドの直径Ｄに著しく依存し、パッドの直径Ｄの約０．３倍である。旧来の研究によれば、スタンドオフ距離Ｘｐｒに対しても同様な（線形の）効果を確かめた。このスタンドオフ距離Ｘｐｒは、パッドの直径Ｄの約０．１５倍である（破線）。しかし、より最近の研究によれば驚いたことに、第１接点パッドが２０μｍを超えない場合に、スタンドオフ距離Ｘｉｎを０又はほぼ０にしうることを確かめた（実線）。パッドの直径を２０μｍよりも小さくした場合、ＩＳＢ処理によって得られたはんだは、重ね合わせた接点パッドの周囲に配置され、従って、はんだはスタンドオフ距離を増大させることに寄与しない。   This object is achieved by a substrate of the kind described above, in which the maximum planar extension of the first contact pad relative to the first surface does not exceed 20 μm. Surprisingly, the standoff distance is zero or almost zero not only if the dimension of the first contact pad is zero (in this case, of course, meaningless) but also if it does not exceed a certain value, ie 20 μm. I confirmed that I could do it. The diagram of FIG. 5 shows the effect described above. This diagram shows the height Hpr of the solder bumps (dashed-dotted line) and the standoff distance Xpr (dashed line) as a function of the diameter D of the pad according to previous studies. As can be easily understood from this diagram, the height Hpr of the solder bumps is significantly dependent on the diameter D of the pad, which is about 0.3 times the diameter D of the pad. Previous studies have shown similar (linear) effects for standoff distance Xpr. This standoff distance Xpr is about 0.15 times the diameter D of the pad (dashed line). However, more recent studies have surprisingly found that the standoff distance Xin can be zero or nearly zero if the first contact pad does not exceed 20 μm (solid line). If the diameter of the pad is made smaller than 20 μm, the solder obtained by the ISB process is placed around the superimposed contact pads, so the solder does not contribute to increasing the standoff distance.

これらの結果は、非常に小さい電子デバイスを製造するのに有利に用いることができる。このことは特に、今日多量に必要であるいわゆる無線周波識別（ＲＦＩＤ）タグにとって都合良いことである。本発明によれば、比較的容易で、従って廉価なＵＢＭ及びＩＳＢ処理を用いることにより、アセンブリの高さを極めて低くしてこれらのタグを形成することができる。   These results can be advantageously used to produce very small electronic devices. This is particularly advantageous for so-called radio frequency identification (RFID) tags, which are needed today in large quantities. According to the present invention, these tags can be formed with an extremely low assembly height by using relatively easy and therefore inexpensive UBM and ISB processes.

「スタンドオフ距離が０」の具体的な数値は、接点パッドの寸法だけでなく、それらの表面状態にも依存することに留意する必要がある。従って、表面をきめ細かい構造にすることにより、表面を粗くした場合よりもスタンドオフ距離を小さくすることができる。更に、はんだ付け処理は小さな力効果を用いて、又はいかなる力効果も用いずに実行することができる。この力効果によってもスタンドオフ距離の値に影響を及ぼす。   It should be noted that the specific numerical value of "the standoff distance is 0" depends not only on the size of the contact pads but also on their surface condition. Therefore, by making the surface finer, the standoff distance can be made smaller than in the case where the surface is roughened. Furthermore, the soldering process can be performed with a small force effect or without any force effect. This force effect also affects the standoff distance value.

本発明の技術用語である「スタンドオフ距離」は、接点間の距離を表すものである為、一般的には前記基板の表面から突出しているＵＢＭの場合、第１基板及び第２基板間にはある距離が存在する。従って、基板間の距離はＵＢＭ層の厚みにより影響され、接続部材であるＵＢＭ層の厚みの合計（実際にはミクロンのオーダーである）より小さくすることはできない。従って、本発明の基板によって形成される電子デバイスには、通常は、既知の技術に従ってアンダーフィル処理が行われる。   The term "standoff distance", which is a technical term of the present invention, represents the distance between the contacts, and therefore, in the case of UBM generally projecting from the surface of the substrate, the distance between the first substrate and the second substrate There is a certain distance. Therefore, the distance between the substrates is influenced by the thickness of the UBM layer and can not be smaller than the total thickness of the connecting member UBM layers (which is actually on the order of microns). Thus, the electronic devices formed by the substrate of the present invention are usually underfilled in accordance with known techniques.

前記第１表面に対する前記第１接点パッドの最小平面伸張長さは５μｍより短くならないようにするのが有利である。接点パッドを容易に製造するためには、これら接点パッドは少なくともある程度の寸法を有する必要があることを確かめた。５μｍから２０μｍまでの距離範囲は、特にＵＢＭ及びＩＳＢ処理において有利な範囲である。接点パッドの形成前に既に、例えば無電解ＮｉＡｕが７μｍまでの寸法でパッド上に実装されているが、この寸法は、「物理的な」下限として解釈されるべきではないこと勿論である。近い将来、より小さいＮｉＡｕ接点パッドを製造することができる可能性がある。しかしながら、これらの小さな寸法は、この処理に使われている浴に、新たな要求を課す。従って、パッド直径に対する「現実的な」下限値は、５μｍであると考えられる。   Advantageously, the minimum planar extension of the first contact pad relative to the first surface is not shorter than 5 μm. It has been found that in order to easily manufacture the contact pads, these contact pads need to have at least some dimensions. A distance range of 5 μm to 20 μm is an advantageous range especially in UBM and ISB processing. Although, for example, electroless NiAu is already mounted on the pads with dimensions up to 7 μm before the formation of the contact pads, it is of course that this dimension should not be interpreted as a “physical” lower limit. In the near future, it may be possible to produce smaller NiAu contact pads. However, these small dimensions impose new requirements on the baths used in this process. Thus, the "realistic" lower limit for the pad diameter is considered to be 5 μm.

更に、第１接点パッドが隆起エッジを有するのが有利である。はんだを接点パッド上に設ける場合、このはんだが接点パッドの金属と接する個所に、金属間化合物が形成される。これらの金属間化合物は、スタンドオフ距離を０にするのを妨げる。その理由は、関連部分を「互いに吸引する」傾向が、必要な程度には強くない為である。隆起エッジがある場合、これらの金属間化合物は、主に中央に、すなわち接点パッドの溝に形成される。従って、これらの金属間化合物は、本質的に２つの接点パッドの密接な接近を妨げることはない。接点パッド、特に第１及び第２基板の表面から突出している隆起エッジを有する接点パッドは、特に、スタンドオフ距離が０の場合に顕著である追加の利点をもたらす。この場合、表面全体が接点となるのではなく、一部のみに接点が存在し、このことは、接点パッドのスタンドオフ距離を０にする上で役立つこと明らかである。   Furthermore, it is advantageous for the first contact pad to have a raised edge. When the solder is provided on the contact pad, an intermetallic compound is formed where the solder contacts the metal of the contact pad. These intermetallic compounds prevent the standoff distance from becoming zero. The reason is that the tendency to "suck together" the relevant parts is not as strong as necessary. If there are raised edges, these intermetallic compounds are mainly formed in the center, ie in the grooves of the contact pads. Thus, these intermetallic compounds do not essentially prevent the close proximity of the two contact pads. Contact pads, in particular contact pads having raised edges projecting from the surfaces of the first and second substrates, offer an additional advantage which is particularly noticeable when the standoff distance is zero. In this case, it is apparent that the entire surface is not a contact, but only a part of the contact is present, which helps to make the standoff distance of the contact pad zero.

本発明による更に他の好適な解決策は、前記第１接点パッドと前記第１表面との間に金属接着パッドが配置され、この金属接着パッドはその境界域において絶縁層によって部分的に覆われており、前記第１接点パッドはこの絶縁層から突出している基板にある。この構造は、例えばＵＢＭ処理の結果であり、その取り扱いは比較的容易である。それ故、上述した基板を製造するために要求される技術的及び経済的努力は、極めて低い。ここで、本発明はＵＢＭに限定されないことを記述しておく。   Yet another preferred solution according to the invention places a metal bond pad between the first contact pad and the first surface, the metal bond pad being partially covered by an insulating layer in its interface area. The first contact pads are on the substrate projecting from the insulating layer. This structure is, for example, the result of UBM processing, and its handling is relatively easy. Therefore, the technical and economic effort required to manufacture the above mentioned substrates is extremely low. It is noted here that the present invention is not limited to UBM.

基板は第１接点パッド上にはんだバンプを有するようにするのが有利である。その理由は、この場合、第１基板は、第２金属接点パッドをも有する第２基板にはんだ付けされるべき準備ができている為である。はんだバンプは、ＩＳＢ処理を利用して製造するのが好ましいが、これに限定されるものではない。上述したＩＳＢに代わるものとしてウェーブはんだ付けがあり、このはんだ付けも、本発明に用いることができる。他の適用可能な技術は、ステンシル印刷及びめっき処理であるが、これらは双方とも、ＩＳＢと比較して高価である。また、はんだ付けは、アンダーバンプメタライゼーション処理に依存しない点に留意すべきである。はんだ付けは、むしろどのような接点パッドに対しても達成することができる。   Advantageously, the substrate has solder bumps on the first contact pads. The reason is that in this case the first substrate is ready to be soldered to the second substrate which also has a second metal contact pad. Solder bumps are preferably manufactured using an ISB process, but are not limited thereto. Wave soldering is an alternative to the above-described ISB, and this soldering can also be used in the present invention. Other applicable techniques are stencil printing and plating processes, both of which are expensive compared to ISB. Also, it should be noted that the soldering does not depend on the under bump metallization process. Soldering can rather be achieved for any contact pad.

更に、はんだバンプは低融点はんだをもって構成するのが有利である。従って、基板は、紙又はプラスチックのような、感温材料をもって構成することができる。従来技術によれば、１００℃よりも低い温度で溶融するはんだが開示されている。この点に対しては、２００４年５月２５日付で特許された、“Solder compositions for attaching a die to a substrate”の名称の米国特許ＵＳ６，７４０，５４４号明細書、特に表１を参照しうる。更に、この米国特許明細書は、いわゆる「はんだ剤」によって、はんだの融点を上げる可能性を開示している。この米国特許は参考のために記載したものである。上述した方法は、周囲温度が高い条件下でデバイスを作動させる場合に特に有利である。   Furthermore, it is advantageous to construct the solder bumps with a low melting point solder. Thus, the substrate can be comprised of a temperature sensitive material, such as paper or plastic. According to the prior art, solders are disclosed which melt at temperatures below 100.degree. In this regard, reference may be made to US Pat. No. 6,740,544 entitled “Solder compositions for attaching a die to a substrate” patented on May 25, 2004, in particular Table 1. . Furthermore, this patent discloses the possibility of raising the melting point of the solder by means of so-called "solder agents". This US patent is described for reference. The method described above is particularly advantageous when operating the device under conditions of high ambient temperature.

更に、第１金属接点パッドを互いに隣接させて電気接点を形成するのが有利である。好ましくは５μｍ〜２０μｍの寸法を有する１つの接点パッドが、ある値の電流のみを流すようにしうる。ある設計の電子回路から生じる必要な電流がこのある値の制限を超える場合には、互いにより隣接させた第１金属接点パッドから成る電気接点を形成することができる。このようにすることにより、スタンドオフ距離を増大させることなく、電気接点がいかなる所望の電流をも流しうるようにしうる。この点で、接点パッドは必ずしも互いに接近させて配置する必要はないことに注意すべきである。また、これらの金属接点パッド間に、他の電気接点の金属接点パッドを存在させることもできる。   Furthermore, it is advantageous to bring the first metal contact pads adjacent to one another to form an electrical contact. One contact pad, preferably having dimensions of 5 [mu] m to 20 [mu] m, may be adapted to carry only a certain value of current. If the required current arising from an electronic circuit of a design exceeds this certain value limit, it is possible to form an electrical contact consisting of first metal contact pads that are more adjacent to one another. This may allow the electrical contacts to carry any desired current without increasing the standoff distance. It should be noted in this respect that the contact pads do not necessarily have to be arranged close to one another. Also, metal contact pads of other electrical contacts can be present between these metal contact pads.

本発明の目的は更に、第１金属接点パッドを有する第１表面を具えた第１基板と、第２金属接点パッドを有する第２表面を具えた第２基板とが設けられた電子デバイスであって、前記第１接点パッドと前記第２接点パッドとが互いにはんだ付けされており、第１基板上の第１接点パッドと、これに対応する第２基板上の第２接点パッドとが互いに対向している当該電子デバイスにおいて、前記第１及び第２表面に対する前記第１及び第２接点パッドの最大平面伸張長さが２０μｍを超えないようになっている電子デバイスによって達成される。   The object of the present invention is also an electronic device provided with a first substrate with a first surface with a first metal contact pad and a second substrate with a second surface with a second metal contact pad. The first contact pad and the second contact pad are soldered to each other, and the first contact pad on the first substrate and the corresponding second contact pad on the second substrate face each other. In the electronic device, the maximum planar extension length of the first and second contact pads relative to the first and second surfaces is achieved by the electronic device not to exceed 20 μm.

本発明の目的はまた、アンダーバンプメタライゼーション処理により、第１金属接点パッドを有する第１表面を具えた基板を製造する基板の製造方法において、前記第１表面に対する前記第１接点パッドの最大平面伸張長さが２０μｍを超えないようにする基板の製造方法により達成される。   An object of the present invention is also a method of manufacturing a substrate for manufacturing a substrate provided with a first surface having a first metal contact pad by an under bump metallization process, wherein the largest plane of said first contact pad with respect to said first surface It is achieved by a method of manufacturing a substrate in which the extension length does not exceed 20 μm.

本発明の基板の説明で述べた利点及び種々の例は、本発明のデバイス及び方法においても有効である点に留意すべきである。従って、本発明のデバイス及び方法に対する例及び利点の説明は省略する。   It should be noted that the advantages and various examples mentioned in the description of the substrate of the invention are also valid in the device and method of the invention. Accordingly, descriptions of examples and advantages for the devices and methods of the present invention are omitted.

本発明の上述した観点及びその他の観点は、以下の実施例の説明から明らかとなるであろう。以下に説明する本発明の実施例は、例示にすぎないものである。   These and other aspects of the invention will be apparent from the following description of the embodiments. The embodiments of the present invention described below are for illustration only.

図３ａは、本発明による基板１０の断面図を示し、図３ｂは、これに対応する頂面図を示す。基板１０は、大きな電子回路の一部とすることができ、この場合、図１ａ及び図１ｂは、通常、この一部を多数有するこのような電子回路の切り取り部のみを示すものである。   FIG. 3a shows a cross-sectional view of a substrate 10 according to the invention, and FIG. 3b a corresponding top view. The substrate 10 can be part of a large electronic circuit, in which case FIGS. 1a and 1b only show the cutout of such an electronic circuit which usually has a large number of such parts.

前記基板１０は、その第１表面上に第１金属接着パッド１１（例えばＣｕ、Ｎｉ、Ｃｏ、Ｎｂ等から成る）を具える。この基板１０の上には、第１絶縁層１２が配置され、この第１絶縁層は第１金属接着パッド１１の境界域をも覆っている。この第１絶縁層１２は、４つの円柱状の溝を第１接着パッド１１の上面上に形成している。第１金属接着パッド１１上でこれらの溝内に、４つの第１接点パッド１３ａ〜１３ｄが配置され、これらの第１接点パッドは、前記第１絶縁層１２から突出している。これらの円柱状の溝の為に、第１接点パッド１３ａ〜１３ｄは、隆起したエッジを有する。最後に、第１接点パッド１３ａ〜１３ｄ上に、はんだバンプ１４ａ〜１４ｄが形成されている。はんだバンプ１４ａ〜１４ｄの高さＨｉｎは、第１接点パッド１３ａ〜１３ｄの直径Ｄｉｎに依存し、前記直径Ｄｉｎの約０．３倍である。図１ａ及び１ｂに示されている構成は、通常、中間生成体である。本例では、この構成を、電子回路を有するダイの一部であるものとする。   The substrate 10 comprises a first metal bond pad 11 (for example made of Cu, Ni, Co, Nb, etc.) on its first surface. A first insulating layer 12 is disposed on the substrate 10, and the first insulating layer also covers the boundary area of the first metal bonding pad 11. The first insulating layer 12 has four cylindrical grooves formed on the top surface of the first adhesive pad 11. Four first contact pads 13 a-13 d are arranged in these grooves on the first metal bonding pads 11, these first contact pads projecting from the first insulating layer 12. Because of these cylindrical grooves, the first contact pads 13a-13d have raised edges. Finally, solder bumps 14a to 14d are formed on the first contact pads 13a to 13d. The height Hin of the solder bumps 14a-14d depends on the diameter Din of the first contact pads 13a-13d and is about 0.3 times the diameter Din. The configurations shown in FIGS. 1a and 1b are usually intermediates. In this example, this configuration is part of a die with electronic circuitry.

電子デバイス３０を完成するために、このダイを、サポート基板上にフリップチップ装着する。このサポート基板の一部を、図４に示してある。図４は、図３ａの部分と、これと同一の鏡像反転された部分とが、互いにはんだ付けされた構成を示している。この鏡像反転された部分は第２基板２０を有し、この第２基板はその第２表面上に第２金属接着パッド２１を有している。第２基板２０の下側には第２絶縁層２２が配置され、この第２絶縁層も第２金属接着パッド２１の境界域を覆っている。この鏡像反転された部分でも、第２接着パッド２１の下側面には円柱状の溝が形成されている。第２金属接着パッド２１の下側でこれらの溝内には、第２接点パッド２３ａ〜２３ｄが形成され（断面図である為、第２接点パッド２３ｃ及び２３ｄは図４に図示されていない）、これら第２接点パッドは、前記第２絶縁層２２から突出している。これらの円柱状の溝のために、第２接点パッド２３ａ〜２３ｄは、隆起したエッジを有する。別のはんだバンプ２４ａ〜２４ｄは、既に第１接点パッド１３ａ〜１３ｄ上にはんだが存在するので省略されている。図３ａの部分と、鏡像反転された部分とを互いにはんだ付けすると、第１接点パッド１３ａ〜１３ｄと、第２接点パッド２３ａ〜２３ｄとが、はんだバンプ１４ａ〜１４ｄの表面張力によって、互いに吸引される。図４は、これら２つの部分が接合される結果、スタンドオフ距離、すなわち接点パッド１３ａ〜１３ｄと接点パッド２３ａ〜２３ｄとの間の距離がＸｉｎとなることを示している。スタンドオフ距離Ｘｉｎがパッド直径Ｄｉｎに直線的に著しく依存するという旧来の見解に反して、図４（及び図５）は、驚いたことに、接点パッド１３ａ〜１３ｄ及び接点パッド２３ａ〜２３ｄの直径が０より大きいにも拘らず、スタンドオフ距離Ｘｉｎが０又はほぼ０であることを示している。   To complete the electronic device 30, this die is flip chip mounted on a support substrate. A portion of this support substrate is shown in FIG. FIG. 4 shows a configuration in which the part of FIG. 3a and the same mirror-inverted part are soldered to one another. The mirror-inverted portion has a second substrate 20, which has a second metal bond pad 21 on its second surface. A second insulating layer 22 is disposed below the second substrate 20, and the second insulating layer also covers the boundary area of the second metal bonding pad 21. A cylindrical groove is formed on the lower surface of the second adhesive pad 21 even in the mirror-inverted portion. Second contact pads 23a-23d are formed in these grooves below the second metal adhesive pad 21 (the second contact pads 23c and 23d are not shown in FIG. 4 because they are cross sectional views). The second contact pads protrude from the second insulating layer 22. Because of these cylindrical grooves, the second contact pads 23a-23d have raised edges. The other solder bumps 24a-24d are omitted because solder is already present on the first contact pads 13a-13d. When the portion of FIG. 3a and the mirror-inverted portion are soldered to each other, the first contact pads 13a to 13d and the second contact pads 23a to 23d are attracted to each other by the surface tension of the solder bumps 14a to 14d. Ru. FIG. 4 shows that as a result of these two parts being joined, the standoff distance, ie the distance between the contact pads 13a-13d and the contact pads 23a-23d, is Xin. Contrary to the old view that the standoff distance Xin is significantly dependent linearly on the pad diameter Din, FIG. 4 (and FIG. 5) surprisingly shows the diameter of the contact pads 13a-13d and the contact pads 23a-23d. Indicates that the standoff distance Xin is zero or almost zero, even though is greater than zero.

はんだバンプ１４ａ〜１４ｄ及び４４の高さは、パッドの直径Ｄｉｎだけに依存するのではなく、接点パッド１３ａ〜１３ｄ、１４ａ〜１４ｄ、４３及び４４の形状にも依存する。図６は、多角形形状、より正確に言うと五角形形状とした第１接点パッド７３の一例を示す。この第１接点パッド７３は、一例であることに留意しなければならない。従って、第１接点パッド７３に対しては種々の形状が考えられ、例えば、三角形、方形（特に正方形）、六角形及び八角形が考えられる。更にまた、例えば、楕円形、長円形、インゲン豆形の形状が可能である。図６は、このような第１接点パッド７３が最大平面伸張長さＤｉｎと最小平面伸張長さｄｉｎを有することを示し、これらの長さは、２０μｍ〜５μｍの範囲とするのが好ましい。   The heights of the solder bumps 14a-14d and 44 depend not only on the pad diameter Din, but also on the shapes of the contact pads 13a to 13d, 14a to 14d, 43 and 44. FIG. 6 shows an example of a first contact pad 73 which has a polygonal shape, more precisely a pentagonal shape. It should be noted that this first contact pad 73 is an example. Therefore, various shapes can be considered for the first contact pad 73, and for example, triangles, squares (especially squares), hexagons and octagons can be considered. Furthermore, for example, oval, oval and kidney-shaped shapes are possible. FIG. 6 shows that such first contact pads 73 have a maximum planar extension length Din and a minimum planar extension length din, which are preferably in the range of 20 μm to 5 μm.

複数の第１接点パッド１３ａ〜１３ｄが１つの電気接点を形成することは、必須ではないことに留意すべきである。本発明は実際には、１つの第１接点パッド１３ａ〜１３ｄが電気接点を形成する場合にも適用しうる。更にまた、第１接点パッド１３ａ〜１３ｄを、ＵＢＭ処理によって製造するか又はＵＢＭのように形成することは、必須ではない。むしろ、第１接点パッド１３ａ〜１３ｄを、第１基板１０の第１表面上の平坦体にしたり、第１基板内に埋め込んだりしたりすることができる。   It should be noted that it is not essential for the plurality of first contact pads 13a-13d to form one electrical contact. The present invention is practically applicable to the case where one first contact pad 13a-13d forms an electrical contact. Furthermore, it is not essential for the first contact pads 13a-13d to be manufactured by UBM processing or to be formed like a UBM. Rather, the first contact pads 13a-13d can be planarized on the first surface of the first substrate 10 or embedded in the first substrate.

更に、上述した実施例は本発明を制限するものではなく、当業者は、請求の範囲に規定された本発明の範囲を逸脱することなく、多くの変形を施すことができることに留意すべきである。複数の手段を列挙しているデバイスの請求項においては、これらの手段の幾つかを１つのハードウェア装置により構成することができる。互いに異なる従属請求項に述べた手段は、これらの手段を組み合わせて有利に利用できないということを意味するものではない。   Furthermore, it should be noted that the above-mentioned embodiments do not limit the present invention, and a person skilled in the art can make many modifications without departing from the scope of the present invention defined in the claims. is there. In the device claim enumerating several means, several of these means can be embodied by one hardware device. The measures recited in mutually different dependent claims do not indicate that a combination of these measures can not be used to advantage.

図１ａは、従来技術の基板の断面図である。FIG. 1a is a cross-sectional view of a prior art substrate. 図１ｂは、図１ａの基板の頂面図である。FIG. 1b is a top view of the substrate of FIG. 1a. 図２は、従来技術の電子デバイスの断面図である。FIG. 2 is a cross-sectional view of a prior art electronic device. 図３ａは、本発明の基板の断面図である。FIG. 3a is a cross-sectional view of the substrate of the present invention. 図３ｂは、図３ａの基板の頂面図である。Figure 3b is a top view of the substrate of Figure 3a. 図４は、本発明の電子デバイスの断面図である。FIG. 4 is a cross-sectional view of the electronic device of the present invention. 図５は、パッドの直径及びバンプ高さ間の関係と、パッドの直径及びスタンドオフ距離間の関係とを示す線図である。FIG. 5 is a diagram showing the relationship between pad diameter and bump height and the relationship between pad diameter and standoff distance. 図６は、五角形の形態の接点パッドを示す線図である。FIG. 6 is a diagram showing a contact pad in the form of a pentagon.

Claims (13)

絶縁領域によって互いに分離された複数の第１金属接点パッドを有する第１表面を具える基板であって、これら第１接点パッドは、他の基板の第２表面上の第２接点パッドにはんだ付けされるべきものであり、前記基板上の前記第１接点パッドとこれに対応する前記他の基板上の第２接点パッドとが互いに対向するようになっている当該基板において、前記第１表面に対する前記第１接点パッドの最大平面伸張長さが２０μｍを超えないようになっている基板。   A substrate comprising a first surface having a plurality of first metal contact pads separated from one another by an insulating region, wherein the first contact pads are soldered to the second contact pads on the second surface of the other substrate The first contact pad on the substrate and the corresponding second contact pad on the other substrate are opposed to each other with respect to the first surface. A substrate in which the maximum planar extension length of the first contact pad does not exceed 20 μm. 請求項１に記載の基板において、前記第１表面に対する前記第１接点パッドの最小平面伸張長さが５μｍより短くならないようにした基板。   The substrate according to claim 1, wherein the minimum planar extension length of the first contact pad with respect to the first surface is not shorter than 5 μm. 請求項１に記載の基板において、前記第１接点パッドが隆起エッジを有している基板。   The substrate of claim 1, wherein the first contact pad comprises a raised edge. 請求項１に記載の基板において、前記第１接点パッドと前記第１表面との間に金属接着パッドが配置され、この金属接着パッドはその境界域において絶縁層によって部分的に覆われており、前記第１接点パッドはこの絶縁層から突出している基板。   A substrate according to claim 1, wherein a metal bond pad is arranged between the first contact pad and the first surface, the metal bond pad being partially covered by an insulating layer in its border area, The first contact pad protrudes from the insulating layer. 請求項１に記載の基板において、前記第１接点パッド上にはんだバンプを具えている基板。   The substrate of claim 1 comprising solder bumps on the first contact pads. 請求項１に記載の基板において、前記はんだバンプが、低融点はんだから成っている基板。   The substrate according to claim 1, wherein the solder bumps comprise low melting point solder. 請求項１〜６のいずれか一項に記載の基板において、前記第１金属接点パッドが、互いに隣接して電気接点を形成している基板。   7. The substrate according to any one of the preceding claims, wherein the first metal contact pads are adjacent to one another to form electrical contacts. 第１金属接点パッドを有する第１表面を具えた第１基板と、第２金属接点パッドを有する第２表面を具えた第２基板とが設けられた電子デバイスであって、前記第１接点パッドと前記第２接点パッドとが互いにはんだ付けされており、第１基板上の第１接点パッドと、これに対応する第２基板上の第２接点パッドとが互いに対向している当該電子デバイスにおいて、前記第１及び第２表面に対する前記第１及び第２接点パッドの最大平面伸張長さが２０μｍを超えないようになっている電子デバイス。   An electronic device provided with a first substrate comprising a first surface having a first metal contact pad and a second substrate comprising a second surface having a second metal contact pad, said first contact pad And the second contact pad are soldered to each other, wherein the first contact pad on the first substrate and the corresponding second contact pad on the second substrate face each other. Electronic device, wherein the maximum planar extension length of the first and second contact pads with respect to the first and second surfaces does not exceed 20 μm. アンダーバンプメタライゼーション処理により、第１金属接点パッドを有する第１表面を具えた基板を製造する基板の製造方法において、前記第１表面に対する前記第１接点パッドの最大平面伸張長さが２０μｍを超えないようにする基板の製造方法。   A method of manufacturing a substrate for manufacturing a substrate comprising a first surface having a first metal contact pad by underbump metallization, wherein the maximum planar extension length of said first contact pad to said first surface exceeds 20 μm. How to make the substrate not to. 請求項９に記載の基板の製造方法において、前記第１表面に対する前記第１接点パッドの最小平面伸張長さが５μｍより短くならないようにする基板の製造方法。   The method of manufacturing a substrate according to claim 9, wherein the minimum planar extension length of the first contact pad with respect to the first surface is not shorter than 5 μm. 請求項９に記載の基板の製造方法において、前記第１接点パッド上のはんだバンプを、はんだ浸漬バンピング処理を用いて製造する基板の製造方法。   10. The method of manufacturing a substrate according to claim 9, wherein the solder bumps on the first contact pads are manufactured using a solder dip bumping process. 請求項９に記載の基板の製造方法において、前記はんだバンプを製造するのに、低融点はんだを用いる基板の製造方法。   10. The method of manufacturing a substrate according to claim 9, wherein a low melting point solder is used to manufacture the solder bumps. 請求項９〜１２のいずれか一項に記載の基板の製造方法において、前記第１金属接点パッドを互いに隣接させて電気接点を形成する基板の製造方法。   The method of manufacturing a substrate according to any one of claims 9 to 12, wherein the first metal contact pads are adjacent to each other to form an electrical contact.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009302539A (en) * 2008-06-16 2009-12-24 Intel Corp Processing method for low profile solder grid array, device, and computer system

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101754579B (en) * 2009-11-16 2012-02-22 华为终端有限公司 Castle-type module and terminal equipment
US8809123B2 (en) * 2012-06-05 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Three dimensional integrated circuit structures and hybrid bonding methods for semiconductor wafers
CN103531562B (en) * 2012-07-04 2016-07-06 颀邦科技股份有限公司 Semiconductor package and lead frame thereof
CN104681530B (en) * 2013-11-26 2017-09-26 日月光半导体制造股份有限公司 Semiconductor structure and its manufacture method
CN106252247B (en) * 2016-09-05 2019-07-05 江苏纳沛斯半导体有限公司 Semiconductor structure and forming method thereof

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB0001918D0 (en) * 2000-01-27 2000-03-22 Marconi Caswell Ltd Flip-chip bonding arrangement
US6596618B1 (en) * 2000-12-08 2003-07-22 Altera Corporation Increased solder-bump height for improved flip-chip bonding and reliability
US20020093106A1 (en) * 2001-01-17 2002-07-18 Ashok Krishnamoorthy Bonding pad for flip-chip fabrication
US6862378B2 (en) * 2002-10-24 2005-03-01 Triquint Technology Holding Co. Silicon-based high speed optical wiring board

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009302539A (en) * 2008-06-16 2009-12-24 Intel Corp Processing method for low profile solder grid array, device, and computer system
JP2012151487A (en) * 2008-06-16 2012-08-09 Intel Corp Processing method and apparatus for flat solder grid array and computer system

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