JP2008311673A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an n-channel field effect transistor and a p-channel field effect transistor, the n-channel field effect transistor and the p-channel field effect transistor have excellent drain current property. <P>SOLUTION: In the n-channel field effect transistor 10 and the p-channel field effect transistor 30, the stress control film 19 covering the gate electrode 15 of the n-channel field effect transistor 10 uses a film having film stress in a tension stress side. A stress control film 39 covering the gate electrode 35 of the p-channel field effect transistor 30 uses a film having film stress in a compress stress side than that of the stress control film 19 of the n-channel field effect transistor 10 so that drain currents both in the n-channel and the p-channel field effect transistors are improved, thus resulting in the improvement of whole properties of the transistors. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a complementary field effect transistor composed of an n-channel field effect transistor and a p-channel field effect transistor.

  In recent years, with the development of information communication equipment, the processing capability required for semiconductor devices such as LSIs has become stricter year by year, and the operation speed of transistors has been increased. In particular, a complementary field effect transistor composed of an n-channel field effect transistor and a p-channel field effect transistor is widely used because of its low power consumption. Has been supported by advances in lithography technology for processing semiconductor devices.

  However, recently, the required minimum processing dimension (minimum processing dimension of the gate) has become lower than the wavelength level of light used for lithography, and further miniaturization processing is becoming difficult.

  Therefore, using the fact that the mobility (effective mass) of electrons changes when the silicon crystal is distorted, Japanese Patent Application Laid-Open No. 11-340337 (Patent Document 1) uses silicon as a base film for forming a field effect transistor. A method has been disclosed in which silicon germanium having a larger lattice constant is used and a silicon layer is epitaxially grown thereon, thereby straining the silicon serving as a channel portion to increase mobility and increase the speed of the transistor. Yes.

Japanese Patent Laid-Open No. 6-232170 (Patent Document 2) discloses a method of controlling the rise delay of the drain current by controlling the stress of the gate electrode of the field effect transistor.
Japanese Patent Laid-Open No. 11-340337 Japanese Patent Laid-Open No. 6-232170

  In recent semiconductor devices, the operation speed of field effect transistors has been increased, and as one of the means for that purpose, a silicon germanium material having a lattice constant larger than that of silicon is used as a silicon base of a channel portion. A method of straining silicon to increase mobility has been studied.

  However, as disclosed in JP-A-11-340337, when materials having different crystal lattice constants are epitaxially grown so as to be lattice-matched, the strain energy generated in the crystal is large. In the manufacturing process of semiconductor devices such as LSI and the problem that dislocations occur, it is not easy to put to practical use an increase in cost due to the introduction of a new manufacturing device by introducing an uncommon material such as silicon germanium.

  Complementary field effect transistors are composed of n-channel field effect transistors that use electrons as carriers and p-channel field effect transistors that use holes as carriers. To increase the speed of semiconductor devices, It is preferable to increase the speed of each of the n-channel type and the p-channel type.

  Further, in Japanese Patent Laid-Open No. 6-232170, the target transistor is a transistor made of a compound semiconductor, and a transistor made on a silicon substrate mainly used for LSI and DRAM is considered. In addition, the field effect transistor is only n-channel type, and the stress control direction is only considered uniaxially.

  As described above, in a semiconductor device such as an LSI, it is essential to increase the speed of the transistor. However, the lithography technique is approaching the limit, and improvement of drain current by a method other than miniaturization is also being studied. However, there were crystal defects and cost problems due to the introduction of new manufacturing equipment.

  An object of the present invention is to effectively provide a semiconductor device having an n-channel field effect transistor and a p-channel field effect transistor, which are excellent in drain current characteristics, in a semiconductor device having an n-channel field effect transistor and a p-channel field effect transistor. Is to realize.

  The inventors of the present application measured the stress dependence of the drain current of the field effect transistor, and clarified that the stress dependence is different between the n-channel field effect transistor and the p-channel field effect transistor.

In this specification, silicon nitride is indicated as SiN, and silicon oxide is indicated as SiO ₂ .

  FIG. 2 is a graph showing the experimental results of the stress dependence of the drain current of the n-channel field effect transistor and the p-channel field effect transistor.

  The result shown in FIG. 2 is obtained by conducting a stress load experiment on a transistor formed on a Si (001) plane so that a drain current flows parallel to the <110> axis. The evaluated field effect transistor has a gate length of 0.2 μm. The stress direction is uniaxial stress in the channel plane parallel to the drain current flowing through the channel of the field effect transistor (stress parallel to the channel) and uniaxial stress in the channel plane perpendicular to the drain current (channel). The stress sign is positive for tensile stress and negative for compressive stress.

  In FIG. 2, in the case of an n-channel field effect transistor, the drain current increases with respect to the tensile stress (about 4% / 100 MPa for stress parallel to the channel and about 2% / 100 MPa for stress perpendicular to the channel).

  On the other hand, in the case of a p-channel field effect transistor, the drain current increases in the direction perpendicular to the channel (about 4% / 100 MPa), but the drain current decreases in the direction parallel to the channel. (About 7% / 100 MPa).

  Further, from this result, in the case of biaxial stress in the channel plane, in the n-channel field effect transistor, the drain current increases with respect to the tensile stress regardless of the absolute value, and conversely, the p-channel field effect transistor. Then, it is considered that when biaxial stress having the same absolute value is applied, it increases with respect to compressive stress.

  In the discussion within elastic deformation, stress and strain are proportional. Therefore, in the above experimental results, for example, when a tensile stress is applied in parallel to the channel to the n-channel field effect transistor, the drain current increases because the crystal lattice of silicon constituting the channel Compared to the previous case, it is considered that the electron mobility increased because of the distortion in the parallel tensile direction in the channel plane.

  That is, the inventors of the present application clearly show that the drain current characteristics of the n-channel field effect transistor and the p-channel field effect transistor depend on the direction of strain generated in the silicon crystal lattice constituting the channel and the absolute value. I made it. The strain generated in the silicon crystal can also be measured by TEM, electron diffraction, Raman spectroscopy, or the like.

  By the way, in a multilayer structure such as a transistor, a thermal stress due to a difference in linear expansion coefficient between materials, an intrinsic stress due to a difference in lattice constant or a film shrinkage during crystallization, and the like remain in the structure. Stress is generated. In general, field effect transistors, which are becoming more and more miniaturized year by year, represent generations by their gate lengths.

  The inventors of the present application conduct stress analysis of the field effect transistor structure, and it is clear that as the gate processing dimension is reduced, the stress generated in the structure increases due to the miniaturization of the structure and the use of new materials. I made it. In particular, in a field effect transistor having a gate length of 0.1 μm, the stress is caused by oxidation-induced stress due to shallow trench isolation (STI), silicide reaction-induced stress, crystallization stress of polycrystalline silicon, etc. Become.

FIG. 24 is a graph showing the result of stress analysis of the channel portion stress of the field effect transistor of each generation of gate length by the finite element method. In FIG. 24, in the 2 μm generation transistor having a relatively large gate length, the stress generated in the channel portion under the gate is low, but when the transistor has a gate length of 0.25 μm or less, the stress rapidly increases. The 1 μm generation is about 3 times the 2 μm generation. Studies have been made on the influence of stress generated in a field effect transistor on transistor characteristics. For example, research has been conducted on the stress dependence of transconductance (Gm), which is one of the characteristics of field effect transistors (Akemi Hamada, et al., IEEE Trans. Electron Devices, vol. 38, No. 4, pp.895-90
0, 1991).

  However, conventionally, it has not been a problem that the characteristics of a field effect transistor fluctuate due to stress. This is presumably because the stress generated in the transistor structure was small in the field effect transistor before 0.25 μm, that is, 0.25 μm or more, as shown in FIG.

  Furthermore, it is considered that the sensitivity of the transistor itself to the stress was low.

  FIG. 25 shows the experimental results (gates) of the stress dependence of transconductance Gm in the above-mentioned literature (Akemi Hamada, et al., IEEE Trans. Electron Devices, vol. 38, No. 4, pp. 895-900, 1991). (Length: 2 μm) and the present inventors' Gm stress dependence experimental results (gate length: 0.2 μm).

  Note that the comparison in FIG. 25 was performed with a stress load in the direction parallel to the channel for an n-channel field effect transistor. A transistor having a gate length of 0.2 μm has a Gm dependency on stress that is about four times as large as that of a transistor having a gate length of 2 μm. That is, as the generation of transistors progresses, the sensitivity of transistor characteristics to stress increases.

  According to the stress analysis, the stress distribution in the substrate depth direction formed in the channel portion of the Si substrate of the field effect transistor forms a stress concentration field in the vicinity of the gate electrode. The formation region of the diffusion layer of the 0.1 μm generation transistor having a small gate length is formed in a shallow region near the substrate surface as compared with a conventional transistor having a large gate length. As a result, in the 0.1 μm generation transistor, it is considered that the element operation region is easily affected by stress.

  Therefore, the inventors of the present invention conduct a stress analysis by a finite element method for the field effect transistor structure, and the influence of the material constituting the field effect transistor and the surrounding material on the stress of the channel portion through which the drain current flows. Sensitivity analysis was performed.

  As a result, the inventors of the present application have clarified that the film including the gate electrode from the upper surface, the silicide film, the gate electrode, and the sidewall have a great influence on the stress of the channel portion.

  According to the present invention, for example, in order to bring the stress of the channel portion to the tensile stress side, the increase in the intrinsic stress of the SiN film covering the gate electrode, the increase in the film thickness, the increase in the silicide film thickness, or the gate electrode It was clarified that this can be achieved by increasing the intrinsic stress of the film or decreasing the stress caused by oxidation of STI (FIGS. 3 to 7).

  By the way, the inventors of the present application also show that the film stress of SiN has a relationship as shown in FIG. 8 to be described later, and the stress is high in the case of a film having a large etching rate. I made it.

  In view of the above matters, it is preferable to configure the following state.

  In a semiconductor device having an n-channel field effect transistor and a p-channel field effect transistor formed on a substrate, the residual in the direction along the direction in which the drain current of the channel portion of the n-channel field effect transistor flows The stress is larger on the tensile stress side than the residual stress in the direction along the direction in which the drain current flows in the channel portion of the p-channel field effect transistor.

  Alternatively, in a semiconductor device having an n-channel field effect transistor and a p-channel field effect transistor formed on a substrate, a direction along a direction in which a drain current flows in the channel portion of the n-channel field effect transistor. Is a tensile stress, and the residual stress in the direction along the direction in which the drain current flows in the channel portion of the p-channel field effect transistor is a compressive stress.

  As a result, the drain current characteristics of both the n-channel type and the p-channel type can be improved, so that a semiconductor device having excellent overall performance can be realized.

  In addition, the semiconductor device of the present invention can realize a highly reliable semiconductor device in which defects and the like are suppressed.

  Alternatively, in a semiconductor device having an n-channel field effect transistor and a p-channel field effect transistor formed on a substrate, each of the transistors includes a gate electrode and reaches a position adjacent to a source / drain region. The insulating film of the n-channel field effect transistor has a tensile stress greater than that of the insulating film of the p-channel field effect transistor.

  The adjacent position refers to, for example, a state where the insulating film is over the source / drain regions. If a silicide region is formed in the source / drain region, it can be formed so as to cover that region.

  Specifically, in order to take one of the above forms, it is preferable to take the following configuration.

  (1) In a semiconductor device having an n-channel field effect transistor and a p-channel field effect transistor formed on a substrate, each of the transistors includes a gate electrode and is adjacent to a source / drain region. The insulating film is mainly composed of silicon nitride, and the film thickness of the insulating film of the n-channel field effect transistor and the film thickness of the insulating film of the p-channel field effect transistor are: , Characterized by differences.

  As a result, the current characteristics of the semiconductor device including the n-channel field effect transistor and the p-channel field effect transistor can be improved as a whole. Further, with the above configuration, even if the adjustment of the insulating film is changed, the current characteristics are not affected, so that the above effect can be achieved effectively.

  For example, the insulating film has a higher tensile stress than the insulating film of the p-channel field effect transistor. For example, when the insulating film of the n-channel field effect transistor and the p-channel field effect transistor has a tensile stress, the insulating film of the n-channel field effect transistor is used as the insulating film of the p-channel field effect transistor. Make it thicker. For example, when the insulating film of the n-channel field effect transistor and the p-channel field effect transistor has a compressive stress, the insulating film of the n-channel field effect transistor is used as the insulating film of the p-channel field effect transistor. Thinner than the insulating film. The insulating film thickness may be compared based on, for example, an average film thickness in a semiconductor device.

  Alternatively, in the semiconductor device, the insulating film contains silicon nitride as a main component, and the insulating film of the p-channel field effect transistor includes silicon (Si), nitrogen (N), oxygen (O), and argon (Ar). , Helium (He), and germanium (Ge) are contained in a larger amount than the insulating film of the n-channel field effect transistor.

  (2) Preferably, in the above (1), the insulating film is mainly composed of silicon nitride, and the area of the portion extending adjacent to the source / drain region of the insulating film is the n-channel field effect transistor. The insulating film differs from the insulating film of the p-channel field effect transistor.

  Instead of the area, the length of the source / drain region may be compared.

  Specifically, for example, when the insulating film of the n-channel field effect transistor and the p-channel field effect transistor has a residual tensile stress, the area of the insulating film of the n-channel field effect transistor is set as the p-channel. Larger than the area of the insulating film of the p-type field effect transistor.

  Further, for example, when the insulating film of the n-channel field effect transistor and the p-channel field effect transistor has a compressive stress, the area of the insulating film of the n-channel field effect transistor is set to the p-channel field effect transistor. The area of the insulating film is made smaller. The areas may be compared based on, for example, an average area in a semiconductor device.

  Note that, instead of the above area, the lengths of the insulating film in the direction crossing the source to the drain may be compared. Specifically, for example, when the insulating film of the n-channel field effect transistor and the p-channel field effect transistor has a tensile stress, the length of the insulating film of the n-channel field effect transistor is set to the p-channel. Longer than the length of the insulating film of the field effect transistor.

  For example, when the insulating film of the n-channel field effect transistor and the p-channel field effect transistor has a compressive stress, the length of the insulating film of the n-channel field effect transistor is set to the p-channel field effect. The length is shorter than the length of the insulating film of the transistor.

  As a result, the current characteristics of the semiconductor device including the n-channel field effect transistor and the p-channel field effect transistor can be improved as a whole. Further, with the above configuration, even if the adjustment of the insulating film is changed, the current characteristics are not affected, so that the above effect can be achieved effectively.

  (3) In a semiconductor device having an n-channel field effect transistor and a p-channel field effect transistor formed on a substrate, a silicide region is formed in the source or drain region of each of the transistors, The thickness of the silicide region of the n-channel field effect transistor is larger than the thickness of the silicide region of the p-channel field effect transistor.

  The film thicknesses may be compared based on the average film thickness in the semiconductor device.

  Thereby, in addition to the improvement effect as a whole as described above, the above-described configuration can effectively achieve the above-described effect because the current characteristic is not affected even by the adjustment change of the insulating film.

(4) Preferably, in (3) above, the main component of the silicide region is cobalt silicide (CoSi ₂ ), titanium silicide (TiSi ₂ ), or nickel silicide.

  (5) As another form, in a semiconductor device having an n-channel field effect transistor and a p-channel field effect transistor formed on a substrate, the gate electrode of the n-channel field effect transistor is The compressive film stress is larger than that of the gate electrode of the p-channel field effect transistor.

  (6) In a semiconductor device having an n-channel field effect transistor and a p-channel field effect transistor formed on a substrate, the impurity contained in the gate electrode of the n-channel field effect transistor is the silicon Does the impurity contained in the gate electrode of the p-channel field effect transistor have a concentration gradient in the direction perpendicular to the main plane of the substrate and within the measurement limit in the direction perpendicular to the main plane of the silicon substrate? Alternatively, it has a smaller gradient than the concentration gradient in the gate electrode of the n-channel field effect transistor.

  For example, the impurity concentration of the gate electrode of an n-channel field effect transistor has a concentration gradient in the direction perpendicular to the main plane of the silicon substrate, and the impurity concentration distribution of the gate electrode of the p-channel field effect transistor is that of the main plane of the silicon substrate. Uniform in the vertical direction.

  (7) In a semiconductor device having an n-channel field effect transistor and a p-channel field effect transistor formed on a substrate, an average crystal grain size of the gate electrode of the n-channel field effect transistor is p It is smaller than the average crystal grain size of the gate electrode of the channel type field effect transistor.

  As a result, the current characteristics of the semiconductor device including the n-channel field effect transistor and the p-channel field effect transistor can be improved as a whole. Furthermore, since the stress is controlled by adjusting the crystal grain size of the gate electrode located immediately above the channel portion with the above configuration, the stress can be effectively applied to the channel portion.

  (8) In a semiconductor device having an n-channel field effect transistor, a p-channel field effect transistor, and element isolation means for electrically isolating adjacent transistor elements formed on a substrate, the n-channel type The distance between the channel portion of the field effect transistor and the element isolation means is larger than the distance between the channel portion of the p-channel field effect transistor and the element isolation means.

  As a result, the current characteristics of the semiconductor device including the n-channel field effect transistor and the p-channel field effect transistor can be improved as a whole. Furthermore, the above-described effect can be easily and effectively achieved by adjusting the mask pattern.

  (9) In a semiconductor device having an n-channel field effect transistor and a p-channel field effect transistor formed on a substrate, Raman spectroscopy when a laser is applied to the channel portion of the n-channel field effect transistor. Is smaller than the Raman shift of Raman spectroscopy when the channel portion of the p-channel field effect transistor is irradiated with laser.

  For example, the crystal lattice spacing when the channel portion of an n-channel field effect transistor is observed with a TEM is wider than the crystal lattice spacing when the channel portion of a p-channel field effect transistor is observed with a TEM.

  As each of the above samples, it is preferable to use a sample formed along a direction crossing the source / drain.

  (10) Preferably, in (1), the insulating film is mainly composed of silicon nitride, the etching rate of the insulating film of the n-channel field effect transistor, and the insulating film of the p-channel field effect transistor. This is different from the etching rate.

  For example, the etching rate of the insulating film on the n-channel field effect transistor side is lower than the etching rate of the insulating film of the p-channel field effect transistor.

  (11) In a method of manufacturing a semiconductor device having an n-channel field effect transistor and a p-channel field effect transistor formed on a substrate, a step of forming an element isolation structure on the substrate, and the element isolation Forming a gate electrode of an n-channel field effect transistor and a gate electrode of a p-channel field effect transistor in a region separated by the structure; forming an insulating layer covering the gate electrode on the gate electrode; And a step of leaving a tensile stress in the channel portion of the n-channel field effect transistor from the channel portion of the p-channel field effect transistor in a direction connecting the source and the drain.

  As another form, in a method of manufacturing a semiconductor device having an n-channel field effect transistor and a p-channel field effect transistor formed on a substrate, a step of forming an element isolation structure on the substrate Forming a gate electrode of an n-channel field effect transistor and a gate electrode of a p-channel field effect transistor in a region isolated by the element isolation structure; and an insulating layer covering the gate electrode on the gate electrode And a step of causing the insulating layer of the n-channel field effect transistor to contain at least one of silicon, nitrogen, oxygen, argon, helium, and germanium more than the insulating layer of the n-channel field effect transistor. .

  In addition, one insulating film may be thinned / thickened by etching. Further, after forming the gate electrode, the impurity may be introduced into the gate electrode of the n-channel field effect transistor. You may have the process of making the particle size of the electrode of an n channel type field effect transistor smaller than the particle size of the electrode of a p channel type field effect transistor.

  For example, in detail, when an insulating film having tensile stress is formed on the n-channel field effect transistor and the p-channel field effect transistor, the first p-channel field effect transistor and the first channel The insulating film formed on the first or second p-channel field effect transistor in a region located between the second p-channel field effect transistor adjacent to the one p-channel field effect transistor The insulating film thinner than the thickness is formed, or etching is performed so that the insulating film is not installed.

  When an insulating film having a compressive stress is formed on the n-channel field effect transistor and the p-channel field effect transistor, a first n-channel type corresponding to the first p-channel field effect transistor is formed. In a region located between the field effect transistor and the second n-channel field effect transistor corresponding to the second p-channel field effect transistor, the first p-channel field effect transistor and the first p-channel field effect transistor The insulating film thinner than the insulating film formed in a region located between the second p-channel field effect transistor adjacent to the p-channel field effect transistor is formed, or the insulating film is not installed Etch to be

  Alternatively, in a semiconductor device having an n-channel field effect transistor and a p-channel field effect transistor formed on a substrate, the insulating film adjacent to the side surface in the longitudinal direction of the gate electrode of the n-channel field effect transistor The film quality is different from that of the insulating film adjacent to the side surface in the longitudinal direction of the gate electrode of the p-channel field effect transistor.

  Alternatively, in a semiconductor device having an n-channel field effect transistor and a p-channel field effect transistor formed on a substrate, the insulating film adjacent to the side surface in the longitudinal direction of the gate electrode of the n-channel field effect transistor The film stress is larger on the tensile stress side than the film stress of the insulating film adjacent to the side surface in the longitudinal direction of the gate electrode of the p-channel field effect transistor.

  Preferably, in the above, the insulating film contains silicon nitride as a main component.

  (12) In a semiconductor device having an n-channel field effect transistor and a p-channel field effect transistor formed on a substrate, the gate electrode of each transistor is included and the region adjacent to the source / drain region When the film stress of the extended insulating film is a tensile stress, the Young's modulus of the insulating film adjacent to the side surface in the longitudinal direction of the gate electrode is smaller in the p-channel field effect transistor than in the n-channel field effect transistor, When the film stress of the insulating film including the gate electrode of each transistor and extending to the region adjacent to the source / drain region is compressive stress, the Young's modulus of the insulating film adjacent to the side surface in the longitudinal direction of the gate electrode is The p-channel field effect transistor is larger than the n-channel field effect transistor.

  As a result, the current characteristics of the semiconductor device including the n-channel field effect transistor and the p-channel field effect transistor can be improved as a whole. Furthermore, even with the above configuration, the above effect can be effectively achieved because the electrical characteristics are not affected.

  (13) Preferably, in the above (12), the insulating film having a large Young's modulus of the insulating film adjacent to the side surface in the longitudinal direction of the gate electrode is mainly composed of silicon nitride and has a small Young's modulus. The material is mainly composed of silicon oxide.

  (14) In a semiconductor device having an n-channel field effect transistor and a p-channel field effect transistor formed on a substrate, the semiconductor device includes a plurality of the n-channel field effect transistor and the p-channel field effect transistor, An insulating film having a tensile stress is formed on the n-channel field effect transistor and the p-channel field effect transistor, so that the first p-channel field effect transistor and the first p-channel field effect transistor The insulating film thinner than the insulating film formed on the first or second p-channel field effect transistor is formed in a region located between adjacent second p-channel field effect transistors. Or the insulating film is not installed.

  The semiconductor device includes an n-channel field effect transistor region in which the n-channel field effect transistors are disposed adjacent to each other, and a p-channel field effect transistor region in which the p-channel field effect transistors are disposed adjacent to each other. It is preferable.

  In other words, a first insulating film having a tensile stress (for example, the stress control film) is formed on the gate electrode of the n-channel field effect transistor and the gate electrode of the p-channel field effect transistor. A region located between one p-channel field effect transistor and a second p-channel field effect transistor adjacent to the first p-channel field effect transistor is thinner than the thickness of the first insulating film The first insulating film is formed or the first insulating film is not installed. A second insulating film (for example, an interlayer insulating film) having a different component can be formed on the first insulating film.

  In addition, a field region having an insulating layer embedded in the semiconductor main surface, first to fourth active regions each surrounded by the field region, and first and second active regions are formed. The first and second p-channel field effect transistors, the third and fourth n-channel field effect transistors formed in the third and fourth active regions, and the first to fourth The first and second actives include the gate electrode and an insulating film extending in a position adjacent to the source / drain region and having a film stress of tensile stress. The drain currents of the first and second transistors are arranged adjacent to each other through the field so that the directions in which the drain currents mainly flow are the same, and the third and fourth actives are the first and second transistors. Drain electricity Arranged to be adjacent to each other through the field so that the directions of flow mainly coincide with each other, the insulating film includes the first to fourth transistors, and is sandwiched between the first and second actives. In the field region, a slit is provided.

  (15) In a semiconductor device having an n-channel field effect transistor and a p-channel field effect transistor formed on a substrate, the semiconductor device includes a plurality of the n-channel field effect transistor and the p-channel field effect transistor, An insulating film having a tensile stress is formed on the n-channel field effect transistor and the p-channel field effect transistor, so that the first p-channel field effect transistor and the first p-channel field effect transistor In a region located between the adjacent second p-channel field effect transistors, the first n-channel field effect transistor corresponding to the first p-channel field effect transistor and the second p-channel The second n-channel field effect transistor corresponding to the type field effect transistor Thin the insulating film from the insulating film formed on a region located is either formed or a non-installation of the insulation film between the.

  The insulating film corresponds to, for example, a stress control film. An interlayer insulating film may be formed on the stress control film.

  Alternatively, in a semiconductor device having an n-channel field effect transistor and a p-channel field effect transistor formed on a substrate, the semiconductor device includes a plurality of the n-channel field effect transistors and the p-channel field effect transistors, An insulating film having tensile stress is formed on the n-channel field effect transistor and the p-channel field effect transistor, and is adjacent to the first p-channel field effect transistor and the first p-channel field effect transistor. The region located between the matching second p-channel field effect transistors includes a first n-channel type corresponding to the first p-channel field effect transistor and the first p-channel field effect transistor. The thickness of the insulating film formed in the region located between the field effect transistors Or thin the insulating film is formed, or to the insulating film and non-installation.

  In any of the above embodiments, the active region in which the first p-channel field effect transistor is disposed and the active region in which the corresponding first n-channel field effect transistor is disposed are also provided. The stress control film can be formed. The stress control film may be disposed on the n-channel field effect transistor.

  Alternatively, in the region located between the first p-channel field effect transistor and the second p-channel field effect transistor, the insulating film (above the first n-channel field effect transistor) For example, the stress control film thinner than the thickness of the stress control film) is formed.

  Alternatively, in the region intersecting (for example, orthogonal to) the longitudinal direction of the gate electrode of the first p-channel field effect transistor, the insulating film formed on the first n-channel field effect transistor (for example, the above-mentioned The insulating film thinner than the stress control film) can be formed, or the insulating film can be omitted. Alternatively, the first p-channel field effect transistor is adjacent to an active region where the first p-channel field effect transistor is formed in a direction intersecting (for example, orthogonal to) the longitudinal direction of the gate electrode of the first p-channel field effect transistor. The field region to be processed is an active region in which the first n-channel field effect transistor is formed in a direction intersecting (for example, orthogonal to) the longitudinal direction of the gate electrode of the first n-channel field effect transistor The insulating film that is thinner than the insulating film formed in the field region adjacent to is formed, or the insulating film is not installed.

  Alternatively, in another form, the first p-channel field effect transistor is formed above the first p-channel field effect transistor in a region intersecting (for example, orthogonal to) the longitudinal direction of the gate electrode of the first p-channel field effect transistor. The insulating film thinner than the insulating film (for example, the stress control film) may be formed, or the insulating film may be omitted.

  (16) In a semiconductor device having an n-channel field effect transistor and a p-channel field effect transistor formed on a substrate, the semiconductor device includes a plurality of the n-channel field effect transistor and the p-channel field effect transistor, An insulating film having a compressive stress is formed on the n-channel field effect transistor and the p-channel field effect transistor, and a first n-channel field effect corresponding to the first p-channel field effect transistor is formed. A region located between a transistor and a second n-channel field effect transistor corresponding to the second p-channel field effect transistor includes a first p-channel field effect transistor and the first p-channel A second p-channel field effect transistor adjacent to the p-type field effect transistor; Or thin the insulating film from the insulating film formed on the region located between is formed, or to the insulating film in the non-installation.

  Alternatively, in a region located between the first p-channel field effect transistor and the first n-channel field effect transistor corresponding to the first p-channel field effect transistor, The insulating film thinner than the insulating film formed in a region located between the p-type field effect transistor and the second p-channel field effect transistor adjacent to the first p-channel field effect transistor is formed Alternatively, the insulating film can be omitted.

  Or a field region having an insulating layer embedded in the semiconductor main surface, first to third active regions each surrounded by the field region, and first and second active regions, 1, a second p-channel field effect transistor, a third n-channel field effect transistor formed in the third active region, and the first to third transistors including a gate electrode. And an insulating film extending in a position adjacent to the source / drain region and having a compressive stress as a film stress. The first and second actives are the drains of the first and second transistors. Arranged adjacent to each other through the field so that the directions in which current mainly flows are the same, the insulating film includes the first to third transistors, and is adjacent to the first and second actives. That on the field region, the first, and the direction perpendicular to the drain current flowing direction mainly of the second transistor, the field perimeter area adjacent to the third active, so that the slit is provided.

  Alternatively, in the region located between the first n-channel field effect transistor and the second n-channel field effect transistor, the insulating film (above the first p-channel field effect transistor) For example, the stress control film thinner than the thickness of the stress control film) is formed.

  Alternatively, in the region located in the longitudinal direction of the gate electrode of the first p-channel field effect transistor, the insulating film formed on the first n-channel field effect transistor (for example, the stress control film) The thinner insulating film can be formed, or the insulating film can be omitted. Alternatively, it is a region in a direction intersecting (for example, orthogonal to) the longitudinal direction of the gate electrode of the first n-channel field effect transistor and adjacent to the active region where the first n-channel field effect transistor is formed. The field region is an active region in which the first p-channel field effect transistor is formed in a direction intersecting (for example, orthogonal to) the longitudinal direction of the gate electrode of the first p-channel field effect transistor The insulating film thinner than the insulating film formed in the field region adjacent to is formed, or the insulating film is not installed.

  (17) In the semiconductor device, the insulating film is mainly composed of silicon nitride.

  As a result of investigating known examples, the following related techniques were extracted in order to impose stress on the channel portion, but none of them exhibited the configuration and operational effects of the present invention.

For example, Japanese Patent Laid-Open No. 60-52052 discloses that a channel layer base layer is separately formed with a spinel layer under a p-channel portion and an SiO ₂ layer under an n-channel portion, Japanese Patent Laid-Open No. 7-32122. In Japanese Patent Application Laid-Open No. 10-92947, Japanese Patent Application Laid-Open No. 2000-243854, and Japanese Patent Application Laid-Open No. 2000-160599, a SiGe layer in which an Si layer is arranged with a p-channel as a base and an SiGe layer with an n-channel as a base However, it is disclosed that a base region (a region below a region where a channel current flows (for example, about 5 nm or more from the interface with the gate insulating film) Since the layer is inserted in a region separated in the opposite direction to the film)), if a defect occurs at the end, the electrical characteristics may be affected. In addition, in Japanese Patent Laid-Open Nos. 2000-36567, 2000-36605, and 2001-24468, the device isolation part adjacent to the transistor in the PMOS part is controlled by controlling the oxidation amount of LOCOS. Although it is disclosed that it is disclosed, it is difficult to effectively cope with high integration due to the use of LOCOS, and there is a possibility that the process will be greatly increased.

  According to the present invention, in a semiconductor device having an n-channel field effect transistor and a p-channel field effect transistor, both the n-channel field effect transistor and the p-channel field effect transistor are effective in drain current characteristics. Can be realized.

  Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. 1 to 3, 8 and 31.

  FIG. 1 is a schematic sectional view of a semiconductor device according to a first embodiment of the present invention, FIG. 2 is a diagram showing the stress dependence of drain current of n-channel and p-channel field effect transistors, and FIG. FIG. 8 is a diagram showing the results of stress analysis of the effect of intrinsic stress of the included SiN film on the channel partial stress (stress in the channel plane parallel to the drain current), and FIG. 8 is a diagram showing the etching rate dependence of the SiN film stress. FIG. 31 is a diagram showing an example in which wirings and the like are formed in the semiconductor device shown in FIG.

As shown in FIG. 1, the semiconductor device according to the first embodiment of the present invention includes an n-channel field effect transistor 10 , a p-channel field effect transistor 30 formed on the main surface of the silicon substrate 1, and these transistors. 10 and 30 and stress control insulating films 19 and 39 formed on the upper surface.

  The n-channel field effect transistor includes an n-type source / drain (12, 13) formed in the p-type well 11, a gate insulating film 14, and a gate electrode 15. The upper surface of the gate electrode 15 and the source / drain Silicides 17 and 18 are formed on the top surfaces of the drains (12 and 13). The n-type source / drain is a source region or a drain region indicated by 12 and 13 facing each other with the gate electrode 14 therebetween. The difference between the source and the drain is the difference in which current flows from which direction, and there is no fundamental structural difference. Therefore, in this specification, it is expressed as source / drain (12, 13). The same applies to the p-channel field effect transistor described below and the following.

The p-channel field effect transistor includes p-type source / drain (32, 33) formed in the n-type well 31, a gate insulating film 34, and a gate electrode 35. Silicides 37 and 38 are formed on the top surfaces of the source / drain (32, 33). These transistors are insulated from other transistors by a shallow trench isolation 2 made of silicon oxide (SiO ₂ ) or silicon nitride (SiN).

The gate oxide films 14 and 34 are, for example, a silicon oxide film (SiO ₂ ), a silicon nitride film (SiN), titanium oxide (TiO ₂ ), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), tantalum pentoxide ( It consists of a dielectric film such as Ta ₂ O ₅ ) or a laminated structure thereof. The gate electrodes 15 and 35 are made of, for example, a polycrystalline silicon film, a metal film such as tungsten (W), platinum (Pt), ruthenium (Ru), or a laminated structure thereof.

Side walls 16, 36 made of silicon nitride (SiN) or silicon oxide film (SiO ₂ ) are formed on the side walls of the gate insulating films 14, 34, the gate electrodes 15, 35, and the silicides 17, 18, 37, 38. Is done.

  Stress control films 19 and 39 are formed on the upper surfaces of the n-channel field effect transistor and the p-channel field effect transistor. Further, on the upper surfaces of the stress control films 19 and 39, for example, BPSG (Boron-doped Phospho Silicate Glass), SOG (Spin On Glass) film, TEOS (Tetra-Ethyl-Ortho-Silicate) film, or covered with an interlayer insulating film 3 made of a silicon oxide film formed by chemical vapor deposition or sputtering. It has been broken.

  As shown in FIG. 31, the n-channel field effect transistor and the p-channel field effect transistor formed on the silicon substrate 1 are electrically connected by contact plugs, wirings or the like so as to constitute a desired circuit. Is done. The first embodiment of the present invention is an example in which the stress control films 19 and 39 are used as means for controlling the stress of the channel portion of the n-channel and p-channel field effect transistors. Other parts may be structures and materials other than the first embodiment of the present invention.

  Further, in the example of FIG. 1, contact plugs, wirings, and the like are omitted, and contact plugs, wirings, and the like are similarly omitted in other examples except for the example of FIG.

  The stress control film 19 and the stress control film 39 are mainly made of silicon nitride (SiN), and are formed by chemical vapor deposition or sputtering. The film stress of the stress control film 19 is a stress on the tensile side with respect to the film stress of the stress control film 39.

  In the development of semiconductor devices such as LSI, improvement of drain current (increase in drain current) of field effect transistors is progressing year by year. The inventors of the present application have clarified that the drain current changes depending on the stress, and in the complementary field effect transistor having the p channel field effect transistor and the n channel field effect transistor, both the n channel type and the p channel type are provided. The present inventors have found a method for effectively improving the drain current of a transistor.

  FIG. 2 is a graph showing the stress dependence of the drain current of the field effect transistor. From FIG. 2, it is clear that the drain current increases due to the tensile stress in the n-channel field effect transistor, and conversely, the drain current increases due to the compressive stress in the p-channel field effect transistor.

  On the other hand, FIG. 3 is a stress analysis of the effect of the film stress of SiN covering the upper surface of the gate electrode on the stress (channel stress in the direction parallel to the drain current) of the portion where the drain current flows (channel). It is a graph which shows a result. As shown in FIG. 3, it is clear that when the film stress of the film covering the gate electrode becomes stronger on the tensile side, the stress of the channel portion also becomes stronger on the tensile side.

  This is because the film containing the gate electrode extends to the upper surface of the source / drain region, and the tensile stress (shrinkage of the film) in this part shifts the stress in the channel part to the tensile side. It is thought that this is a phenomenon that occurs.

  Therefore, in a semiconductor device having an n-channel field effect transistor and a p-channel field effect transistor, a film having a tensile stress side is used as a film covering the gate electrode of the n-channel field effect transistor. The film covering the gate electrode of the p-channel field effect transistor has a film stress that is more compressive than the n-channel film, thereby improving both the n-channel and p-channel drain currents. Can be expected. For this reason, the characteristic as a whole can be improved.

  The inventors of the present application also revealed that the etching rate of the silicon nitride (SiN) film is stress dependent.

  FIG. 8 is a graph showing an example of an experimental result of stress dependence of the etching rate of a silicon nitride (SiN) film. From the results shown in FIG. 8, it can be seen that when the film stress is different, the etching rate is different.

In the semiconductor device according to the first embodiment of the present invention, as shown in FIG. 1, a source in which at least part of a gate electrode 15 is included and a silicide 18 is formed on the upper surface of an n-channel field effect transistor 10 . A stress control film 19 in contact with the drain regions 12 and 13 is formed, includes at least a part of the gate electrode 35 of the p-channel field effect transistor 30 , and is formed in the source / drain regions 32 and 33 where the silicide 38 is formed. A stress control film 39 in contact therewith is formed, and the stress stress of the stress control film 19 is a stress on the tension side of the stress stress of the stress control film 39, more preferably, the stress control film 19 is a tensile stress, and the stress control film 39 is Compressive stress.

  As a result, as for the stress in the channel plane parallel to the drain current of the channel portion, a strong tensile stress is obtained in the n-channel type, and conversely, a stress on the compression side is obtained in the p-channel type than in the n-channel type. Therefore, it is possible to improve the drain currents of both the n channel type and the p channel type.

  Further, since the stress control film 19 and the stress control film 39 are made of silicon nitride (SiN), after the formation of the interlayer insulating film 3, the silicon oxide film is used for electrical connection from the upper wiring to the source / drain region. An effect is obtained that it can also be used as an etch stopper when a contact hole is opened in the interlayer insulating film 3.

  The contact plug 7 and the wiring 21 after forming the contact hole are as shown in FIG. 31, for example. A plurality of wiring layers are formed. The contact plug 7 and the wiring 21 are made of, for example, tungsten, aluminum, copper, titanium, titanium nitride, or a laminated structure thereof. Further, as shown in FIG. 31, the contact plug 7 and the wiring 21 may be configured with barrier metals 8 and 22 made of a laminated film such as titanium nitride or titanium.

  Further, since the stress control film 19 and the stress control film 39 can be obtained by using the same film forming apparatus and changing the film forming conditions, the effect can be obtained without introducing a new apparatus.

  In the semiconductor device according to the first embodiment of the present invention, the stress in the channel plane parallel to the drain current of the channel portion of the n-channel field effect transistor is greater than the stress of the channel portion of the p-channel field effect transistor. On the side of the tensile stress, more preferably, the stress of the n-channel type channel portion is a tensile stress, and the stress of the p-channel type channel portion is a compressive stress. The film to be used is not necessarily the film stress of the stress control film 19 if the film stress of the stress control film 39 is on the tensile side, more preferably if the stress control film 19 is tensile stress and the stress control film 39 is compressive stress. It need not be SiN.

  In the following, detailed contents constituting the state will be described with reference to FIG. 9 and FIG.

  FIG. 9 is a schematic diagram of a cross-sectional structure of the semiconductor device according to the first embodiment of the present invention. FIG. 4 is a graph showing an analysis result of the dependence of the stress of the channel portion of the field effect transistor on the thickness of the SiN film covering the gate electrode. It is.

  The first embodiment and the state of the first embodiment are configured such that the thicknesses of the stress control films 192 and 392 are different from each other in the n-channel field effect transistor and the p-channel field effect transistor. Thus, when the stress control film is a tensile stress, the p-channel type stress control film 392 is compared with the n-channel type stress control film 192 as shown in FIG. Thin out.

  On the other hand, when the stress control film is a compressive stress, on the contrary, it is preferable that the n-channel type stress control film 192 be thinner (not shown) than the stress control film 392. These stress control films 192 and 392 are formed by forming a silicon nitride (SiN) film on the entire upper surface of the n-channel and p-channel field effect transistors by a chemical vapor deposition method or a sputtering method. It is obtained by etching back to a film thickness of

  The first embodiment of the present invention is an example in which stress control films 192 and 392 are used as means for controlling the stress of the channel portion of the n-channel and p-channel field effect transistors. Other parts may be structures or materials other than the third embodiment of the present invention (however, the film thickness is determined by the data shown in FIG. 4).

  Next, functions and effects of the semiconductor device according to the third embodiment of the present invention will be described.

  FIG. 4 is a graph showing an analysis result of the film thickness dependence of the stress control film covering the gate electrode of the channel portion stress. FIG. 4 shows that when the stress control film is a tensile stress, the channel portion stress shifts to the tensile stress side if the film thickness is large. On the contrary, when the stress control film is a compressive stress, it means that the channel stress shifts to the compression side if the film thickness is large.

  According to the first embodiment of the present invention, when the stress control film is a tensile stress, as shown in FIG. 9, the p-channel type is thinner and the drain current of the p-channel field effect transistor is improved. It is done.

  On the other hand, when the stress control film is compressive stress, the drain current of the n-channel field effect transistor is improved by conversely reducing the thickness of the n-channel type.

  As described in the first embodiment, the stress control film 192 and the stress control film 392 are made of silicon nitride (SiN). An effect is obtained that it can also be used as an etch stopper when a contact hole is opened in the interlayer insulating film 3 made of a silicon oxide film for connection. Note that the film is not limited to SiN.

  Whether the insulating film or the like has residual tensile stress or compressive stress is determined by, for example, reducing the thickness of the semiconductor device from the substrate side or from the laminated structure side above the insulating film, leaving the insulating film. . Then, it can be seen that if the remaining thin film is warped with the substrate side facing out, the tensile stress remains. On the other hand, if the remaining thin film is warped with the substrate side inward, it can be understood that the film is a film in which compressive stress remains.

  The semiconductor device according to the first embodiment of the present invention shows an example of the stress control of the channel portion. Even if the stress of the channel portion is controlled by other means such as the embodiment described below. I do not care.

  Next, a second embodiment of the present invention will be described with reference to FIGS.

  FIG. 14 is a schematic view of a cross section (cross section taken along the line aa ′ in FIG. 15) of the semiconductor device according to the second embodiment of the present invention. FIG. 15 is an upper surface showing the shapes of the stress control films 193 and 393. It is the schematic diagram seen from. FIG. 15 shows only the outer shapes of the gate electrodes 15 and 35, the wiring 6 connected to the source / drain, the active region 5 (transistor formation region), and the stress control films 193 and 393. 14 and 15 show the case where the stress control films 193 and 393 are tensile stresses.

  The difference between the second embodiment and the first embodiment is that the planar shape of the stress control films 193 and 393 is different between the n-channel field effect transistor side and the p-channel field effect transistor side in the second embodiment. It is. As shown in FIG. 14, when the stress stress of the stress control films 193 and 393 is a tensile stress, the area of the side surface portion of the gate electrode 35 of the stress control film 393 is equal to the side surface portion of the gate electrode 15 of the stress control film 193. If the film stress of the stress control films 193 and 393 is compressive stress, the area of the side surface portion of the gate electrode 35 of the stress control film 393 is the area of the side surface portion of the gate electrode 15 of the stress control film 193. It is characterized by being larger.

  More preferably, when the stress control films 193 and 393 are tensile stress, the area of both the n-channel field effect transistor and the p-channel field effect transistor is increased with respect to the extending direction of the gate electrodes 15 and 35 (see FIG. 15).

  On the contrary, when the stress control films 193 and 393 are compressive stress, the area of both the n-channel field effect transistor and the p-channel field effect transistor is reduced in the extending direction of the gate electrodes 15 and 35 (FIG. Is omitted).

  The second embodiment is an example in which the stress control films 193 and 393 are used as means for controlling the stress of the channel portion of the n-channel and p-channel field effect transistors. Other parts may be structures and materials other than the second embodiment.

  Next, functions and effects of the semiconductor device according to the second embodiment of the present invention will be described.

  According to the second embodiment, the stress of the channel portion of the field effect transistor is controlled by the area of the stress control films 193 and 393. When the stress control film extending to the source / drain region is tensile stress, the n-channel type increases the area to give a strong tensile stress to the channel portion, and the p-channel type reduces the area as much as possible. Thus, the stress in the channel portion is reduced. On the other hand, when the stress control film is compressive stress, this is reversed.

  More preferably, in the direction perpendicular to the drain current, when the stress control film is tensile stress, both transistors have a large area, and tensile stress is applied to the channels of both field-effect transistors. When the control film is compressive stress, the stress in the channel portion is reduced by reducing the area.

  Therefore, in the semiconductor device according to the second embodiment of the present invention, as described above, the stress control films 193 and 393 can make the stress of the channel portion a tensile stress in the n channel type than in the p channel type, The effect that the drain current is improved is obtained.

  Further, according to the second embodiment of the present invention, since the stress is controlled also in the direction perpendicular to the channel, the effect of further improving the drain current can be obtained.

  According to the second embodiment of the present invention, as described above, since the stress control film 193 and the stress control film 393 are made of silicon nitride (SiN), the source / drain regions are formed after the interlayer insulating film 3 is formed. In addition, there is an effect that it can also be used as an etch stopper when a contact hole is opened in the interlayer insulating film 3 made of a silicon oxide film for electrical connection from the upper layer wiring.

  The semiconductor device of the second embodiment has a structure in which one n-channel field effect transistor and one p-channel field effect transistor are formed. In this second embodiment, the stress control film The portion expressing the large area does not need to be discontinuous in the portion where the n-channel or p-channel field effect transistors are continuously formed.

  Next, another example will be described with reference to FIGS.

  FIG. 10 is a schematic diagram of a cross-sectional structure of a semiconductor device according to another embodiment, and FIGS. 11 to 13 are schematic cross-sectional views illustrating a part of a manufacturing process of the semiconductor device according to another embodiment.

  The difference between this other embodiment and the first embodiment is that the compositions of the films are made different from each other in order to make the stresses of the two films indicated by the stress control films 191 and 391 different.

  The first embodiment is preferable because it is effective even if the film composition is not changed. However, it is also preferable to adopt this configuration if accepting the fear of increasing the steps for producing another composition.

  Specifically, the stress control film 391 is similar to the stress control film 191 in contrast to the stress control film 191 mainly made of silicon nitride (SiN), and the silicon nitride (SiN) film is silicon (Si). It is formed by implantation so as to contain at least one of nitrogen (N), oxygen (O), germanium (Ge), argon (Ar), and helium (He) in excess.

  The first embodiment of the other embodiment is an example in which the stress control films 191 and 391 are used as means for controlling the stress of the channel portion of the n-channel type and p-channel type field effect transistor. Other structures and materials may be used.

  The manufacturing process of the stress control films 191 and 391 of the semiconductor device of this embodiment is as follows, for example.

  (1) An n-channel field effect transistor 10 and a p-channel field effect transistor 30 are formed on the main surface of the silicon substrate 1, and sidewalls 16 and 36, silicides 17, 18, 37, and 388 are formed ( FIG. 11).

  (2) A silicon nitride (SiN) film to be the stress control film 191 is formed on the entire upper surface of the n-channel and p-channel field effect transistors by, for example, sputtering or chemical vapor deposition (see FIG. 12).

  (3) The portions other than the upper surface of the p-channel field effect transistor 30 are masked 4 so that silicon (Si), germanium (Ge), nitrogen (N), oxygen (O), argon (Ar), etc. These inert elements are ion-implanted (FIG. 13).

  (4) After removing the mask 4, the interlayer insulating film 3 is formed. Thereby, the semiconductor device having the structure shown in FIG. 10 is manufactured.

  Next, functions and effects of the semiconductor device according to the first embodiment of the other embodiment of the present invention will be described.

  According to the second embodiment of the present invention, after the stress control film 191 is formed on the entire upper surface (FIG. 12), ions are implanted into the portion covering the p-channel field effect transistor, and the atoms of the film in the portion are covered. The density is higher than before ion implantation. As a result, the film stress of the stress control film 391 is shifted to the compression side as compared with the stress control film 191.

  Therefore, the channel in-plane stress in the direction parallel to the drain current of the channel portion is also shifted to the compression side, and the effect of improving the drain current of the p-channel field effect transistor can be obtained.

  Further, according to the first embodiment of the other aspect of the present invention, the silicon nitride (SiN) as the main component of the stress control film may be formed only once. When silicon nitride having different film stresses is formed as in the first embodiment, it is preferable to use two film forming apparatuses or to change the film forming conditions each time with one apparatus. Even when it is difficult to change the film formation conditions or when a plurality of apparatuses cannot be prepared, the first embodiment of the other embodiment of the present invention can be used to form an n channel by using a single film formation apparatus. The drain current of both the field effect transistor and the p-channel field effect transistor can be improved.

  Thus, for example, when the stress control film 19 and the stress control film 39 have different impurity concentrations, the stress control film 19 and the stress control film 39 can be configured to have different stresses. Therefore, it is possible to cope without introducing a new device.

  Further, as described in the description of the first embodiment, since the stress control film 191 and the stress control film 391 are made of silicon nitride (SiN), the upper layer wiring is formed in the source / drain region after the formation of the interlayer insulating film 3. In addition, an effect is obtained that it can also be used as an etch stop when a contact hole is opened in the interlayer insulating film 3 made of a silicon oxide film for electrical connection.

  Next, a third embodiment of the present invention will be described with reference to FIGS.

  FIG. 16 is a schematic cross-sectional view of a semiconductor device according to a third embodiment of the present invention. FIG. 5 is a diagram showing a silicide film thickness of a channel portion stress (a stress in the channel plane parallel to the drain current) of the field effect transistor. It is a graph which shows the analysis result of dependence.

  The difference between the third embodiment and the first embodiment is that the thickness of the silicide 181 on the n-channel field effect transistor side is thicker than the silicide 381 on the p-channel field effect transistor side. These silicides (titanium silicide, cobalt silicide, nickel silicide, etc.) are obtained by forming a film of titanium, cobalt, nickel, etc. using a sputtering method, a chemical vapor deposition method, or the like, and then performing a heat treatment to cause a silicide reaction. Note that the stress control films 19 and 39 of the first embodiment shown in FIG. 1 may be omitted.

  In the third embodiment, silicide 181 and 381 are used as means for controlling the stress of the channel portion of the n-channel and p-channel field effect transistors. Other parts may be structures or materials other than the third embodiment.

  Hereinafter, the function and effect of this semiconductor device will be described.

  Silicides formed in n-channel and p-channel field effect transistors are indispensable for electrical connection between the contact plug and the transistor with a low resistance, but even a material that generates a strong tensile stress by heat treatment. is there.

  Accordingly, the inventors of the present application have studied to improve the drain current by applying stress to the channel portion by using the stress of the silicide. FIG. 5 is a graph showing the analysis result of the dependency of the channel stress on the silicide film thickness. From FIG. 5, it is clear that the stress in the channel portion shifts toward a higher tensile stress as the silicide film thickness increases.

  According to the third embodiment, as shown in FIG. 16, by increasing the thickness of the silicide 181 of the n-channel field effect transistor, the drain current of the n-channel field effect transistor is improved, and conversely, By reducing the thickness of the silicide 381 on the channel-type field effect transistor side, an effect of suppressing a decrease in p-channel drain current can be obtained.

  In addition, according to the third embodiment, since the silicide which is essential for forming the complementary field effect transistor is used, it is not necessary to introduce a new material, and the conventional manufacturing process can cope with it. Is obtained.

  Next, a fourth embodiment of the present invention will be described with reference to FIGS.

  FIG. 17 is a schematic diagram of a cross-sectional structure of a semiconductor device according to the fourth embodiment of the present invention. FIG. 6 shows the dependence of the stress of the channel portion (stress in the channel plane parallel to the drain current) on the gate electrode intrinsic stress. It is a sex analysis result.

The difference between the fourth embodiment and the first embodiment is that the impurity concentration distribution of the gate electrode 151 of the n-channel field effect transistor 10 in the fourth embodiment has a gradient in the direction perpendicular to the main surface of the silicon substrate 1. Furthermore, the impurity of the gate electrode 351 of the p-channel field effect transistor 30 is uniform.

  The gate electrode 151 of the fourth embodiment is obtained by ion implantation of impurities such as phosphorus (P), boron (B), and arsenic (As) after the gate electrode is formed. The gate electrode 351 is formed of phosphorus (P). , Boron (B), arsenic (As) and other impurities are added in advance and formed. In the fourth embodiment, the stress control films 19 and 39 of the first embodiment shown in FIG. 1 may be omitted.

  In the fourth embodiment, gate electrodes 151 and 351 are used as means for controlling the stress of the channel portion of the n-channel and p-channel field effect transistors. Other parts may be structures and materials other than the fourth embodiment.

  The operation and effect of the semiconductor device according to the fourth embodiment will be described below.

  FIG. 6 is a graph showing an analysis result of the gate intrinsic stress dependence of the stress of the channel portion (stress in the channel plane parallel to the drain current). As shown in FIG. 6, when the intrinsic stress of the gate electrode is a tensile stress, the stress of the channel portion becomes a compressive stress.

  Normally, polycrystalline silicon used for a gate electrode is obtained by forming amorphous silicon to which impurities are added, and performing heat treatment for the purpose of crystallization and activation of the added impurities. At this time, tensile crystallization stress due to film shrinkage occurs. On the other hand, when crystallization heat treatment is performed on amorphous silicon to which no impurity is added, crystallization stress that becomes tensile stress is generated. However, when an impurity element is ion-implanted thereafter, the stress is shifted to the compression side.

  According to the above two types of gate electrode forming methods, the former is polycrystalline silicon in which impurities are distributed almost uniformly in the film, while the latter is distributed in the direction perpendicular to the main surface of the silicon substrate 1. It becomes polycrystalline silicon (Gaussian distribution or distribution in which the concentration decreases in the direction perpendicular to the main surface of the silicon substrate 1).

  According to the fourth embodiment, polycrystalline silicon having an impurity concentration of substantially uniform tensile stress in the film is used for the gate electrode of the p-channel field effect transistor, and the gate electrode of the n-channel field effect transistor is used for the gate electrode of the n-channel field effect transistor. Polycrystalline silicon having a stress on the compression side with respect to the stress of the gate electrode used for the n-channel type so that the impurity concentration decreases toward the substrate 1 side is used.

  As a result, the stress of the channel portion of the n-channel type field effect transistor becomes a stress on the tensile side rather than the stress of the p-channel type channel portion, and the drain current of both the n-channel type and the p-channel type can be improved. can get.

  In addition, according to the fourth embodiment, since the gate electrode structure in the field effect transistor structure is used as a means for controlling the stress of the channel portion, it is not necessary to introduce a new material, and the conventional manufacturing process is used. The effect that it can respond is acquired.

In the semiconductor device of the fourth embodiment, the stress of the gate electrode is used as a means for controlling the stress of the channel portion. Therefore, the gate electrode material is not limited to polycrystalline silicon. For example, a metal material such as ruthenium (Ru), platinum (Pt), tungsten (W), titanium (Ti), or titanium nitride (TiN) is used. It may be used, or a laminated structure of these metal materials and polycrystalline silicon may be used. For example, a ruthenium Ru film becomes a tensile stress with a strong film stress by heat treatment.

  Therefore, a Ru film having a high tensile stress is formed by high-temperature heat treatment on the gate electrode of the p-channel field effect transistor, and a Ru film having a low stress without being subjected to heat treatment is formed on the gate electrode of the n-channel field effect transistor. By controlling the stress, the stress of the channel portion of both the n-channel type and the p-channel type is controlled.

  Next, a fifth embodiment of the present invention will be described with reference to FIGS.

  FIG. 18 is a schematic diagram of a cross-sectional structure of a semiconductor device according to a fifth embodiment of the present invention, and FIGS. 19 to 21 are schematic cross-sectional views showing a part of the manufacturing process of the semiconductor device according to the fifth embodiment of the present invention. It is.

  The difference between the fifth embodiment and the fourth embodiment is that the crystal grains constituting the gate electrodes 152 a and 152 b of the n-channel field effect transistor 10 have a plurality of interfaces in the vertical direction of the substrate 1. However, the crystal grains constituting the p-channel gate electrode 352 do not form a layer, or the average crystal grain size of the n-channel gate electrodes 152a and 152b is the average of the p-channel gate electrode 352. It is smaller than the crystal grain size. In the fifth embodiment, the stress control films 19 and 39 of the first embodiment shown in FIG. 1 may be omitted.

  In the fifth embodiment, gate electrodes 152a, 152b and 352 are used as means for controlling the stress of the channel portion of the n-channel and p-channel field effect transistors. Other parts may be structures and materials other than the fifth embodiment.

  The manufacturing process of the gate electrodes 152a, 152b, and 352 of the semiconductor device according to the fifth embodiment is as follows, for example.

  (1) On the main surface of the silicon substrate 1, the shallow trench isolation 2 and the p-well 11 in the region of the n-channel field effect transistor 10 and the n-well 31 in the region of the p-channel field effect transistor 30 are formed ( FIG. 19).

  (2) Next, the gate insulating film 14 and the gate electrode 152a are formed (FIG. 20).

  (3) Subsequently, the gate electrode film 152a on the p-channel field effect transistor side is removed, and a gate electrode 152b is formed (FIG. 21).

  (4) Next, the gate electrode is processed to form the gate electrodes 152a and 152b of the n-channel field effect transistor and the gate electrode 352 of the p-channel field effect transistor, and the sidewalls 16 and 36 and the source / drain electrodes 12 are formed. , 13, 32, 33, silicides 17, 18, 37, 38, and interlayer insulating film 3 are formed (FIG. 18).

  The operational effects of the semiconductor device according to the fifth embodiment will be described below.

  When amorphous silicon is formed, tensile stress is generated with the growth of crystal grains. Since this crystallization stress increases with the growth of crystal grains, the crystallization stress can be suppressed by reducing the grain size.

  According to the fifth embodiment, since the gate electrode 352 that generates a strong tensile stress of the p-channel field effect transistor is used, the stress of the channel portion becomes a compressive stress. On the other hand, since the gate electrodes 152a and 152b of the n-channel field effect transistor are formed twice, the grain size of the crystal grains of the gate electrodes 152a and 152b is reduced, the generated stress is relaxed, and the channel portion Stress is also reduced. As a result, the drain current can be improved in both the p-channel field effect transistor and the n-channel field effect transistor.

  Note that the gate electrode of the semiconductor device of the fifth embodiment does not necessarily have to be formed twice, and may be formed twice or more. Alternatively, n-channel and p-channel gate electrodes are formed in separate processes, respectively, by changing the film formation conditions so that the n-channel type has smaller crystal grains and the p-channel type has larger crystal grains. May be.

  In the fifth embodiment, as described in the fourth embodiment, since the gate electrode structure in the field effect transistor structure is used as a means for controlling the stress in the channel portion, a new material is introduced. There is no need to do this, and the effect of being able to cope with the conventional manufacturing process is obtained.

  Next, a sixth embodiment of the present invention will be described with reference to FIGS.

  FIG. 22 is a schematic view of a cross section (cross section taken along the line aa ′ in FIG. 23) of the semiconductor device according to the sixth embodiment of the present invention. FIG. 23 shows shallow trench isolation (STI) and FIG. It is the schematic diagram seen from the upper surface which shows that the distance to a gate electrode differs with an n channel type field effect transistor and a p channel type field effect transistor.

  FIG. 23 shows only the shallow trench isolation 2, the gate electrodes 15 and 35, the wiring 6 connected to the source / drain, and the active region 5 (transistor formation region). FIG. 7 is a graph showing the analysis result of the stress dependency of the stress of the channel portion (stress in the channel plane parallel to the drain current) due to the STI oxidation.

The difference between the sixth embodiment and the first embodiment is that the distance from the gate electrode 15 of the n-channel field effect transistor 10 to the shallow trench isolation 2 (distance in the direction parallel to the channel) is p-channel electric field. This is larger than the distance from the gate electrode 35 of the effect transistor 30 to the shallow trench isolation 2 (distance in the direction parallel to the channel). In the sixth embodiment, the stress control films 19 and 39 of the first embodiment shown in FIG. 1 may be omitted.

  In the sixth embodiment, as means for controlling the stress of the channel portion of the n-channel and p-channel field effect transistors, the distance from the gate electrode 15 to the shallow trench isolation 2 and the shallow trench from the gate electrode 35 are used. The use of the distance to the element isolation 2 is described. Other parts may be structures and materials other than the sixth embodiment.

  The operational effects of the semiconductor device according to the sixth embodiment will be described below.

  FIG. 7 is a graph showing an analysis result of the STI oxidation-induced stress dependence of the stress in the channel portion (stress in the channel plane parallel to the drain current). As shown in FIG. 7, when the stress caused by STI oxidation is reduced, it has been clarified that the high compressive stress in the channel portion decreases.

  The STI is formed so as to surround the transistor formation region, and insulates the transistors from each other. However, since a shallow groove is dug in the surface of the silicon substrate and a silicon oxide film is embedded therein, When there is an oxidation process, volume expansion accompanying the formation of the silicon oxide film occurs, and high compressive stress is generated in the active region.

  As a result, it has been clarified that the stress of the channel portion strongly depends on the stress of STI.

  According to the sixth embodiment, the channel portion of the n-channel field effect transistor is formed at a distance from the STI, and conversely, the channel portion of the p-channel field effect transistor is formed close to the STI. Since the compressive stress due to this STI can be reduced if it is separated from the STI, the stress in the channel portion of the n-channel field effect transistor is reduced, and conversely, the stress in the channel portion of the p-channel field effect transistor is high compressive stress. be able to.

  As a result, there is an effect that both n-channel and p-channel drain currents can be improved. For this reason, the performance as a whole can be improved.

  Further, according to the sixth embodiment, since only the layout change is required, an effect that the conventional manufacturing process can be used as it is can be obtained.

  The distance from the STI in the long side direction of the gate electrodes 15 and 35 to the STI in both the n-channel type and the p-channel type is preferably large. More preferably, the p-channel type is larger than the n-channel type.

  The semiconductor device according to the sixth embodiment is characterized in that the distance from the STI to the channel is different between the n-channel type and the p-channel type. The same effect can be obtained by making the STI trench width wider on the n-channel field effect transistor side and narrower on the p-channel field effect transistor side.

  In this case, it is desirable that the STI trench width in the direction perpendicular to the channel is wider for both field effect transistors.

  As described above, according to the sixth embodiment of the present invention, the drain current can be favorably increased. Further, according to the sixth embodiment of the present invention, a semiconductor device capable of reducing the manufacturing cost can be realized.

  Next, a seventh embodiment of the present invention will be described with reference to FIGS.

  FIG. 26 is a schematic diagram of a cross-sectional structure of a semiconductor device according to a seventh embodiment of the present invention, and FIG. 27 is a graph showing an analysis result of a sidewall film stress dependency of a stress of a channel portion of a field effect transistor. is there.

  The difference between the seventh embodiment and the first embodiment is that the film quality of the sidewall 16 on the n-channel field effect transistor side is different from the film quality of the sidewall 36 on the p-channel field effect transistor side.

  Specifically, the film stress of the sidewall 16 on the n-channel field effect transistor side is closer to the tensile stress side than the sidewall 36 on the p-channel field effect transistor side, that is, the tensile stress of the sidewall 16 is This is a point that is larger than the tensile stress of the sidewall 36. The main component of these sidewalls 16 and 36 is preferably silicon nitride, but may be other than that.

  The sidewalls 16 and 36 are preferably single-layer films, but may have a laminated structure of silicon nitride and silicon oxide. In the first embodiment, the stress control films 19 and 39 are formed. However, in the seventh embodiment shown in FIG. 26, the stress control films 19 and 39 may be omitted.

  In the seventh embodiment, the side walls 16 and 36 are used as means for controlling the stress of the channel portion of the n-channel field effect transistor and the p-channel field effect transistor. Other parts may be structures and materials other than the seventh embodiment.

  The operational effects of the semiconductor device according to the seventh embodiment will be described below.

  The analysis result shown in FIG. 27 is a result obtained by assuming silicon nitride as the sidewall film. From FIG. 27, it can be seen that as the film stress of the sidewall becomes the tensile stress side, the stress of the channel portion also shifts to the tensile stress side.

  According to this seventh embodiment, a film having a tensile stress side is used for the sidewall 16 of the n-channel field effect transistor, and a film stress is applied to the sidewall 36 of the p-channel field effect transistor. By using a film on the compressive stress side rather than the n-channel type film, it is possible to expect an improvement in the drain current of both the n-channel type and the p-channel field effect transistor. For this reason, the characteristic as a whole can be improved.

  The difference in film stress can also be known from the film quality (dense / dense) or the like, and the more dense the film, the more the film stress is on the compression side.

  Next, an eighth embodiment of the present invention will be described with reference to FIGS.

  FIG. 28 is a schematic diagram of a cross-sectional structure of a semiconductor device according to an eighth embodiment of the present invention, and FIG. 29 is a graph showing an analysis result of a sidewall material dependency of a stress of a channel portion of a field effect transistor. is there.

  The difference between the eighth embodiment and the first embodiment is that the stress control film 9 has a difference in film stress between the n-channel field effect transistor side and the p-channel field effect transistor side as in the first embodiment. do not have.

  In the eighth embodiment, when the stress stress of the stress control film 9 is a tensile stress, the average Young's modulus of the sidewall 16 is larger than the average Young's modulus of the sidewall 36. For example, the sidewall 16 is mainly made of silicon nitride, and the sidewalls 36 are mainly made of silicon oxide.

  On the other hand, when the film stress of the stress control film 9 is a compressive stress, the average Young's modulus of the sidewall 16 is smaller than the average Young's modulus of the sidewall 36. For example, the sidewall 16 is mainly made of silicon oxide. The sidewalls 36 are mainly made of silicon nitride.

  The sidewalls 16 and 36 may have a laminated structure made of a plurality of materials. The eighth embodiment utilizes a phenomenon in which the stress of the film covering the gate electrode and the sidewall from above is not transmitted to the channel portion due to the Young's modulus (hardness) of the sidewall. .

  Therefore, a film covering the gate electrode and the sidewall is important, and the stress control film 9 may be omitted. However, since the stress of the interlayer insulating film 3 may act on the sidewalls 16 and 36, the stress control film 9 is not present, and when the stress of the interlayer insulating film 3 is a tensile stress, the Young of the sidewall 16 The Young's modulus of the sidewall 36 is set to be smaller than the Young's modulus of the sidewall 16 when the stress of the interlayer insulating film 3 is a compressive stress.

  The eighth embodiment uses sidewalls 16 and 36 as means for controlling the stress of the channel portion of the n-channel and p-channel field effect transistors, and further covers the gate electrodes and sidewalls from above. It is stated that is used. For this reason, the other parts may be structures and materials other than the eighth embodiment.

  Next, functions and effects of the semiconductor device according to the eighth embodiment will be described.

  FIG. 29 is a graph showing an analysis result of the dependency of the stress of the channel portion on the sidewall material. However, the result shown in FIG. 29 is a result obtained by assuming that silicon oxide is used for a material having a low Young's modulus and silicon nitride is used for a material having a high Young's modulus as a sidewall material.

  As shown in FIG. 29, when the sidewall material is silicon oxide and silicon nitride, when the stress control film 9 is tensile stress, the silicon nitride is larger on the tensile stress side, When the stress control film 9 is compressive stress, silicon oxide is larger on the tensile stress side.

  According to the eighth embodiment, when the stress control film 9 has a tensile stress, silicon nitride is used for the sidewall 16 of the n-channel field effect transistor, and the sidewall 36 of the p-channel field effect transistor is used. In this case, silicon oxide is used.

  Contrary to the above, when the stress control film 9 is compressive stress, silicon oxide is used for the sidewall 16 of the n-channel field effect transistor, and silicon nitride is used for the sidewall 36 of the p-channel field effect transistor. Is used.

  Therefore, the drain current of both the n-channel and p-channel field effect transistors can be improved. For this reason, the characteristic as a whole can be improved.

  The Young's modulus of the film can also be measured by a microindentation test or the like.

  Next, a ninth embodiment of the present invention will be described with reference to FIG.

  FIG. 30 is a schematic diagram of a cross-sectional structure of a semiconductor device according to the ninth embodiment of the present invention.

  In the eleventh embodiment, when the film stress of the stress control film 19 is tensile stress and the film stress of the stress control film 39 is compressive stress, the film stress of the sidewall 16 is tensile stress, and the film stress of the sidewall 36 is Is a combination that becomes compressive stress.

  The stress control films 19 and 39 are preferably films mainly made of silicon nitride, but may be other than that.

  The sidewalls 16 and 36 are preferably films mainly made of silicon nitride, but may be a laminated structure with silicon oxide or the like, or other materials.

  Further, the ninth embodiment is an example in which the stress control films 19 and 39 and the sidewalls 16 and 36 are used as means for controlling the stress of the channel portion of the n-channel and p-channel field effect transistors. For this reason, the other parts may be structures and materials other than the ninth embodiment.

  Next, the function and effect of the semiconductor device according to the ninth embodiment will be described.

  According to the ninth embodiment of the present invention, as described in the first embodiment, the stress control film 19 is tensile stress and the stress control film 39 is compressive stress. Both drain currents of the transistor can be improved.

  Further, according to the ninth embodiment, as described in the eighth embodiment, both the n-channel and p-channel field effect transistors are formed by using a material having a high Young's modulus, for example, silicon nitride as the sidewall. The drain current can be further improved.

  Further, according to the ninth embodiment, as described in the seventh embodiment, the n-channel and p-channel field effects are further increased by setting the side wall 16 to tensile stress and the side wall 36 to compressive stress. Both drain currents of the transistor can be improved.

  Further, the stress control film 19 and the sidewall 16 can be formed under the same film formation conditions, and furthermore, the stress control film 39 and the sidewall 36 can be formed under the same film formation conditions. The effect that simplification can be achieved is obtained.

  In the example described above, the contact plug is omitted except for the example of FIG. 31, but the shape of the contact plug formed on the n-channel field effect transistor side and the p-channel field effect transistor side are shown. It is also possible to change the stress acting on the n-channel type and the p-channel type by changing the shape of the formed contact plug.

  Next, a tenth embodiment of the present invention will be described with reference to FIG. 2 and FIGS. This embodiment is an actual device circuit application example in which the direction perpendicular to the channel is also taken into consideration when the stress control film 9 has a tensile stress. FIG. 2 is a diagram showing experimental results of the stress dependence of drain current of n-channel and p-channel field effect transistors, FIG. 32 is an electric circuit diagram showing a 2NAND circuit to which the present invention is applied, and FIGS. 33 is a schematic diagram of a planar layout of the semiconductor device (FIG. 33 is a schematic diagram enlarging a part of FIG. 34 (in the vicinity of the frame indicated by X)), and FIG. 35 is a sectional view from A to D of the planar layout of FIG. It is the schematic diagram which showed.

As shown in FIG. 32, the electric circuit to which the present invention is applied is a 2NAND circuit including two p-channel field effect transistors P1 and P2 and two n-channel field effect transistors N1 and N2. These transistors N1, N2, P1, and P2 correspond to the transistors N1 , N2 , P1 , and P2 shown in FIG. 33, respectively.

In FIG. 33, one 2-NAND circuit is designed to electrically connect the p-channel field effect transistor P1 and the n-channel field effect transistor N2 that share the gate electrode FG , and similarly P2 and N1 , respectively. Therefore , the contact plug CONT and the wiring ML are used. Here, the p-channel field effect transistors P1 and P2 are formed on one active ACT1, and the n-channel field effect transistors N1 and N2 are formed on one active ACT2.

The semiconductor device according to the present embodiment has a repeated pattern in which a plurality of 2NAND circuits are continuously arranged. That is, as shown in FIG. 34, a p-channel field effect transistor P1 , P2 and a plurality of n-channel field effect transistors N1 , N2 are repeatedly arranged, a region NM where n-channel field effect transistors are continuous, and A p-channel field effect transistor is constituted by a continuous region PM.

Here, in this embodiment, the stress control film described in the second embodiment is a film stress of a tensile stress, and an n-channel type and a p-channel field effect transistor are formed in the portions shown in FIGS. The planar pattern shown in FIG. In other words, among the stress control films covering the entire circuit layout, the stress control film in the direction in which the drain current of the p-channel field effect transistor flows is discontinuous on the active sandwiched field of the p-channel field effect transistor. (In the transistor circuit shown in FIG. 33, the stress control film 209 is a portion other than the field on the active side of the p-channel field effect transistor, the longitudinal direction of the gate electrode of the transistor, n (In the continuous direction of the channel-type field effect transistor, the stress control film is continuously formed on other elements.)
When viewed macroscopically, as shown in FIG. 34, in the region PM where a large number of p-channel field effect transistors are formed, the stress control film 209 has slits (parts where the film is discontinuous). ing.

FIG. 35 shows a schematic diagram of the cross-sectional structures A to D in the plan layout diagram of FIG. Similar to the second embodiment, the semiconductor device of this embodiment has an n-channel field effect transistor 210 , a p-channel field effect transistor 230, and an upper surface of these transistors formed on the main surface of the silicon substrate 201. The stress control film 209 is formed.

n-channel type field effect transistor, the source and drain of the n type formed in the p-type well 211 (212, 213), a gate insulating film 214 is formed of a gate electrode 215, the upper surface of the gate electrode 215, and source Silicides 217 and 218 are formed on the upper surfaces of the drains ( 212 and 213 ). The P-channel field effect transistor is composed of p-type source / drain ( 232 , 233 ) formed in the n-type well 231 , a gate insulating film 34, and a gate electrode 35. The upper surface of the gate electrode 235 and the source Silicides 237 and 238 are formed on the upper surfaces of the drains ( 232 and 233 ). Side walls 216 and 236 are formed on the side walls of the gate insulating films 214 and 234 , the gate electrodes 215 and 235 , and the silicides 217 , 218 , 237 , and 238 , respectively. These transistors are insulated from other transistors by the shallow trench isolation 202.

A stress control film 209 is formed on the upper surface of the n-channel and p-channel field effect transistors, and a wiring 223 electrically connected by a contact plug 207 and an interlayer insulating film 203 are formed on the upper surface. The

The stress control film 209 uses the material and the film formation method described in the first embodiment in which the film stress becomes a tensile stress, and is a cross section crossing the source / drain of the p-channel field effect transistor (A-- in FIG. 34). In the cross section B, FIG. 35 (a)), the shallow trench isolation is formed discontinuously, and the stress control film is discontinuous between adjacent transistors sandwiching shallow trench isolation, for example, 202a. On the other hand, in the cross section across the n-channel field effect transistor (cross section taken along the line CD in FIG. 34, FIG. 35 (c)), the stress control films are continuous between adjacent transistors. That is, the stress control film is continuous on the shallow trench isolation, for example, on 202d and 202e.

In addition, as shown in the B-C cross section of FIG. 34 and FIG. 35 (b), stress control is performed on shallow channel element separation in the longitudinal direction of the gate electrode of the n-channel and p-channel field effect transistors, for example, on 202c. A film 209 is formed and is continuous with the stress control film on the transistor in the longitudinal direction of the gate electrode or on another element.

  The 2NAND circuit shown in this embodiment is one example in which the present invention is applied to an actual electric circuit layout. The planar layout may be other than this embodiment, and the applied electric circuit may be, for example, an AND circuit, a NOR circuit, an OR circuit, or an input / output buffer circuit. Further, the structure, material, and manufacturing method other than the stress control film may be other than the present embodiment.

  Hereinafter, the effect of the present embodiment will be described. As described in the second embodiment, the stress of the channel portion of the field effect transistor can be controlled by the area of the stress control film 9. FIG. 14 of the second embodiment mainly optimizes the stress in the direction parallel to the channel by using n-channel and p-channel field effect transistors.

  However, as shown in FIG. 2, the drain current of the n-channel and p-channel field effect transistors changes not only in the direction parallel to the channel but also in the direction perpendicular to the channel, and is perpendicular to the channel. For a direction tensile stress of 100 MPa, the n-channel field effect transistor increases by about 2% and the p-channel field effect transistor decreases by about 7%.

  In an actual device circuit, since the film is formed in a plane, biaxial stress, that is, stress in a direction perpendicular to the direction parallel to the channel acts on the channel portion of the transistor. When the stress control film whose film stress is tensile stress is uniformly formed on the entire circuit surface, the tensile stress acts on the channel portion of the transistor in both the parallel direction and the perpendicular direction.

  For an n-channel field effect transistor, the tensile stress increases the drain current both in the direction parallel to and perpendicular to the channel, so that improvement in characteristics can be expected.

  However, in the p-channel field effect transistor, the tensile stress in the direction parallel to the channel reduces the drain current, and thus it is necessary to reduce this tensile stress. However, since the drain current can be increased in the direction perpendicular to the channel, we would like to make effective use of this.

  Therefore, according to the semiconductor device of this embodiment, the p-channel field effect is removed by removing the stress control film in the direction parallel to the channel of the p-channel field effect transistor from the stress control film covering the entire circuit surface. The tensile stress in the direction parallel to the channel of the transistor can be reduced. Tensile stress can be applied to the other direction, the direction parallel to the channel of the n-channel field effect transistor and the direction perpendicular to the channel of the n-channel type and p-channel type field effect transistor.

  Therefore, since both the n-channel and p-channel field effect transistors are controlled in the biaxial direction in the channel plane, the drain current can be increased for both the n-channel and p-channel transistors.

  By the way, as a material of the stress control film, silicon nitride is given as an example in the first embodiment. As a result, the stress control film can also be used as a self-aligned contact film for opening a contact hole in an interlayer insulating film mainly made of silicon oxide.

  In the semiconductor device of this embodiment, the stress control film is removed only on the field region sandwiched actively of the p-channel field effect transistor. That is, since the stress control film is formed in the portion where the contact plug is connected to the source / drain of the p-channel field effect transistor, the effect that it can be used as a film for self-aligned contact is obtained.

Further, since the processing of the stress control film described in this embodiment can be performed in the same process as the formation of the self-aligned contact hole, the mask can be shared with the self-aligned contact. That is, after the stress control film 209 is uniformly formed, the stress control film processing process (removal of the stress control film on the shallow groove element isolation 202c or 202b) can be performed simultaneously with the self-aligned contact hole forming process. it can. Subsequent processing may be performed by continuing the conventional process for performing self-aligned contact. As described above, according to this embodiment, the conventional process can be used only by changing the mask layout, so that an effect of obtaining a semiconductor device excellent in manufacturing cost can be obtained.

  Note that the tensile stress applied in the direction parallel to the channel of the p-channel field effect transistor is preferably as small as possible. Therefore, it is desirable that the stress control film on the p-channel field effect transistor side be formed only in the contact hole forming region, that is, the portion used as the self-aligned contact.

  Note that the slit portion of the stress control film does not necessarily have to be completely free of the film. A slightly thin film may be formed.

  As another form, a region (for example, a field) located between a first p-channel field effect transistor and a second p-channel field effect transistor adjacent to the first p-channel field effect transistor is used. Region) and a region (for example, a field region) located between the first p-channel field effect transistor and the first n-channel field effect transistor corresponding to the first p-channel field effect transistor. The stress control film thinner than the thickness of the stress control film formed on the first p-channel field effect semiconductor may be formed, or the stress control film may be omitted.

  Alternatively, a region (for example, a field region) positioned between a first p-channel field effect transistor and a second p-channel field effect transistor adjacent to the first p-channel field effect transistor, and the first A first n-channel field effect transistor corresponding to one p-channel field effect transistor and a second n-channel field effect transistor adjacent to the first n-channel field effect transistor and corresponding to the second p-channel field effect transistor. In a region (for example, a field region) between the n-channel field effect transistor, the stress relaxation layer having a thickness smaller than that of the stress relaxation layer formed on the first n-channel field effect transistor is formed. It is also conceivable that the stress relaxation layer is not installed.

  In a region (for example, a field region) located between the first p-channel field effect transistor and the first n-channel field effect transistor corresponding to the first p-channel field effect transistor, the first The stress control film thinner than the thickness of the stress control film formed on the p-channel field effect semiconductor may be formed, or the stress control film may be omitted.

  At the same time, the field region is formed in the field region formed around the active region where the first n-channel field effect transistor is disposed corresponding to the first p-channel field effect transistor. The thickness may be smaller than the thickness of the stress control film or may not be installed.

  Next, an eleventh embodiment of the present invention will be described with reference to FIG. 2 and FIGS. This embodiment is an actual device circuit application example in which stress in the direction perpendicular to the channel is also taken into consideration when the stress control film 9 has a compressive stress in the second embodiment. FIG. 2 is a diagram showing the experimental results of the stress dependence of the drain current of n-channel and p-channel field effect transistors. FIGS. 36 and 37 are schematic views of the planar layout of the semiconductor device of the present invention (FIG. FIG. 38 is a schematic diagram showing a cross-sectional structure from A to D in the planar layout of FIG. 36.

The difference between this embodiment and the tenth embodiment is that the film stress of the stress control film 209 is a compressive stress and that the region where the stress control film 209 is formed is different.

That is, the semiconductor device of this example is a p-channel type of the stress control film that covers the entire circuit layout as shown in the plan layout schematic diagrams of FIGS. 36 and 37 and the cross-sectional structure schematic diagram of FIG. No film is formed on the field region (shallow trench isolation) perpendicular to the drain current adjacent to the field effect transistor active and on the field region surrounding the active region of the n-channel field effect transistor. It is said. (The stress control film 209 is continuously formed up to adjacent elements in the repetitive direction of the p-channel field effect transistor (direction parallel to the channel), and the stress control film is formed on the n-channel field effect transistor side. Is characterized by active only.)
The arrangement of the transistors other than the stress control film, the wiring ML , and the contact plug CONT is the same as that described in the tenth embodiment.

Hereinafter, the effect of the present embodiment will be described. Contrary to the case of the tenth embodiment, when the stress control film is a compressive stress, a compressive stress is generated in the channel portion in a direction perpendicular to the channel and parallel to the channel. As described with reference to FIG. 14 of the second embodiment, in the direction parallel to the channel, the stress control film 209 may be formed discontinuously on the n-channel field effect transistor side and continuously on the p-channel field effect transistor side. .

  On the other hand, in the direction perpendicular to the channel, the drain current decreases in both the n-channel and p-channel field effect transistors due to the compressive stress.

By the way, as described in the tenth embodiment, the stress control film 209 can also be used as a film for self-aligned contact for forming contact plugs CONT and 207 .

Therefore, in the semiconductor device of this example, the stress control film 209 is formed on the shallow trench isolation, for example, on 202f and 202g in the direction parallel to the channel of the p-channel field effect transistor as shown in FIG. By forming and continuing to the stress control film on the adjacent transistor, a region of the stress control film acting on the channel portion is made wider. On the other hand, in the direction perpendicular to the channel, as shown in FIG. 38 (b), the stress control film 209 is not formed on the shallow trench isolation 202h, and the area of the stress control film acting in the direction perpendicular to the channel is minimized. It is staying at. Therefore, the compressive stress is applied to the channel portion of the p-channel field effect transistor in the direction parallel to the channel, and the compressive stress is suppressed in the perpendicular direction. As a result, the drain current is reduced. The effect that it can be increased is obtained.

In the case of an n-channel field effect transistor, the stress control film of compressive stress acts in the direction of decreasing the drain current, and therefore the stress control film 209 need not be formed.

However, when the stress control film is also used as a film for a self-aligned contact, the stress control film 209 is also formed on the n-channel field effect transistor side as in this embodiment. At this time, the region for forming the stress control film may be formed only in a portion necessary for making the contact plugs CONT and 207 , and as shown in FIG. 38 (c), for example, 202i, 202j It is desirable not to form it on top. More preferably, the stress control film on the side where the contact plugs CONT , 207 are not formed on the two transistors N1 , N2 formed on one active, for example, the stress control film on the side 212a, or the side walls, for example, 216a, 216b It is desirable not to form a stress control film adjacent to the. As a result, the stress control film 209 formed on the n-channel field effect transistor side can be used as a self-aligned contact film while minimizing the decrease in drain current. As described in the first embodiment, the thickness of the stress control film on the n-channel field effect transistor side is preferably thin.

  Also, in the semiconductor device of this embodiment, as in the tenth embodiment, the stress control film can be processed in the same process as the formation of the self-aligned contact hole, so that the mask is shared with the self-aligned contact. Can do. Therefore, an effect that a semiconductor device excellent in manufacturing cost can be obtained can be obtained.

  Note that the semiconductor device of this embodiment is one of the embodiments in which the method for controlling the stress in the direction perpendicular to the channel is described using an actual 2NAND circuit. The applied circuit is not limited to this embodiment.

  Next, a twelfth embodiment of the present invention will be described with reference to FIG. 35 (a) and FIGS. In this example, the manufacturing method of the tenth example is described with reference to FIG. 35 (a) which is a typical sectional structure of the tenth example. The eleventh embodiment can be manufactured by a similar method.

The manufacturing method of this example is as follows.
(1) A field effect transistor 230 , silicides 218 , 217, etc. are formed on a silicon substrate 201 , and a stress control film 209 is formed on the entire upper surface. (Fig. 39)
(2) on the upper surface of the stress control film 209, a mask 204 for processing the stress control film 209. The mask pattern serves both as a process for stress control and a process for forming the contact plug 207 . (Fig. 40)
(3) The stress control film 209 is processed by etching. (Fig. 41)
(4) An interlayer insulating film 203 is formed, and a hole is formed only in a portion where the contact plug 207 is formed. (Figure 42)
(5) A contact plug 207 is formed. (Fig. 43)
(6) An upper layer wiring 223 , an interlayer insulating film 220, and the like are formed. (Fig. 35 (a))
According to the present embodiment, the stress control processing process of the stress control film 209 and the self-aligned contact process for forming the contact plug can be performed simultaneously using the same mask. Therefore, an effect that a highly reliable semiconductor device with excellent manufacturing cost can be obtained.

  The manufacturing method shown in the present embodiment is merely an example of a method for manufacturing the tenth embodiment. The manufacturing methods of the tenth embodiment and the eleventh embodiment may be other than the present embodiment.

  The present invention is effective when applied to a semiconductor device having a field effect transistor.

1 is a schematic view showing a cross section of a semiconductor device according to a first embodiment of the present invention. It is a graph which shows the experimental result of the stress dependence of the drain current of an n channel type and a p channel type field effect transistor. It is a graph which shows the result of having analyzed the influence which the intrinsic stress of the SiN film which encloses a gate electrode from the upper surface gives to the stress of a channel part. It is a graph which shows the result of having analyzed the influence which the film thickness of the SiN film which includes a gate electrode from the upper surface gives to the stress of a channel part. It is a graph which shows the result of having analyzed the influence which the film thickness of silicide has on the stress of a channel part. It is a graph which shows the result of having analyzed the influence which the intrinsic stress of a gate electrode has on the stress of a channel part. It is a graph which shows the result of having analyzed the influence which the oxidation origin stress of STI has on the stress of a channel part. It is a graph which shows the experimental result of the etching rate dependence of SiN film stress. 1 is a schematic view showing a cross section of a semiconductor device according to a first embodiment of the present invention. It is a schematic diagram which shows the cross section of the semiconductor device which is the other 1st Example of this invention. It is a cross-sectional schematic diagram which shows a part of manufacturing process of the semiconductor device which is the other 1st Example of this invention. It is a cross-sectional schematic diagram which shows a part of manufacturing process of the semiconductor device which is the other 1st Example of this invention. It is a cross-sectional schematic diagram which shows a part of manufacturing process of the semiconductor device which is the other 1st Example of this invention. It is a schematic diagram which shows the cross section of the semiconductor device which is 2nd Example of this invention. It is a plane schematic diagram of the semiconductor device which is 2nd Example of this invention. It is a schematic diagram which shows the cross section of the semiconductor device which is 3rd Example of this invention. It is a schematic diagram which shows the cross section of the semiconductor device which is 4th Example of this invention. It is a schematic diagram which shows the cross section of the semiconductor device which is 5th Example of this invention. It is a cross-sectional schematic diagram which shows a part of manufacturing process of the semiconductor device which is 5th Example of this invention. It is a cross-sectional schematic diagram which shows a part of manufacturing process of the semiconductor device which is 5th Example of this invention. It is a cross-sectional schematic diagram which shows a part of manufacturing process of the semiconductor device which is 5th Example of this invention. It is a schematic diagram which shows the cross section of the semiconductor device which is 6th Example of this invention. It is a plane schematic diagram of the semiconductor device which is the 6th example of the present invention. It is a graph which shows the result of having analyzed the stress of the channel part of each generation of gate length. It is a graph which shows the experimental result which showed the difference in the dependence with respect to the stress of the mutual conductance (Gm) by the generation of a field effect transistor. It is a schematic diagram which shows the cross section of the semiconductor device which is 7th Example of this invention. It is a graph which shows the result of having analyzed the influence which the film stress of a side wall has on the stress of a channel part. It is a schematic diagram which shows the cross section of the semiconductor device which is 8th Example of this invention. It is a graph which shows the result of having analyzed the influence which the material of sidewall gives to the stress of a channel part. It is a schematic diagram which shows the cross section of the semiconductor device which is 9th Example of this invention. 1 is a schematic view showing a cross section of an example in which contact plugs, wirings, and the like are formed in a semiconductor device according to a first embodiment of the present invention. It is an electrical circuit diagram of the semiconductor device which is 10th Example of this invention. FIG. 36 is a schematic plan view (a partially enlarged view of FIG. 34) of a semiconductor device according to a tenth embodiment of the present invention. It is a plane schematic diagram of the semiconductor device which is 10th Example of this invention. It is a schematic diagram which shows the cross section of the semiconductor device which is 10th Example of this invention. FIG. 38 is a schematic plan view (a partially enlarged view of FIG. 37) of a semiconductor device according to an eleventh embodiment of the present invention. It is a plane schematic diagram of the semiconductor device which is 11th Example of this invention. It is a schematic diagram which shows the cross section of the semiconductor device which is 11th Example of this invention. It is the cross-sectional schematic diagram which showed a part of manufacturing process of the semiconductor device which is 10th Example of this invention. It is the cross-sectional schematic diagram which showed a part of manufacturing process of the semiconductor device which is 10th Example of this invention. It is the cross-sectional schematic diagram which showed a part of manufacturing process of the semiconductor device which is 10th Example of this invention. It is the cross-sectional schematic diagram which showed a part of manufacturing process of the semiconductor device which is 10th Example of this invention. It is the cross-sectional schematic diagram which showed a part of manufacturing process of the semiconductor device which is 10th Example of this invention.

Explanation of symbols

1, 201 Silicon substrate 2, 202 , 202a to 202j Shallow trench isolation 3, 20, 203 Interlayer insulating film 4, 204 mask 5, ACT , ACT1, ACT2 Active 6, 21, 223 , ML wiring 7, 207 , CONT contact Plug 8, 22 Barrier metal 9, 19, 39, 209 Stress control film
10 , 210 , N 1 , N 2 n-channel field effect transistors 11, 211 , P-WELL p-type wells 12, 13, 212 , 213 n-type source / drains 14, 34, 214 , 234 Gate insulating films 15, 35, 215 , 235 Gate electrode 16, 36, 216 , 236 , 216a, 216b Side wall 17, 18, 37, 217 , 218 silicide
30 , 230 , P 1 , P 2 p-channel field effect transistor 31, 231 n-type well 32, 33, 232 , 233 p-type source / drain 38, 181, 381 silicide 151, 152 a, 152 b gate electrode 191, 192, 193 stress Control film 351, 352 Gate electrode 391, 392, 393 Stress control film

Claims (12)

In a semiconductor device having an n-channel field effect transistor and a p-channel field effect transistor formed on a substrate,
Each of the transistors includes an insulating film that includes a gate electrode and extends to a position adjacent to a source / drain region. The insulating film includes silicon nitride as a main component, and the insulating film of the n-channel field effect transistor. And the thickness of the insulating film of the p-channel field effect transistor are different from each other. In a semiconductor device having an n-channel field effect transistor and a p-channel field effect transistor formed on a substrate,
Each transistor includes an insulating film that includes a gate electrode and extends to a position adjacent to the source / drain region. The insulating film is mainly composed of silicon nitride and is adjacent to the source / drain region of the insulating film. The area of the extending portion differs between the insulating film of the n-channel field effect transistor and the insulating film of the p-channel field effect transistor. In a semiconductor device having an n-channel field effect transistor and a p-channel field effect transistor formed on a substrate,
In the transistor, a silicide region is formed in a source or drain region, and the thickness of the silicide region of the n-channel field effect transistor is larger than the thickness of the silicide region of the p-channel field effect transistor. Semiconductor device. The semiconductor device according to claim 3.
A semiconductor device characterized in that a main component of the silicide region is cobalt silicide (CoSi ₂ ), titanium silicide (TiSi ₂ ), or nickel silicide. In a method for manufacturing a semiconductor device having an n-channel field effect transistor and a p-channel field effect transistor formed on a substrate, the gate electrode of the transistor being made of polycrystalline silicon.
The polycrystalline silicon of the gate electrode of the n-channel field effect transistor is formed by laminating at least two layers,
The method of manufacturing a semiconductor device, wherein the polycrystalline silicon of the gate electrode of the p-channel field effect transistor is formed with a smaller number of layers than the gate electrode of the n-channel field effect transistor. A shallow trench is formed in a substrate, and a silicon oxide film is embedded in the shallow trench, and an n-channel field effect transistor and a p-type region are formed in a region on the substrate separated by the device isolation structure. In a semiconductor device having a channel-type field effect transistor,
A semiconductor device, wherein a distance between a channel portion of the n-channel field effect transistor and the element isolation structure is larger than a distance between a channel portion of the p-channel field effect transistor and the element isolation structure. In a semiconductor device having an n-channel field effect transistor and a p-channel field effect transistor formed on a substrate,
When the film stress of the insulating film including the gate electrode of each transistor and extending to the region adjacent to the source / drain region is tensile stress, the Young's modulus of the insulating film adjacent to the side surface in the longitudinal direction of the gate electrode is The p-channel field effect transistor is smaller than the n-channel field effect transistor,
When the film stress of the insulating film including the gate electrode of each transistor and extending to the region adjacent to the source / drain region is compressive stress, the Young's modulus of the insulating film adjacent to the side surface in the longitudinal direction of the gate electrode is A p-channel field effect transistor is larger than an n-channel field effect transistor. The semiconductor device according to claim 7.
The material of the insulating film having a large Young's modulus of the insulating film adjacent to the side surface in the longitudinal direction of the gate electrode is mainly composed of silicon nitride, and the material of the insulating film having a small Young's modulus is mainly composed of silicon oxide. A semiconductor device. In a semiconductor device having an n-channel field effect transistor and a p-channel field effect transistor formed on a substrate,
A plurality of n-channel field effect transistors and p-channel field effect transistors;
An insulating film having a tensile stress is formed on the n-channel field effect transistor and the p-channel field effect transistor,
In the region located between the first p-channel field effect transistor and the second p-channel field effect transistor adjacent to the first p-channel field effect transistor, the first or second p-channel A semiconductor device, wherein the insulating film thinner than a thickness of the insulating film formed on a type field effect transistor is formed, or the insulating film is not installed. In a semiconductor device having an n-channel field effect transistor and a p-channel field effect transistor formed on a substrate,
A plurality of n-channel field effect transistors and p-channel field effect transistors, and an insulating film having a tensile stress is formed on the n-channel field effect transistors and the p-channel field effect transistors;
The region located between the first p-channel field effect transistor and the second p-channel field effect transistor adjacent to the first p-channel field effect transistor includes the first p-channel field effect transistor. The insulation formed in a region located between a first n-channel field effect transistor corresponding to an effect transistor and a second n-channel field effect transistor corresponding to the second p-channel field effect transistor A semiconductor device, wherein the insulating film thinner than the film is formed or the insulating film is not provided. In a semiconductor device having an n-channel field effect transistor and a p-channel field effect transistor formed on a substrate,
A plurality of n-channel field effect transistors and p-channel field effect transistors;
An insulating film having a compressive stress is formed on the n-channel field effect transistor and the p-channel field effect transistor,
A region located between a first n-channel field effect transistor corresponding to the first p-channel field effect transistor and a second n-channel field effect transistor corresponding to the second p-channel field effect transistor The insulating layer formed in a region located between the first p-channel field effect transistor and the second p-channel field effect transistor adjacent to the first p-channel field effect transistor. A semiconductor device, wherein the insulating film thinner than the film is formed, or the insulating film is not installed. The semiconductor device according to claim 11.
A semiconductor device characterized in that the insulating film is mainly composed of silicon nitride.

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