JP2008203478A - 表示装置とその駆動方法 - Google Patents
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Abstract
【解決手段】閾値補正動作を時分割で複数回繰り返す際に、その期間中において、発光制御トランジスタとサンプリングトランジスタの双方を連動して、閾値補正用の固定電位の期間には道通状態にする一方、映像信号が信号電位の期間には非道通状態にする。複数回に亘る閾値補正期間における各回の閾値補正期間の合間にブートストラップ動作がなされることで閾値補正が破綻してしまうような事態を回避することができる。
【選択図】図6
Description
図1は、本発明に係る表示装置の一実施形態であるアクティブマトリクス型表示装置の構成の概略を示すブロック図である。本実施形態では、たとえば画素の表示素子として有機EL素子を、能動素子としてポリシリコン薄膜トランジスタ(TFT;Thin Film Transistor)をそれぞれ用い、薄膜トランジスタを形成した半導体基板上に有機EL素子を形成してなるアクティブマトリクス型有機ELディスプレイ(以下「有機EL表示装置」と称する)に適用した場合を例に採って説明する。
図2は、図1に示した有機EL表示装置1を構成する本実施形態の画素回路Pの一例を示す図である。なお、表示パネル部100の基板101上において画素回路Pの周辺部に設けられた垂直駆動部103と水平駆動部106も合わせて示している。図3は有機EL素子や駆動トランジスタの動作点を説明する図である。図3Aは、有機EL素子や駆動トランジスタの特性ばらつきが駆動電流Idsに与える影響を説明する図である。
先ず、図2に示す本実施形態の画素回路Pの特徴を説明する上での比較例として、発光制御トランジスタ122,検知トランジスタ124を備えておらず、また、保持容量120は、一方の端子がノードND122に接続され、他方の端子が全画素共通の接地配線Vcath(GND )に接続されている場合での動作について説明する。以下、このような画素回路Pを比較例の画素回路Pと称する。
図3A(1)に示す有機EL素子で代表される電流駆動型の発光素子の電流−電圧(Iel−Vel)特性において、実線で示す曲線が初期状態時の特性を示し、破線で示す曲線が経時変化後の特性を示している。一般的に有機EL素子を始めとする電流駆動型の発光素子のI−V特性は、グラフに示すように時間が経過すると劣化する。
また、駆動トランジスタ121の製造プロセスのばらつきにより、画素回路Pごとに閾値電圧や移動度などの特性変動がある。駆動トランジスタ121を飽和領域で駆動する場合においても、この特性変動により、駆動トランジスタ121に同一のゲート電位を与えても、画素回路Pごとにドレイン電流(駆動電流Ids)が変動し、発光輝度のばらつきになって現れる。
本実施形態の画素回路Pに対する駆動タイミングについて、先ず、定性的な観点から説明する。本実施形態の画素回路Pにおける駆動タイミングとしては、先ず、サンプリングトランジスタ125は、書込走査線104WSから供給された書込駆動パルスWSに応じて導通し、映像信号線106HSから供給された映像信号Vsig をサンプリングして、映像信号Vsig の有効期間の電位である信号電位Vinに対応する情報を駆動電位として保持容量120に保持する。この点は、一般的な画素回路を駆動する場合と同じである。
図4は、本実施形態の画素回路Pにおける比較例の動作を説明するタイミングチャートである。図4では、時間軸tに沿って、書込駆動パルスWS、閾値&移動度補正パルスAZ、および走査駆動パルスDSの波形を表してある。前述の説明から理解されるように、スイッチングトランジスタ122,124,125は、nチャネル型なので各パルスDS,WS,AZがそれぞれハイ(H)レベルのときにオンし、ロー(L)レベルのときにはオフする。なお、このタイミングチャートは、各パルスWS,AZ,DSの波形とともに、映像信号Vsig 並びに駆動トランジスタ121のゲート端Gの電位変化およびソース端Sの電位変化も表してある。
図5は、図4に示した比較例の駆動タイミングにおける閾値補正動作による弊害について説明する図である。ここで、図5は、図4に示した比較例の駆動タイミングにおける複数回に亘る閾値補正期間の一部を拡大して示したタイミングチャートである。
図6は、本実施形態の画素回路の駆動タイミングを説明するタイミングチャートである。図7は、図6に示した本実施形態の駆動タイミングにおける複数回に亘る閾値補正期間の一部を拡大して示したタイミングチャートである。これらのタイミングチャートは、分割閾値補正に伴う閾値補正動作破綻現象の抑制手法を適用したものである。
なお、発光期間Lの開始を規定する走査駆動パルスDSをアクティブHにするタイミングt68を信号書込期間K内に設定すれば(t68μ:図中の点線を参照)、保持容量120に信号電位Vinの情報を書き込んでから、あるいは保持容量120に信号電位Vinの情報を書き込むと同時に、サンプリングトランジスタ125をオンさせたままで発光制御トランジスタ122をオンさせることになる。よって、信号電位Vinの情報を保持容量120に書込みながら、駆動トランジスタ121にドレイン電流を流すことができ、駆動トランジスタ121の移動度に対する補正分を保持容量120に書き込まれる駆動信号に書き加える移動度補正を行なうことができる。
たとえば、回路理論上は「双対の理」が成立するので、画素回路Pに対しては、この観点からの変形を加えることができる。この場合、図示を割愛するが、先ず、図2に示した4TR構成の画素回路Pがnチャネル型の駆動トランジスタ121を用いて構成しているのに対し、pチャネル型の駆動トランジスタ(以下p型駆動トランジスタ121pと称する)を用いて画素回路Pを構成する。これに合わせて、その他のトランジスタ122,124,125もアクティブLの駆動パルスが供給されるpチャネル型にし、また映像信号Vsig の信号電位Vinの極性や電源電圧の大小関係を逆転させるなど、双対の理に従った変更を加える。
Claims (7)
- 駆動電流を生成する駆動トランジスタ、前記駆動トランジスタの出力端に接続された電気光学素子、映像信号の信号電位に応じた情報を保持する保持容量、前記信号電位に応じた情報を前記保持容量に書き込むサンプリングトランジスタ、前記駆動トランジスタの電源供給端と電源線との間に配され前記電気光学素子の発光期間を調整する発光制御トランジスタを具備し、前記保持容量に保持された情報に基づく駆動電流を前記駆動トランジスタで生成して前記電気光学素子に流すことで当該電気光学素子が発光する画素回路が行列状に配置されている画素アレイ部と、
前記サンプリングトランジスタを水平周期で順次制御することで前記画素回路を線順次走査して1行分の各保持容量に映像信号の信号電位に応じた情報を書き込むための書込走査パルスを前記サンプリングトランジスタに出力する書込走査部、前記サンプリングトランジスタによる信号電位の書込動作に合わせて1行分の映像信号を前記映像信号線に供給する水平駆動部を具備する制御部とを備え、
前記制御部は、前記駆動トランジスタの閾値電圧に対応する電圧を前記保持容量に保持するための閾値補正動作用の固定電位が前記駆動トランジスタの制御入力端に供給されるように制御するとともに、前記閾値補正動作を時分割で複数回繰り返すことで、前記保持容量の両端電圧を前記駆動トランジスタの閾値電圧にする際に、複数回に亘る前記閾値補正動作の期間中は、前記固定電位の供給期間に、前記発光制御トランジスタと前記サンプリングトランジスタを連動して導通状態に切り替えて各回の前記閾値補正動作をするように制御する
ことを特徴とする表示装置。 - 前記水平駆動部は、水平走査期間の一部で前記映像信号に前記閾値補正動作用の固定電位を出力する
ことを特徴とする請求項1に記載の表示装置。 - 前記制御部は、前記閾値補正動作に先立って、前記保持容量の両端電圧が前記駆動トランジスタの閾値電圧以上となるように設定する、前記閾値補正動作用の準備動作を行なうように制御する
ことを特徴とする請求項1に記載の表示装置。 - 前記画素回路は、前記保持容量が前記駆動トランジスタの制御入力端と前記出力端との間に配され、前記駆動トランジスタ、前記サンプリングトランジスタ、および前記発光制御トランジスタの他に、前記保持容量の両端電圧が前記駆動トランジスタの閾値電圧以上となるように設定するための基準電位と前記駆動トランジスタの前記出力端との間に配されたスイッチトランジスタを有し、
前記制御部は、前記閾値補正動作用の準備動作時に前記スイッチトランジスタを導通状態にする
ことを特徴とする請求項3に記載の表示装置。 - 前記制御部は、前記閾値補正動作の後、前記駆動トランジスタの移動度に対する補正分を前記保持容量に書き込まれる情報に加えるための移動度補正動作を行なうように制御する
ことを特徴とする請求項1に記載の表示装置。 - 前記制御部は、前記保持容量に前記信号電位に対応する情報が書き込まれた時点で前記サンプリングトランジスタを非導通状態にして前記駆動トランジスタの前記制御入力端への前記映像信号の供給を停止させ、当該駆動トランジスタの前記出力端の電位変動に前記制御入力端の電位が連動する動作を可能にする
ことを特徴とする請求項1に記載の表示装置。 - 駆動電流を生成する駆動トランジスタ、前記駆動トランジスタの出力端に接続された電気光学素子、映像信号の信号電位に応じた情報を保持する保持容量、前記信号電位に応じた情報を前記保持容量に書き込むサンプリングトランジスタ、前記駆動トランジスタの電源供給端と電源線との間に配され前記電気光学素子の発光期間を調整する発光制御トランジスタを具備し、前記保持容量に保持された情報に基づく駆動電流を前記駆動トランジスタで生成して前記電気光学素子に流すことで当該電気光学素子が発光する画素回路の駆動方法であって、
前記制御部は、前記駆動トランジスタの閾値電圧に対応する電圧を前記保持容量に保持するための閾値補正動作用の固定電位が前記駆動トランジスタの制御入力端に供給されるように制御するとともに、前記閾値補正動作を時分割で複数回繰り返すことで、前記保持容量の両端電圧を前記駆動トランジスタの閾値電圧にする際に、複数回に亘る前記閾値補正動作の期間中は、前記固定電位の供給期間に、前記発光制御トランジスタと前記サンプリングトランジスタを連動して導通状態に切り替えて各回の前記閾値補正動作をするように制御する
ことを特徴とする駆動方法。
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- 2008-02-19 CN CN2008100079412A patent/CN101251978B/zh not_active Expired - Fee Related
- 2008-02-20 KR KR1020080015313A patent/KR20080077584A/ko not_active Application Discontinuation
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JP2008224787A (ja) * | 2007-03-09 | 2008-09-25 | Sony Corp | 表示装置及び表示装置の駆動方法 |
US8659522B2 (en) | 2007-03-09 | 2014-02-25 | Sony Corporation | Display apparatus having a threshold voltage and mobility correcting period and method of driving the same |
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US8368681B2 (en) | 2008-10-29 | 2013-02-05 | Sony Corporation | Image display apparatus and method of driving the image display apparatus |
Also Published As
Publication number | Publication date |
---|---|
TW200901127A (en) | 2009-01-01 |
KR20080077584A (ko) | 2008-08-25 |
CN101251978A (zh) | 2008-08-27 |
US8174466B2 (en) | 2012-05-08 |
CN101251978B (zh) | 2010-06-02 |
US20080198103A1 (en) | 2008-08-21 |
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