JP2008299993A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a configuration of a semiconductor device capable of executing an efficient operation test in accordance with the performance level of a memory tester to be used. <P>SOLUTION: A test mode for performing data compression of test output data from a memory core part and transferring the test output data to a data input-output node 50 includes a normal mode and a fine mode, the degree of data compression of which is lower than that of the normal mode. In the normal mode, a test data compression circuit 100 outputs compression data TD0123 compressed to one bit every four bits (TD0 to TD3) of test output data of a plurality of bits as data DQ0. On the other hand, in the fine mode, a parallel-serial conversion circuit 130 converts compression data TD01 and TD23 obtained by compressing every 2 bits (TD0, TD1 and TD2, TD3) of the test output data of the plurality of bits to one bit into one piece of serial data and then sequentially outputs the one piece of serial data as data DQ0. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a test mode for compressing and outputting the number of bits of read data from a memory core.

  In an operation test of a semiconductor memory device typified by a wafer test, whether or not test data read from a memory cell is equal to a predetermined level (expected value) written after writing a predetermined level of data to each memory cell. Whether the memory cell is normal or abnormal is determined.

  At this time, a technique for shortening the usage time of an operation test by compressing a plurality of bits of test data simultaneously read from a memory cell and reducing the number of output bits is disclosed in Japanese Patent Laid-Open No. 5-135600 (hereinafter referred to as “JP-A”). Patent Document 1) or Japanese Patent Application Laid-Open No. 2001-291399 (hereinafter referred to as Patent Document 2) and the like.

  As disclosed in Patent Documents 1 and 2, if the number of I / O pins to be used is reduced by compressing the number of bits of output data at the time of an operation test, the number of objects to be tested that can be simultaneously tested by one memory tester ( Hereinafter, the test co-measurement number) can be increased. As a result, it is possible to reduce the test cost by shortening the time required for the operation test per semiconductor memory device.

In the semiconductor memory device, a redundant circuit for replacing and repairing a defective memory cell row and / or memory cell column is mounted in advance. The semiconductor memory device in which the defective portion is analyzed by the operation test can be made non-defective by replacing a predetermined area on the memory cell array including the defective portion with a normal memory cell by a redundant circuit. Thereby, the product yield can be improved by utilizing the redundant circuit.
JP-A-5-135600 JP 2001-291399 A

  When data compression as disclosed in Patent Documents 1 and 2 is performed at the time of an operation test, identification of a defective portion of a memory cell becomes rough as the degree of compression is increased. On the other hand, in order to avoid a significant increase in test time, replacement repair by a redundant circuit is generally executed in correspondence with a bit range (memory cell region) that can be specified from test data that has been compressed. For example, when a product having a 32-bit I / O configuration is tested by compressing data into 4-bit I / O using an existing data compression technique, I / O is performed every 8 bits among the 32 bits. When a pass / fail judgment is made collectively in units or addresses, and a defect is detected, replacement by a redundant circuit is executed for each unit.

  Thus, the bit range (memory cell area) compressed into 1-bit test data during the operation test coincides with the repair unit by the redundant circuit. For this reason, if the data compression degree during the operation test is increased, the test cost can be reduced by reducing the number of I / O pins required for the operation test, but the redundancy circuit becomes defective as the repair unit becomes coarse. There is a possibility that the yield cannot be reduced because the part cannot be completely replaced.

  The time required for the operation test is also greatly affected by the performance of the memory tester used. In other words, since a high performance memory tester can perform an operation test in synchronization with a high frequency clock, even if the data compression degree in the test mode is low, the time required for the test does not become so long. In this case, if the degree of data compression is lowered, the repair unit can be made finer, and therefore, there is a high possibility that all defective portions can be replaced and repaired by the redundant circuit, so that the yield can be improved.

  However, when testing with a relatively low performance memory tester, if the data compression rate in the operation mode is low, the test co-measurement number cannot be increased. It will rise.

  Thus, the level of data compression during the operation test is in a trade-off relationship between productivity (test cost) and yield. For this reason, when considering the actual situation of the actual production line where the performance of all memory testers is not complete, if the data compression degree at the time of operation test is designed generically, it depends on the performance of the memory tester used, It is difficult to always perform an efficient operation test, and there is a possibility that the test cost increases or the yield decreases.

  On the other hand, considering the performance and production status of the memory tester installed in the production line, if the data compression degree at the time of the operation test is subdivided and designed, the possibility that an efficient operation test can be executed increases. The manufacturing cost increases due to the decrease in design versatility.

  The present invention has been made to solve such problems, and an object of the present invention is to be able to flexibly execute an efficient operation test corresponding to the performance of the memory tester used. It is to provide a configuration of a semiconductor device.

  In summary, the semiconductor memory device according to the present invention includes a memory core unit and a test data compression circuit. The memory core unit includes a plurality of memory cells selected by an address signal, and outputs M-bit (M: integer of 2 or more) data in parallel during an operation test. During the operation test, the test data compression circuit compresses M-bit data output from the memory core unit to L: 1 (L: an integer equal to or less than M and a divisor of M), and (M / L) Bit test data is output. Further, the operation test has a plurality of test modes, and the test data compression circuit includes a selection circuit that variably sets L in accordance with the selected test mode among the plurality of test modes.

  According to an embodiment of the present invention, the plurality of test modes includes a first mode (normal mode) in which L is set to a maximum value L1 (L1: an integer satisfying the condition of L), and L is L2 ( L2: a second mode (fine mode) that satisfies the condition of L and is set to an integer satisfying L1 <L2, and the selection circuit includes a plurality of second modes in the second mode. Test data from the data compression circuit is sequentially output from the same data node at different timings.

  According to another embodiment of the present invention, the plurality of test modes includes a first mode (normal mode) in which L is set to a maximum value L1 (L1: an integer satisfying the condition of L), and L Includes a second mode (fine mode) set to L2 (L2: an integer satisfying the condition of L and L1 <L2), and the selection circuit includes a plurality of modes in the second mode. Based on the test data from the second data compression circuit, one of the three or more voltage levels is selectively output from the data node.

  In the semiconductor memory device, in the test mode in which the M-bit test data output from the memory core unit during the operation test is compressed to 1 bit for every L bits, the operation test is executed with L indicating the data compression degree being variable. Can do. For this reason, at the time of an operation test using a memory tester having a relatively low operation speed, it is possible to suppress an increase in the required test by increasing the data compression degree by the first mode. On the other hand, during an operation test using a memory tester with a high operating speed, the data compression degree is lowered (L is reduced) in the second mode, so that the location where a defect occurs in the memory core can be specified more precisely in the same test time. can do. As a result, by reducing the repair unit, it is possible to increase the number of defects that can be repaired by the redundant circuit and improve the yield.

  In this way, the test data compression circuit designed in common makes the data compression level variable during operation tests that involve data compression, so that an appropriate compression level can be selected according to the performance of the available memory tester. Thus, the operation test can be executed efficiently.

  Embodiments of the present invention will be described below in detail with reference to the drawings. In the following, the same or corresponding parts in the drawings are denoted by the same reference numerals, and detailed description thereof will not be repeated in principle.

[overall structure]
FIG. 1 is a schematic block diagram showing the overall configuration of a semiconductor memory device according to the present invention.

  Referring to FIG. 1, a semiconductor memory device 1000 according to the present invention includes a control circuit 10, an address register 20, a memory core unit 30, a data input / output circuit 40, a data input / output node 50, and a redundant circuit 60. A test data compression circuit 100.

  The control circuit 10 receives a command control signal SCMD given from the outside of the semiconductor memory device 1000 and generates a control signal for controlling the operation of the semiconductor memory device 1000. Command control signal SCMD includes, for example, a row address strobe signal / LAS, a column address strobe signal / CAS, a write enable signal / WE, and the like.

  Address register 20 receives a row address and a column address from the outside of semiconductor memory device 1000, or in addition to this, an address signal ADD for indicating a bank address.

  The control circuit 10 includes a mode register 15. The mode register 15 stores parameters indicating the operating conditions of the semiconductor memory device 1000 and mode selection. For example, the mode register 15 stores information for selecting the column latency indicating the operating condition, the burst length, etc., and the type of the test mode during the operation test. The stored contents of the mode register 15 are written according to a specific bit of the address signal ADD input to the address register 20 in a mode register set command set according to a predetermined combination of command control signals SCMD.

  Based on the mode or parameter value set by mode register 15, control circuit 10 generates a control signal so that semiconductor memory device 1000 operates in accordance with a command instructed by command control signal SCMD, and generates memory core unit 30 and Send to redundant circuit 60.

  In accordance with a control signal from control circuit 10, memory core unit 30 reads a command for reading data from the selected memory cell designated by address signal ADD, a write command for writing data to the selected memory cell, or a data A precharge command or the like for preparing for reading and writing is executed.

  At the time of data reading (read command), output data from the memory core unit 30 is output to the data input / output node 50 via the data input / output circuit 40. At the time of data writing (write command), input data to the data input / output node 50 is written to the memory core unit 30 via the data input / output circuit 40.

  The semiconductor memory device 1000 according to the present invention may be a single memory product or a product mixedly mounted on the same chip as a processor or the like. Therefore, the node to which the command control signal SCMD and the address signal ADD are input and the data input / output node 50 may be pins that are electrically accessible from the outside of the chip, or a processor or the like arranged in the same chip. It may be a wiring such as a bus disposed between the two.

  The redundant circuit 60 is provided to replace defective portions of the memory core unit 30 every predetermined unit. When a defective memory cell is found in the memory core unit 30 in the operation test, a predetermined unit including the defective memory cell is replaced with a normal memory cell in the redundancy circuit 60. Hereinafter, the predetermined unit in which replacement repair by the redundant circuit 60 is performed is also referred to as a repair unit. In other words, when the memory core unit 30 is divided into M bit ranges corresponding to the number of bits (M bits) of test output data read in parallel during an operation test, the repair unit is an operation test without data compression. When replacing and relieving according to the result, each bit range can be matched. On the other hand, in the case of replacing and relieving according to the operation test result of compressing to 1 bit of test data for every L bits (L <M) of the test output data (data compression degree L: 1), the relief unit is the above bit range. Of L.

  Information (defective address) indicating a predetermined unit including a defective memory cell, which is found during the operation test, is written in the redundancy circuit 60 and stored in a nonvolatile manner. When the predetermined unit corresponding to the defective address is designated by the address signal ADD, the control circuit 10 replaces the predetermined unit in the memory core unit 30 with the data input to the redundant circuit 60. The operation of the semiconductor memory device 1000 is controlled so as to execute the output.

  The test data compression circuit 100 is configured to be able to execute a test mode in which data compression is performed on output data (test data) from the memory core unit 30 and then transmitted to the data input / output node 50 during an operation test. . Here, an outline of data compression will be described with reference to FIGS. 2 and 3. Hereinafter, in FIG. 2 and FIG. 3, a section for every 4 bits of the plurality of bit data output in parallel from the memory core unit 30 will be representatively described. Note that data compression may be performed in units of I / O output as shown in FIG. 3, or may be performed in units of addresses.

  Referring to FIG. 2, a plurality of memory cells 32 are arranged in a matrix in memory core unit 30. Normally, 4 bits of the plurality of bit data (test output data) read out from the memory core unit 30 through the sense amplifier 34 and the preamplifier 36 are supplied as data DQ0 to DQ3 from separate data input / output nodes 50, respectively. Is output.

  On the other hand, as shown in FIG. 3, in the test mode in which data compression is performed, a plurality of bits of test output data read from the memory core unit 30 is sent to the multiplexer 101 provided in the test data compression circuit 100 every 4 bits. Is compressed into 1-bit test data.

  This compressed data is set to “1” when all 4 bits of the test output data of the memory core unit 30 match the expected value, otherwise, at least 1 bit is different from the expected value. Is set to “0”.

FIG. 4 is a waveform example of an operation test at the time of data compression shown in FIG.
Referring to FIG. 4, it is assumed that semiconductor memory device 1000 operates with a column latency of 2 and a burst length of 1 as an example.

  When a read command (READ) is executed and inputted during an operation test, test data in which 4 bits are compressed to 1 bit is output as data DQ0 in synchronization with the external clock EXTCLK from the memory tester. In the example shown in FIG. 4, four test data TDa to TDd are continuously output corresponding to four consecutive read commands. The value of the output test data is “1” indicating normal with respect to TDa, TDb, and TDd, whereas the test data TDc is “0” indicating failure.

  Therefore, it can be seen that there is a defect in one of the memory cells from which the 4-bit data output from the memory core unit 30 is read by the third read command. Therefore, it can be recognized that the predetermined division in the memory core unit 30 corresponding to these 4-bit data is defective.

  By performing the operation test with such data compression, it is possible to comprehensively detect the result of the 4-bit test output data from the memory core unit 30 using one data input / output node 50. As a result, the number of pins required for the operation test is reduced, so the number of semiconductor memory devices that can be tested in parallel with a common memory tester (that is, the test co-measurement number) can be increased, and the test cost can be increased. Can be reduced.

  On the other hand, when data compression is performed, if the value of the obtained test data is “0” (defective), it takes an enormous amount of time to perform an operation test for specifying a defective portion. Therefore, replacement redundancy is generally performed by the redundancy circuit 60 using the bit range corresponding to one bit of the test data after compression as a repair unit. In this case, since the unit of repair by the redundant circuit 60 is increased by performing data compression, if the degree of data compression is increased during the operation test, the number of defects that can be repaired by the redundant circuit 60 of the same scale is relatively Will be reduced.

  Therefore, in semiconductor memory device 1000 according to the present invention, the data compression degree by test data compression circuit 100 is made variable in accordance with the performance of the memory tester. The configuration of the semiconductor device 1000 other than the test data compression circuit 100 is not particularly limited, and the present invention can be applied to various types of memories. Further, as described above, the semiconductor memory device 1000 according to the present invention is not limited to a single memory product, and may be a memory portion of an LSI product in which a processor, a memory, and the like are mounted on the same chip.

[Embodiment 1]
In the following embodiments, a configuration example of a test data compression circuit in which the data compression degree at the time of an operation test involving data compression is made variable will be described.

  FIG. 5 is a block diagram showing a configuration of test data compression circuit 100 according to the first embodiment of the present invention.

  In the following, in semiconductor memory device 1000 according to the present invention, the operation test to which data compression is applied is based on the first test mode (hereinafter referred to as “normal mode”) in which the data compression degree is a normal value, and the normal mode. Includes a second test mode (hereinafter referred to as “fine mode”) for reducing the data compression degree. Hereinafter, as an example, in the normal mode, the data compression degree is set to 4: 1, and 4 bits of the test output data from the memory core unit 30 are compressed to 1 bit of the test data. In the fine mode, the data compression degree is set to 2: 1, and every 2 bits of test output data from the memory core unit 30 is compressed to 1 bit of test data.

  Selection between the normal mode and the fine mode is indicated by test mode signals TMBT1 and TMBT2. In the normal mode, the test mode signal TMBT1 is activated while TMBT2 is deactivated. On the contrary, in the fine mode, the test mode signal TMBT2 is activated while TMBT1 is deactivated.

  For example, test mode signals TMBT1 and TMBT2 are generated according to the stored contents of mode register 15. In other words, when the operation test is executed, the mode register set command is executed to select whether the operation test is in the normal mode or the fine mode. Alternatively, the activation of the test mode signals TMBT1 and TMBT2 may be controlled according to a control signal input from the outside during an operation test.

  In addition to the normal mode and the fine mode, a test mode for executing an operation test without data compression may be further provided. For example, in such a test mode, data compression by the test data compression circuit 100 can be stopped in response to deactivation of both TMBT1 and TMBT2. In this case, each bit of the test output data from the memory core unit 30 is output from each data input / output node 50 as in the normal operation.

  As described above, in the illustrated semiconductor memory device 1000, the maximum value of the data compression degree at the time of the operation test is 4: 1. Therefore, hereinafter, a configuration of the test data compression circuit 100 that outputs test data corresponding to the 4 bits TD0 to TD3 of the test output data from the memory core unit 30 will be described. In other words, depending on the number of bits of test output data from the memory core unit 30, a plurality of test data compression circuits 100 described below are provided in parallel, regardless of the number of output bits from the memory core unit 30. The present invention can be applied.

  Referring to FIG. 5, test data compression circuit 100 includes multiplexers 102 and 104, multiplexer 110, internal clock generation circuit 120, parallel / serial conversion circuit 130, selection circuit 150, and output circuit 170. Of the constituent elements of the test data compression circuit 100, at least the parallel-serial conversion circuit 130 and the output circuit 170 are not dedicated elements for the test data output configuration, but are the data input / output circuit shown in FIG. It is also possible to share with 40.

  The multiplexer 102 generates compressed data TD01 based on the comparison result between the test output data TD0, TD1 from the memory core unit 30 and the expected value (1/0). The compressed data TD01 is set to “1” when both the test output data TD0 and TD1 match the expected value, and set to “0” when at least one of the test output data TD0 and TD1 is different from the expected value. Is done.

  Similarly, the multiplexer 104 generates compressed data TD01 based on the comparison result between the test output data TD2 and TD3 from the memory core unit 30 and the expected value (1/0). The compressed data TD23 is set to “1” when both the test output data TD2 and TD3 match the expected value, and set to “0” when at least one of the test output data TD2 and TD3 is different from the expected value. Is done.

  The multiplexer 110 generates compressed data TD0123 based on the compressed data TD01 from the multiplexer 120 and the compressed data TD23 from the multiplexer 104. The compressed data TD0123 is set to “1” when both the compressed data TD01 and D23 are “1”, and is set to “0” otherwise. That is, the compressed data TD0123 is set to “1” when all the test output data TD0 to TD3 match the expected value, and when at least one of the test output data TD0 to TD3 does not match the expected value. Set to “0”.

  Internal clock generation circuit 120 generates internal clock CLKP in response to the rising edge of external clock EXTCLK from the memory tester. Furthermore, internal clock generation circuit 120 further generates internal clock CLKN in response to the falling edge of external clock EXTCLK when test mode signal TMBT2 is activated, that is, in the fine mode.

  The parallel-serial conversion circuit 130 is configured to receive parallel bit data and output the parallel bit data serially one bit at a time in response to an input internal clock. That is, the parallel-serial conversion circuit 130 shown in FIG. 5 receives the compressed data TD01, TD23 from the multiplexers 102, 104 in parallel in the fine mode, and converts it into 1-bit serial data in response to the internal clocks CLKP, CLKN. Convert and output.

  The selection circuit 150 selects 4: 1 compressed data RSN (that is, compressed data TD0123) corresponding to the normal mode from the multiplexer 110 and 2: 1 compressed data RSF (corresponding to the fine mode from the parallel-serial conversion circuit 130). That is, in response to the compressed data TD01 or TN23), one of the compressed data corresponding to the selected test mode is selectively output.

  The output circuit 170 outputs the compressed data RSN (TD0123) or RSF (TD01, TD23) output by the selection circuit 150 as data DQ0 from the data input / output node 50. That is, the output circuit 170 corresponds to one of two predetermined voltage levels (high level / low level) depending on whether the compressed data from the selection circuit 150 is “1” or “0”. It functions as an output buffer for driving the data input / output node 50 with a voltage to be applied.

  In the normal mode in which test mode signal TMBT1 is activated, selection circuit 150 outputs compressed data RSN corresponding to the normal mode to output circuit 170, while outputting compressed data RSF corresponding to the fine mode to output circuit 170. To do. Thus, since the compressed data RSN output in the normal mode is compressed by the multiplexers 102, 104, and 110, the “first data compression circuit” in the present invention is configured by the multiplexers 102, 104, and 110. Is done. Similarly, since the compressed data RSF output in the fine mode is compressed by the multiplexers 102 and 104, the multiplexers 102 and 104 constitute the “second data compression circuit” in the present invention. Note that the increase in circuit area can be suppressed by using the multiplexers 102 and 104 for data compression in each of the fine mode and the normal mode.

  Next, the data output mode of test data compression circuit 100 according to the first embodiment in the fine mode and the normal mode will be described using FIG. 6 and FIG.

  Referring to FIG. 6, in the fine mode, test mode signal TMBT2 is activated while test mode signal TMBT1 is deactivated. Internal clock generation circuit 120 generates internal clocks CLKP and CLKN in response to the rising edge and falling edge of external clock EXTCLK.

  In the fine mode, the selection circuit 150 outputs compressed data TD01 and TD23 transmitted from the parallel-serial conversion circuit 130 as serial data synchronized with the internal clocks CLKP and CLKN. Thus, test data compression circuit 100 compresses data DQ0 (test data) from the same data input / output node 50 in a data compression ratio of 2: 1 in response to the rising edge and falling edge of external clock EXTCLK. Data TD01 and compressed data TD23 are sequentially output. That is, in the fine mode, a plurality of test data generated by lowering the compression degree than in the normal mode is output from the same data input / output node 50 in a time division manner without lowering the test coincidence number. Can do.

  On the other hand, referring to FIG. 7, in the normal mode, test mode signal TMBT1 is activated while test mode signal TMBT2 is deactivated. The internal clock CLKP is generated in response to the rising edge of the external clock EXTCLK, while the internal clock CLKN in response to the falling edge of the external clock EXTCLK is not generated.

  In the normal mode, the selection circuit 150 outputs the compressed data TD0123 from the multiplexer 110. Thereby, the test data compression circuit 100 outputs compressed data TD0123 having a data compression degree of 4: 1 in synchronization with the external clock EXTCLK as data DQ0 (test data) at the time of the operation test. Since the data compression degree is high, the test data output frequency is lower in the normal mode than in the normal mode.

  On the other hand, in the fine mode shown in FIG. 6, since the output frequency of the test data is high, an operation test by a high performance tester having a relatively high operation speed is required. On the other hand, in the normal mode, an operation test can be performed by a tester (normal tester) having a relatively low operation speed.

  Therefore, when the high-performance tester is used, the compression of the test data can be reduced without lowering the test coincidence by selecting the fine mode as shown in FIG. As a result, the defect occurrence region can be more precisely identified as compared with the normal mode without increasing the test time, so that the repair unit by the redundant circuit 60 can be reduced. As a result, it can be expected that the yield can be improved by relatively increasing the number of defects that can be remedied by the redundant circuit 60.

  On the other hand, when the normal tester is used, it is possible to obtain an operation test in which an increase in the time required for the test is suppressed by increasing the degree of compression by selecting the normal mode as shown in FIG.

  As described above, by providing a mechanism for changing the data compression degree at the time of the operation test involving data compression, the test data compression circuit 100 designed in common can be used in accordance with the performance of the usable memory tester. The degree of compression can be selected, and an efficient operation test can be flexibly executed.

  Therefore, it is possible to test in fine mode by introducing a high-performance tester based on the time required for testing by a normal tester realized by securing test co-measurements in normal mode. When a situation occurs in which the production situation changes and a test time can be secured, the yield can be improved by changing the compression degree.

  In addition, since the compression mode is lowered by switching the test mode signals TMBT1 and TMBT2, it is possible to increase the analysis accuracy for specifying the location where the defect occurs and reduce the repair unit. For this reason, it is not necessary to prepare a dedicated test tool for increasing the analysis accuracy, and the analysis accuracy can be increased without changing the test coincidence with the equipment at the time of mass production. Is also effective.

  In addition, the semiconductor memory device 1000 operates normally as a DDR-SDRAM (Double Data Rate-Synchronous Dynamic Random Access Memory) and performs parallel-serial conversion on data read in parallel from the memory core unit 30 and outputs the data to the outside. In some cases, the parallel-serial conversion circuit 130 can be used in common with the data output configuration (data input / output circuit 40) during normal operation, so the configuration as shown in FIG. 5 is relatively simple. Can be realized.

  On the other hand, in a semiconductor memory device that does not execute parallel-serial conversion during normal operation, the test data compression circuit 100 can be configured without the arrangement of the parallel-serial conversion circuit 130 as shown in FIG.

  Referring to FIG. 8, test data compression circuit 100 # is different from the configuration of test data compression circuit 100 shown in FIG. The difference is that a selection circuit 150 # is provided instead. Since the circuit configuration of other parts is the same as that of FIG. 5, detailed description will not be repeated.

  Selection circuit 150 # includes selection switches 151-153, and controls on / off of selection switches 151-153 in accordance with internal clocks CLKP, CLKN and test mode signals TMBT1, TMBT2. The selection switch 151 is provided between the multiplexer 110 and the output circuit 170. The selection switch 152 is provided between the multiplexer 102 and the output circuit 170. The selection switch 153 is provided between the multiplexer 104 and the output circuit 170.

  When both test mode signals TMBT1 and TMBT2 are inactivated, selection circuit 150 # turns off each of selection switches 151-153. On the other hand, in the normal mode in which test mode signal TMBT1 is activated, selection circuit 150 # turns on selection switch 151 and turns off selection switches 152 and 153. As a result, in the normal mode, as shown in FIG. 7, the compressed data TD0123 output from the multiplexer 110 is output from the data input / output node 50 as data DQ0.

  On the other hand, in fine mode in which test mode signal TMBT2 is activated, selection circuit 150 # turns selection switch 151 off, while selection switches 152 and 153 are alternately turned on in response to internal clocks CLKP and CLKN. Specifically, the selection switch 152 is turned on in response to the activation of the internal clock CLKP, while the selection switch 153 is turned off. On the other hand, when the internal clock CLKN is activated, the selection switch 153 is turned on while the selection switch 152 is turned off.

  Thus, as shown in FIG. 6, in the fine mode, in response to the rising edge and falling edge of external clock EXTCLK, compressed data TD01 and TD23 are output from data input / output node 50 as data DQ0, respectively. The

  Thus, the configuration of test data compression circuit 100 # shown in FIG. 8 also provides a semiconductor memory device that has the same effect as that provided by test data compression circuit 100 according to the first embodiment shown in FIG. It is possible to realize.

[Embodiment 2]
In the second and subsequent embodiments, other configuration examples of the test data compression circuit will be sequentially described. That is, the semiconductor memory device according to the following embodiment has a configuration in which the test data compression circuit 100 in FIG. 1 is replaced with the test data compression circuit according to each embodiment, and other parts are the same as those in FIG. is there. Therefore, in each of the following embodiments, the configuration and operation of the test data compression circuit will be described focusing on differences from the first embodiment.

  FIG. 9 is a block diagram showing a configuration of the test data compression circuit according to the second embodiment of the present invention.

  Referring to FIG. 9, test data compression circuit 100a according to the second embodiment has external clock EXTCLK and parallel / serial conversion circuit 130 as compared with the configuration of test data compression circuit 100 shown in FIG. The difference is that an external control signal EXTDQM input from the signal input pin 6 is input. Parallel serial conversion circuit 130 outputs compressed data TD01 from multiplexer 102 in response to the rising edge of external clock EXTCLK for compressed data TD01 and TD23 received in parallel, and in response to an input of external control signal EXTDQM. The compressed data TD23 from the multiplexer 104 is output.

  That is, in test data compression circuit 100a, the trigger for switching the output of compressed data in parallel-serial conversion circuit 130 is different from that in test data compression circuit 100 according to the first embodiment.

  External control signal EXTDQM is shown as a representative example of a control signal that is not used during an operation test (wafer test). For example, at the time of an operation test involving data compression, the mask control function cannot be checked. Therefore, the signal input pin 6 for inputting the external control signal EXTDQM instructing the data mask becomes an unnecessary pin.

  Therefore, test data compression circuit 100a according to the second embodiment uses a signal input pin 6 that is not used at the time of an operation test to input a signal that specifies the switching timing of compressed data from a memory tester as a trigger. . Thereby, it is possible to specify the switching timing of the compressed data in the fine mode from the outside of the semiconductor memory device 1000, that is, from the memory tester.

  10 and 11 show data output modes in the fine mode and in the normal mode of test data compression circuit 100a according to the second embodiment.

  Referring to FIG. 10, in the fine mode, compressed data TD01 is output in response to a rising edge of external clock EXTCLK after the elapse of a predetermined column latency after generation of a read command (READ). Then, in response to the input of the external control signal EXTDQM from the outside of the semiconductor memory device 1000 to the signal input pin 6, the output of the parallel-serial conversion circuit 130 is switched from the compressed data TD01 to the compressed data TD23. Thus, the compressed data TD01 and TD23 having a compression ratio of 2: 1 are sequentially output from the same data input / output node 50 (corresponding to the data DQ0) in such a manner that the contents of the data DQ0 are switched at the timing specified by the external control signal EXTDQM. Is done.

  Referring to FIG. 11, in the normal mode, the switching instruction of data DQ0 as in the fine mode is unnecessary, so external control signal EXTDQM is not used and the level is fixed. Therefore, in the normal mode, as shown in FIG. 7, the compressed data TD0123 having the compression ratio of 4: 1 is the data input / output node 50 by the number of clocks corresponding to the burst length at the timing synchronized with the external clock EXTCLK. Is output as data DQ0.

  Further, test data compression circuit 100a according to the second embodiment can be realized using selection circuit 150 # shown in FIG. 8, that is, without providing parallel-serial conversion circuit 130.

  FIG. 12 is a block diagram showing a modification of the configuration of the test data compression circuit according to the second embodiment of the present invention.

  Referring to FIG. 12, test data compression circuit 100a # is different from the configuration of test data compression circuit 100a shown in FIG. The difference is that a selection circuit 150 # is provided instead. Since the circuit configuration of other parts is the same as that of test data compression circuit 100a, detailed description will not be repeated.

  Selection circuit 150 # includes selection switches 151-153 similar to those shown in FIG. The selection switch 151 is controlled in the same manner as in FIG. 8, and is turned on in the normal mode and turned off in the fine mode. On the other hand, on / off switching of selection switches 152 and 153 that are alternately turned on and off in the fine mode is executed in response to the rising edge of external clock EXTCLK and the input edge of external control signal EXTDQM.

  In this way, it is possible to implement test data compression circuit 100a # that executes test data output in the same manner as test data compression circuit 100a according to the second embodiment without providing parallel-serial conversion circuit 130.

  As described above, the configuration of test data compression circuit 100a # shown in FIG. 12 also provides a semiconductor memory device that has the same effect as that provided by test data compression circuit 100a according to the second embodiment shown in FIG. It is possible to realize.

[Embodiment 3]
FIG. 13 is a block diagram showing a configuration of test data compression circuit 100b according to the third embodiment.

  Referring to FIG. 13, test data compression circuit 100 b according to the third embodiment replaces external control signal EXTDQM with respect to parallel-serial conversion circuit 130 as compared with test data compression circuit 100 a shown in FIG. 9. The difference is that the test signal WTPS input from the test dedicated pin 7 is input. Since the other configuration is similar to that of test data compression circuit 100a, detailed description will not be repeated.

  The test-dedicated pins 7 can be electrically contacted from the outside of the semiconductor memory device 1000 in the wafer state, but cannot be contacted from the outside after product molding and are not used.

  That is, also in the test data compression circuit 100b, the switching timing of the compressed data TD01 and TD23 in the parallel-serial conversion circuit 130 can be set by the test signal WTPS input from the test dedicated pin 7.

  14 and 15 show data output modes in the fine mode and in the normal mode of test data compression circuit 100b according to the third embodiment.

  Referring to FIG. 14, in the fine mode, compressed data TD01 is output in response to a rising edge of external clock EXTCLK after the elapse of a predetermined column latency after generation of a read command (READ). Then, in response to the input of the test signal WTPS to the test dedicated pin 7 from the outside of the semiconductor memory device 1000, the output of the parallel-serial conversion circuit 130 is switched from the compressed data TD01 to the compressed data TD23. Thus, the compressed data TD01 and TD23 having a compression ratio of 2: 1 are sequentially output from the same data input / output node 50 (corresponding to the data DQ0) in such a manner that the contents of the data DQ0 are switched at the timing specified by the test signal WTPS. The

  On the other hand, as shown in FIG. 15, in the normal mode, the test signal WTPS is not inputted, and in the same way as in FIG. 7 or FIG. 11, in response to the external clock EXTCLK, compression is performed by the number of clocks corresponding to the burst length. The compressed data TD0123 having a degree of 4: 1 is output from the data input / output node 50 as data DQ0. Output as data DQ0.

  The test data compression circuit 100b according to the third embodiment can also be realized without providing the parallel-serial conversion circuit 130.

  FIG. 16 is a block diagram showing a modification of the configuration of the test data compression circuit according to the third embodiment of the present invention.

  Referring to FIG. 16, test data compression circuit 100b # is different from the configuration of test data compression circuit 100b shown in FIG. The difference is that a selection circuit 150 # is provided instead. Since the circuit configuration of the other parts is the same as that of test data compression circuit 100b, detailed description will not be repeated.

  Selection circuit 150 # differs from selection circuit 150 # shown in FIG. 12 only in that it operates in response to test signal WTPS input to test dedicated pin 7 instead of external control signal EXTDQM. Therefore, on / off switching of selection switches 152 and 153 is executed in response to the rising edge of external clock EXTCLK and the input edge of test signal WTPS.

  As described above, it is possible to realize test data compression circuit 100b # for executing test data output similarly to test data compression circuit 100b according to the third embodiment without providing parallel-serial conversion circuit 130.

  As described above, the configuration of test data compression circuit 100b # shown in FIG. 16 also provides a semiconductor memory device that has the same effect as that provided by test data compression circuit 100b according to the third embodiment shown in FIG. It is possible to realize.

  As described above, also in the test data compression circuit 100b according to the third embodiment, a plurality of items generated by lowering the degree of compression than in the normal mode in the fine mode, similarly to the test data compression circuit 100a according to the second embodiment. Can be performed at a timing according to an input signal from the outside of the semiconductor memory device 1000 (typically a memory tester) when the test data is output from the same data input / output node 50 in a time division manner. It becomes like this.

  In particular, in the semiconductor memory device according to the third embodiment, by performing an operation test using a dedicated pin during a wafer test, it is possible to prevent such an input signal from being erroneously input during a product after molding.

[Embodiment 4]
FIG. 17 is a schematic block diagram showing the configuration of the test circuit according to the fourth embodiment of the present invention.

  Referring to FIG. 17, test data compression circuit 100c according to the fourth embodiment has an internal clock generation circuit 120 in any of the normal mode fine mode as compared with the configuration of test data compression circuit 100 shown in FIG. The difference is that only the internal clock CLKP responding to the rising edge of the external clock EXTCLK is generated, and the delay circuit 125 is further provided.

  Delay circuit 125 inputs delay clock CLKPD by delaying internal clock CLKP generated by internal clock generation circuit 120 for a predetermined time in the fine mode in which test mode signal TMBT2 is activated. The parallel-serial conversion circuit 130 receives the internal clock CLKP and the delay clock CLKPD.

  The parallel-serial conversion circuit 130 is configured to operate in response to the delay clock CLKPD instead of the internal clock CLKN, as compared with the configuration of FIG. Thereby, switching of the compressed data TD01 and the compressed data TD23 in the parallel-serial conversion circuit 130 is executed in response to the delay clock CLKPD. Since the configuration of other parts of test data compression circuit 100c is the same as that of test data compression circuit 100, detailed description will not be repeated.

  18 and 19 show data output modes in the fine mode and in the normal mode of test data compression circuit 100c according to the fourth embodiment.

  Referring to FIG. 18, in the fine mode, delay circuit 125 generates delay clock CLKPD obtained by delaying internal clock CLKP for a predetermined time. The delay time by delay circuit 125 is set corresponding to a time shorter than one cycle of external clock EXTCLK, preferably a half cycle of external clock.

  The parallel-serial conversion circuit 130 switches the compressed data in response to the delay clock CLKPD, so that in the fine mode, the compressed data TD01 and TD23 are switched at a timing in response to the delay clock CLKPD.

  Thus, the compressed data TD01 and TD23 having a compression ratio of 2: 1 are sequentially output from the same data input / output node 50 (corresponding to data DQ0) in such a manner that the contents of the data DQ0 are switched at a timing in response to the delay clock CLKPD. .

  On the other hand, in the normal mode shown in FIG. 19, the generation of the delay clock CLKPD is stopped. Similarly to FIG. 7, FIG. 11, or FIG. 15, the compressed data TD0123 having a compression ratio of 4: 1 is output as data DQ 0 from the data input / output node 50 by the number of clocks corresponding to the burst length.

  In test data compression circuit 100c according to the fourth embodiment, it is not necessary to generate two internal clocks for both the rising edge and falling edge of external clock EXTCLK, so that the current consumption of internal clock generation circuit 120 is reduced. Can do.

  That is, the test data compression circuit 100c can realize the same fine mode as in the first embodiment with lower power consumption than the test data compression circuit 100a. However, if the delay time of the clock by the delay circuit 125 is inappropriate, there is a possibility that the test data cannot be acquired correctly by the memory test. Therefore, the delay time is set to an appropriate value (for example, 1/2 cycle of the external clock EXTCLK). ) Must be set. Therefore, it is preferable that the delay time by the delay circuit 125 can be variably adjusted according to the stored contents set in the mode register 15 or the control signal input from the outside during the operation test.

  Test data compression circuit 100c according to the fourth embodiment can also be realized using selection circuit 150 # shown in FIGS. 8, 12, etc., that is, without providing parallel-serial conversion circuit 130.

  FIG. 20 is a block diagram showing a modification of the configuration of the test data compression circuit according to the fourth embodiment of the present invention.

  Referring to FIG. 20, test data compression circuit 100c # is different from test data compression circuit 100c shown in FIG. The difference is that a selection circuit 150 # is provided instead. Since the circuit configuration of other parts is the same as that of test data compression circuit 100c, detailed description will not be repeated.

  Selection circuit 150 # includes selection switches 151 to 153 similar to those shown in FIG. The selection switch 151 is controlled in the same manner as in FIG. 8 and the like, and is turned on in the normal mode and turned off in the fine mode. On the other hand, on / off switching of selection switches 152 and 153 that are alternately turned on and off in the fine mode is executed in response to internal clock CLKP and its delayed clock CLKPD.

  In this way, it is possible to implement test data compression circuit 100c # that executes test data output similarly to test data compression circuit 100c according to the fourth embodiment, without providing parallel-serial conversion circuit 130.

  As described above, the configuration of test data compression circuit 100c # shown in FIG. 20 also provides a semiconductor memory device that has the same effect as that provided by test data compression circuit 100c according to the fourth embodiment shown in FIG. It is possible to realize.

[Embodiment 5]
In the fifth embodiment, as in the fourth embodiment, another configuration example of the test data compression circuit using the internal clock corresponding to only one edge of the external clock EXTCLK will be described.

  FIG. 21 is a block diagram showing a configuration of a test data compression circuit according to the fifth embodiment of the present invention.

  Referring to FIG. 21, test data compression circuit 100d according to the fifth embodiment has an internal clock generation circuit 120 in which only the rising edge of external clock EXTCLK is compared with the configuration of test data compression circuit 100 according to the first embodiment. The difference is that only the internal clock CLKP responding to is generated and the selection circuit 150 is configured to operate in response to the burst reset signal BRST from the burst counter 190.

  Further, burst counter 190 changes the generation timing of burst reset signal BRST between the normal mode and the fine mode in response to test mode signals TMBT1 and TMBT2.

  Burst counter 190 is determined by column latency CL and burst length BL when a read (READ) command is generated based on column latency CL and burst length BL set in mode register 15 and external clock EXTCLK. The burst reset signal BRST is turned on after a predetermined clock cycle has elapsed. Since the configuration of the other parts of test data compression circuit 100d is the same as that of test data compression circuit 100, detailed description will not be repeated.

  FIG. 22 is an operation waveform diagram illustrating a data output mode in each of the normal mode and the fine mode of the test data compression circuit according to the fifth embodiment of the present invention.

  Referring to FIG. 22, in the fine mode, the generation timing of burst reset signal BRST is a predetermined clock corresponding to the increased number of bits of test data output from the same data input / output node 50 as compared to the normal mode. Shifted by the number. As described above, the present embodiment exemplifies a configuration in which 1-bit test data is output from the same data input / output node 50 in the normal mode while 2-bit test data is output in the fine mode. Therefore, the increased number of bits is 1 bit. Therefore, in the fine mode, the generation timing of the burst reset signal BRST is delayed by one clock cycle as compared with the normal mode.

  On the other hand, in the normal mode, the burst reset signal BRST is turned on after one clock cycle has elapsed since the test data was output corresponding to the burst length BL = 1.

  Therefore, according to the test data compression circuit 100d according to the fifth embodiment, in the normal mode, as shown in the first to fourth embodiments, at the same timing as that shown in FIGS. Compressed data TD0123 having a degree of compression of 4: 1 can be output from the data input / output node 50. Further, in the fine mode, as shown in FIG. 22, compressed data TD01 and TD23 having a compression ratio of 2: 1 are sequentially output from the same data input / output node 50 (corresponding to data DQ0) in synchronization with the external clock EXTCLK. Can do.

  In test data compression circuit 100d according to the fifth embodiment, the number of clock cycles required to output test data having the same number of bits in the fine mode is increased as compared with the test data compression circuit according to the first to fourth embodiments. The output frequency of test data is the same as that in the normal mode.

  Therefore, according to the test data compression circuit 100d according to the fifth embodiment, the operation test in the fine mode can be executed as it is even by the relatively low performance normal memory tester to which the normal mode is applied. That is, according to the test data compression circuit 100d according to the fifth embodiment, even in a situation where only the normal tester can be used, the test data compression circuit 100d is suitable for an application in which the normal mode and the fine mode are switched according to the available test time. .

[Embodiment 6]
Of the test data compression circuits according to the first to fifth embodiments described so far, in the second and third embodiments, the test data switching timing in the fine mode is directly set from the outside of the semiconductor memory device 1000, that is, from the memory tester. It is possible to specify. However, in other test data compression circuits according to the first, fourth, and fifth embodiments, the test data (compressed data) is switched based on the internal clock. Therefore, a signal for notifying the outside of semiconductor memory device 1000 of this switching timing. Is preferably generated. In the sixth embodiment, a circuit configuration for generating such a notification signal together with test data will be described.

  FIG. 23 is a block diagram showing a configuration for generating a test data output timing notification signal included in the test data compression circuit according to the sixth embodiment. That is, the test data compression circuit according to the sixth embodiment is not shown in its entire configuration, but the circuit configuration shown in FIG. 23 is added to the configuration of the test data compression circuits 100, 100c, and 100d according to the first, fourth, and fifth embodiments. It is realized by adding.

  Referring to FIG. 23, latency counter 205 receives output of a read command (READ) and generates output enable signal OE after elapse of a predetermined column latency CL.

  DQS generation circuit 200 generates data strobe signal DQS to generate an output timing notification signal for test data in response to test mode signals TMBT1 and TMBT2 and internal clocks CLKP and CLKN (or CLKPD). Data strobe signal DQS is output from the outside (memory tester) of semiconductor memory device 1000 to signal pin 9 that can be electrically contacted, at least during an operation test. In the DDR-SDRM described above, a dedicated pin for the data strobe signal DQS is provided, so that it can be used as the signal pin 9.

  As shown in FIGS. 24 and 25, the DQS generation circuit 200 generates a data strobe signal so that the signal level changes in accordance with the output of the test data (compressed data) described in the first, fourth, and fifth embodiments. Generate DQS.

  Referring to FIG. 24, in the fine mode in which test mode signal TMBT2 is activated, DQS generation circuit 200 transitions the level of data strobe signal DQS in response to internal clocks CLKP and CLKN (or CLKPD).

  On the other hand, referring to FIG. 25, in the normal mode in which test mode signal TMBT1 is activated, DQS generation circuit 200 changes the level of data strobe signal DQS that changes the level in response to the generation of internal clock CLKP. .

  With this configuration, according to the test data compression circuit according to the sixth embodiment, a plurality of bits output in a time division manner from the same data input / output node 50 in synchronization with the internal clock in the fine mode. Test data switching timing can be notified to the outside of the semiconductor memory device 1000 by a notification signal (typically, a data strobe signal DQS) output from a predetermined signal pin 9. This improves the convenience of the operation test.

[Embodiment 7]
In the first to sixth embodiments described so far, binary digital data of “0” or “1” is output from the data input / output node 50 as test data indicating an operation test result. Therefore, in order to maintain the test co-measurement number, it is necessary to have a configuration in which a plurality of bits of test data are output from the same data input / output node 50 in a time division manner in the fine mode.

  On the other hand, in the seventh embodiment, the test data output from the data input / output node 50 in the fine mode is multi-valued to three or more levels, so that a plurality of bits of test data can be output collectively. The configuration of the test data compression circuit will be described.

  FIG. 26 is a block diagram showing a configuration of test data compression circuit 100e according to the seventh embodiment of the present invention.

  Referring to FIG. 26, test data compression circuit 100e according to the seventh embodiment includes multiplexers 102, 104, 110, output circuit 170, compressed data decoder 210, multilevel driver 220, and output selection switch 230. Including.

  Multiplexers 102, 104, and 110 are configured similarly to the test data compression circuit according to the first to sixth embodiments, and output compressed data TD01, TD23, and TD0123, respectively.

  The output circuit 170 receives the compressed data TD0123 from the multiplexer 110 and is connected to the data input / output node 50 via the output selection switch 230. The compressed data decoder 210 selectively activates one of the plurality of decode signals RS0 to RS3 according to the compressed data TD01 and TD23 having a compression degree of 2: 1 that should be output in the fine mode.

  Output selection switch 230 connects either output circuit 170 or multilevel driver 220 to data input / output node 50 in response to test mode signals TMBT1 and TMBT2. Thereby, in the normal mode, the output circuit 170 outputs data to one of two predetermined voltage levels (for example, VDD1 and VSS) depending on whether the compressed data TD0123 is “1” or “0”. The input / output node 50 is driven.

  On the other hand, in the fine mode, the data input / output node 50 uses the multilevel driver 220 to select one of the predetermined voltages VDD1, VSS, VKK, and VBB according to the plurality of decode signals RS0 to RS3 based on the compressed data TD01 and TD23. Driven by one.

FIG. 27 is a circuit diagram showing a configuration of the compressed data decoder 210.
Referring to FIG. 27, compressed data decoder 210 includes level shifters 240-243 and AND gates 250-253.

  The AND gate 250 outputs an AND operation result of the compressed data TD01 and TD23. The level shifter 240 activates the decode signal RS0 and sets it to the voltage VDD1 when the output of the AND gate 250 is “1”. On the other hand, when the output of the AND gate 250 is “0”, the level shifter 240 deactivates the decode signal RS0 and sets it to the voltage VBB.

  Similarly, AND gate 251 outputs an AND operation result of inverted signal / TD01 of compressed data TD01 and inverted signal / TD23 of compressed data TD23. The level shifter 241 activates the decode signal RS1 to set the voltage VDD1 when the output of the AND gate 251 is “1”. On the other hand, when the output of the AND gate 251 is “0”, the level shifter 241 deactivates the decode signal RS1 and sets it to the voltage VBB.

  AND gate 252 outputs an inverted signal / TD01 of compressed data TD01 and an AND operation result of compressed data TD23. The level shifter 242 activates the decode signal RS2 to set the voltage VDD1 when the output of the AND gate 252 is “1”. On the other hand, when the output of the AND gate 252 is “0”, the level shifter 242 deactivates the decode signal RS2 and sets it to the voltage VBB.

  The AND gate 253 outputs the AND operation result of the compressed data TD01 and the inverted signal / TD23 of the compressed data TD23. The level shifter 243 activates the decode signal RS3 and sets it to the voltage VDD1 when the output of the AND gate 253 is “1”. On the other hand, when the output of the AND gate 253 is “0”, the level shifter 243 inactivates the decode signal RS3 and sets it to the voltage VBB.

  As a result, the decode signal RS0 is activated when both the compressed data TD01 and TD23 are “1”, that is, when there is no defect in the memory cells corresponding to the test output data TD0 to TD3, and otherwise. Is deactivated. On the other hand, the decode signal RS1 is activated when both the compressed data TD01 and TD23 are “0”, that is, when there is a defect in the memory cell corresponding to each of the test output data TD0 to TD3. When deactivated.

  The decode signal RS2 is activated when the compressed data TD01 is “0” and the compressed data TD23 is “1”, that is, when there is a defect in a memory cell corresponding to at least one of the test output data TD0 and TD1. Otherwise it is deactivated. On the other hand, the decode signal RS3 is activated when the compressed data TD01 is “1” and the compressed data TD23 is “0”, that is, when there is a defect in the memory cell corresponding to at least one of the test output data TD2 and TD3. Otherwise it is deactivated.

  Referring to FIG. 26 again, multilevel driver 220 includes drive transistors 221 to 224. The drive transistors 221 to 223 are composed of n-MOS (Metal Oxide Semiconductor) transistors, and the drive transistor 224 is composed of an n-MOS transistor. Drive transistor 224 is connected between output node N0 connected to data input / output node 50 via output selection switch 230 and a supply node of voltage VDD1 (for example, +1.8 V). An inverted signal of the decode signal RS0 is input to the gate of the drive transistor 224.

  Drive transistor 221 is connected between output node N0 and a supply node of voltage VBB (for example, -1.0 V), and receives decode signal RS1 at its gate. Drive transistor 222 is connected between output node N0 and a supply node of voltage VKK (for example, -0.5V), and receives decode signal RS2 at its gate. In addition, drive transistor 223 is connected between output node N0 and a supply node of voltage VSS (for example, −0.0 V), and receives decode signal RS3 at its gate.

  By adopting such a configuration, the multilevel driver 220 has the data according to which one of the plurality of decode signals RS0 to RS3 is activated, that is, the values of the compressed data TD01 and TD23 having a data compression degree of 2: 1. The input / output node 50 is driven by any one of four levels of voltages VDD1, VBB, VKK, and VSS.

  Note that the decode signals RS2 and RS3 indicating that one of the compressed data TD01 and TD23 is “0” are merged into one decode signal, and the data input / output node 50 is driven by one of three stages of voltages. As such, the multi-level driver 220 may be configured.

  As a result, as shown in FIG. 28, in the fine mode, the voltage of the data input / output node 50 to which the data DQ0 is output is a multi-value voltage of 3 or more depending on the values of the compressed data TD01 and TD23 of multiple bits Set to one of the levels.

  Thus, in the fine mode, the operation indicated by the compressed data of a plurality of bits without switching the output data at each data input / output node 50 in a time division manner as in the test data compression circuit according to the first to fourth embodiments. Test results can be output from a single data input / output node 50.

  Therefore, according to the test data compression circuit according to the seventh embodiment, the operation test in the fine mode can be performed without increasing the time required for the test even when using the relatively low performance normal memory tester to which the normal mode is applied. Can be executed.

  In the first to seventh embodiments described above, the data compression degree in the normal mode is 4: 1, that is, 1-bit compressed data is obtained for every 4 bits of test output data from the memory core unit 30, and An example of a configuration in which the compression degree in the fine mode is 2: 1, that is, 1-bit compressed data is obtained for every 2 bits of test output data. However, in the application of the present invention, it will be confirmed that the data compression degree in each mode is not limited to these examples.

  That is, with respect to the data compression level L: 1 in the normal mode and the fine mode at the time of an operation test to which data compression is applied, L is L = 2 (fine mode) and L = 4 (normal mode) exemplified in the present embodiment. ) Can be any integer. However, L in the fine mode is preferably a divisor of L in the normal mode. In this way, the repair unit in the fine mode can be determined in such a manner that the repair unit in the normal mode is further subdivided, so that the replacement control by the redundant circuit 60 can be simplified.

  In the first to seventh embodiments, the normal mode and the fine mode are provided one by one. However, in order to set the data compression level (L: 1) in a stepwise manner, a configuration in which a plurality of subdivided fine modes are provided. It is also possible. In that case, in each of the test data compression circuits according to the first to seventh embodiments, the number of multiplexers arranged is increased as appropriate, and the selection circuits 150 and 150 # also receive compressed data that can be output in the fine mode. The configuration may be changed as appropriate according to the number of bits.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a schematic block diagram showing an overall configuration of a semiconductor memory device according to the present invention. It is a conceptual diagram explaining the data output mode at the time of normal operation. It is a conceptual diagram explaining the data output mode at the time of an operation test. It is a wave form diagram explaining the data output mode at the time of the operation test by the data compression shown in FIG. It is a block diagram which shows the structure of the test data compression circuit according to Embodiment 1 of this invention. FIG. 7 is an operation waveform diagram illustrating a data output mode in the fine mode of the test data compression circuit according to the first embodiment of the present invention. FIG. 7 is an operation waveform diagram illustrating a data output mode in the normal mode of the test data compression circuit according to the first embodiment of the present invention. It is a block diagram which shows the modification of the structure of the test data compression circuit according to Embodiment 1 of this invention. It is a block diagram which shows the structure of the test data compression circuit according to Embodiment 2 of this invention. FIG. 12 is an operation waveform diagram illustrating a data output mode in the fine mode of the test data compression circuit according to the second embodiment of the present invention. FIG. 11 is an operation waveform diagram illustrating a data output mode in the normal mode of the test data compression circuit according to the second embodiment of the present invention. It is a block diagram which shows the modification of a structure of the test data compression circuit according to Embodiment 2 of this invention. It is a block diagram which shows the structure of the test data compression circuit according to Embodiment 3 of this invention. It is an operation | movement waveform diagram explaining the data output mode in the fine mode of the test data compression circuit according to Embodiment 3 of this invention. It is an operation waveform diagram explaining the data output mode in the normal mode of the test data compression circuit according to the third embodiment of the present invention. It is a block diagram which shows the modification of a structure of the test data compression circuit according to Embodiment 3 of this invention. It is a block diagram which shows the structure of the test data compression circuit according to Embodiment 4 of this invention. It is an operation | movement waveform diagram explaining the data output mode in the fine mode of the test data compression circuit according to Embodiment 4 of this invention. It is an operation | movement waveform diagram explaining the data output mode in the normal mode of the test data compression circuit according to Embodiment 4 of this invention. It is a block diagram which shows the modification of a structure of the test data compression circuit according to Embodiment 4 of this invention. It is a block diagram which shows the structure of the test data compression circuit according to Embodiment 5 of this invention. FIG. 17 is an operation waveform diagram illustrating a data output mode in each of a normal mode and a fine mode of the test data compression circuit according to the fifth embodiment of the present invention. FIG. 17 is a block diagram showing a configuration for generating a test data output timing notification signal included in a test data compression circuit according to a sixth embodiment. It is an operation | movement waveform diagram explaining the data output mode at the time of the fine mode of the test data compression circuit according to Embodiment 6 of this invention. It is an operation | movement waveform diagram explaining the data output mode in the normal mode of the test data compression circuit according to Embodiment 6 of this invention. It is a block diagram which shows the structure of the test data compression circuit according to Embodiment 7 of this invention. FIG. 27 is a block diagram illustrating a configuration example of a compressed data decoder illustrated in FIG. 26. It is an operation waveform diagram explaining the data output mode in each of the normal mode and the fine mode of the test data compression circuit according to the seventh embodiment of the present invention.

Explanation of symbols

  6 signal input pins, 7 test dedicated pins, 9 signal pins, 10 control circuit, 15 mode register, 20 address register, 30 memory core, 32 memory cells, 34 sense amplifier, 36 preamplifier, 40 data input / output circuit, 50 data Input / output node, 60 redundant circuit, 100, 100a, 100a #, 100b, 100b #, 100c, 100c #, 100d, 100e Test data compression circuit, 101, 102, 104, 110 multiplexer, 120 internal clock generation circuit, 125 delay Circuit, 130 parallel-serial conversion circuit, 150, 150 # selection circuit, 151-153 selection switch, 170 output circuit, 190 burst counter, 200 DQS generation circuit, 205 latency counter, 210 compressed data Coder, 220 Multi-level driver, 221 to 224 drive transistor, 230 output selection switch, 240 to 243b level shifter, 250 to 253 AND gate, 1000 semiconductor memory device, ADD address signal, BL burst length, BRST burst reset signal, CL column latency , CLKN, CLKP internal clock, CLKPD delay clock, DQ0 to DQ3 data, DQS data strobe signal, EXTCLK external clock, EXTDQM external control signal, N0 output node, OE output enable signal, RS0 to RS3 decode signal, RSN compressed data ( Normal mode), SCMD command control signal, TD0 to TD3 test output data (from memory core), TD01, TD23, TD012 Compressed data, TDa～TDd test data, TMBT1, TMBT2 test mode signal, VDD1, VSS, VKK, VBB predetermined voltage, WTPs test signal.

Claims (14)

A memory core unit configured to include a plurality of memory cells selected by an address signal, and outputting M-bit (M: integer of 2 or more) data in parallel during an operation test;
During the operation test, the M-bit data output from the memory core unit is compressed to L: 1 (L: an integer equal to or less than M and a divisor of M), and (M / L) bits A test data compression circuit for outputting test data;
The operation test has a plurality of test modes,
The test data compression circuit includes a selection circuit that variably sets L according to a test mode selected from the plurality of test modes. The plurality of test modes include a first mode in which L is set to a maximum value L1 (L1: an integer satisfying the condition of L), L being L2 (L2: satisfying the condition of L, and A second mode set to an integer such that L1 <L2),
The test data compression circuit includes:
A first data compression circuit for compressing output data from the memory core into 1-bit test data for each L1 bit;
A second data compression circuit for compressing output data from the memory core into 1-bit test data for each L2 bits;
The selection circuit is configured to receive test data from each of the first and second data compression circuits and selectively output test data from the data compression circuit corresponding to the selected test mode. The semiconductor memory device according to claim 1.   3. The semiconductor memory according to claim 1, wherein the selection circuit sequentially outputs test data from the plurality of second data compression circuits from the same data node at different timings in the second mode. apparatus. The test data compression circuit further includes an internal clock generation circuit for generating first and second internal clocks in response to one edge and the other edge of a clock signal from the outside of the semiconductor memory device,
In the second mode, the selection circuit receives the test data from the second data compression circuit different from the same data node at timings corresponding to the first and second internal clock signals, respectively. 4. The semiconductor memory device according to claim 3, which outputs the semiconductor memory device. The semiconductor memory device further includes a control circuit for controlling the operation of the memory core unit according to a plurality of external control signals,
In the second mode, the selection circuit outputs the test data output from the same data node at a timing in response to an external control signal that is not used during the operation test among the plurality of external control signals. The semiconductor memory device according to claim 3, wherein: The semiconductor memory device further includes a dedicated test pin that is not used when the product is assembled.
4. The semiconductor memory according to claim 3, wherein the selection circuit switches the test data output from the same data node at a timing in response to an external signal input to the test dedicated pin in the second mode. apparatus. The test data compression circuit includes:
An internal clock generation circuit for generating a first internal clock in response to one edge of a clock signal from the outside of the semiconductor memory device;
A delay circuit for generating a second internal clock obtained by delaying the first internal clock generated by the internal clock generation circuit for a predetermined time;
The selection circuit receives the test data from the second data compression circuit different from the same data node at timings synchronized with the first and second internal clock signals, respectively, in the second mode. Output,
The semiconductor memory device according to claim 3, wherein the predetermined time is less than one cycle of the clock signal. The selection circuit is configured to switch the test data output from the same data node at a timing synchronized with a clock signal from the outside of the semiconductor memory device in the second mode.
4. The semiconductor memory device according to claim 3, wherein a reset timing at which an output from the data node is reset in the second mode is set later than the reset timing in the first mode. A notification signal generation circuit for generating a notification signal for notifying the outside of the semiconductor memory device of the data output timing from the data node;
In the second mode, the notification signal generation circuit outputs the notification signal in synchronization with the output timing of the test data from the plurality of second data compression circuits output from the same data node. The semiconductor memory device according to claim 4, wherein the semiconductor memory device is generated. The semiconductor memory device is a double data rate synchronous semiconductor memory device,
The semiconductor memory device according to claim 9, wherein the notification signal is a data strobe signal.   The selection circuit selectively outputs one voltage level of three or more voltage levels from the data node based on the test data from the plurality of second data compression circuits in the second mode. The semiconductor memory device according to claim 1 or 2. The memory core unit is divided into a plurality of bit ranges respectively corresponding to the M-bit data,
The semiconductor memory device according to claim 1, further comprising a redundancy circuit for replacing and repairing the bit range in which a defect exists in the plurality of bit ranges in units of the L bit ranges. .   13. The semiconductor memory device according to claim 12, wherein the plurality of bit ranges are set corresponding to the address signal. A plurality of data input / output units for outputting a plurality of bits of data in parallel from the memory core unit;
13. The semiconductor memory device according to claim 12, wherein the plurality of bit ranges are set corresponding to the plurality of data input / output units.

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