JP2008135829A - Power amplifying circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a matter that a compensation reactance component has an adverse effect on the high frequency matching conditions of a class F amplifier to cause fall off of efficiency when a high efficiency linear amplifier is implemented by combining a Chirex combiner and a class F amplifier. <P>SOLUTION: A LINC amplifier 100 functioning as a power amplifier has an LINC signal separation circuit 10, a delay unit 12, a phase shifter 14, and a power amplifier IC 40. The power amplifier IC 40 has matching circuits 32 and 34, FETs 16 and 18, transmission lines 22 and 24, a λ/8 open stub 26 connected with the transmission line 22 and a 3λ/8 open stub 28 connected with the transmission line 24. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an amplifier that amplifies high-frequency power, and in particular, a distributor that separates a high-frequency signal into two signals having a constant amplitude and a phase difference, an amplifier that amplifies each of the two signals separated by the distributor, and an amplifier The present invention relates to a power amplifying circuit having a transmission line for transmitting the signal amplified in (1) and a combiner for synthesizing the amplified signals.

  In a wireless device that amplifies high-frequency power, most of the power is consumed by a power amplifier that requires high output, and energy that is not converted into transmission power is consumed as heat. Increasing the amount of heat generated by the power amplifier has a problem that it is difficult to reduce the size because it is necessary to provide heat radiating fins.

  As one of means for realizing a high-efficiency linear amplifier, an amplification circuit using a saturation amplifier by a LINC (Linear Amplification with Nonlinear Components) system is known. In the LINC amplifier, when the input signal Vin is separated into two constant amplitude signals V1 and V2 having different phases, and the separated signals are amplified by the saturation amplifiers and synthesized at the output end, the signals are changed in amplitude because the phases are different. A signal equivalent to a signal obtained by linearly amplifying Vin is obtained.

  FIG. 5 shows the configuration of the LINC amplifier 300. The LINC amplifier 300 includes a LINC signal separation circuit 10, FETs 16 and 18, and transmission lines 22 and 24. The Vin signal input to the LINC signal separation circuit 10 is separated into a V1 signal and a V2 signal. The separated V1 signal is inputted to the gate of the FET 16, the V2 signal is inputted to the gate of the FET 18 in the same manner, a synthesis point 23 is provided at a position λ / 4 long away from the drain end, and the synthesized signal is Vout. Is output from.

  FIG. 6 shows the relationship between the V1 signal and the V2 signal output from the LINC signal separation circuit 10 shown in FIG. 5, and Vom output from Vout. The LINC amplifier 300 amplifies a signal whose envelope changes using two FET elements which are saturation amplifiers. The two FETs 16 and 18 are supplied with a V1 signal and a V2 signal which are signals having a constant amplitude (VomPEP (Peak Envelope Power)) shifted by a phase angle φm. The relational expression of each signal is shown below.

  The LINC amplifier 300 outputs a Vom signal whose amplitude varies depending on the phase relationship between the two signals synthesized at the synthesis point after amplification of the saturation operation by the FET. Since the two FETs 16 and 18 always operate in saturation, the respective efficiencies are very high. Next, a relational expression of the Vom signal is shown.

  FIG. 7 shows processing when the output phases of the two FETs are different. When the phases of the output signals of the two FETs match, all the power is output. However, when the phases are different, the power is distributed to the output side and the transmission line side. For example, the relationship between the V1 signal and the V2 signal when the output phases are different is expressed by the following equation.

  Here, since the signal e is out of phase, the impedance is 0 at the synthesis point 23 in FIG. 5, and the impedance is infinite at the drain end of the FET that is away from the synthesis point 23 by the electrical length λ / 4. Power consumption becomes zero. However, the impedance at this time does not become infinite as a pure resistance, but has a reactance component according to the magnitude of the signal e. For this reason, there is a problem that the power consumption does not become “0” and the efficiency is lowered. Therefore, Non-Patent Document 1 discloses a technique that cancels this reactance component and makes it appear as a pure resistance component.

  FIG. 8 shows a Chirex synthesizer 400 in which a + jBs element 42 and a −jBs element 44 are added to the subsequent stage of the FETs 16 and 18 for inputting the signals separated by the LINC signal separation circuit 10 in order to solve the above problem. Has been.

  Patent Document 1 discloses a class F amplifier as another circuit configuration for increasing the efficiency of the amplifier. The class F amplifier has an output matching circuit at the output end of an amplifying FET or the like that is short-circuited to even-order high-frequency signals and open to odd-order high-frequency signals. Are converted into fundamental high-frequency power.

JP-A-11-112252 FREDERICK H. RAAB, “Efficiency of RF Power-Amplifier Systems”, IEEE TRANSACTIONS ON COMMUNICATIONS. VOL. COM-33, NO, 10 OCTOBER 1985. 1094-1099

  When a high-efficiency linear amplifier is realized by combining the above-mentioned Chirex synthesizer and a class F amplifier, there is a problem that the compensated reactance component adversely affects the high-frequency matching conditions of the class F amplifier and the efficiency is lowered.

  Therefore, an object of the present invention is to provide a power amplifier that divides and amplifies a high-frequency signal, synthesizes and outputs the resultant signal, and releases the high-frequency signal from the signal e that is a reverse phase component of the bi-distributed high-frequency signal. An object of the present invention is to provide a power amplifier that satisfies an output matching condition that is short-circuited with respect to the second harmonic and can be realized with a simple circuit.

  In order to achieve the above object, a power amplifier circuit according to the present invention includes a distributor that separates a high-frequency signal into two signals having a constant amplitude and a phase difference, and two signals separated by the distributor. In a power amplifying circuit having an amplifier that amplifies, a transmission line that transmits a signal amplified by the amplifier, and a combiner that synthesizes the amplified signals, the transmission line is configured for a fundamental wave of a high-frequency signal. a first path provided with an open stub of λ / 8 and a second path provided with an open stub of 3λ / 8 for the fundamental wave, the first and second paths being a high-frequency signal The fundamental wave has a compensation reactance for compensating the load reactance of each amplifier.

  In the power amplifier circuit according to the present invention, the transmission line has a first path provided with an open stub of λ / 8 for the fundamental wave of the high frequency signal, and a short stub of λ / 4 for the fundamental wave. And a second path provided.

  Furthermore, in the power amplifier circuit according to the present invention, the distributor includes a phase adjuster and a delay device that correct a phase shift and a delay difference generated between the two paths.

  The power amplifier IC according to the present invention is a FET element that amplifies two signals separated by a distributor that separates a high-frequency signal into two signals having a constant amplitude and a phase difference, and is amplified by the FET element. In a power amplifier IC having a transmission line for transmitting a signal and a synthesizer for synthesizing the amplified signals, the transmission line is a first in which an open stub of λ / 8 is provided for a fundamental wave of a high-frequency signal. And a second path provided with an open stub of 3λ / 8 with respect to the fundamental wave, and the first and second paths are short-circuited with respect to the double wave of the high-frequency signal. It is characterized by having a compensating reactance that compensates for the load reactance of each amplifier with respect to the wave.

  Furthermore, in the power amplifier IC according to the present invention, the transmission line has a first path provided with an open stub of λ / 8 for the fundamental wave of the high frequency signal, and a short stub of λ / 4 for the fundamental wave. And a second path provided.

  The power amplifying circuit according to the present invention has a simple output matching condition in which a high-frequency signal is divided into two parts and amplified, and then open to the fundamental wave of the high-frequency signal and short-circuited to the second harmonic of the high-frequency signal. It is possible to synthesize and output each in the circuit.

  Hereinafter, embodiments of the present invention (hereinafter referred to as embodiments) will be described with reference to the drawings.

(First embodiment)
FIG. 1 shows a configuration diagram of a power amplifier (LINC amplifier) according to a first embodiment of the present invention. The LINC amplifier 100 includes a LINC signal separation circuit 10, a delay device 12, a phase shifter 14, and a power amplification IC 40. The power amplifier IC 40 includes matching circuits 32 and 34, FETs 16 and 18, transmission lines 22 and 24, a λ / 8 open stub 26 connected to the transmission line 22, and 3λ / 8 open stubs 28.

  What is characteristic in the present embodiment is that the double-frequency processing circuit of the class F amplifier is used as the compensation reactance. One transmission line 22 side uses a λ / 8 open stub 26 for the fundamental wave, and the other transmission line 24 side uses a 3λ / 8 open stub for the fundamental wave. With this configuration, both lines appear to be λ / 4 open stubs for the double wave, and for the fundamental wave, the λ / 8 open stub 26 is capacitive, and the 3λ / 8 open stub 28 is Looks inductive and acts as a compensating reactance.

  However, a phase shift or delay occurs between the two lines due to variations in characteristics of the FETs and stubs (stubs having different characteristics of λ / 8 and 3λ / 8). Adjustment is performed by the phase shifter 14. In addition, the transmission line and the open stub function as a matching circuit on the output side.

  FIG. 2 shows an outline of the power amplifier IC 40. One end of the matching circuits 32 and 34 is connected to the gate side of the power amplifier IC 40, and the gates of the FETs 16 and 18 are connected to the other ends of the matching circuits 32 and 34. Transmission lines 22 and 24 are connected to the drain sides of the FETs 16 and 18. The transmission lines 22 and 24 are provided with open stubs 26 and 28, respectively, and the two transmission lines are connected by a synthesis point 23 provided at a distance of λ / 4 from the FET drain end. Further, the end portions of the transmission lines 22 and 24 are connected to the drain side terminal of the power amplifier IC 40. In addition, the connection between each element is connected by the some wire.

  In the case of the layout shown in FIG. 2, the phase and delay from the upper FET 16 to the synthesis point 23 and the phase and delay from the lower FET 18 to the synthesis point 23 cause a shift. In this embodiment, the phase and delay are adjusted on the input side of the previous stage.

  As shown in FIG. 7, when the two separated signals have different phases, power is distributed to the output side and the transmission line side. In this case, since the signal e is out of phase, the impedance is 0 at the synthesis point, and the impedance is infinite at the drain end of the FET that is away from the synthesis point by the electrical length λ / 4, so that the power consumption for the signal e Becomes 0. However, the impedance at this time does not become infinite as a pure resistance, but has a reactance component according to the magnitude of the signal e.

  In the Chirex synthesizer of FIG. 8, the shunt susceptance (Bs), which is the imaginary part of the admittance component, can be expressed by the following Equation 4.

  Here, the normalized shunt susceptance (Bs ′) can be expressed by Equation 5.

  Further, the efficiency η can be expressed by Equation 6.

  Here, the impedance Zin of the open stub provided in the transmission lines 22 and 24 can be expressed by EL which is the electrical length of the open stub and the characteristic impedance Z0 of the open stub. Therefore, the input admittance Yin of the open stub is obtained, and the shunt susceptance (Bs) component can be expressed as an imaginary part of the admittance component. Equation 7 is shown below.

  The admittance component shown in Equation 7 changes depending on the magnitude of the signal e, that is, the phase difference between the V1 signal and the V2 signal. Also, since the output power is determined by the phase difference between the V1 signal and the V2 signal, the most effective output power can be obtained by canceling Bs. Therefore, characteristics due to changes in Bs were calculated by simulation.

  FIG. 3 is an example of a back-off characteristic diagram showing the difference between the maximum output amplitude level and the output saturation power level of the LINC amplifier according to the present embodiment. Generally, the back-off is required up to about −10 dB, so that the request cannot be satisfied when Bs = 0. As a result of calculation, it became clear that the requirement can be satisfied when Bs = 0.06 and 0.045. Note that this value varies depending on circuit constants, and it is necessary to obtain an optimum value for each circuit.

(Second Embodiment)
FIG. 4 shows a LINC amplifier 200 according to the second embodiment of the present invention. The difference from the first embodiment is that the combination of the λ / 8 open stub 26 and the 3λ / 8 open stub 28 is a combination of the λ / 8 open stub 26 and the λ / 4 short stub 29 in the first embodiment. That is. In addition, the same code | symbol was used for the same component as 1st Embodiment. In this embodiment, the same function as in the first embodiment can be realized.

  In the present embodiment, the delay unit 12 and the phase shifter 14 are provided in the subsequent stage of the LINC signal separation circuit 10, but these functions may be incorporated in the digitally controlled LINC signal separation circuit 10.

  As described above, the power amplifying circuit of the present embodiment is divided into a high frequency signal and amplifies each, and then opens to the fundamental wave of the high frequency signal and shorts to the second harmonic of the high frequency signal. According to the output matching condition, the compensation reactance component does not adversely affect the high-frequency matching condition of the class F amplifier, and can be realized with a simple circuit without reducing the efficiency.

1 is a configuration diagram of a power amplifier according to a first embodiment of the present invention. It is a schematic diagram which shows the outline | summary of the power amplification IC which concerns on embodiment of this invention. It is a characteristic view of the back-off characteristic which concerns on embodiment of this invention. It is a block diagram of the power amplifier which concerns on the 2nd Embodiment of this invention. It is a block diagram of the conventional LINC system amplifier. It is explanatory drawing explaining the synthetic | combination operation | movement of the signal isolate | separated by the LINC signal separation circuit. It is explanatory drawing explaining a process when the output phase of two FETs differs. It is a block diagram which shows the structure of the conventional Chirex synthesizer.

Explanation of symbols

  10 LINC signal separation circuit, 12 delay circuit, 14 phase shifter, 16, 18 FET, 22, 24 transmission line, 23 synthesis point, 26, 28 open stub, 29 short stub, 32, 34 matching circuit, 40 power amplification IC 42, 44 jBs element, 100, 200, 300 LINC amplifier, 400 Chirex synthesizer.

Claims (5)

A distributor for separating a high-frequency signal into two signals having a constant amplitude and a phase difference; an amplifier for amplifying the two signals separated by the distributor; a transmission line for transmitting the signal amplified by the amplifier; A power amplifying circuit having a synthesizer for synthesizing the amplified signals;
Transmission line is
A first path having an open stub of λ / 8 with respect to the fundamental wave of the high-frequency signal;
A second path having an open stub of 3λ / 8 with respect to the fundamental wave;
Have
The first and second paths are short-circuited with respect to a double wave of a high-frequency signal, and have a compensation reactance that compensates for a load reactance of each amplifier with respect to a fundamental wave. The power amplifier circuit according to claim 1,
Transmission line is
A first path having an open stub of λ / 8 with respect to the fundamental wave of the high-frequency signal;
A second path having a short stub of λ / 4 with respect to the fundamental wave;
A power amplification circuit comprising: The power amplifier circuit according to claim 1 or 2,
The distributor includes a phase adjuster and a delay device for correcting a phase shift and a delay difference generated between both paths, and a power amplifier circuit. A FET element that amplifies two signals separated by a distributor that separates a high-frequency signal into two signals having a constant amplitude and a phase difference, and a transmission line that transmits the signal amplified by the FET element, respectively. A power amplifying IC comprising:
Transmission line is
A first path having an open stub of λ / 8 with respect to the fundamental wave of the high-frequency signal;
A second path having an open stub of 3λ / 8 with respect to the fundamental wave;
Have
The power amplification IC characterized in that the first and second paths are short-circuited with respect to the double wave of the high-frequency signal and have a compensation reactance for compensating the load reactance of each amplifier for the fundamental wave. The power amplifier IC according to claim 4,
Transmission line is
A first path having an open stub of λ / 8 with respect to the fundamental wave of the high-frequency signal;
A second path having a short stub of λ / 4 with respect to the fundamental wave;
A power amplifying IC comprising:

Images