JP2008124310A - Solid-state imaging device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make it possible to effectively suppress a contamination of a high melting point metal in the case of a silicide formation, and to intend to raise a productivity of an advanced image sensor and to improve a yield. <P>SOLUTION: On a Si substrate 100 in which a photodiode 101 is formed, there is formed a polysilicon gate electrode 103 through a gate insulating film 102. On the polysilicon gate electrode 103 there are laminated insulating films 111, 112, 113 of three layers for forming a side wall. The insulating film 111 of a first layer consists of, for example, a SiO<SB>2</SB>film. The insulating film 112 of a second layer consists of, for example, a SiN film. Moreover, the insulating film 113 of a third layer consists of, for example, the SiO<SB>2</SB>film and is used as a spacer of the side wall. At the photodiode 101 side, an etch back of the insulating film 113 of the third layer isn't carried out, but the insulating film 113 of the third layer remains on the insulating film 112 of the second layer and is constituted as a protective film of a high melting metal film block film. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device such as a CMOS image sensor having a silicide region and a non-silicide region on a semiconductor chip, and a method for manufacturing the same.

In general, a CMOS image sensor has a pixel region in which a plurality of pixels composed of a photodiode (photoelectric conversion unit) and several transistors are arranged in a two-dimensional direction in one semiconductor chip, and a signal flowing in the pixel region. And a peripheral circuit region for processing signals output from the pixel region.
Each pixel has a transfer transistor that transfers signal charges generated by a photodiode to an FD (floating diffusion) unit, an amplification transistor that detects a potential variation in the FD unit and outputs a pixel signal, and resets the potential of the FD unit A reset transistor or the like is provided.
Then, after collecting light from the outside on the photodiode and generating a signal charge corresponding to the light amount by photoelectric conversion, the signal charge of the photodiode is transferred to the FD portion by the transfer transistor, and the FD portion by this signal charge Is detected by an amplification transistor, and a pixel signal (for example, a current signal) is generated and output to a peripheral circuit via a vertical signal line.

Recently, due to the increasing demand for improvement in control and processing capabilities of CMOS circuits constituting peripheral circuits, miniaturization of each component device has been promoted. At the same time, in the pixel area, it is necessary to miniaturize the device in that the number of pixels in the light collecting area can be increased.
However, as the miniaturization of CMOS devices progresses, the gate electrode resistance, the sheet resistance of the source / drain region of the transistor, and the contact resistance increase, and there is a problem that the speed cannot be increased as expected on the scaling side.
Therefore, in order to reduce these resistances, the use of metal silicide is progressing.
Specific examples of the silicide material include TiSi ₂ , CoSi ₂ , NiSi, and PtSi. In addition, it is generally known that salicide (SALICIDE), which is a self-aligned process, is used for silicidation of minute gate electrodes and source / drain diffusion regions.

Here, the formation of the source / drain regions including the salicide process will be described.
First, a gate electrode is formed of polysilicon or the like, source / drain extension regions are formed, and then an SiO ₂ film or SiN film having isotropic step coverage is formed.
Next, anisotropic etching mainly including a vertical component is performed by reactive ion etching. This is the same technique as etch back. This leaves a spacer (SiO ₂ or SiN) on the side wall of the gate electrode. In this way, an LDD (Lightly Doped Drain) structure is formed in the transistor by implanting ions into the source / drain with the spacer left on the side wall of the gate electrode.
Subsequently, after the Si surface is cleaned by an appropriate pretreatment, a refractory metal film such as Ti or Co is formed on the entire surface of the wafer by sputtering. Next, when this is heated in an appropriate atmosphere, silicidation is performed in a self-aligned manner only in the region where the substrate Si and polysilicon are exposed.
Thereafter, the unreacted metal layer is selectively removed by wet etching or the like. Since only the silicide layer formed at this time has a high resistance, a heat treatment for a long time or a long time is applied to reduce the resistance to form a silicide layer having a different composition or structure.
As a result, the speed can be increased by lowering the resistance.

However, on the other hand, it may be necessary to create a silicide region and a non-silicide region separately in one chip due to a required difference in Tr characteristics.
In general, when a non-silicide region is formed, the non-silicide region is covered with SiN, SiO ₂ or the like before sputtering the refractory metal layer, thereby preventing the exposure of Si or polysilicon. Block reaction with. Particularly in an image sensor, contamination of a refractory metal to a photodiode causes a defect such as generation of a large leakage current or white spot.
Therefore, it is necessary to block the refractory metal, and the block film is required to have a high blocking property.

On the other hand, as a method not using a block film, there is a conventional technique as described below (see, for example, Patent Document 1).
In this method, first, a gate insulating film is deposited on a silicon substrate on which an element isolation portion is formed, and then a polysilicon film and a tungsten silicide film as gate electrode materials are deposited. Then, the tungsten silicide film is etched using the photoresist formed in the portion to be left as the gate electrode as a mask, and the polysilicon film is etched as it is while leaving a partial thickness.
Next, after removing the resist, a tungsten (W) protective oxide film of the first layer is deposited and etched back. A sidewall dielectric layer is formed by leaving a part of the W protective oxide film on the sidewalls of the tungsten silicide film and the polysilicon film. After removing the remaining polysilicon film by etching and further removing the gate insulating film, a source / drain diffusion layer and a photodiode diffusion layer are formed. This prevents tungsten atoms from adhering to the silicon substrate from the tungsten silicide film constituting the gate electrode.
In this method, refractory metal contamination for silicidation of the gate electrode can be suppressed without a blocking film, but a blocking film is necessary for silicidation of the source / drain regions.

In addition, regarding the formation of the block film, the number of steps can be reduced by providing the other target film with the function of a refractory metal block. For example, it has been proposed to use a gate insulating film of a transistor as a refractory metal block film in a photodiode region (see, for example, Patent Document 2).
However, in this case, since the thickness of the gate insulating film must be thick enough to obtain the block capability, the threshold modulation type MOS type image whose sensitivity is improved in proportion to the thickness of the gate insulating film. Although effective for sensors, there is a problem that it is difficult to use for general CMOS sensors.

  As another method, since the timing of forming the refractory metal block film in the non-silicide region is before and after the process of forming the source and drain of the transistor, the formation of the block film and the formation of the sidewall spacer are performed simultaneously. A method for reducing the number of steps by performing the method has been proposed (see, for example, Patent Document 3).

FIG. 14 is a cross-sectional view showing the structure of a transistor formed by this conventional technique. FIG. 14A shows a silicide region, and FIG. 14B shows a non-silicide region.
A polysilicon gate electrode 203 is formed on the Si substrate 200 on which the photodiode 201 is formed via a gate insulating film 202, and three layers of insulating films 211, 212, and 213 for forming sidewalls thereon are formed. Laminated. The first insulating film 211 is, for example, a SiO ₂ film, and the second insulating film 212 is, for example, a SiN film. In the non-silicide region, this second layer film constitutes a refractory metal film block film. The third insulating film 213 is, for example, a SiO ₂ film and is used as a sidewall spacer.

In other words, in this prior art, the sidewall is made into a three-layer structure, and the non-silicide region is covered with the photoresist at the time of etch-back when forming the sidewall by the second-layer film 212, so that the second-layer film The feature is that 212 is left as a refractory metal block film.
Further, by forming a sidewall spacer on the polysilicon gate side wall in the non-silicide region using the third layer film 213, stepwise ion implantation in the source / drain region is possible, and the transistor in the non-silicide region is formed. Makes it possible to provide an LDD structure.
JP 2005-129594 A JP 2005-174968 A WO2003-096421 (Japanese Patent Application No. 2004-508586)

As described above, the conventional technique shown in FIG. 14 employs a three-layer sidewall structure, thereby realizing the formation of the sidewall spacer of the refractory metal block film and the polysilicon gate in the non-silicide region with a small number of steps. Yes.
However, when the sidewall spacer is formed with the third layer film, it is necessary to completely remove the third layer film on the second layer film (refractory metal block film). . Therefore, there is a problem that etching damage enters the block film.
In the case of a block film having etching damage, there is a possibility that defects that cause contamination of the refractory metal may occur. In particular, when refractory metal contamination occurs in a photodiode, it causes a serious problem in yield due to junction leakage and the occurrence of a white spot, which becomes a serious problem.

In order to improve the blocking ability of the refractory metal of the block film, a method of simply increasing the film thickness is also conceivable. However, since the ion implantation into the source / drain in the non-silicide region is performed through the refractory metal block film, the refractory metal to be an ion passage film is required as long as the source / drain region requires shallow ion implantation. It is difficult to increase the thickness of the block film.
Further, even if the thickness of the block film is increased, etching damage to the block film is not changed when the third sidewall is formed.

  Therefore, the present invention can effectively suppress contamination of a refractory metal during silicidation, improve the productivity of a high-performance image sensor, and improve the yield, and its manufacture. It aims to provide a method.

  In order to achieve the above-described object, the solid-state imaging device of the present invention includes a first region where a silicide layer is formed on a semiconductor substrate and a second region where the silicide layer is not formed. A side wool spacer formed by a three-layer insulating film on the side wall of the gate electrode of the field effect transistor in the region, and a three-layer insulating film forming the side wool spacer in the second region And a region for blocking a refractory metal when forming the silicide layer.

  Further, the manufacturing method of the present invention includes a first region where a silicide layer is formed on a semiconductor substrate, and a second region where the silicide layer is not formed, and a field effect transistor is provided in the first region. A side wool spacer formed of a three-layer insulating film on a side wall of the gate electrode, and the second region is covered with a three-layer insulating film forming the side wool spacer, and the silicide layer is A method of manufacturing a solid-state imaging device having a region for blocking a refractory metal when forming, a step of forming a first insulating film after forming a gate insulating film and a gate electrode on a semiconductor substrate; A step of forming a second insulating film on the first insulating film, masking the second region with a first photoresist, and then performing etching to form a field effect transistor in the first region. Forming a second insulating film on the side wall of the gate electrode of the star, removing the first photoresist, and then forming a third insulating film; and the second region Etching is performed after masking the region where the refractory metal is blocked with the second photoresist, and a third insulating film is formed on the side wall of the gate electrode of the field effect transistor in the region other than the region where the refractory metal is blocked. The method includes a step of forming a sidewall, and a step of forming a silicide by laminating a refractory metal after removing the second photoresist.

According to the solid-state imaging device and the method of manufacturing the same according to the present invention, in the configuration having the silicide region and the non-silicide region, by forming a plurality of films that block the non-silicide region from the refractory metal, Etching damage can be eliminated and high blocking ability can be provided.
Therefore, contamination of the refractory metal during silicidation can be suppressed, and productivity of a high-performance image sensor can be improved and yield can be improved.

FIG. 1 is a cross-sectional view showing the structure of a non-silicide region of a solid-state imaging device (CMOS image sensor) formed according to an embodiment of the present invention. In the present embodiment, the structure of the silicide region is assumed to be common to the prior art shown in FIG.
A polysilicon gate electrode 103 is formed on a Si substrate 100 on which the photodiode 101 is formed via a gate insulating film 102, and three layers of insulating films 111, 112, and 113 for forming sidewalls thereon are formed. Laminated. The first insulating film 111 is, for example, a SiO ₂ film, and the second insulating film 112 is, for example, a SiN film. The third insulating film 113 is, for example, a SiO ₂ film and is used as a sidewall spacer 113A. In this embodiment, the third insulating film 113 is not etched back on the photodiode 101 side. In addition, it remains on the second layer film 112 and is configured as a protective film for the refractory metal film block film.

That is, in the prior art shown in FIG. 14, etch back is performed on the entire surface of the wafer when the third-layer sidewall is formed. In the example shown in FIG. 1, refractory metal contamination is a serious problem using photolithography. A resist pattern was formed at a location (for example, a photodiode region) so that the third-layer sidewall film was not etched back.
Thereby, since the layer which combined the 2nd layer and the 3rd layer turns into a refractory metal block film, the improvement of a block capability can be anticipated significantly. Further, by not etching back the third layer, it is possible to suppress the occurrence of defects such as plasma damage in the second layer block film, and it is possible to suppress refractory metal contamination.
Also, when patterning the third layer film, an LDD structure can be formed at the same time by performing etch back as it is without leaving a resist in the portion of the transistor that requires sidewall spacers in the non-silicide region. Become.
Conversely, when patterning the third layer film, a method may be used in which an opening is provided in the resist pattern only in a region where the sidewall spacer is required in the non-silicide region, and etching back is performed.

Hereinafter, specific embodiments of the present invention will be described with reference to the drawings.
FIG. 2 is a block diagram showing the overall configuration of the solid-state imaging device (CMOS image sensor) according to this embodiment, and FIG. 3 is a circuit diagram showing the configuration of each pixel of the image sensor according to this embodiment.
4 is a plan view showing the arrangement of each element on the semiconductor chip in the image sensor of this embodiment, FIG. 4A shows the whole, and FIG. 4B shows the light receiving portion of each pixel. ing.
First, the overall configuration of the image sensor according to the present embodiment will be described with reference to these drawings.

The image sensor of this embodiment includes a pixel array unit 2 in which a plurality of pixels 1 are arranged in a two-dimensional matrix, a vertical selection drive circuit 3, a column signal processing unit 4, a horizontal scanning circuit 5, and a timing generator 6. And an output processing unit 8 for processing a signal output to the horizontal signal line 7.
In the pixel array section 2, a plurality of vertical signal lines (not shown in FIG. 2) for reading out the signal of each pixel 1 in the vertical direction are formed along with the plurality of pixels 1.

The vertical selection drive circuit 3 selects and drives each pixel 1 of the pixel array unit 2 row by row. A signal of each pixel 1 in the pixel array unit 2 is taken into the column signal processing unit 4 through a vertical signal line formed for each column.
The column signal processing unit 4 processes the signal of each pixel 1 taken in through the vertical signal line, and is configured using, for example, a load MOS transistor and a sample hold / CDS (Correlated Double Sampling) circuit.

The horizontal scanning circuit 5 selectively scans the signal of each pixel 1 read through the vertical signal line of each column and processed by the column signal processing unit 4 in order in the horizontal direction and guides it to the horizontal signal line 7. is there. The horizontal scanning circuit 5 includes, for example, a plurality of selection transistors connected to the vertical signal lines in each column and a shift circuit that sequentially turns on the plurality of selection transistors in the horizontal direction.
The timing generator 6 supplies various pulse signals necessary for the operation of each unit to the vertical selection drive circuit 3, the column signal processing unit 4, and the horizontal scanning circuit 5 based on a reference clock having a predetermined period.
The output processing unit 8 performs output processing of the pixel signal read to the horizontal signal line 7 by the horizontal scanning circuit 5. The output processing unit 8 includes pixel signal amplification processing, selection processing, AGC (Auto Gain Control) processing, A / D (analog / digital) conversion processing, and the like.

  Next, in FIG. 3, each pixel 1 of the pixel array unit 2 has a photodiode 11 that performs photoelectric conversion, a transfer transistor 12 that reads the signal charge generated by the photodiode 11 to the FD, and is read to the FD. An amplification transistor 13 that converts the signal charge into a pixel signal and outputs it to the vertical signal line 19, a reset transistor 14 that resets the signal charge of the FD, and a selection transistor 15 that selects the output timing of the amplification transistor are provided. .

  As shown in FIG. 4, the image sensor having such a configuration is divided into a pixel region 21 centered on the pixel array unit 2 and a peripheral circuit region 22 in which other logic circuits are formed, as shown in FIG. 4. The pixel region 21 is mainly formed as a non-silicide region, and the peripheral circuit region 22 is mainly formed as a silicide region.

5 to 10 and 12 are cross-sectional views showing the manufacturing process of the image sensor according to the present embodiment. In each figure, (A) shows a peripheral circuit region, and (B) shows a pixel region. FIG. 11 is a plan view showing the manufacturing process of the image sensor according to the present embodiment, and shows a resist pattern in the pixel region.
In the following description, as shown in FIG. 5, a gate oxide film 102 is provided on a Si substrate 100 on which an element isolation portion (STI) 104, a photodiode 101, etc. are formed, and a polysilicon film is patterned thereon. Steps after forming the polysilicon gate electrode 103 will be described.

First, in FIG. 6, a first-layer film 111 serving as a sidewall is formed. Here, a silicon oxide film (SiO ₂ ) having a film thickness of 15 nm is used. A silicon nitride film (SiN) may be used as the first layer, but an oxide film is preferable because crystal defects are likely to occur at the interface between Si and SiN, which may increase white spots. .

Subsequently, as shown in FIG. 7, a silicon nitride film (SiN) 112 is formed as a second layer by a low pressure CVD method with good step coverage so as to have a film thickness of 40 nm. Since the second layer becomes a refractory metal block film in the pixel region which is a non-silicide region, a silicon nitride film having a high film density was used.
Subsequently, as shown in FIG. 8, in order to form the side wool spacer using the second layer film in the peripheral circuit region while leaving the second layer film in the pixel region, the pixel is formed by a photoresist method. The entire area is covered with a photoresist 105.
In this state, etching back is performed by a reactive etching method, and sidewall spacers 112A are formed in the transistors in the peripheral circuit region by the second layer film 112. Note that it is desirable to optimize the film thickness because the second-layer film 112 remains in the pixel region and becomes part of the multilayer film over the photodiode 101 and affects spectral sensitivity. However, in that case, it is necessary to select a thickness that does not hinder shallow ion implantation into the source / drain regions of the non-silicide region while maintaining the blocking capability.

Subsequently, as shown in FIG. 9, a third layer film 113 is formed. In this embodiment, a silicon oxide film (SiO) is formed to a thickness of 100 nm by using a hot wall CVD method. In this embodiment, it is the photodiode 101 that should suppress refractory metal contamination most, and the resist 106 is left on the photodiode 101 by photolithography.
FIG. 11 shows the resist pattern as viewed from above. As shown in the figure, the resist 106 is formed so as to cover almost half of the transfer gate electrode 103 </ b> A adjacent to the photodiode 101 and the element isolation portion 104. Further, the gate electrode portions 103B and 103C of the pixel transistors other than the transfer gate electrode 103A and the channel region 107 thereof are not covered with the resist 106.
Thus, by leaving the resist pattern only on the photodiode, the sidewall spacer 113A can be formed in the transistor portion of the pixel. Further, by cutting the resist 106 on the transfer gate portion, the ion implantation into the region from the transfer gate portion to the FD is not affected.

  Then, with the resist 106 left in this way, etch back is performed again by the reactive etching method, and finally the shape of FIG. 12 can be obtained. Thereby, the second-layer silicon nitride film on the photodiode is not exposed to the plasma atmosphere during the etch-back, and damage can be suppressed.

Subsequently, a salicide process is performed (not shown). In this embodiment, the case where Co is used as the refractory metal will be described.
First, before silicidation, cleaning is performed to obtain a clean Si surface. Subsequently, a Co / TiN laminated film was formed on the entire wafer by sputtering. The TiN cap on Co is for protecting Co which is very easily oxidized.
Next, the wafer is heated by RTA (Rapid Thermal Annealing) at 470 ° C. for 30 seconds. At this time, an alloying reaction occurs only at a portion where Si and Co are in contact. In the non-silicide region, the alloying reaction does not occur because it is covered with the second silicon nitride film.
Subsequently, unreacted Co is removed by wet etching using HCl + H ₂ O ₂ . Then, in order to further reduce the resistance of the silicided portion, the second heating with RTA is performed at 830 ° C. for 30 seconds.

An image quality characteristic comparison experiment was performed between the image sensor of the present embodiment created in this way and the image sensor created by the prior art. As a prototype based on the prior art, the element isolation, well formation, photodiode formation, contact, via and wiring formation are the same except that the third layer silicon oxide film on the photodiode is not etched back. A sample was created.
And when both were compared, in the sample shown in the present Example, it was observed that the white spot considered to be caused by the refractory metal (Co) was suppressed.
As described above, by applying this embodiment, contamination of refractory metal during silicidation can be effectively suppressed, and the yield in the production of high-performance CMOS image sensors can be greatly improved. it can.

In the above example, the example in which the present invention is applied to a single CMOS image sensor has been described. However, the solid-state imaging device to which the present invention can be applied is not limited to one in which a CMOS image sensor is configured on one chip. A module in which the imaging unit, the signal processing unit, and the optical system are packaged together may be used. The solid-state imaging device to which the present invention can be applied is basically a CMOS image sensor, but it can of course be applied to other types of image sensors that are produced using the same salicide process. is there.
Moreover, the apparatus utilized for a camera system or a mobile telephone device may be used. In the present invention, a configuration having a CMOS image sensor function alone is called a solid-state imaging device, and the solid-state imaging device and other elements (control circuit, operation unit, display unit, data storage function, communication function, etc.) An integrated configuration is referred to as an imaging device.

Hereinafter, a specific example of an imaging device equipped with a solid-state imaging device according to the present invention will be described.
FIG. 13 is a block diagram showing a configuration example of a camera device using the CMOS image sensor of this example.
In FIG. 13, the imaging unit 310 performs imaging of a subject using, for example, the CMOS image sensor shown in FIG. 2, and outputs an imaging signal to the system control unit 320 mounted on the main board.
That is, the imaging unit 310 performs processing such as AGC (automatic gain control), OB (optical black) clamping, CDS (correlated double sampling), and A / D conversion on the output signal of the above-described CMOS image sensor, and performs digital processing. An imaging signal is generated and output.

In this example, an example in which an imaging signal is converted into a digital signal and output to the system control unit 320 in the imaging unit 310 is shown. However, an analog imaging signal is sent from the imaging unit 310 to the system control unit 320, and the system The control unit 320 may convert to a digital signal.
Various methods have been conventionally provided for specific control operations, signal processing, and the like in the imaging unit 310, and it is needless to say that the imaging device of the present invention is not particularly limited.

  The imaging optical system 300 includes a zoom lens 301 and an aperture mechanism 302 disposed in a lens barrel, and forms a subject image on the light receiving unit of the CMOS image sensor. Under the control of the drive control unit 330 based on this, each part is mechanically driven to perform control such as autofocus.

The system control unit 320 includes a CPU 321, a ROM 322, a RAM 323, a DSP 324, an external interface 325, and the like.
The CPU 321 uses the ROM 322 and the RAM 323 to send an instruction to each part of the camera apparatus to control the entire system.
The DSP 324 performs various kinds of signal processing on the imaging signal from the imaging unit 310, thereby generating a still image or moving image video signal (for example, a YUV signal) in a predetermined format.
The external interface 325 is provided with various encoders and D / A converters, and with external elements (in this example, the display 330, the memory medium 340, and the operation panel unit 350) connected to the system control unit 320. Various control signals and data are exchanged.

The display 330 is a small display such as a liquid crystal panel incorporated in the camera apparatus, and displays a captured image. In addition to the small display device incorporated in such a camera device, it is of course possible to transmit the image data to an external large display device for display.
The memory medium 340 can appropriately store images taken on various memory cards, for example, and the memory medium can be exchanged with the memory medium controller 341, for example. As the memory medium 340, in addition to various memory cards, a disk medium using magnetism or light can be used.
The operation panel unit 350 is provided with input keys for a user to give various instructions when performing a photographing operation with the camera device. The CPU 321 monitors an input signal from the operation panel unit 350, Various operation controls are executed based on the input contents.

Further, in such an imaging apparatus, the imaging target (subject) is not limited to a general image such as a person or a landscape, but can be applied to imaging a special fine image pattern such as a counterfeit detector or a fingerprint detector. Is. The apparatus configuration in this case is not the general camera apparatus shown in FIG. 13, but further includes a special imaging optical system and a signal processing system including pattern analysis. In this case as well, the operational effects of the present invention are included. This makes it possible to realize accurate image detection.
Furthermore, when configuring a remote system such as telemedicine, security monitoring, personal authentication, etc., it is also possible to configure the device configuration including a communication module connected to the network as described above, and a wide range of applications can be realized. It is.

It is sectional drawing which shows the structure of the non-silicide area | region of the solid-state imaging device (CMOS image sensor) formed by embodiment of this invention. It is a block diagram which shows the whole structure of the image sensor shown in FIG. It is a circuit diagram which shows the structure of each pixel of the image sensor shown in FIG. It is a top view which shows arrangement | positioning of each element on the semiconductor chip in the image sensor shown in FIG. It is sectional drawing which shows the manufacturing process of the image sensor shown in FIG. It is sectional drawing which shows the manufacturing process of the image sensor shown in FIG. It is sectional drawing which shows the manufacturing process of the image sensor shown in FIG. It is sectional drawing which shows the manufacturing process of the image sensor shown in FIG. It is sectional drawing which shows the manufacturing process of the image sensor shown in FIG. It is sectional drawing which shows the manufacturing process of the image sensor shown in FIG. It is a top view which shows the manufacturing process of the image sensor shown in FIG. It is sectional drawing which shows the manufacturing process of the image sensor shown in FIG. It is a block diagram which shows an example of the camera apparatus carrying the image sensor shown in FIG. It is sectional drawing which shows the structure of the transistor in the image sensor formed by the prior art.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 ... Si substrate, 101 ... Photodiode, 102 ... Gate insulating film, 103 ... Polysilicon gate electrode, 111, 112, 113 ... Insulating film.

Claims (10)

A first region where a silicide layer is formed on a semiconductor substrate; and a second region where the silicide layer is not formed;
In the first region, there is a side wool spacer formed by a three-layer insulating film on the side wall of the gate electrode of the field effect transistor,
The second region has a region that is covered with a three-layer insulating film that forms the side wool spacer and blocks a refractory metal when the silicide layer is formed.
A solid-state imaging device.   The solid-state imaging device according to claim 1, wherein the second area is a pixel area, and the first area is a peripheral circuit area.   The solid-state imaging device according to claim 1, wherein the region that is covered with the three-layer insulating film and blocks the refractory metal is a light receiving region of a photoelectric conversion unit.   The region covered with the three-layer insulating film in the second region extends on a gate electrode of a field effect transistor adjacent to a light receiving region of the photoelectric conversion unit. 3. The solid-state imaging device according to 3.   2. The solid-state imaging device according to claim 1, further comprising a side wool spacer formed by an uppermost insulating film among the three insulating films on a side wall of a gate electrode of the field effect transistor in the second region. .   2. The solid-state imaging device according to claim 1, wherein a source / drain region of the field effect transistor in the first region has an LDD structure by the side wool spacer.   6. The solid-state imaging device according to claim 5, wherein a source / drain region of the field effect transistor in the first region has an LDD structure by the side wool spacer. _2. The solid-state imaging device according to claim 1, wherein the three-layer insulating film is composed of an SiO ₂ film, an SiN film, and an SIO ₂ film in this order from the semiconductor substrate side. A first region where a silicide layer is formed on a semiconductor substrate; and a second region where the silicide layer is not formed;
In the first region, there is a side wool spacer formed by a three-layer insulating film on the side wall of the gate electrode of the field effect transistor,
In the method of manufacturing a solid-state imaging device, the second region includes a region that is covered with a three-layer insulating film that forms the side wool spacer and blocks a refractory metal when the silicide layer is formed. ,
Forming a first insulating film after forming the gate insulating film and the gate electrode on the semiconductor substrate;
Forming a second insulating film on the first insulating film;
Etching the mask after masking the second region with a first photoresist to form a sidewall of the second insulating film on the side wall of the gate electrode of the field effect transistor in the first region;
Forming a third-layer insulating film after removing the first photoresist;
Etching is performed after masking the region for blocking the refractory metal in the second region with a second photoresist, and three layers are formed on the side wall of the gate electrode of the field effect transistor in the region other than the region for blocking the refractory metal. Forming a sidewall by an eye insulating film;
Removing the second photoresist and then stacking a refractory metal to form a silicide;
A method for manufacturing a solid-state imaging device. 10. The first insulating film is formed of an SiO ₂ film, the second insulating film is formed of a SiN film, and the third insulating film is formed of an SIO ₂ film. Manufacturing method of solid-state imaging device.

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