JP2008123458A - Method for designing semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the difference from an actual characteristic by using effective capacitance and effective resistance corresponding to the characteristic of a gate level of a logic circuit to be calculated. <P>SOLUTION: In the gate level characteristic calculation of a design stage of a semiconductor integrated circuit, delay effective capacitance Cdelay, transition effective capacitance Cslew and effective resistance Cjk are stored in a library 1 in advance. After the layout of a design stage of the semiconductor integrated circuit, delay calculation of a logic gate circuit is executed on the basis of input slew data and the delay effective capacitance Cdelay, transition calculation of the logic gate circuit is executed on the basis of the input slew data and the transition effective capacitance Cslew, and current consumption calculation of the logic gate circuit is executed on the basis of the input slew data and current consumption effective capacitance Cpower. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for calculating characteristics of a logic circuit constituting a semiconductor integrated circuit.

  In recent years, miniaturization of semiconductor elements and lowering of voltage have progressed, and semiconductor integrated circuits have been increased in scale, speeded up, and reduced in power consumption. Many logic circuits are provided in a semiconductor integrated circuit. At the design stage of a semiconductor integrated circuit, a technique for calculating gate level timing, current consumption, noise characteristics, or the like of a logic circuit is frequently used (for example, see Patent Document 1).

  In the logic circuit gate level characteristic calculation method described in Patent Document 1 or the like, the gate level characteristic calculation is performed by replacing the gate visible from the outside of the logic circuit cell with an effective capacitance or an effective resistance.

However, the gate level timing characteristics, current consumption characteristics, or noise characteristics of the logic circuit have different potentials at each node of the gate, and if simply replaced with one effective capacitance or effective resistance, there is a difference from the actual characteristics. There is a problem of becoming larger.
US Pat. No. 5,740,347

  The present invention provides a method for designing a semiconductor integrated circuit, which can reduce a difference from an actual characteristic by using an effective capacitance or an effective resistance according to a gate level characteristic of a logic circuit to be calculated.

  A method for designing a semiconductor integrated circuit according to one aspect of the present invention is used for calculating a gate level characteristic at a design stage of a semiconductor integrated circuit, and includes a logic gate circuit, an effective capacitance set for each calculated characteristic calculation, and the logic gate. There is a library in which at least one effective resistance set for each circuit and characteristic calculation to be calculated is provided, and from the library, at least one of the effective capacitance and the effective resistance according to a target metric. A metric corresponding to the purpose based on at least one of the effective capacitance and the effective resistance corresponding to the selected gate circuit, and input Slew data input to the logic gate circuit; Performing a gate level characteristic calculation of the logic gate circuit.

  Furthermore, a semiconductor integrated circuit design method according to another aspect of the present invention is used for calculating a gate level characteristic at the design stage of the semiconductor integrated circuit, and includes a first crosstalk effective capacitance of the first logic gate circuit, a second A library in which a second crosstalk effective capacitance of a logic gate circuit and a signal wiring capacitance between the first logic gate circuit and the second logic gate circuit are provided in advance, and the library Selecting the first crosstalk effective capacitance, the second crosstalk effective capacitance, and the signal wiring capacitance, and first input slew data input to the first logic gate circuit, The first crosstalk effective capacitance, the second input slew data input to the second logic gate circuit, the second crosstalk effective capacitance, and the signal And a step of calculating a crosstalk noise between the first logic gate circuit and the first logic gate circuit based on an interwiring capacitance.

  According to the present invention, there is provided a method for designing a semiconductor integrated circuit capable of reducing a difference from an actual characteristic by using an effective capacitance or an effective resistance according to a gate level characteristic of a logic circuit to be calculated. Can do.

  Embodiments of the present invention will be described below with reference to the drawings.

  First, a method for designing a semiconductor integrated circuit according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a flowchart showing a method for designing a semiconductor integrated circuit as a system LSI, FIG. 2 is a diagram showing library information used for designing a semiconductor integrated circuit as a system LSI, and FIG. 3 is a semiconductor integrated circuit as a system LSI. FIG. 4 is a diagram showing a simplified model used for calculating the gate level characteristics, FIG. 5 is a diagram showing input / output characteristics of the gate, and FIG. 6 is a diagram showing gate delay calculation. 7 is a diagram showing the gate delay calculation result, FIG. 8 is a diagram showing the gate transition calculation, and FIG. 9 is a diagram showing the gate transition calculation result. In this embodiment, effective capacitance and execution resistance corresponding to gate level delay calculation, transition calculation, and consumption current calculation are provided.

  In the system LSI design method, as shown in FIG. 1, first, an RTL (Register Transfer Level) description using an HDL (Hardware Description Language) from an operation description close to a software program based on system designed information. Is synthesized. A semiconductor integrated circuit as a system LSI can be designed using various methods, and can be designed using a design method other than the flowchart shown in FIG. 1, and this embodiment is not limited to the flowchart shown in FIG. No (step S1).

  Next, a gate level logic circuit in which the RTL description is detailed is synthesized. At this time, as shown in FIG. 2, information of the library 1 in which physical design information 11, logical design information 12, timing information 13, noise information 14, gate level calculation information 15 and the like are stored (logical design information 12 and the like). ) Is used for logic synthesis.

  As the physical design information 11, the logical design information 12, the timing information 13, and the noise information 14, standardized information such as ALF (Advanced Library Format) information can be used. The gate level calculation information 15 is information corresponding to the logic gate circuit whose characteristics are to be calculated. The gate level calculation information 15 includes, for example, a delay effective capacitance Cdelay for delay calculation used for calculating a gate level characteristic of a semiconductor integrated circuit, a transition effective capacitance Cslew for transition calculation, a current consumption effective capacitance Cpower for current consumption calculation, A delay effective resistance Rdelay for delay calculation, a transition effective resistance Rslew for transition calculation, and a current consumption effective resistance Rpower for current consumption calculation are provided.

  The delay effective capacitance Cdelay, transition effective capacitance Cslew, current consumption effective capacitance Cpower, and effective resistance Rjk are values set for each logic gate circuit, and are different from each other, and also depend on the value of the applied power supply voltage. Different.

  Here, the delay effective capacitance Cdelay, the transition effective capacitance Cslew, the current consumption effective capacitance Cpower, the delay effective resistance Rdelay, the transition effective resistance Rslew, and the current consumption effective resistance Rpower are determined according to the logic gate circuit characteristics evaluated in advance as prototypes. It is preferable to leave it on. In the subsequent steps, the information of the library 1 is used as appropriate (step S2).

  Subsequently, equivalence verification is performed to determine whether the logic function is correct using the logic simulator and the library 1 or the like. Here, in addition to equivalence verification, timing verification using STA (Static Timing Analysis) may be performed (step S3). Then, the connection relation data (net list) such as macro cells constituting the logic circuit is checked. Here, the steps up to the floor plan are the simulations before the layout, and the steps after the floor plan are the simulations after the layout (step S4).

  Next, LSI size estimation, power consumption estimation, chip area estimation, package estimation, etc. (floor plan) are performed (step S5). Subsequently, power supply wirings between the macrocells and within the macrocells are arranged (step S6). Then, trial and estimation of CTS (Clock Tree Synthesis) are performed (step S7).

  Subsequently, placement and routing is performed between the macro cells and within the macro cells. Here, the power supply connection and the arrangement wiring of the logic gate circuit for calculating the gate level characteristic of the semiconductor integrated circuit are made. Logic gate circuits include inverters, AND gates, NAND gates, OR gates, NOR gates, etc., which input “High” or “Low” level signals and output “High” or “Low” level signals. (Step S8).

  Then, as shown in FIG. 3, characteristic calculations such as delay calculation, transition calculation, and current consumption calculation are performed at the logic gate circuit level where the power supply connection and the placement and routing are made. The logic gate circuit is generally expressed in a simplified form (modeling) as shown in FIG. An input signal IN is input to the input side of the gate 2 as a logic gate circuit, and an effective capacitor 3 is provided between the output side node N1 and the low potential side power supply (ground potential) Vss, and the output signal is output from the node N1. OUT is output. In addition to the effective capacitance 3, modeling may be performed by adding an effective resistance between the gate 2 and the node N1.

Here, in the case where the gate 2 as the logic gate circuit is an inverter, for example, as shown in FIG. 5A, when the input signal IN changes from “High” level to “Low” level, The signal level of the output signal OUT gradually changes from the “Vss” level to the “Vdd” level. The falling characteristic (Input Slew) of the input signal IN is displayed as a linear change. Here, the delay time t _delay is expressed as a time between a time t1 when the input signal IN becomes 50% Vdd and a time t2 when the output signal OUT becomes 50% Vdd. The transition time t _slew is represented by a time between a time t11 when the output signal OUT becomes 10% Vdd and a time t12 when the output signal OUT becomes 90% Vdd. The output signal OUT during the time delay _{t delay} is different in waveform from the output signal OUT after a delay time _{t delay,} the larger the value of the slope. This difference in inclination is because the potential of the node of the gate 2 as the applied logic gate circuit is different.

On the other hand, when the gate 2 as the logic gate circuit is an inverter, for example, as shown in FIG. 5B, when the input signal IN changes from the “Low” level to the “High” level, the output is performed after a predetermined time elapses. The signal level of the signal OUT gradually changes from the “Vdd” level to the “Vss” level. Note that the rising characteristic (Input Slew) of the input signal IN is displayed as a linear change. Here, the delay time t _delay is represented by a time between a time t1a when the input signal IN becomes 50% Vdd and a time t2a when the output signal OUT becomes 50% Vdd. The transition time t _slew is represented by a time between a time _t12a when the output signal OUT becomes 90% Vdd and a time t11a when the output signal OUT becomes 10% Vdd. The output signal OUT during the time delay _{t delay} is different in waveform from the output signal OUT after a delay time _{t delay,} the larger the value of the slope. This difference in inclination is because the potential of the node of the gate 2 as the applied logic gate circuit is different.

  Next, in the delay calculation of the logic gate circuit, as shown in FIG. 6, the delay is performed using a simulation tool such as SPICE (Simulation Program with Integrated Circuit Emphasis) or HSPICE based on the input slew data and the delay effective capacitance Cdelay. Calculation is performed. Note that the value of the delay effective capacitance Cdelay is not necessarily one, and a plurality of values may be set in accordance with the potential of the node of the logic gate circuit. In that case, the accuracy is further improved, but the simulation time is increased. Here, the input slew data and the delay effective capacitance Cdelay are used, but the simulation may be executed by adding the delay effective resistance Rdelay (step S9a).

Subsequently, the delay calculation result of the logic gate circuit shows that when the gate 2 as the logic gate circuit is an inverter, for example, as shown in FIG. 7, the calculated delay time t _delayA has an input signal IN of 50% Vdd. Is expressed as a time between the time t1 and the time t2 when the output signal OUT becomes 50% Vdd. Here, the output signal OUT indicated by a broken line is a waveform when the transition effective capacitance Cslew is used as the effective capacitance, and the delay time t _delayB calculated using the transition effective capacitance Cslew is 50% of the input signal IN. It is expressed as a time between a time t1 when Vdd is reached and a time t3 when the output signal OUT becomes 50% Vdd. The relationship between the actual delay time t _delay , delay time t _{delayA ,} and delay time t _delayB is
| tdelay-tdelayA | <<< tdelay-tdelayB |
Can be expressed as Although not shown, even when the common effective capacity 3 is used, the difference from the actual delay time t _delay cannot be reduced. That is, when using the delay effective capacitance Cdelay as delay calculations provided beforehand library 1, it becomes possible to minimize the difference between the actual delay time t _delay (step S9b).

  In the transition calculation of the logic gate circuit, as shown in FIG. 8, the transition calculation is performed using a simulation tool such as SPICE (Simulation Program with Integrated Circuit Emphasis) or HSPICE based on the input slew data and the transition effective capacitance Cslew. Is executed. Note that the value of the transition effective capacitance Cslew is not necessarily one, and a plurality of values may be set in accordance with the potential of the node of the logic gate circuit. In that case, the accuracy is further improved, but the simulation time is increased. Here, the Input Slew data and the transition effective capacitance Cslew are used, but the simulation may be executed by adding the transition effective resistance Rslew (step S9c).

Next, the transition calculation result of the logic gate circuit shows that when the gate 2 as the logic gate circuit is an inverter, for example, as shown in FIG. 9, the calculated transition time t _slewA is 10% Vdd as the input signal IN. Is expressed as a time between the time t11 and the time t12 when the output signal OUT becomes 90% Vdd. Here, the output signal OUT indicated by a broken line is a waveform when the effective delay capacity Cdelay is used as the effective capacity, and the transition time t _slewB calculated using the effective delay capacity Cdelay is 10% of the input signal IN. It is expressed as a time between time t4 when Vdd is reached and time t5 when the output signal OUT becomes 90% Vdd. The relationship between the actual transition time t _slew , transition time t _slewA, and transition time t _slewB is
| tslew-tslewA | <<<< tslew-tslewB |
Can be expressed as Although not shown, even if a common effective capacity is used, the difference from the actual transition time t _sew cannot be reduced. That is, if the transition effective capacity Cslew for transition calculation provided in the library 1 in advance is used, the difference from the actual transition time _tslew can be minimized (step S9d).

  Subsequently, in the current consumption calculation of the logic gate circuit, the current consumption calculation is executed using a simulation tool such as SPICE (Simulation Program with Integrated Circuit Emphasis) or HSPICE based on the Input Slew data and the effective current consumption capacitance Cpower. The The simulation may be performed by adding an effective current consumption resistance Rpower. Here, the current consumption effective capacitance Cpower is a value set according to the potential of the node of the logic gate circuit, and is different from the delay effective capacitance Cdelay and the transition effective capacitance Cslew (step S9e). Then, the difference between the current consumption calculation result of the logic gate circuit and the actual current consumption can be minimized (step S9f).

  If the gate level characteristic calculation result is larger than a predetermined difference compared to the actual characteristic, the work is restarted from the floor plan.

  Next, SI (Signal Integrity) is verified. In the SI verification after calculating the gate level characteristic in step S9, verification of crosstalk, crosstalk delay, power supply drop, voltage (IR) drop, etc. of the entire semiconductor integrated circuit as the system LSI is performed (step S10).

  Subsequently, for example, layout data is verified using a layout verification tool such as DRC (Design Rule Checker), LVS (Layout Versus Schematic), and the designed data is a CAD layout in GDS (Graphic Data System) II format. It is replaced with data (step S11).

  Subsequently, for example, after DFM (Design for Manufacturing) is performed, the design work of the semiconductor integrated circuit is completed.

  As described above, in the design method of the semiconductor integrated circuit of this embodiment, the delay effective capacitance Cdelay, the transition effective capacitance Cslew, the current consumption effective capacitance Cpower, the delay effective resistance Rdelay, the transition effective resistance Rslew, and the current consumption effective resistance Rpower are: Stored in the library 1 in advance. After the layout of the design stage of the semiconductor integrated circuit, the delay calculation of the logic gate circuit is executed using the simulation tool based on the input slew data and the delay effective capacitance Cdelay of the logic gate circuit, and the transition calculation of the logic gate circuit is executed. The simulation tool is executed based on the data and the transition effective capacitance Cslew of the logic gate circuit, and the current consumption calculation of the logic gate circuit is performed based on the Input Slew data and the current consumption effective capacitance Cpower of the logic gate circuit. To be executed.

  For this reason, the delay effective capacitance Cdelay, transition effective capacitance Cslew, consumption current effective capacitance Cpower, delay effective resistance Rdelay, transition effective resistance Rslew, and consumption current effective resistance Rpower selected for each logic gate circuit are used. Since the gate level characteristic corresponding to the metric is calculated, the difference from the actual characteristic can be reduced as compared with the conventional case.

  Although the present embodiment is applied to gate level delay calculation, transition calculation, or current consumption calculation after layout, it can be applied to gate level characteristic calculation before layout.

  Next, a method for designing a semiconductor integrated circuit according to the second embodiment of the present invention will be described with reference to the drawings. FIG. 10 is a diagram showing library information used for designing a semiconductor integrated circuit as a system LSI, and FIG. 11 is a diagram showing crosstalk noise calculation. In this embodiment, library information is changed.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 10, the library 1a is provided with physical design information 11, logic design information 12, timing information 13, noise information 14, and gate level calculation information 15a. The gate level calculation information 15a includes, for example, a delay effective capacitance Cdelay for delay calculation used for calculating gate level characteristics of a semiconductor integrated circuit, a transition effective capacitance Cslew for transition calculation, a current consumption effective capacitance Cpower for current consumption calculation, Delay effective resistance Rdelay, transition effective resistance Rslew, current consumption effective resistance Rpower, crosstalk effective capacitance Ccta, crosstalk effective capacitance Cctb, and signal wiring capacitance Ch are provided.

  The crosstalk effective capacitance Ccta, the crosstalk effective capacitance Cctb, and the signal wiring capacitance Ch are used to calculate crosstalk noise generated between the logic gate circuits. The crosstalk effective capacitance Ccta, the crosstalk effective capacitance Cctb, and the signal wiring capacitance Ch are set to values different from the delay effective capacitance Cdelay, the transition effective capacitance Cslew, and the current consumption effective capacitance Cpower, respectively.

  Here, the crosstalk effective capacitance Ccta and the crosstalk effective capacitance Cctb are effective capacitances when the logic gate circuit is operating, and are fitted in accordance with the logic gate circuit characteristics evaluated in advance as a prototype. Is preferred. The inter-signal line capacitance Ch is the inter-signal line capacitance between the logic gate circuits after layout. For example, when the output signal line is disposed between the interlayer insulating films, the data of the interlayer insulating film (such as relative dielectric constant) ) And the like.

  As shown in FIG. 11, in the crosstalk noise calculation, a gate 2a as a logic gate circuit, a gate 2b as a logic gate circuit, a crosstalk effective capacitance Ccta, a crosstalk effective capacitance Cctb, and a signal wiring capacitance Ch are used. It can be expressed in a simplified form (modeling).

  An input signal INa is input to the gate 2a as a logic gate circuit, and a crosstalk effective capacitance Ccta is provided between the output-side node N2 and the low-potential-side power supply (ground potential) Vss. An output signal OUTa is output. An input signal INb is input to the gate 2b as a logic gate circuit, and a crosstalk effective capacitance Cctb is provided between the output-side node N3 and the low-potential-side power supply (ground potential) Vss. An output signal OUTb is output. A signal wiring capacitance Ch is provided between the node N2 and the node N3.

  The crosstalk noise calculation is performed based on, for example, SPICE based on input slew data input to the gate 2a, crosstalk effective capacitance Ccta, input slewb data input to the gate 2b, crosstalk effective capacitance Cctb, and signal wiring capacitance Ch. (Simulation Program with Integrated Circuit Emphasis) and simulation tools such as HSPICE are used. It is calculated how much crosstalk noise is included in the signal levels of the output signal OUTa and the output signal OUTb.

  Here, the input slew data, the crosstalk effective capacitance Ccta, the input slewb data, the crosstalk effective capacitance Cctb, and the signal wiring capacitance Ch are used, but the effective resistance during the operation of the gate 2a and the operation during the operation of the gate 2b are used. The simulation may be executed by adding an effective resistance.

  As described above, in the design method of the semiconductor integrated circuit of this embodiment, the delay effective capacitance Cdelay, transition effective capacitance Cslew, effective resistance Cjk, crosstalk effective capacitance Ccta, crosstalk effective capacitance Cctb, and signal wiring capacitance Ch are It is stored in advance in the library 1a. After layout at the design stage of the semiconductor integrated circuit, the calculation of the crosstalk noise of the logic gate circuit is performed using a simulation tool based on the crosstalk effective capacitance Ccta, the crosstalk effective capacitance Cctb, and the signal wiring capacitance Ch.

  For this reason, since the crosstalk noise calculation, which is the target metric, is calculated using the crosstalk effective capacitance Ccta, the crosstalk effective capacitance Cctb, and the signal wiring capacitance Ch selected for each logic gate circuit, The difference from the characteristic can be reduced as compared with the prior art.

  The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention.

  For example, in the embodiment, the present invention is applied to a system LSI, but it can also be applied to a SoC (System on a Chip) in which a memory, a logic circuit, an analog circuit, and the like are mounted on the same chip. In the first embodiment, the SI verification is performed at the semiconductor correction circuit level after performing a plurality of items of the gate level characteristic calculation of the logic gate circuit. The characteristic verification at the logic gate circuit level and the semiconductor correction circuit level may be performed at the same time by switching appropriately.

The present invention can be configured as described in the following supplementary notes.
(Appendix 1) Used for calculating gate level characteristics at the design stage of a semiconductor integrated circuit, and for each logic gate circuit, effective delay capacity, effective transition capacity, effective current consumption capacity, effective delay resistance, effective effective resistance, and effective current consumption A resistor having a pre-set library, and selecting from the library at least one of the delayed effective capacitance and the effective resistance; Input Slew data input to the logic gate circuit; and the delay A method for designing a semiconductor integrated circuit, comprising: calculating delay characteristics of the logic gate circuit using a simulation tool based on an effective capacitance and at least one of the delay effective resistance.

(Appendix 2) Used to calculate gate level characteristics at the design stage of a semiconductor integrated circuit, and for each logic gate circuit, effective delay capacity, effective transition capacity, effective current consumption capacity, effective delay resistance, effective effective resistance, and effective current consumption A resistor having a library provided in advance, and selecting from the library at least one of the transition effective capacitance and the transition effective resistance; Input Slew data input to the logic gate circuit; and A method for designing a semiconductor integrated circuit, comprising: executing a transition characteristic calculation of the logic gate circuit using a simulation tool based on at least one of a transition effective capacitance and the effective resistance.

(Supplementary Note 3) Used for calculating gate level characteristics at the design stage of a semiconductor integrated circuit, and for each logic gate circuit, effective delay capacity, effective transition capacity, effective current consumption capacity, effective delay resistance, effective effective resistance, and effective current consumption A resistor having a previously provided library, selecting at least one of the current consumption effective capacity and the current consumption effective resistance from the library; and input slew data input to the logic gate circuit; A method for designing a semiconductor integrated circuit, comprising: calculating a current consumption characteristic of the logic gate circuit using a simulation tool based on at least one of the current consumption effective capacitance and the current consumption effective resistance.

3 is a flowchart showing a method for designing a semiconductor integrated circuit as a system LSI according to the first embodiment of the present invention. FIG. 3 is a diagram showing library information used for designing a semiconductor integrated circuit as a system LSI according to the first embodiment of the present invention. 5 is a flowchart showing a method for calculating gate level characteristics of a semiconductor integrated circuit as a system LSI according to the first embodiment of the present invention. FIG. 5 is a diagram illustrating a simplified model used for gate level characteristic calculation according to the first embodiment of the present invention. The figure which shows the input-output characteristic of the gate which concerns on Example 1 of this invention. FIG. 6 is a diagram illustrating gate delay calculation according to the first embodiment of the invention. The figure which shows the gate delay calculation result which concerns on Example 1 of this invention. The figure which shows the gate transition calculation which concerns on Example 1 of this invention. The figure which shows the gate transition calculation result which concerns on Example 1 of this invention. FIG. 10 is a diagram showing library information used for designing a semiconductor integrated circuit as a system LSI according to the second embodiment of the present invention. The figure which shows the crosstalk noise calculation which concerns on Example 2 of this invention.

Explanation of symbols

1, 1a Library 2, 2a, 2b Gate 3 Effective capacity 11 Physical design information 12 Logical design information 13 Timing information 14 Noise information 15 Gate level calculation information Ccta, Cctb Crosstalk effective capacity Cdelay Delay effective capacity Ch Signal wiring capacity Cslew Transition effective capacitance Cpower Current consumption effective capacitance IN, Ina, INb Input signal N1-3 Node OUT, OUTa, OUTb Output signal Rjk Effective resistance t1, 11a, t2, t2a, t3, t4, t5, t11, t11a, t12, t12a time _{t delay, t delayA, t delayB} delay time _{t slew, t slewA, t slewB} transition time Vdd high-potential-side power supply voltage Vss lower potential power source (ground potential)

Claims (5)

An effective capacitance that is used for calculating a gate level characteristic at the design stage of a semiconductor integrated circuit and is set for each of the logic gate circuit and the calculated characteristic calculation, and an effective resistance that is set for each of the logical gate circuit and the calculated characteristic calculation Has at least one pre-installed library,
Selecting at least one of the effective capacitance and the effective resistance from the library according to a target metric;
Based on Input Slew data input to the logic gate circuit and at least one of the effective capacitance and the effective resistance corresponding to the selected gate circuit, the gate level of the logic gate circuit with a metric according to the purpose Performing a characteristic calculation; and
A method for designing a semiconductor integrated circuit, comprising:   The delay characteristic of the logic gate circuit is calculated based on the input sleep data input to the logic gate circuit and at least one of the effective delay capacity and effective delay resistance of the logic gate circuit stored in the library. The method of designing a semiconductor integrated circuit according to claim 1.   The transition characteristics of the logic gate circuit are calculated based on input slew data input to the logic gate circuit and at least one of a transition effective capacitance and a transition effective resistance of the logic gate circuit stored in the library. The method of designing a semiconductor integrated circuit according to claim 1.   The current consumption characteristic of the logic gate circuit is based on at least one of the input sleep data input to the logic gate circuit and the effective current consumption capacity and effective current resistance of the logic gate circuit stored in the library. The method for designing a semiconductor integrated circuit according to claim 1, wherein the method is calculated as follows. The first crosstalk effective capacitance of the first logic gate circuit, the second crosstalk effective capacitance of the second logic gate circuit, and the first logic gate circuit are used for calculating the gate level characteristic at the design stage of the semiconductor integrated circuit. A signal wiring capacitance between the logic gate circuit and the second logic gate circuit has a library provided in advance,
Selecting the first crosstalk effective capacitance, the second crosstalk effective capacitance, and the signal line capacitance from the library;
The first input slew data input to the first logic gate circuit, the first crosstalk effective capacitance, the second input slew data input to the second logic gate circuit, the second cross Performing a crosstalk noise calculation between the first logic gate circuit and the first logic gate circuit based on the talk effective capacitance and the signal line capacitance;
A method for designing a semiconductor integrated circuit, comprising:

Images