JP2008109331A - Transmission path, wiring board having the same and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To adjust a transmission loss by appropriately controlling the cross-sectional structure of a transmission path in a wiring board connected to a multi-pin high speed LSI. <P>SOLUTION: In the multi-layer wiring board, where every signal wiring is arranged in different two wiring layers and a plurality of differential pairs are formed so as to be shifted with fixed distances in a horizontal direction so that they can be prevented from being vertically overlapped with each other, when the shifting quantity of the two signal wiring in the horizontal direction is defined as d, and the thickness of an insulating layer separating the two signal wiring is defined as t, and the sum of a wiring cycle with adjacent signal wiring, that is, the interval with the adjacent differential wiring and the signal wiring width is defined as p, there is a section where a value D shown by D=d(t/p<SP>3</SP>)<SP>1/2</SP>falls within the range of 0.2<D<1,2. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a wiring board for mounting a semiconductor element that inputs and outputs a large number of high-speed signals.

  With the recent increase in speed of LSI (Large Scale Integrated Circuit), signal attenuation in a transmission line on a wiring board on which the LSI is mounted has become a problem. In the case of a signal having a speed in the GHz range, signal attenuation due to the skin effect increases, and the deterioration of the transmission waveform becomes remarkable. Therefore, it is required to realize a transmission line capable of transmitting a high-speed signal while maintaining a good signal waveform with low loss.

  At the same time as increasing the speed of LSI, the number of LSI signals and the miniaturization of substrate connection pads are also progressing. In other words, the number of signals input / output from the LSI is increasing for higher functionality of the LSI, but it is necessary to reduce the outer size to increase the functionality and cost of the LSI. Refinement of the diameter and pad spacing is progressing. As a result, there is a demand for the realization of a transmission line that can route multiple signals with high density in a wiring board connected to an LSI.

  Thus, in order to cope with higher speed, higher pins, and miniaturization of LSIs, there is a demand for signal wiring that can transmit high-speed signals with low loss and can be wired with high density.

  In order to meet this demand, a differential transmission line that transmits one signal by two signal wirings has been proposed. Since the differential transmission line uses the difference between the signals propagated through the two signal wirings as one signal, common mode noise can be canceled and the amplitude can be doubled.

  Typical differential transmission line structures include a coplanar structure as shown in FIG. 25 (a), a microstrip structure as shown in FIG. 25 (b), a strip structure as shown in FIG. 25 (c), and FIG. There are a tandem structure as shown in (d), a diagonal structure as shown in FIG.

  As for the differential transmission line having a diagonal structure, an example applied to a transmission line in an LSI is shown in Patent Document 1, and an example applied to a wiring board is shown in Non-Patent Document 1. The diagonal structure has a structure in which signal wirings are arranged in different wiring layers and are shifted by a certain distance in the horizontal direction. By adopting this structure, an effect of reducing crosstalk with adjacent wirings in particular is shown.

  On the other hand, in order to transmit high-speed signals with low loss, not only transmission lines but also LSIs connected to these transmission lines are controlled. For example, in order to correct a transmission loss generated in a signal line of a wiring board, a waveform correction circuit called pre-emphasis is incorporated in an LSI transmission circuit. This is because the general digital waveform is a rectangular wave and includes a wide frequency component from low frequency to high frequency, but the loss amount in the transmission line is larger in the high frequency component, so the waveform rises dull and the waveform deteriorates Will occur. As a countermeasure, the amount of attenuation of the high-frequency component is preliminarily compensated by amplifying only the high-frequency component of the transmission signal, and the frequency spectrum of the signal after propagating through the transmission line is brought close to the ideal distribution, thereby reducing the waveform. Pre-emphasis is a method for sharpening the rise. As an example, Patent Document 2 discloses a technique for evaluating transmission line loss by experiment or simulation, and shows an example of calculating a transmission waveform when pre-emphasis is applied to a transmission signal. As a technique for preliminarily compensating for the loss of high-frequency components in the transmission line, Patent Document 3 discloses a technique for adaptively controlling the driver on the transmission side in response to the transmission loss. In this way, an optimum transmission waveform can be obtained by determining the pre-emphasis setting after evaluating the propagation characteristics of the transmission line in advance.

Japanese Patent Laid-Open No. 2005-101588 JP 2006-090788 A JP-T-2002-525977 Proceedings of the 2006 IEICE General Conference p316 “Crosstalk Measurement on Shifted Pairline Signal Lines”

  However, in Patent Document 1 and Non-Patent Document 1, there is no clear design guideline for minimizing the loss of the differential transmission line having a diagonal structure.

In general, the transmission loss α of the transmission line is expressed by the following formula (1) using the resistance R, conductance G, and characteristic impedance Z ₀ per unit length.

_{α = (1/2) (R /} Z 0) + (1/2) GZ 0 (1)
In Equation (1), the first term represents conductor loss and the second term represents dielectric loss. The conductor loss is caused by the resistance of the transmission line conductor. Particularly at high frequencies, the current flows only on the surface of the conductor due to the skin effect, so that the cross-sectional area through which the current flows becomes small, and the conductor loss increases. The dielectric loss of the second term is due to the dielectric constituting the line, and is proportional to the dielectric loss tangent tan δ of the dielectric and the frequency f. The second term G can be expressed by the following equation (2) using the capacitance C of the line, the frequency f, and the dielectric loss tangent tan δ of the insulator.

G = 2πfCtanδ (2)
In general, when the width of the signal line is increased, the cross-sectional area through which the current passes is increased, so that the resistance R is reduced and the conductor loss is reduced. On the other hand, the capacitance C is increased and the conductance G is increased and the dielectric loss is increased. To increase. Accordingly, the relationship between the dimensions such as the width and interval of the signal line and the transmission loss is not clear, and there is no design guideline generally applicable to reduce the transmission loss. And in actual transmission line design, the line width is determined so that the termination resistance and the characteristic impedance of the transmission line are equal, and the line width and line spacing are changed to reduce transmission loss. It was not done.

  Further, there are the following problems with respect to a method for determining the pre-emphasis setting after evaluating the propagation characteristics of the transmission line as disclosed in Patent Documents 2 and 3 in advance. The pre-emphasis set in the LSI is adjusted according to the loss of the wiring. However, since the length of many wirings connected to the LSI is not constant, the size of the loss varies depending on the wiring. Accordingly, if the waveform correction for all wirings is set to the same setting, optimum correction cannot be performed for all signals. However, adjusting the waveform correction for each signal wiring requires much cost and man-hours in an LSI having multiple signals.

  In view of the above problems, an object of the present invention is to realize a differential transmission line capable of adjusting transmission loss by appropriately designing a cross-sectional structure of the transmission line in a wiring board connected to a multi-pin high-speed LSI. That is.

  The present invention also uses the above-described differential transmission line to perform waveform correction with the same setting for all signals when connecting to an LSI having multiple signals, so that an optimal correction can be obtained. An object of the present invention is to provide a wiring board having a line.

According to the present invention, a plurality of pairs of differential pairs are formed in which signal wirings are arranged one by one in two different wiring layers, and the two signal wirings are shifted by a certain distance in the horizontal direction so as not to overlap each other. In the multilayer wiring board, the horizontal shift amount of the two signal wirings is d, the thickness of the insulating layer separating the two signal wirings is t, the wiring cycle between adjacent signal wirings, that is, the adjacent differential wiring and Where the value D represented by D = d (t / p ³ ) ^1/2 falls within the range of 0.2 <D <1.2, where p is the sum of the distance between the two and the signal wiring width There is provided a transmission line characterized in that

  In the above transmission line, a ground plane or a power plane may be formed on the upper, lower, or both upper and lower wiring layers of the two wiring layers.

  In the above transmission line, it is preferable that the wiring period with the adjacent signal wiring is different depending on the position, or the signal wiring width may be different depending on the position.

The wiring board according to the present invention has a plurality of pairs of differential pairs in which signal wirings are arranged one by one in two different wiring layers, and the two signal wirings are shifted by a certain distance in the horizontal direction so as not to overlap each other. In the multi-layered wiring board, the horizontal shift amount of the two signal wirings is d, the thickness of the insulating layer separating the two signal wirings is t, the wiring cycle between adjacent signal wirings, that is, the adjacent differential wiring The value D represented by D = d (t / p ³ ) ^1/2 is within the range of 0.2 <D <1.2, where p is the sum of the distance between the two and the signal wiring width. It is characterized by that. Hereinafter, this D is referred to as a standardized shift amount.

  The differential pair is characterized in that an interval between adjacent differential pairs is increased as the distance from the semiconductor element mounted on the upper part of the wiring board increases. At this time, the standardized shift amount D is maintained in the range of 0.2 <D <1.2 while simultaneously adjusting the shift amount to keep the characteristic impedance constant.

  Further, the differential pair is characterized in that the wiring width increases as the distance from the semiconductor element increases.

  The wiring board having the differential pair includes a differential pair having a long wiring length and a differential pair having a short wiring length, and the differential pair is connected to a semiconductor element mounted on the wiring board. The wiring period at a point where the differential pair having a long wiring length is present is wider than the wiring period of the differential pair having a short wiring length at an equal distance from the semiconductor element.

  The present invention also provides a semiconductor device in which a semiconductor element or a semiconductor package is mounted on the wiring board.

[Operation of the invention]
The differential pair has a structure in which signal wires are arranged one by one in two different wiring layers and shifted by a certain distance in the horizontal direction. The differential characteristic impedance of this differential pair is uniquely determined by the signal wiring width w, the insulating layer thickness t, the shift amount d, the wiring period p, and the dielectric constant ε _r of the insulating layer. Usually, the dielectric constant and thickness of the insulating layer are determined by the material and type of the substrate, and the wiring cycle is determined to some extent by restrictions such as the pad pitch of the semiconductor element to which the signal wiring is connected, the via pitch of the substrate, and the area of the substrate. Is done. The remaining two elements are the signal wiring width w and the shift amount d. These two elements have a certain degree of freedom, and the differential characteristic impedance can be adjusted by changing the two elements. A certain value of the differential characteristic impedance can be realized by a combination of a plurality of signal wiring widths and shift amounts. That is, an equal differential characteristic impedance can be realized by increasing the shift amount when the signal wiring width is wide and decreasing the shift amount when the signal wiring width is narrow.

  When changing the signal wiring width and shift amount while keeping the differential characteristic impedance constant, reducing the shift amount and narrowing the signal wiring width will reduce the cross-sectional area of the signal wiring, resulting in increased conductor loss. . Conversely, when the signal wiring width is increased and the shift amount is increased with respect to the wiring period / insulating layer thickness, the coupling between adjacent signal wirings becomes stronger than the electric field coupling between the signal wirings constituting the differential pair. As a result, the current concentrates on the end portion of the signal wiring and the cross-sectional area through which the current passes becomes small, and the conductor loss increases. Accordingly, the conductor loss increases if the signal wiring width and the shift amount are too small or too large. In view of this, the cross-sectional area through which the current passes can be widened by keeping the above-mentioned standardized shift amount D within the range of 0.2 <D <1.2, thereby realizing a differential transmission line with a small conductor loss. Can do.

  In addition, if the wiring period is widened while keeping the differential characteristic impedance constant, the electromagnetic coupling with the adjacent wiring is reduced to reduce the shift amount or widen the signal wiring width. A current flows through the surface, and the conductor loss can be reduced. Thus, the transmission loss can be reduced by widening the wiring cycle.

  The transmission line according to the present invention has an effect that transmission loss can be reduced, and the wiring board having this transmission line can be used even when a wiring is drawn out from a semiconductor element in which a large number of signal wirings (signal pads) are formed at high density. The transmission loss can be kept small while keeping the differential characteristic impedance constant.

  Further, by making the transmission loss per unit length of the signal wiring having a long wiring length smaller than that of the signal wiring having a short wiring length, it is possible to make the transmission loss in the entire wiring the same level. As a result, even if the waveform correction circuit mounted on the semiconductor element has the same setting, optimum waveform correction can be performed for a plurality of signal wirings having different wiring lengths, and an increase in circuit scale is suppressed. Thus, a semiconductor device can be provided at low cost.

[First Embodiment]
Next, a first embodiment of the present invention will be described with reference to the drawings.

[Construction]
First, the structure will be described.

  FIG. 1 is a perspective view of a semiconductor device according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view of the semiconductor device. In this semiconductor device, a semiconductor integrated circuit element 2 is mounted on the upper surface of a multilayer wiring board 1 and connected to another circuit via a connection conductor 3.

  The wiring substrate 1 is configured by laminating a first insulating layer 1a, a second insulating layer 1b, a third insulating layer 1c, and a fourth insulating layer 1d. The first wiring layer 5a is formed on the upper surface of the first insulating layer 1a, the second wiring layer 5b is formed on the upper surface of the second insulating layer 1b, and the third wiring layer 5c is formed on the upper surface of the third insulating layer 1c. A fourth wiring layer 5d is formed on the upper surface of the fourth insulating layer 1d, and a fifth wiring layer 5e is formed on the lower surface. The signal wiring 4a is formed in the second wiring layer 5b, and the signal wiring 5b is formed in the third wiring layer 5c. Each signal wiring is provided in the fifth wiring layer 5e through the interlayer connection via. In addition to being connected to a BGA (Ball Grid Array) land 6, it is connected to a semiconductor element 2 on the upper part of the wiring board. The first wiring layer 5a is provided with a ground electrode 7, and the fourth wiring layer 5d is provided with a ground electrode 8. Both ground electrodes are connected to one of the wiring layers to have the same potential. . This ground electrode is also connected to the semiconductor element 2 and the BGA land 6 through the interlayer connection via and the connection conductor 3 in the same manner as the signal wiring.

FIG. 3 is a cross-sectional view of the wiring board 1 taken along the line AA ′ of FIG. Signal wiring 4a ₁ and 4b _1, the signal lines 4a ₂ and 4b _2, the signal lines 4a ₃ and 4b ₃ respectively constitute a pair of differential pairs. In this differential line, two signal wirings are arranged in a wiring layer adjacent to each other in the vertical direction, and are arranged at a distance d in the horizontal direction. In other words, the signal lines 4a ₁ and 4b _1, the signal lines 4a ₂ and 4b _2, and shifting the signal wiring 4a ₃ and 4b ₃ only in the horizontal direction, respectively distance d. These differential pairs are arranged at intervals of the wiring period p. The wiring period p is the distance between adjacent differential lines in the same layer, in other words, the sum of the distance between adjacent differential lines and the signal line width. The conductor thickness of each wiring is t _m , the thickness of the insulating layer is t _d , and the width of each signal wiring 4 is w.

The wiring period p, the shift amount d, the wiring width (line width) w, the insulating layer thickness t _d satisfies the following equation (4).

D = d (t _d / p ³ ) ^1/2 = 0.5 (4)
By keeping the standardized shift amount D within the range of 0.2 <D <1.2, a transmission line with a small transmission loss can be provided. The effect on the electrical characteristics will be described later using examples.

  Next, a method for manufacturing the package substrate will be described. A generally used circuit board is used as the board 1 in FIG. For example, a substrate using an organic material (epoxy, polyimide, fluororesin, PPE resin, phenol resin, or the like) or a substrate using an insulating material such as ceramic, glass, silicon, or a composite material can be used. Formation of patterning of each layer uses techniques such as etching and printing. The interlayer connection via is formed by forming a hole in the insulating material by laser irradiation or drilling, and conducting by filling with metal paste or plating.

[Example 1]
The wiring board 1 shown in the first embodiment is realized with a relative dielectric constant ε _r = 3.1 and a dielectric loss tangent tan δ = 0.024. This numerical value is a physical property value of an epoxy resin widely used as a material for a printed circuit board. When the insulating layer thickness t _d = 100 μm and the wiring period p = 100 μm, the differential characteristic impedance Z _diff when the wiring width w and the shift amount d were changed was calculated by an electromagnetic field simulator. The result is shown in FIG.

As can be seen from the calculation result of FIG. 4, when the wiring width w is fixed and the shift amount d is increased, the differential characteristic impedance increases. When the shift amount d is fixed and the wiring width w is increased, the differential characteristic impedance is increased. Z _diff decreases. When the target value of the differential characteristic impedance Z _diff of the differential pair is 100Ω, the combination of the wiring width w and the shift amount d can be realized by a plurality of combinations as shown in Table 1.

Similarly, in the case where the wiring period p is 75 μm and 150 μm, the combination of the wiring width w and the shift amount d at which the differential characteristic impedance Z _diff becomes 100Ω was obtained by electromagnetic field simulation. Then, the transmission loss α at a frequency of 10 GHz when Z _diff = 100Ω was obtained by simulation. FIG. 5 shows the relationship between the shift amount d and the transmission loss α per unit length.

  From FIG. 5, it can be seen that the transmission loss α has a minimum point with respect to the change in the shift amount d, and the transmission loss becomes large whether the shift amount is smaller or larger than that. The reason for this is shown below.

  6 is a magnetic field distribution when p = 100 μm, w = 33 μm, and d = 0 μm, FIG. 7 is a magnetic field distribution when p = 100 μm, w = 46 μm, and d = 82 μm, and FIG. 8 is p = 100 μm, w = 55 μm. , D = 160 μm. According to the simulation result, the transmission loss is the smallest in the structure of FIG.

  The transmission line having the structure shown in FIG. 6 has a shift amount d = 0 μm, the magnetic field is concentrated between the two signal wires constituting the differential pair, and the current is distributed on the sides where the signal wires face each other. On the other hand, in the transmission line of FIG. 7, the current is distributed also on the side surface of the signal wiring, and the wiring width w is wider than that of the transmission line of FIG.

  In the transmission line having the structure of FIG. 8, the wiring width w and the shift amount d are further increased. The magnetic field is concentrated between the signal wiring through which the current passes and the adjacent signal wiring. There is no magnetic field coupling between the differential pairs, and the electromagnetic field coupling with the ground electrode is weak. This indicates that the current is concentrated on the side of the signal wiring. As a result, the cross-sectional area of the path through which the current passes is reduced, and the transmission loss is increased.

  Thus, when the wiring width and the shift amount are small, the current is concentrated only on the opposite sides of the differential pair and the wiring width is small, so that the cross-sectional area through which the current passes becomes small. On the other hand, when the shift amount is large with respect to the wiring period and the insulation layer thickness, the magnetic field coupling is concentrated between adjacent signal wirings, and the current is distributed only on the horizontal side, and the current is not interrupted. The area becomes smaller. This indicates that the cross-sectional area of the current path is maximized when the shift amount d and the wiring width w are increased within a range where the signal wiring is not coupled to the adjacent signal wiring. That is, by setting the wiring width w and the shift amount d to appropriate values, the current is distributed on both the opposite side and the side of the differential pair of signal wirings, and the wiring width w can be increased to some extent. Therefore, the cross-sectional area through which the current passes can be increased. If the cross-sectional area of the current path is large, the resistance becomes small and the transmission loss can be reduced.

An appropriate value of the shift amount d varies depending on the wiring period p as can be seen from FIG. This is because even if the shift amount d is constant, if the wiring period p is large, the coupling amount with the adjacent signal wiring is small, the coupling between the signal lines of the differential pair is large, and the cross-sectional area of the current path is large. . The appropriate shift amount d also varies depending on the ratio p / t _d between the insulating layer thickness t _d and the wiring period p. This relative wiring period is reduced the greater the insulating layer thickness t _d with respect to the wiring period p, because the relative shift amount increases. Therefore, the optimum shift amount d depends on the wiring period p and the ratio p / t _{d of} the insulating layer thickness t _d and the wiring period p. Therefore, a standardized shift amount D obtained by normalizing the shift amount d with the wiring period p and (p / t) ^1/2 is defined as D = d (t / p ³ ) ^1/2 .

FIG. 9 is a graph in which the transmission loss shown in FIG. 5 is plotted against the normalized shift amount D. Since transmission loss becomes small when 0.2 <D <1.2, by selecting the wiring period p, the insulating layer thickness t _d , and the shift amount d so that the normalized shift amount D falls within this range. Thus, it is possible to provide a transmission line having a large cross-sectional area of the current path and a small resistance and a small transmission loss.

As an example of values of the wiring period p, the insulating layer thickness t _d , the shift amount d, and the wiring width w, D = 0.82 by setting p = 100 μm, t _d = 100 μm, d = 82 μm, and w = 46 μm. , 0.2 <D <1.2. Further, as an example in the case where the insulating layer thicknesses are different, by setting p = 75 μm, t _d = 30 μm, d = 50 μm, and w = 20 μm, D = 0.42, which can be within the above range. At these values, the transmission loss is minimal.

[Example 2]
As an example of realizing the wiring board 1 shown in the first embodiment with another insulating resin, it was realized with a relative dielectric constant ε _r = 4.0 and a dielectric loss tangent tan δ = 0.006. This numerical value is a physical property value of polyphenylene ether (PPE) widely used as a low-loss material for printed circuit boards.

The combination of the wiring width w and the shift amount d for the differential characteristic impedance Z _diff = 100Ω when the insulating layer thickness t _d = 100 μm and the wiring period p = 75 μm, 100 μm, 150 μm, and 200 μm is obtained by electromagnetic field simulation, The transmission loss at that time was calculated.

The transmission loss α per unit length with respect to the standardized shift amount D is shown in FIG. From this result, it can be seen that the transmission loss is small when the normalized shift amount D is in the range of 0.2 <D <1.2. This indicates that even if the relative dielectric constant of the insulating material changes, the optimal standardization shift amount does not change. Examples of values of the wiring period p, the insulating layer thickness t _d , the shift amount d, and the wiring width w are D = 0.83 by setting p = 150 μm, t _d = 100 μm, d = 152 μm, and W = 65 μm. , 0.2 <D <1.2. At this time, a transmission line with a small transmission loss can be realized.

[Example 3]
As an example in which the wiring substrate 1 shown in the first embodiment is realized with another insulating resin, it is realized with a relative dielectric constant ε _r = 2.0 and a dielectric loss tangent tan δ = 0.0005. This numerical value is a physical property value of tetrafluoroethylene / hexafluoropropylene copolymer (FEP) known as a fluororesin material.

When the insulating layer thickness is t _d = 30 μm, which is different from those of the first and second embodiments, and the wiring period p = 50 μm, 75 μm, and 100 μm, the wiring width w and the shift amount d of the differential characteristic impedance Z _diff = 100Ω are obtained. The combination was obtained by electromagnetic field simulation, and the transmission loss at that time was calculated.

The transmission loss α per unit length with respect to the standardized shift amount D is shown in FIG. From this result, it can be seen that the transmission loss α is small when the normalized shift amount is in the range of 0.2 <D <1.2. As an example of the values of the wiring period p, the insulating layer thickness t _d , the shift amount d, and the wiring width w, D = 0.83 by setting p = 100 μm, t _d = 30 μm, d = 90 μm, and w = 40 μm. , 0.2 <D <1.2. At this time, a transmission line with a small transmission loss can be realized.

[Second Embodiment]
Next, a second embodiment of the present invention will be described with reference to the drawings.

  FIG. 12 is a top view of the semiconductor device shown in FIG. 1, and shows only the signal wiring 4 among the conductors of each wiring layer shown in FIG. The signal wiring group 4 connected to the semiconductor element 2 spreads radially around the semiconductor element 2, and the wiring is densely arranged in a region close to the semiconductor element 2. It is a feature of this embodiment that the interval is wide.

FIGS. 13A and 13B are cross-sectional views of the wiring board 1 taken along the lines BB ′ and CC ′ in FIG. 12, respectively. Signal wiring 4a ₁ and 4b _1, the signal lines 4a ₂ and 4b _2, the signal lines 4a ₃ and 4b ₃ respectively constitute a pair of differential lines. In this differential line, two signal wirings are arranged in a wiring layer adjacent to each other in the vertical direction, and are shifted in the horizontal direction. The conductor thickness of each wiring is constant at t _m , the thickness of the insulating layer is t _d , and the width of the signal wiring 4 is constant at w.

In the cross section BB ′, the differential lines are arranged with _a period of pa, and the two signal wirings constituting the differential line are arranged with _a distance of da in the horizontal direction. In other words, the signal lines 4a ₁ and 4b _1, the signal lines 4a ₂ and 4b _2, and shifting the signal wiring 4a ₃ and 4b ₃ only in the horizontal direction, respectively distances _{d a.} In contrast in the cross section C-C 'is arranged between the differential lines in a cycle of p _b, it is shifted by a distance d _b two signal lines constituting the differential lines in the horizontal direction. _Here, a _{d a> d b, p a} <p b.

  In general, the characteristic impedance Z of the line is expressed by the following equation (5), where C is the capacitance between the inductance L of the signal line and the surrounding conductor.

Z = (L / C) ^1/2 (5)
Here, the inductance L and the capacitance C vary depending on the wiring width w, the differential inner line spacing d, the insulating layer thickness t _d , the conductor thickness t _m , the dielectric constant of the insulating layer, and the distance to the surrounding conductors. This embodiment is characterized in that the period p of the differential line increases as the distance from the semiconductor element 2 increases. However, the differential characteristic impedance is kept constant by decreasing the shift amount d of the line as the period p increases. ing.

  In this way, by changing the wiring period while keeping the differential characteristic impedance constant, a high-density wiring is provided in the region close to the semiconductor element, and a differential transmission line with low transmission loss is provided in the region far from the semiconductor element. can do. Since the differential characteristic impedance is kept constant, a transmission line without unnecessary reflection can be provided. The reason why the transmission loss is reduced when the wiring period is large will be described in Example 4.

[Example 4]
The wiring substrate 1 shown in the second embodiment is realized by a resin substrate having a relative dielectric constant ε _r = 3.1 and a dielectric loss tangent tan δ = 0.024. This is the same physical property value as the substrate of Example 1. The insulating layer thickness _{t d} and 100 [mu] m, 75 [mu] m wiring period p, 100 [mu] m, as 150 [mu] m, a differential characteristic impedance is determined by the electromagnetic field simulation of the shift amount d and the wiring width w to be 100 [Omega. FIG. 14 shows the result of plotting the transmission loss α in these cases against the wiring width w. It can be seen that the transmission loss α is reduced by increasing the wiring period p even if the wiring width w is constant.

Now, the wiring width w is constant in 35 [mu] m, 13 (a) 75 [mu] m wires period _{p a} near region in the semiconductor device, shift amount _{d a} and 37 [mu] m, 13 from the semiconductor element region away of (b) 25 [mu] m wiring period _{p b,} the shift amount _{d b} have configured the transmission line to 25 [mu] m. The transmission loss α obtained by electromagnetic field simulation when (p, d) = (75 μm, 37 μm) is 0.741 dB, and the transmission loss α when (p, d) = (150 μm, 25 μm) is 0.707 dB. In addition, the transmission loss was smaller when the wiring period was large (p, d) = (150 μm, 25 μm).

The magnetic field distribution and transmission loss in each cross section were obtained by electromagnetic field simulation. Figure 15 is a magnetic field distribution in the cross section of the _p a = 75 [mu] m, 16 is a magnetic field distribution in the cross section of the _p a = 150 [mu] m. When the wiring period p is large (FIG. 16), the magnetic field is concentrated and distributed between the differential pairs, and no magnetic field coupling is observed between adjacent wirings. On the other hand, when the wiring period p is small (FIG. 15), magnetic field coupling is also observed between adjacent wirings. Thus, by increasing the wiring period p, it is possible to weaken the magnetic field coupling between adjacent wirings, thereby providing a differential transmission line with a small transmission loss.

[Third embodiment]
Next, a third embodiment will be described with reference to the drawings.

FIGS. 17A and 17B are cross-sectional views of the wiring board 1 along BB ′ and CC ′ in FIG. 12, respectively. As in the second embodiment, the signal wirings 9a ₁ and 9b ₁ , the signal wirings 9a ₂ and 9b ₂ , and the signal wirings 9a ₃ and 9b ₃ each constitute a pair of differential lines. 'The shift amount of the differential line in _{d a2,} the wiring width _{w a2,} and the period between the differential lines and _{p a2,} sectional C-C' cross section B-B of the shift amount of the differential line in _{d b2,} wiring width _Is w _b2 and the period between the differential lines is p _b2 . Here, d _a2 > d _b2 , p _a2 <p _b2 , and w _a2 <w _b2 . The difference from the second embodiment is that the wiring width increases as the distance from the semiconductor element 2 increases. Here, d _a2 > d _b2 is set. However, since the relationship between d _a2 and d _b2 varies depending on the wiring period p and the wiring width w, there may be a case where d _a2 <d _b2 .

  As can be seen from FIG. 14, the transmission loss α can be reduced if the wiring period p and the wiring width w are appropriately increased. Since the transmission loss α has a minimum point with respect to the change in the wiring width w, it is desirable to increase the wiring width w in a range where the normalized shift amount D is 0.2 <D <1.2.

FIG. 18 is a diagram of the signal wirings 9a ₁ , 9a ₂ , 9a ₃ as viewed from above, and the wiring width is continuously increased as the distance from the semiconductor element 2 increases. In addition, as shown in FIG. 19, the wiring width of each signal wiring may be increased stepwise.

  In this way, by extending the wiring period and width of multiple signal wirings as the distance from the semiconductor element increases, wiring is performed at a high density in areas close to the semiconductor element, and differential transmission with low transmission loss in areas far from the semiconductor element. A track can be provided. Since the differential characteristic impedance is kept constant, a transmission line without unnecessary reflection can be provided.

[Example 5]
The wiring substrate 1 shown in the third embodiment is realized by a resin substrate having a relative dielectric constant ε _r = 3.1 and a dielectric loss tangent tan δ = 0.024. This is the same physical property value as the substrate of Example 1. The insulating layer thickness t _d = 30 μm, (p, w, d) = (50, 20, 60) in the region close to the semiconductor element of FIG. 17A, and ( p, w, d) = (75, 25, 80). The transmission loss α when (p, w, d) = (50, 20, 60) obtained by electromagnetic field simulation is 0.94 dB, and when (p, w, d) = (75, 25, 80). The transmission loss α was 0.87 dB, and the transmission loss was smaller when the wiring width and wiring period were wider.

[Fourth embodiment]
Next, a fourth embodiment of the present invention will be described. FIG. 20 is a top view of the semiconductor device of this embodiment. The semiconductor element 10 is mounted on the upper center of the multilayer wiring board 11, and the signal wiring provided on the wiring board 11 extends radially from the semiconductor element 10. The wiring substrate 11 is square, and some signal wirings 12 are routed toward the center of each side of the square, and another signal wiring 13 is routed toward the corner of the square. Therefore, the signal wiring 13 has a longer wiring length than the signal wiring 12. When the transmission line structure is the same, the transmission loss increases as the wiring length of the signal wiring increases. However, the wiring board of the present embodiment has the following structure to reduce the transmission loss between the signal wiring 12 and the signal wiring 13 substantially. The values are equal.

FIG. 21 is a sectional view taken along a curve DD ′ in FIG. FIG. 21A is a cross-sectional view in the vicinity of the signal wiring 12, and FIG. 21B is a cross-sectional view in the vicinity of the signal wiring 13. Note that each point on the curve DD ′ has the same wiring length from the semiconductor element 10. In FIG. 21, the wiring width of the signal wiring 12, the period between the differential wirings, and the shift amount are w _D1 , p _D1 , and d _D1 , respectively, and the wiring width of the signal wiring 13, the period between the differential wirings, and the shifting amount are w _D2, and _{p D2, d} D2.

The points on the curve DD ′ have the same wiring length from the semiconductor element 10, but here, the wiring widths of the signal wirings 12 and 13 and the period between the differential wirings are not the same, and p _D1 <p _D2 , w _D1 and _{<w D2,} the differential characteristic impedance by adjusting the amount of shift to the 100 _[Omega, is set to d D1 _{<d D2.}

  As described above, when a long signal wiring and a short signal wiring exist in the substrate, the signal wiring with a long wiring length is increased by widening the period between the differential wiring and the wiring width of the long signal wiring. Transmission loss per unit length can be reduced. Therefore, the transmission loss of the entire long signal wiring can be made substantially equal to the total transmission loss of the short signal wiring.

[Fifth embodiment]
Next, a fifth embodiment of the present invention will be described. FIG. 22 is a cross-sectional view of the semiconductor device of this embodiment. A semiconductor element 10 is mounted at the center of the upper surface of the multilayer wiring board 14, and a semiconductor module 17 is mounted at the end of the upper surface. The wiring board 14 includes first to fifth wiring layers 14a, 14b, 14c, 14d, and 14e in order from the top. The signal wiring 15 is formed on the second wiring layer 14b, and the signal wiring 16 is formed on the third wiring layer 14c. The semiconductor element 10 and the semiconductor module 17 are connected. The signal lines 15 and 16 form a pair of diagonal lines.

  FIG. 23 is a top view of the semiconductor device of this embodiment. The semiconductor element 10 is mounted at the center of the upper surface of the wiring board 14, and a plurality of semiconductor modules 17 (for example, 17 a and 17 b) are disposed around the semiconductor element 10. The signal wiring extends radially from the semiconductor element 10 and transmits high-speed signals to and from the semiconductor module 17. The wiring board 14 has a shape close to a square, and the distance between the semiconductor module 17b and the semiconductor element 10 mounted at a position near the corner of the square is relatively long, and is mounted at a position near the center of each side of the square. The distance between the semiconductor module 17a and the semiconductor element 10 is relatively short. The wiring cycle of the signal wiring connected to the semiconductor module 17a is narrower than the wiring cycle of the signal wiring connected to the semiconductor module 17b.

FIG. 24 is a cross-sectional view of the wiring board along the curve EE ′ of FIG. Each point on the curve EE ′ has the same wiring length from the semiconductor element 10. 24A is a cross-sectional view of the signal wirings 15a and 16a connected to the semiconductor module 17a, and FIG. 25B is a cross-sectional view of the signal wirings 15b and 16b connected to the semiconductor module 17b. The wiring width, shift amount, and wiring period of the signal wirings 15a and 16a are set to w _Ea , d _Ea , and p _Ea , respectively. The wiring width, shift amount, and wiring cycle of the signal wirings 15b and 16b are set to w _Eb , d _Eb , and p _Eb , respectively. And Here, the differential pair (a15a, 16a) and (A15B, 16b) of the wiring width, not the same differential line _period, p _{Ea <p Eb,} and w Ea _{<w Eb,} the differential characteristic impedance The shift amount is adjusted so as to obtain 100Ω, and d _Ea <d _Eb . As a result, the differential pair (a15a, 16a) has a shorter wiring length and a larger transmission loss per unit length than the differential pair (a15b, 16b).

  As described above, when the semiconductor element 10 and the plurality of semiconductor modules 17 are mounted on the wiring board 14 and the distance from each semiconductor module to the semiconductor element 10 is different, the signal wiring connected to the semiconductor module far from the semiconductor element 10 By increasing the period between the differential wiring and the wiring width to reduce the transmission loss per unit length, the increase in transmission loss due to the long wiring length can be offset, and the transmission loss of the entire signal wiring is equalized. can do. As a result, when the semiconductor element 10 is equipped with a waveform correction function such as pre-emphasis that preliminarily compensates for transmission loss of the signal wiring, even if the pre-emphasis setting for all the signal wirings is single, all signals Optimal waveform correction can be applied to the wiring.

  Examples of the semiconductor module 17 include a semiconductor element such as an LSI, a semiconductor package in which the semiconductor element is mounted on the substrate, and an optical module in which the photoelectric conversion element is mounted on the substrate.

FIG. 1 is a perspective view of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view of the semiconductor device of FIG. 3 is a cross-sectional view taken along line A-A ′ of the wiring board of FIG. 2. FIG. 4 is a graph showing the relationship between the shift amount of the diagonal line using the material of the wiring board of Example 1 and the differential characteristic impedance in the first embodiment. FIG. 5 is a graph showing the relationship between the shift amount and the transmission loss at the differential characteristic impedance of 100Ω of the diagonal line using the material of the wiring board of the first embodiment. FIG. 6 is a diagram showing a magnetic field distribution when p = 100 μm, w = 33 μm, and d = 0 μm of the diagonal line using the wiring board material of Example 1. FIG. 7 is a diagram showing the magnetic field distribution of the diagonal line using the wiring board material of Example 1 when p = 100 μm, w = 46 μm, and d = 82 μm. FIG. 8 is a diagram showing the magnetic field distribution when p = 100 μm, w = 55 μm, and d = 160 μm of the diagonal line using the wiring board material of Example 1. FIG. 9 is a graph showing the relationship between the standardized shift amount and the transmission loss at a differential characteristic impedance of 100Ω of the diagonal line using the wiring board material of Example 1. FIG. 10 is a graph showing the relationship between the normalized shift amount and the transmission loss at a differential characteristic impedance of 100Ω of the diagonal line using the wiring board material of the second embodiment. FIG. 11 is a graph showing the relationship between the standardized shift amount and the transmission loss at the differential characteristic impedance of 100Ω of the diagonal line using the wiring board material of Example 3. FIG. 12 is a top view of the semiconductor device according to the second embodiment. FIGS. 13A and 13B are cross-sectional views taken along lines B-B ′ and C-C ′ of the wiring board of FIG. 12 in the second embodiment. FIG. 14 is a graph showing the relationship between the wiring width of a diagonal line using the wiring board of Example 4 and transmission loss. FIG. 15 is a diagram showing the magnetic field distribution in the cross section of FIG. FIG. 16 is a diagram showing the magnetic field distribution in the cross section of FIG. FIGS. 17A and 17B are cross-sectional views of the wiring board at B-B ′ and C-C ′ in FIG. 12 of the third embodiment. FIG. 18 is a top view partially showing an example of the transmission line of the wiring board according to the third embodiment. FIG. 19 is a top view partially showing another example of the transmission line of the wiring board according to the third embodiment. FIG. 20 is a top view of the semiconductor device according to the fourth embodiment. 21A and 21B are cross-sectional views taken along the line D-D 'of the wiring board of FIG. FIG. 22 is a cross-sectional view of the semiconductor device according to the fifth embodiment. FIG. 23 is a top view of the semiconductor device according to the fifth embodiment. 24A and 24B are cross-sectional views taken along line E-E 'of the wiring board of FIG. It is sectional drawing of the conventional typical differential transmission line structure.

Explanation of symbols

1,11,14: wiring board 1a: first insulating layer 1b: second insulating layer 1c: Third insulating layer 1d: fourth insulating layer 2, 10: semiconductor element 3: connection conductors 4a _1, 4a ₂ , 4a ₃ , 9a ₁ , 9a ₂ , 9a ₃ : signal wiring of the second wiring layer 4b ₁ , 4b ₂ , 4b ₃ , 9b ₁ , 9b ₂ , 9b ₃ : signal wiring of the third wiring layer 5a, 14a : First wiring layer 5b, 14b: Second wiring layer 5c, 14c: Third wiring layer 5d, 14d: Fourth wiring layer 5e, 14e: Fifth wiring layer 6: BGA land 7, 8: Ground electrode 12: Wiring Short signal wiring 13: Signal wiring with long wiring 15: Signal wiring on second wiring layer 16: Signal wiring on third wiring layer 17: Semiconductor module

Claims (9)

In a multilayer wiring board in which a plurality of a pair of differential pairs formed by placing a signal wiring on two different wiring layers one by one and shifting the two signal wirings by a certain distance in the horizontal direction so as not to overlap each other,
The horizontal shift amount of the two signal wirings is d, the thickness of the insulating layer separating the two signal wirings is t, the wiring period between the adjacent signal wirings, that is, the distance between the adjacent differential wirings and the signal wiring. When the sum of the widths is p, there is a portion where the value D represented by D = d (t / p ³ ) ^1/2 is within the range of 0.2 <D <1.2. A transmission line.   2. The transmission line according to claim 1, wherein a ground plane or a power plane is formed on the upper, lower, or both upper and lower wiring layers of the two wiring layers.   The transmission line according to claim 1 or 2, wherein a wiring cycle with the adjacent signal wiring is different depending on a position.   The transmission line according to claim 1, wherein the signal wiring width is different depending on a position.   A wiring board having the transmission line according to claim 1.   A semiconductor device comprising a semiconductor substrate or a semiconductor package mounted on a wiring board having the transmission line according to claim 1 and connecting the transmission line and the semiconductor device or semiconductor package.   7. The semiconductor device according to claim 6, wherein the wiring board includes a differential pair having a long wiring length and a differential pair having a short wiring length, and the differential pair is mounted on the wiring board. The wiring period at a point of the long differential pair connected to the semiconductor element is wider than the wiring period of the short differential pair at the same distance from the semiconductor element. Semiconductor device.   The semiconductor device according to claim 6, wherein the semiconductor element is mounted in the center of the wiring board, and the distance between the differential pair is increased as the distance from the semiconductor element increases. A featured semiconductor device.   7. The semiconductor device according to claim 6, wherein the semiconductor element is mounted in the center of the wiring board, and the signal wiring width increases as the differential pair moves away from the semiconductor element. Semiconductor device.