JP2008105157A - Manufacturing method of mems-semiconductor composite circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a manufacturing cost by reducing the number of processes without sacrificing a performance by integrally forming a sacrifice layer for forming an MEMS structure and a structural layer provided so as to be in contact with this sacrifice layer with a manufacturing process of constitutional elements. <P>SOLUTION: Provided is a manufacturing method of an MEMS-semiconductor composite circuit having: a semiconductor substrate 10; an MEMS structure 20S; and a semiconductor element 30S provided on a surface layer part of the semiconductor substrate. The method includes: a first forming step of forming a sacrifice layer 23 and simultaneously forming an element insulating film 31; a second forming step of forming an MEMS structural layer 24 so as to be in contact with the sacrifice layer and simultaneously forming an element electrode layer 32; and a release step of removing the sacrifice layer so that the MEMS structural layer is operated. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a MEMS / semiconductor composite circuit, and more particularly to a manufacturing technique suitable for integrating a MEMS element and a semiconductor circuit.

  In general, various techniques for manufacturing various MEMSs (micro electro mechanical systems) by forming a MEMS structure on a substrate have been proposed (for example, see Patent Document 1 below). In manufacturing these MEMS structures, a normal semiconductor manufacturing technique is used. However, since the MEMS structure has a structure different from that of the semiconductor element, the MEMS structure and the semiconductor element are formed on the same semiconductor substrate. In this case, there is a problem that the number of processes is increased as compared with a normal semiconductor manufacturing process, and the manufacturing cost is increased.

In the process using the semiconductor manufacturing technique as described above, the element isolation layers 18, 19, 21, the insulating film 24 and the tunnel oxide film 27, the fixed electrode 28 and the floating gate 31 are formed in the respective regions of the sensor 10 and the MOS transistor. A method of forming each in the same process is known (for example, see Patent Document 2 below). In this method, the characteristics of the semiconductor element may be changed by annealing one layer of the sensor 10 in particular. Therefore, in order to prevent a change in the characteristics of the semiconductor element, It has been proposed to perform activation annealing of the polysilicon layer 38 constituting the diaphragm of the sensor 10 simultaneously.
JP 2004-181567 A JP-T-2004-526299

  However, in the above-described conventional manufacturing method (Patent Document 2), the source / drain implantation portion of the semiconductor element and the annealing treatment of the diaphragm are simultaneously performed to avoid the change in the characteristics of the MOS transistor. Since the steps of forming the sacrificial layer 36 and the diaphragm 38 formed on the sacrificial layer 36 which are important manufacturing elements are provided separately from the manufacturing process of the constituent elements of the semiconductor element and are performed after the manufacturing process, the characteristics of the MOS transistor There is a problem that the influence on the process cannot be completely prevented, the number of processes is not sufficiently reduced, and the production cost is difficult to reduce.

  Therefore, the present invention solves the above-described problems, and the problem is that a sacrificial layer for forming a MEMS structure and a structural layer provided so as to be in contact with the sacrificial layer are integrated with a manufacturing process of components of a semiconductor element. By reducing the manufacturing cost, the manufacturing cost is reduced by reducing the number of processes without sacrificing performance.

  In view of such circumstances, a method for manufacturing a MEMS / semiconductor composite circuit according to the present invention is a method for manufacturing a MEMS / semiconductor composite circuit having a semiconductor substrate, a MEMS structure and a semiconductor element provided on a surface layer portion of the semiconductor substrate. In the method, a sacrificial layer used to form the MEMS structure is formed, and at the same time, a first forming step in which an element insulating film constituting the semiconductor element is formed, and the MEMS is in contact with the sacrificial layer. A second forming step in which an element electrode layer forming the semiconductor element is formed on the element insulating film simultaneously with the formation of the MEMS structure layer forming the structure; the first forming step; and the second forming step. A release step in which the MEMS structure layer is configured to be operable by removing the sacrificial layer after the step.

  According to the present invention, the sacrificial layer used for forming the MEMS structure and the element insulating film constituting the semiconductor element are simultaneously formed in the first formation step, and the MEMS structure layer and the semiconductor constituting the MEMS structure are formed. Since the element electrode layer constituting the element is formed at the same time in the second formation step, the number of processes can be further reduced as compared with the conventional method, and thus the manufacturing cost can be reduced. In particular, the sacrificial layer and the MEMS structure layer configured to be operable by removing the sacrificial layer are the most important elements in manufacturing the MEMS structure, and are formed at the same time. Since the element insulating film and the element electrode layer are constituent elements of the semiconductor element, forming them in the same step can greatly simplify the manufacturing process. In addition, since the element insulating film and the element electrode layer constituting the semiconductor element are formed with high accuracy, the sacrificial layer and the MEMS structure layer formed at the same time can be formed with high accuracy. As a result, the MEMS structure Can be formed with high accuracy, and there is little possibility of degrading the performance of the MEMS / semiconductor composite circuit. Further, the sacrificial layer for forming the MEMS structure and the subsequent MEMS structure layer are formed at the same time as the element insulating film and the element electrode layer of the semiconductor element, thereby improving the characteristics of the semiconductor element by the manufacturing process of the MEMS structure. Can be further reduced than in the prior art.

  In the present invention, the method further comprises a lower layer forming step of forming a lower MEMS structure layer constituting the MEMS structure in a lower layer of the sacrificial layer before the first forming step, and in the first forming step, the lower portion Preferably, the surface of the MEMS structure layer is thermally oxidized to form the sacrificial layer, and the surface of the semiconductor substrate is thermally oxidized to form the element insulating film. The lower MEMS structure layer is also an element constituting a part of the MEMS structure. A sacrificial layer is formed by thermal oxidation of the lower MEMS layer, and at the same time, an element insulating film is formed by thermal oxidation of the surface of the semiconductor substrate. As a result, a high-quality element insulating film can be formed and the thickness of the sacrificial layer can be adjusted by the structure, composition, and the like of the lower MEMS layer.

  In this case, the semiconductor substrate is preferably made of a single crystal semiconductor, and the lower MEMS structure layer is preferably made of a polycrystalline semiconductor made of the same basic material as the semiconductor material constituting the semiconductor substrate. According to this, since the thermal oxide film formed on the polycrystalline semiconductor can be formed thicker than the thermal oxide film formed on the single crystal semiconductor constituting the semiconductor substrate, the sacrificial layer is made thicker than the element insulating film. It becomes possible to form. Here, the same basic material means that elements such as Si and Ge are the same in the case of a single element semiconductor, and the combination of basic constituent elements such as GaAs and InP is the same in the case of a compound semiconductor (the composition ratio is not limited). .) Say that.

  The lower MEMS structure layer preferably has an impurity concentration different from that of the element insulating film formation region of the semiconductor substrate. The relationship between the thickness of the sacrificial layer formed by thermal oxidation and the thickness of the element insulating film is adjusted by setting the lower MEMS structure layer provided in the MEMS structure to an impurity concentration different from that of the element insulating film formation region of the semiconductor substrate. It becomes possible. In particular, by setting the lower MEMS structure layer provided in the MEMS structure to an impurity concentration higher than the formation region of the element insulating film of the semiconductor substrate, it is possible to impart good conductivity to the lower MEMS structure and Since the difference in thermal oxidation rate can be increased, the thickness of the sacrificial layer and the element insulating film can be adjusted in a wider range.

  In the present invention, the first formation step includes a step of forming two or more element insulating films, and the sacrificial layer includes the element insulating film formed in at least one of the two or more stages. Preferably, they are formed simultaneously. In the case where a plurality of semiconductor elements are formed, the plurality of semiconductor elements may have element insulating films made of different thicknesses or different materials. In such a case, one of these two or more element insulating film formation stages By forming the sacrificial layer simultaneously with at least one element insulating film, options regarding the thickness and material of the sacrificial layer are increased.

  In this case, it is preferable that the sacrificial layer is formed by laminating insulating films formed in a plurality of stages among the two or more stages. According to this, a sacrificial layer can be formed thickly by forming a sacrificial layer by laminating | stacking the insulating film formed in the step of forming a some element insulating film.

  In the present invention, the second forming step includes forming the MEMS structure layer and the device electrode layer from polycrystalline silicon, and diffusing metal into the MEMS structure layer and the device electrode layer to form a metal silicide. Are preferably provided. According to this, since the MEMS structure layer and the element electrode layer are made of metal silicide, the electrical resistance of the MEMS structure layer can be reduced and the electrical characteristics can be easily improved while improving the performance of the semiconductor element. Examples of the metal include Ti, W, Co, Mo, and Ni.

  In the present invention, it is preferable that the method further includes a step of forming an impurity region of the semiconductor element after the second forming step. According to this, by forming the impurity region of the semiconductor element after the second formation process, it is possible to prevent the MEMS structure formation process from affecting the characteristics of the semiconductor element.

  Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 to FIG. 8 are schematic process diagrams showing the manufacturing process of the MEMS / semiconductor composite circuit according to this embodiment in a simplified manner.

  A semiconductor substrate 10 shown in FIG. 1 is a wafer having a thickness of about several hundred μm, for example, and is composed of a silicon single crystal or the like in this embodiment. However, in the present invention, a substrate made of a compound semiconductor such as GaAs may be used as the semiconductor substrate. A field insulating film (made of an element isolation film, silicon oxide, etc.) 11 is formed on the surface layer portion of the semiconductor substrate 10 by a known oxidation process (a photolithography technique and a thermal oxidation technique) to form an element isolation structure. . Here, the element isolation structure may be formed by a trench structure.

  The field insulating film 11 is formed over the entire region (hereinafter simply referred to as “MEMS region”) 20 in which a MEMS structure to be described later is formed, and the MEMS region 20 is insulated and separated from the semiconductor substrate 10 and other regions. Also, a region (hereinafter simply referred to as “semiconductor region”) 30 in which a semiconductor element to be described later is formed is provided to be separated from the surroundings. In the illustrated example, the field insulating film 11 is configured to be entirely interposed between the MEMS structure, which will be described later, and the semiconductor substrate 10, so that the parasitic between the MEMS structure and the semiconductor substrate 10 is present. Capacity etc. can be reduced.

  Next, in the MEMS region 20, the base layer 21 is formed of silicon nitride or the like by a CVD method, a sputtering method, or the like. The underlayer 21 becomes an etching stop layer in a release process described later.

Thereafter, as the lower layer MEMS forming step, the lower MEMS structure layer 22 is formed on the base layer 21 in the MEMS region 20. The lower MEMS structure layer 22 is formed by a film forming process such as a CVD method or a sputtering method and a patterning process. The lower MEMS structure layer 22 is made of, for example, polycrystalline silicon. The lower MEMS structure layer 22 functions as, for example, a lower electrode in the MEMS structure. When the lower MEMS structure layer 22 is made of the above-described polycrystalline silicon, the lower MEMS structure layer 22 is doped with a predetermined impurity such as n-type P or p-type B. Conductivity is imparted. Doping is performed by depositing a dopant in a gas such as POCl ₃ or BBr ₃ and thermally diffusing the dopant. However, doping may be performed simultaneously with film formation. The thickness of the lower MEMS layer 22 is not particularly limited, but is generally in the range of 0.3 to 1.5 μm, and particularly preferably in the range of 0.5 to 1.2 μm.

  Next, as the first forming step, thermal oxidation treatment is performed at a temperature of 800 to 1100 ° C. Wet oxidation or dry oxidation may be used, but in order to improve the film quality of the gate insulating film, it is preferable to select dry oxidation and oxidize at a low temperature of 800 to 900 ° C. In this step, as shown in FIG. 2, a sacrificial layer 23 is formed on the lower MEMS structure layer 22 in the MEMS region 20, and a gate insulating film 31 that is an element insulating film on the semiconductor substrate 10 in the semiconductor region 30. Is formed. The sacrificial layer 23 has a thickness of, for example, 30 to 300 nm, and the gate insulating film 31 generally has a thickness of 10 to 100 nm.

  Here, when the lower MEMS structure layer 22 is polycrystalline silicon and the semiconductor substrate 10 is single crystal silicon, the lower MEMS structure layer 22 has a higher thermal oxidation rate than the semiconductor substrate 10. The sacrificial layer 23 can be formed thicker than the gate insulating film 31.

When the lower MEMS structure layer 22 uses an n-type dopant such as P as an impurity, the thermal oxidation rate increases according to the doping concentration, so that the sacrificial layer 23 is formed thicker than the gate insulating film 31. be able to. For example, for the polycrystalline silicon doped at a concentration of at least 10 ¹⁹ units of P, which may be twice or more the thickness of the intrinsic silicon. However, when a p-type dopant such as B is used as an impurity, there is almost no increase in the thermal oxidation rate, and there is a case where it decreases instead.

  As described above, by adjusting the relationship between the crystallinity and impurity concentration of the lower MEMS structure layer 22 and the semiconductor substrate 10, the thickness of the sacrificial layer 23 and the gate insulating film 31 formed in the same step is set to a desired relationship. It becomes possible to do. In the first formation step, the sacrificial layer 23 and the gate insulating film 31 may be formed by a method other than thermal oxidation, such as a CVD method or a sputtering method.

Thereafter, as the second forming step, as shown in FIG. 3, an upper MEMS structure layer 24 is formed on the sacrificial layer 23 in the MEMS region 20, and an element electrode is formed on the gate insulating film 31 in the semiconductor region 30. A gate electrode layer 32 which is a layer is formed. Here, the upper MEMS structure layer 24 and the gate electrode layer 32 are formed of, for example, polycrystalline silicon by a CVD method or a sputtering method. In this case, conductivity is imparted by doping a predetermined impurity, for example, n-type P, p-type B, or the like. Doping is performed by depositing a dopant in a gas such as POCl ₃ or BBr ₃ and thermally diffusing the dopant. However, doping may be performed simultaneously with film formation. The thickness of the lower MEMS layer 21 is not particularly limited, but is generally in the range of 0.3 to 1.5 μm, and particularly preferably in the range of 0.5 to 1.2 μm.

  The upper MEMS structure layer 24 may be formed on the sacrificial layer 23 as described above, but may be formed so as to be in contact with the side surface of the sacrificial layer 23, for example. That is, the upper MEMS structure layer 24 may be formed so as to be in contact with the sacrificial layer 23. In any case, in the present embodiment, the lower MEMS structure layer 22 and the upper MEMS structure layer 24 are at least partially opposed to each other with the sacrificial layer 23 interposed therebetween. This completes the basic structure of the MEMS structure 20S.

  This second formation step can also be performed by a silicide gate process. That is, as a first stage, after the upper MEMS structure layer 24 and the gate electrode layer 32 are formed of polycrystalline silicon, as a second stage, metal is diffused into these surfaces to form a metal silicide. Examples of the metal include Ti, W, Co, Mo, Ni, and the like. The metal diffusion method in the second stage is not particularly limited. For example, the metal film can be silicided by forming a metal film by vapor deposition, sputtering, or the like and thermally diffusing it. The part to be silicided is generally the upper layer part of the upper MEMS structure layer 24 and the gate electrode layer 32, but it is also possible to make almost the entire part silicide. In any case, since the resistance of the upper MEMS structure layer 24 and the gate electrode layer 32 can be reduced as described above, not only the performance of the semiconductor element but also the electrical characteristics of the MEMS structure are improved. Can be made.

  In the illustrated semiconductor region 30, only a single semiconductor element 30S (transistor structure) is shown, but a semiconductor circuit having a plurality of semiconductor elements 30S, such as a CMOS circuit, may be formed.

  In the present embodiment, the source region 33 and the drain region 34, which are impurity regions of the semiconductor element 30S, are provided in the second region so that the characteristics of the semiconductor element 30S are not affected by the process of forming the MEMS structure 20S. It is formed after the formation process, that is, after the basic structure of the MEMS structure 20S is formed. This is because, for example, in the formation process of the MEMS structure 20S, when forming the lower MEMS structure layer 22 and the upper MEMS structure layer 24, doping treatment, annealing treatment, film formation treatment at a high temperature, etc. are required. This is because the characteristics of the semiconductor element 30S may be affected by a heating process such as processing, annealing, or film formation.

  Thereafter, as shown in FIG. 4, an interlayer insulating film 12 is formed on the MEMS structure 20S and the semiconductor element 30S. This interlayer insulating film 12 can be formed by sputtering or CVD. Here, after the interlayer insulating film 12 is formed, a surface flattening process may be performed, and the surface of the interlayer insulating film 12 may be flattened by, for example, a chemical mechanical polishing process. In this way, it is possible to prevent the structure above the interlayer insulating film 12 from being affected by the step due to the MEMS structure 20S. The thickness of the interlayer insulating film 12 is set to a value that can sufficiently cover the upward protrusion of the MEMS structure 20S with respect to the substrate surface. For example, if the upward protrusion is, for example, 1.0 to 2.0 μm, the thickness of the interlayer insulating film 12 is preferably at least about 0.5 μm thick, for example, about 1.5 to 2.5 μm.

  Next, after forming an opening 12a in the interlayer insulating film 12, a wiring layer 13 is formed of aluminum or the like. The wiring layer 13 is conductively connected to the MEMS structure 20S and the semiconductor element 30S formed in the lower layer through the opening 12a. In the illustrated example, the MEMS structure 20S and the semiconductor element 30S are not conductively connected, but both may be conductively connected via the wiring layer 13. In any case, the present invention is not limited to such a connection mode.

  Thereafter, as shown in FIG. 5, an interlayer insulating film 14 is further formed on the wiring layer 13, an opening 14a is formed in the interlayer insulating film 14, and a wiring layer 15 is formed thereon. The wiring layer 15 is conductively connected to the lower wiring layer 13 through the opening 14a. The laminated structure of the insulating film and wiring such as the interlayer insulating film 12, wiring layer 13, interlayer insulating film 14, and wiring layer 15 may be a two-layer structure with one insulating film and one wiring, Any number of layers of 2 or more may be alternately stacked.

  Next, as shown in FIG. 6, a surface protective film 16 is formed on the interlayer insulating film 14 and the wiring layer 15. The surface protective film 16 is made of, for example, silicon nitride. Then, the surface protection film 16 is partially opened to form an opening 16a, and a part of the wiring layer 15 is exposed through the opening 16a to form a connection pad. Further, not only the surface protective film 16 but also the underlying interlayer insulating films 12 and 14 are removed to form the opening recess P. In the step of forming the opening recess P, an unnecessary upper layer structure is removed in advance in order to enable a later-described release step for removing the insulating layer around the MEMS structure 20S and making it operable. This is an opening process for keeping the opening.

  Thereafter, as a release step, the inside of the opening recess P is etched using an etching solution made of buffered hydrofluoric acid (BHF) or the like, and the interlayer insulating film 12 and the sacrificial layer 23 around the upper MEMS structure layer 24 are removed. The opening space S is formed so that the MEMS structure 20S (the upper MEMS structure layer 24 in the illustrated example) can be operated (deformed), and the lower MEMS structure layer 22 and the upper MEMS structure layer 24 are separated from each other by a space. Make them face each other. This release process is not limited to the illustrated example because unnecessary portions may be removed according to the structure and function of the MEMS structure 20S. For example, if a pair of comb-shaped electrodes is supported on a substrate so as to be movable by a support beam, a sacrificial layer made of silicon oxide or the like between the pair of electrodes and between these electrodes and the base surface The sacrificial layer may be removed by a release process. As a result, the MEMS structure 20 </ b> S is placed in the opening space S formed above the semiconductor substrate 10.

  Finally, the opening space S in which the MEMS structure 20S is disposed is closed with a sealing material (not shown) as necessary. The sealing material can be composed of an organic resin or an inorganic glass material. Here, after the opening space S is depressurized, it may be closed in a reduced pressure state (vacuum state) by a sealing material, or may be closed in a normal pressure state.

  According to the present embodiment described above, the sacrificial layer 23 used in configuring the MEMS structure 20S and the gate insulating film 31 that is a component of the semiconductor element 30S are formed at the same time, and the components of the MEMS structure 20S are used. By simultaneously forming a certain upper MEMS structural layer 24 and the gate electrode layer 32 that is a component of the semiconductor element 20S, the number of processes can be greatly reduced, and the manufacturing cost can be reduced. Can be easily integrated. Furthermore, since the sacrificial layer 23 and the upper MEMS structure layer 24 are formed at the same time as the gate insulating film 31 and the gate electrode layer 32, respectively, the influence on the characteristics of the semiconductor element by the MEMS process can be completely prevented as compared with the prior art.

  Next, a modification of the above embodiment will be described with reference to FIGS. In this example, since a plurality of semiconductor elements are formed in the semiconductor regions 30A and 30B, and at least two of the plurality of semiconductor elements are configured as elements having different characteristics, a gate that is an element insulating film The insulating film is formed to have different thickness, film quality, composition, and the like. In the following description of this example, the description of the same parts as those in the above embodiment will be omitted, and the same parts will be denoted by the same reference numerals and different from those in the above embodiments, that is, the first formation described above. Only the process corresponding to the process will be described in detail.

  In this example, as shown in FIG. 7, the field insulating film 11 is formed on the semiconductor substrate 10, and the base layer 21 and the lower MEMS structure layer 22 are formed in the MEMS region 20, as in the above embodiment. Then, a first insulating film 17 is formed on these by a thermal oxidation method, a CVD method or the like. In the illustrated example, an example formed by a thermal oxidation method is shown. Thereafter, a mask 17M made of resist or the like is selectively formed, and unnecessary portions are removed by etching or the like, so that the first sacrificial layer 23A is formed on the lower MEMS structure layer 22 in the MEMS region 20 as shown in FIG. The first element insulating film 31A is formed in the semiconductor region 30A, and the first insulating film 17 is completely removed in the semiconductor region 30B to expose the surface of the semiconductor substrate 10 (first insulating film forming step).

  Next, the second insulating film 18 is formed on the above structure by a thermal oxidation method, a CVD method or the like. In the illustrated example, an example formed by a CVD method or a sputtering method is shown. When the second insulating film 18 is formed by the thermal oxidation method, the second insulating film 18 is formed above and below the first sacrificial layer 23A and the first element insulating film 31A that have already been formed. Thereafter, a mask 18M made of a resist or the like is selectively formed, and unnecessary portions are removed by etching or the like, whereby the second sacrificial layer 23B is formed on the first sacrificial layer 23A in the MEMS region 20 as shown in FIG. Is laminated. On the other hand, in the semiconductor region 30A, the second element insulating film 31B is laminated on the first element insulating film 31A, and only the second element insulating film 31B is formed in the semiconductor region 30B (second insulating film forming stage). .

  In this example, whether each of the MEMS region 20, the semiconductor region 30A, and the semiconductor region 30B is provided with an insulating film formed in each of the first insulating film forming step and the second insulating film forming step is independently determined. Can be set. That is, in the illustrated example, in the MEMS region 20, the first sacrificial layer 23A and the second sacrificial layer 23B are laminated to form an integral sacrificial layer, but only one of them may be formed. Further, only the second element insulating film 31B is formed in the semiconductor region 30A, but only the first element insulating film 31A may be formed, or the first element insulating film 31A and the second element insulating film 31B may be formed. It may be laminated. Furthermore, in the semiconductor region 30B, the first element insulating film 31A and the second element insulating film 31B are stacked to form an integral element insulating film, but only the first element insulating film 31A may be formed, Only the second element insulating film 31B may be formed.

  However, since the thickness of the sacrificial layer formed in the MEMS region 20 and the thickness of the element insulating film formed in the semiconductor region 30 are generally set from different viewpoints, they are formed to have different structures. It is preferable. Usually, the thickness of the gate insulating film of the semiconductor element is about 10 to 100 nm, whereas the thickness of the sacrificial layer of the MEMS structure is about 30 to 300 nm, and the thickness of the sacrificial layer is larger than the thickness of the element insulating film. In many cases, the sacrificial layer is desirably formed by a stacked body of insulating layers formed in a plurality of insulating film forming steps in the MEMS region 20.

  The MEMS / semiconductor composite circuit and the manufacturing method thereof according to the present invention are not limited to the above-described illustrated examples, and various modifications can be made without departing from the scope of the present invention. For example, in the above embodiment, the MOS transistor is exemplified as the semiconductor element. However, the semiconductor element of the present invention is not limited to this, and any MIS may be used as long as the element includes an element insulating film and an element electrode layer. Various elements such as (MOS) diodes, capacitors, and light emitting transistors can be formed.

The schematic sectional drawing which shows the manufacturing process of the MEMS and semiconductor composite circuit of embodiment. The schematic sectional drawing which shows the manufacturing process of the MEMS and semiconductor composite circuit of embodiment. The schematic sectional drawing which shows the manufacturing process of the MEMS and semiconductor composite circuit of embodiment. The schematic sectional drawing which shows the manufacturing process of the MEMS and semiconductor composite circuit of embodiment. The schematic sectional drawing which shows the manufacturing process of the MEMS and semiconductor composite circuit of embodiment. The schematic sectional drawing which shows the manufacturing process of the MEMS and semiconductor composite circuit of embodiment. The schematic sectional drawing which shows the manufacturing process of the MEMS and semiconductor composite circuit of embodiment. The schematic sectional drawing which shows the manufacturing process of the MEMS and semiconductor composite circuit of embodiment. The schematic sectional drawing which shows the manufacturing process of the MEMS and semiconductor composite circuit of embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate, 11 ... Field insulating film, 12, 14 ... Interlayer insulating film, 13, 15 ... Wiring layer, 16 ... Surface protective film, 20 ... MEMS area | region, 20S ... MEMS structure, 21 ... Underlayer, 22 ... Lower MEMS structural layer, 23 ... Sacrificial layer, 24 ... Upper MEMS structural layer, 30 ... Semiconductor region, 30S ... Semiconductor element, 31 ... Gate insulating film, 32 ... Gate electrode layer, 33 ... Source region, 34 ... Drain region

Claims (8)

In a manufacturing method of a MEMS / semiconductor composite circuit comprising a semiconductor substrate, a MEMS structure and a semiconductor element provided on a surface layer portion of the semiconductor substrate,
A first forming step in which a sacrificial layer used to form the MEMS structure is formed, and at the same time, an element insulating film constituting the semiconductor element is formed;
A second forming step in which a MEMS structure layer constituting the MEMS structure is formed so as to be in contact with the sacrificial layer, and simultaneously, an element electrode layer constituting the semiconductor element is formed on the element insulating film;
A release step in which the MEMS structure layer is configured to be operable by removing the sacrificial layer after the first formation step and the second formation step;
A method for manufacturing a MEMS / semiconductor composite circuit, comprising: Before the first forming step, further comprising a lower layer forming step of forming a lower MEMS structure layer constituting the MEMS structure in a lower layer of the sacrificial layer;
In the first formation step, the surface of the lower MEMS structure layer is thermally oxidized to form the sacrificial layer, and the surface of the semiconductor substrate is thermally oxidized to form the element insulating film. The method for producing a MEMS / semiconductor composite circuit according to claim 1.   3. The MEMS according to claim 2, wherein the semiconductor substrate is made of a single crystal semiconductor, and the lower MEMS structure layer is made of a polycrystalline semiconductor made of the same basic material as a semiconductor material constituting the semiconductor substrate. A method for manufacturing a semiconductor composite circuit.   4. The method for manufacturing a MEMS / semiconductor composite circuit according to claim 2, wherein the lower MEMS structure layer has an impurity concentration different from that of the element insulating film formation region of the semiconductor substrate. 5.   The first forming step includes a step of forming two or more element insulating films, and the sacrificial layer is formed simultaneously with the element insulating film formed in at least one of the two or more stages. The method for manufacturing a MEMS / semiconductor composite circuit according to any one of claims 1 to 4.   6. The method of manufacturing a MEMS / semiconductor composite circuit according to claim 5, wherein the sacrificial layer is formed by laminating insulating films respectively formed in a plurality of stages among the two or more stages.   The second forming step includes a step of forming the MEMS structure layer and the device electrode layer from polycrystalline silicon, and a step of diffusing metal into the MEMS structure layer and the device electrode layer to form a metal silicide. The method for manufacturing a MEMS / semiconductor composite circuit according to claim 1, wherein the method is provided.   8. The method of manufacturing a MEMS / semiconductor composite circuit according to claim 1, further comprising a step of forming an impurity region of the semiconductor element after the second forming step.

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