JP2008103483A - Semiconductor light-emitting element and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor light-emitting element solving a problem caused by the relationship of a trade-off between a radiation angle and a modulating speed and realizing the coexistence of a low radiation angle and a high modulating speed. <P>SOLUTION: The semiconductor light-emitting element has a resonator held by two reflecting mirrors. The semiconductor light-emitting element has a pattern layer configuring a part of the resonator and having a specified layer-thickness distribution. The semiconductor light-emitting element further has a first buried layer formed on the film-forming direction side of the pattern layer more than the pattern layer and a second buried layer being formed while being brought into contact with the first buried layer, having the compositions of constituent elements different from those of the first buried layer and having the layer-thickness distribution reverse to the pattern layer. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor light emitting device including a semiconductor laser used in the fields of optical communication and optical interconnection, and a method for manufacturing the same.

  Since optical communication is capable of long-distance and large-capacity transmission, long-distance communication has been widely used practically from early on. Generally, a semiconductor laser is used as a light source in a transmitter for optical communication. Among them, a surface emitting laser (VCSEL) has advantages such as small size and low power consumption. It is used as a light source.

As a current confinement mechanism of a surface emitting laser, there are an air post structure by etching, a proton injection type, an oxidation constriction type, and the like. The oxidized constriction type has the advantages that it is not affected by side surface recombination, and that diffraction loss is greatly reduced due to light collection caused by the difference in refractive index between the oxide layer and the semiconductor layer. It has become. Although the oxidation length is controlled by time, the uniformity within the wafer surface and the reproducibility are not so high, and this causes variations in aperture width and, consequently, variations in characteristics. In order to avoid this, a method has been proposed in which a pattern is formed on a wafer and an oxide layer is grown thereon to improve the controllability of the aperture diameter by utilizing the difference in oxidation rate between the flat surface and the inclined surface. Yes. In addition, a structure using a buried tunnel junction or a current blocking layer, which is a current confinement structure other than the oxide constriction type, is also being studied.
GRHadley, Optics Letters, vol.20, No.13, p.1483-5, 1995

  In the structure in which an oxide layer is grown on the pattern, the buried tunnel junction structure, the current block structure, and the like as described above, a pattern of recesses and protrusions is formed on the wafer, unlike the normal oxide constriction type. If the mirror is formed with the recesses and projections remaining, the resonance wavelength will be different between the recesses and other regions, or between the projections and other regions. As a result, as described in Non-Patent Document 1, a difference in equivalent refractive index is generated, and optical confinement occurs. Therefore, in general, the larger the step between the concave and convex portions, the greater the equivalent refractive index difference.

  When the equivalent refractive index at the center is smaller, a so-called reverse waveguide structure is formed, causing problems such as an increase in threshold current and no oscillation. Conversely, when the equivalent refractive index at the center is larger, the light confinement becomes stronger. In this case, a higher-order mode is likely to occur and cannot be used for applications that require a single mode. Although it can be used when used in a multimode, generally, the higher the mode, the larger the radiation angle, and the lower the coupling efficiency with the optical fiber or optical waveguide. In the case of high-density integration, it is desirable not to use a lens in order to reduce the cost. In this case, however, a reduction in coupling efficiency due to an increase in radiation angle becomes significant. In order to avoid such a problem, it is desirable to planarize the surface of the buried layer located on the layer having the concave portion or the convex portion.

  FIG. 9 is a diagram for explaining a conventional buried structure. FIG. 9A shows the case where the surface is flattened by increasing the thickness of the buried layer, and FIG. 9B shows that the stepped portion due to the convex shape is moved away from the light reachable region by increasing the thickness of the buried layer. Is the case. The dotted line shows how the stepped portion moves away from the center as the buried layer becomes thicker.

  In general, as shown in FIG. 9A, even if there is a convex shaped layer 501a, if the buried layer 502a is made sufficiently thick, the surface can be flattened. This is because the step shape is absorbed by thickly forming a highly embedded film. Further, as shown in FIG. 9B, even if there is a convex layer 501b, the buried layer 502b can be made sufficiently thick so that the stepped portion can be moved to a region where light does not reach. If the mirrors (upper mirrors 503a and 503b) are formed on this, the equivalent refractive index difference due to the difference in the layer height is eliminated, so that the generation of higher-order modes as described above and the accompanying increase in the radiation angle. It is suppressed.

  However, the thicker the buried layer, the longer the laser cavity length. This is disadvantageous in terms of direct modulation speed. That is, in the element structure in which the structure having the concave portion and the convex portion as described above is embedded, there is a trade-off relationship between the radiation angle and the modulation speed.

  The present invention has been made to solve the problems of the conventional techniques as described above, and solves the problem due to the trade-off relationship between the radiation angle and the modulation speed, and achieves both low radiation angle and high speed modulation. An object of the present invention is to provide a semiconductor light emitting device and a manufacturing method thereof.

In order to achieve the above object, the semiconductor light emitting device of the present invention comprises:
A semiconductor light emitting device having a resonator sandwiched between two reflecting mirrors,
A pattern layer having a predetermined layer thickness distribution, constituting a part of the current confinement structure of the resonator;
A first embedded layer provided on the patterning layer side of the pattern layer with respect to the pattern layer;
A second buried layer provided in contact with the first buried layer, having a composition different from that of the first buried layer and having a layer thickness distribution opposite to that of the pattern layer;
It is the structure which has.

  In the present invention, since the second embedded layer is formed with a layer thickness distribution opposite to that of the pattern layer through the first embedded layer in the pattern layer forming direction, the concave or convex portions of the pattern layer are formed. Is absorbed in the second buried layer. In addition, since the composition of the constituent elements of the first and second buried layers is different, a selective etchant having an etching rate different from that of the first buried layer is used when etching the second buried layer. The amount of scraping of the first buried layer serving as the base film can be suppressed. Thereby, it becomes possible to planarize with good reproducibility and uniformity. In addition, since the change in the optical length of the resonator due to the variation in the etching amount can be suppressed, it is possible to suppress the variation in wavelength and, in turn, the variation in laser characteristics.

On the other hand, the manufacturing method of the semiconductor light emitting device of the present invention for achieving the above object is as follows.
Forming a first reflecting mirror on the substrate;
Forming a first clad layer, an active layer and a second clad layer in order on the first reflecting mirror;
Forming a pattern layer having a predetermined layer thickness distribution constituting a part of the current confinement structure above the second cladding layer;
Forming a first buried layer on the pattern layer;
Forming a second buried layer having a constituent element composition different from that of the first buried layer on the first buried layer;
Forming a layer thickness distribution opposite to the pattern layer in the second buried layer by selective etching;
A second reflecting mirror is formed above the second buried layer.

  In the present invention, since two or more types of buried layers having different constituent element compositions are used, a technique such as selective etching using any one of the buried layers as an etching target film can be used. As a result, an embedding layer having a convex shape opposite to the concave portion in the resonator is formed, or an embedding layer having a concave shape opposite to the convex portion in the resonator is formed to flatten the surface. Easy to do.

  According to the present invention, since the surface of the resonator can be flattened even if the buried layer is thinner than the conventional one, the optical confinement factor can be adjusted to an appropriate value without increasing the resonator length. Can do. Therefore, the problem due to the trade-off relationship between the radiation angle and the modulation speed, which was a problem of the prior art, can be solved, and a device capable of low-radiation angle and high-speed modulation can be realized. Contributes greatly to improvement.

  The semiconductor light-emitting device of the present invention has two or more types of buried layers having different constituent element compositions, and one of the buried layers has a pattern shape opposite to the pattern constituting a part of the current confinement structure. It is characterized by that.

  “Two or more kinds of buried layers having different constituent element compositions” means that the main elements constituting the buried layer are different in composition, and those containing only trace elements such as dopants are not included. For example, when a p-type GaAs layer and an n-type GaAs layer are used for embedding, the number of buried layers is one, not two. Similarly, when p-type GaAs using C as a dopant and p-type GaAs using Zn as a dopant are used, the buried layer is one kind.

Specifically, “the composition of the main elements is different” means that the constituent elements belonging to the same group differ by 1% or more. For example, compared to the GaAs layer, the composition of As and N, which are group V elements, is 2% different in the GaAs _0.98 N _0.02 layer, so these layers can be regarded as different layers.

  Examples of the semiconductor light emitting device of the present invention will be described below.

  The configuration of the semiconductor light emitting device of this example will be described. Here, it is assumed that the present invention is applied to a surface emitting laser having an oscillation wavelength of 1.3 μm formed on a GaAs substrate. The current confinement structure of the semiconductor light emitting device of this example is a buried tunnel junction.

  FIG. 1 is a schematic cross-sectional view showing a configuration example of a surface emitting laser according to this embodiment.

As shown in FIG. 1, the surface emitting laser according to the present embodiment has a first DBR layer 102, an n-type Al _0.3 Ga _0.7 As cladding layer 103, an active layer 104, a p-type Al on an n-type GaAs substrate 101. _0.3 Ga _0.7 As cladding layer 105, p-GaAs layer 106, p ⁺ -GaAs _0.9 Sb _0.1 layer 107, n ⁺ -In _0.15 GaAs _0.85 layer 108, n-GaAs layer 109, n-InGaP layer 110, n-GaAs layer 111 and the second DBR layer 113 are sequentially stacked.

p ⁺ -GaAs _0.9 Sb _0.1 layer 107 and n ⁺ - In _0.15 GaAs _0.85 layer 108 has a configuration same pattern are laminated, each have the same layer thickness distribution. The layer thickness distribution means the existence distribution of pattern shapes having different thicknesses. These layers have a distribution of sites with and without a pattern. p ⁺ -GaAs _0.9 Sb _0.1 layer 107 and n ⁺ - In _0.15 GaAs _0.85 layer 108 constituting a tunnel junction at the site with a pattern. Each of the two layers constituting this tunnel junction corresponds to the pattern layer of the present invention.

The tunnel junction portion is embedded in the n-GaAs layer 109, and the n-InGaP layer 110 and the n-GaAs layer 111 on the n-GaAs layer 109 have a layer thickness distribution opposite to that of the tunnel junction portion. That is, there is a pattern on the n-InGaP layer 110 and the n-GaAs layer 111 at positions corresponding to the pattern portions of the p ⁺ -GaAs _0.9 Sb _0.1 layer 107 and the n ⁺ -In _0.15 GaAs _0.85 layer 108 constituting the tunnel junction. There is no. Conversely, the n-InGaP layer 110 and the n-GaAs layer 111 at positions corresponding to the unpatterned portions of the p ⁺ -GaAs _0.9 Sb _0.1 layer 107 and the n ⁺ -In _0.15 GaAs _0.85 layer 108 have a pattern. Therefore, the convex shape of the tunnel junction is absorbed by the concave shapes of the n-InGaP layer 110 and the n-GaAs layer 111. With this structure, the height of the upper surface of the n-GaAs layer 111 and the exposed surface of the n-GaAs layer 109 coincide with each other, and the surfaces thereof are flat.

  Next, a method for manufacturing the surface emitting laser according to this embodiment will be described.

  2A to 2E are schematic cross-sectional views for explaining a method of manufacturing the surface emitting laser shown in FIG. In the following description, not only the substrate itself but also those in the process of manufacturing elements on the substrate are referred to as “wafer”. The same applies to the other embodiments.

First, as shown in FIG. 2A, a plurality of DBRs (n-type semiconductor mirror layers) having a basic unit of a pair of an n-type GaAs layer and an n-type Al _0.9 Ga _0.1 As layer are stacked on an n-type GaAs substrate 101. 1 DBR layer 102, n-type Al _0.3 Ga _0.7 As cladding layer 103, active layer 104 composed of non-doped GaInNAs quantum well and GaAs barrier layer, p-type Al _0.3 Ga _0.7 As cladding layer 105, p-GaAs layer 106, p ⁺ -GaAs _0.9 Sb _0.1 layer 107 and n ⁺ -In _0.15 GaAs _0.85 layer 108 are sequentially deposited by metal organic chemical vapor deposition (MOCVD) (step 1).

Here, C is used as the p-type dopant of the p ⁺ -GaAs _0.9 Sb _0.1 layer 107, Si is used as the n-type dopant of the n ⁺ -In _0.15 GaAs _0.85 layer 108 layer, and the p doping concentration is 1 × 10 ²⁰ cm ^−3. The n doping concentration was 5 × 10 ¹⁹ cm ⁻³ . The thickness of each layer was 5 nm for the p ⁺ -GaAs _0.9 Sb _0.1 layer 107 and 10 nm for the n ⁺ -In _0.15 GaAs _0.85 layer 108.

Next, a circular resist mask having a diameter of about 6 μm is formed on the wafer by photolithography, and then the p ⁺ -GaAs _0.9 Sb _0.1 layer 107, n ⁺ -In _0.15 GaAs in the portion not covered with the resist mask by etching. _0.85 layer 108 is removed. Thereafter, the photoresist is removed (step 2).

Next, again using MOCVD, as shown in FIG. 2B, an n-GaAs layer 109, an n-InGaP layer 110, and an n-GaAs layer 111 are sequentially stacked on the wafer (step 3). In this structure, the p ⁺ -GaAs _0.9 Sb _0.1 layer 107 and the n ⁺ -In _0.15 GaAs _0.85 layer 108 form a tunnel junction. A part of this is removed and then buried with a semiconductor, and a current flows only through the remaining tunnel junction.

  Next, a resist is applied on the n-GaAs layer 111, and a resist mask 112 whose center is opened in a circular shape so that the center axis coincides with the 6 μm diameter tunnel junction formed in step 2 is formed by photolithography. To do. Next, as shown in FIG. 2C, the n-GaAs layer 111 and the n-InGaP layer 110 in the opening of the resist mask 112 are etched using selective etching (step 4). Thereafter, the resist mask 112 is removed.

  The etching process in step 4 will be described in detail. The etching apparatus etches the n− GaAs layer 111 in the opening of the resist mask 112 to remove the exposed portion of the n− GaAs layer 111. Subsequently, the n-InGaP layer 110 is etched. By this etching, the height of the semiconductor surface in the opening of the resist mask 112 and the upper surface of the n-GaAs layer 111 under the resist mask 112 can be made flat.

  In order to realize the planarization as described above, it is necessary to strictly control the etching amount. If the etching of the n-InGaP layer 110 is insufficient, a convex pattern remains at the center, and conversely, when etching proceeds to the n-GaAs 109, a concave pattern is formed at the center, and surface flattening is insufficient. It is to become. Further, such excessive or insufficient etching of the central portion causes a change in the optical length of the resonator. As a result, the oscillation wavelength of the laser changes, and the difference from the gain peak wavelength of the active layer, that is, the so-called detuning amount also changes.

  In order to strictly control the etching amount, it is generally necessary to grasp the etching rate of each layer and strictly control the etching time. However, since some variation in etching conditions and distribution within the wafer surface are inevitable, it is not easy to realize the same etching amount with good reproducibility and uniformity. On the other hand, when two types of buried layers having different compositions are used, this control condition can be greatly relaxed by using selective etching. In the case of the second buried layer n-InGaP layer 110 and the first buried layer n-GaAs layer 109 used in this embodiment, the selective etching ratio can be made particularly large. For example, the etching rate of n-GaAs with respect to hydrochloric acid is one tenth or less of the etching rate of n-InGaP. Therefore, considering the case of using hydrochloric acid during the etching of the n-InGaP layer 110, if etching is performed longer than the etching time calculated from the etching rate, there is no shortage of etching, and the etching time is increased as such. Even in this case, the n-GaAs layer 109 is not etched at all. By using selective etching in this way, etching can be stopped at the surface of the n-GaAs 109 layer, etching can be performed with good reproducibility and uniformity, and the optical length of the resonator can be made constant. Further, as shown in FIG. 2B, the flattening by the etching is performed by making the heights of the projections of the n-GaAs layer 109 and the projections other than the projections of the n-GaAs layer 111 the same during crystal growth. It can be realized.

  In order to realize etching with good reproducibility and uniformity, the larger the etching selectivity of the two buried layers, the better. In the embodiment, a combination of n-GaAs and n-InGaP that can take very large selectivity. Is used. However, since the amount of etching of each layer is grasped at the time of actual device fabrication and the etching time is controlled, the selection ratio only needs to be able to absorb variations that cannot be avoided even if such control is performed, specifically, A selection ratio of 1: 2 or more is sufficient for practical use.

  The etchant to be used may be appropriately selected to have as large a selection ratio as possible depending on the type of buried layer to be used, and the etching method may be wet etching or dry etching.

The thickness of the n-GaAs layer 111 and the n-InGaP layer 110 opposite to the convex portions of the tunnel junctions (p ⁺ -GaAs _0.9 Sb _0.1 layer 107 and n ⁺ -In _0.15 GaAs _0.85 layer 108) is obtained by the process of step 4 described above. The thickness distribution can be provided, and the convex shape on the buried layer surface caused by the convex portion of the tunnel junction can be eliminated, and the surface can be flattened.

Next, as shown in FIG. 2D, a plurality of DBRs (dielectric mirror layers) having a basic unit of a pair of an SiO ₂ layer and an amorphous Si (a-Si) layer are stacked on the wafer by using a sputtering method. The DBR layer 113 is formed (step 5). The film thicknesses of the SiO ₂ layer and the a-Si layer are set so that the respective optical path lengths in these media are approximately 1/4 of the oscillation wavelength.

  Next, as shown in FIG. 2D, unnecessary portions of the second DBR layer 113 are removed leaving a circular portion having a diameter of about 10 μm coaxially with the circular tunnel junction formed in step 2 by photolithography and etching. (Step 6).

  Next, a resist is applied on the wafer, and a circular resist mask having a diameter of about 20 μm is formed coaxially with the circular tunnel junction formed in step 2 by photolithography, and then the first DBR layer 102 is formed. Etching (mesa etching) is performed until the surface is exposed to form the columnar structure 114 (step 7). Thereafter, the resist is removed.

  Next, an electrode is formed on the first DBR layer 102 exposed by the mesa etching as follows. First, after applying a photoresist on the wafer, only a portion where an electrode is to be formed is removed by lithography. After depositing Ti / Pt / Au, the photoresist is removed and Ti / Pt / Au on the photoresist is lifted off to form an electrode 115 on a part of the first DBR layer 102 (process) 8).

  Next, after filling the mesa with polyimide 116, the polyimide 116 on the electrode 115 formed in step 8 is removed by lithography (step 9). Subsequently, an electrode is formed as follows. First, a photoresist is applied on the wafer, patterned by mask exposure, Ti / Pt / Au is then deposited, the photoresist is removed, and Ti / Pt / Au on the photoresist is lifted off to form electrodes 117 and A pad electrode 118 connected thereto is formed. At the same time, a pad electrode 119 is formed on the polyimide 116 and connected to the electrode 115 on the first DBR layer 102 formed in step 8 (step 10: see FIG. 2E).

  The VCSELs thus fabricated on the GaAs substrate can be cut out one by one or in a desired array (for example, 1 × 10, 100 × 100, etc.).

  In this embodiment, since the surface is flattened in step 4, the difference in optical path length between the mirror at the central portion where the tunnel junction is present and the surrounding portion is caused only by the difference in refractive index between GaAs and InGaP. Since the difference in optical path length resulting from this is greatly reduced as compared with the case where flattening is not performed, excessive light confinement can be suppressed. As a result, it is possible to suppress the generation of higher order modes and reduce the radiation angle.

  The configuration of the semiconductor light emitting device of this example will be described. Here, it is assumed that the present invention is applied to a surface emitting laser having an oscillation wavelength of 0.85 μm formed on a GaAs substrate. The current confinement structure of the semiconductor light emitting device of this embodiment is an oxide confinement type.

  FIG. 3 is a schematic cross-sectional view showing a configuration example of the surface emitting laser according to the present embodiment.

As shown in FIG. 3, the surface emitting laser according to the present embodiment has a first DBR layer 202, an n-type Al _0.3 Ga _0.7 As cladding layer 203, an active layer 204, a p-type Al on an n-type GaAs substrate 201. _0.3 Ga _0.7 As cladding layer 205, p-Al _0.1 Ga _0.9 As layer 206, p-GaAs layer 207, oxide layer forming layer 208, p-Al _0.1 Ga _0.9 As layer 209, p-Al _0.35 Ga _0.65 As layer 210, The p-GaAs layer 211, the second DBR layer 213, and the p-GaAs contact layer 214 are stacked in this order.

As shown in FIG. 3, the p-Al _0.1 Ga _0.9 As layer 206 has a layer thickness distribution having a portion having a predetermined thickness and a portion having a smaller thickness, and the portion having the predetermined thickness has a convex shape. Forming. p-Al _0.1 Ga _0.9 As layer 206 p-GaAs layer 207 laminated on the convex shape of the p-Al _0.1 Ga _0.9 As layer 206 in oxide layer formation layer 208 and p- Al _0.1 Ga _0.9 As layer 209 It is reflected.

The p-Al _0.35 Ga _0.65 As layer 210 and the p-GaAs layer 211 stacked on the p-Al _0.1 Ga _0.9 As layer 209 have a layer thickness distribution opposite to that of the p-Al _0.1 Ga _0.9 As layer 206. The convex shape of the p-Al _0.1 Ga _0.9 As layer 209 is absorbed by the concave shapes of the p-Al _0.35 Ga _0.65 As layer 210 and the p-GaAs layer 211. With this structure, the height of the upper surface of the p-GaAs layer 211 and the exposed surface of the p-Al _0.1 Ga _0.9 As layer 209 coincide with each other, and their surfaces are flat.

  Next, a method for manufacturing the surface emitting laser according to this embodiment will be described.

  4A to 4E are schematic cross-sectional views for explaining a method of manufacturing the surface emitting laser shown in FIG.

First, as shown in FIG. 4A, a plurality of DBRs (n-type semiconductor mirror layers) whose basic unit is a pair of an n-type Al _0.1 Ga _0.9 As layer and an n-type Al _0.9 Ga _0.1 As layer are formed on an n-type GaAs substrate 201. Stacked first DBR layer 202, n-type Al _0.3 Ga _0.7 As cladding layer 203, active layer 204 composed of non-doped GaAs quantum well and Al _0.2 GaAs barrier layer, p-type Al _0.3 Ga _0.7 As cladding layer 205, p-Al _{A 0.1} Ga _0.9 As layer 206 is sequentially deposited by metal organic chemical vapor deposition (MOCVD) (step 1).

Next, after a circular resist mask having a diameter of about 6 μm is formed on the wafer by photolithography, etching is performed from above the resist mask to the middle of the p-Al _0.1 GaAs layer 206 (step 2). As a result, a central cylinder with a diameter of 6 μm is formed. The height of this cylinder is about 50 nm.

Next, again using MOCVD, as shown in FIG. 4B, a p-GaAs layer 207, a p-type Al _x Ga _1-x As (where 0.9 <x ≦ 1) oxide layer forming layer 208, p-Al _0.1 Ga _0.9 As layer 209, p-Al _0.35 Ga _0.65 As layer 210 and p-GaAs layer 211 are sequentially stacked on the wafer (step 3). At this time, reflecting the convex structure formed in the p-Al _0.1 Ga _0.9 As layer 206, the p-GaAs layer 207 to the p-GaAs layer 211 laminated thereon are also convex.

Next, a resist is applied on the p-GaAs layer 211, and a resist mask 212 whose center is opened in a circular shape so that the central axis coincides with the 6 μm diameter convex portion formed in step 2 is formed by photolithography. To do. Next, etching is used to etch the p-GaAs layer 211 and the p-Al _0.35 Ga _0.65 As layer 210 in the opening of the resist mask 212 so that the surface becomes flat as shown in FIG. 4C (step 4). Thereafter, the resist mask 212 is removed.

The relationship between the p-Al _0.35 Ga _0.65 As layer 210 as the etching target film and the p-Al _0.1 Ga _0.9 As layer 209 as the underlying film in Step 4 is the same as that of the n-InGaP layer 110 and the n-GaAs layer 109 in Example 1. It is the same as the relationship. Therefore, also in the present embodiment, the same effects as those of the first embodiment can be obtained because the composition of the constituent elements of these buried layers is different.

Through the process of Step 4, the p-GaAs layer 211 and the p-Al _0.35 Ga _0.65 As layer 210 can have a thickness distribution opposite to the convex portion of the p-Al _0.1 Ga _0.9 As layer 206, and p-Al The convex shape on the buried layer surface caused by the convex portion of the _0.1 Ga _0.9 As layer 206 is eliminated, and the surface can be flattened.

Next, using the MOVPE method again, as shown in FIG. 4D, a second layer in which a plurality of DBRs (non-doped semiconductor mirror layers) having a pair of p-type Al _0.1 Ga _0.9 As layer and Al _0.9 Ga _0.1 As layer as a basic unit are stacked is used. A DBR layer 213 and a p-GaAs contact layer 214 are sequentially stacked on the wafer (step 5). In each DBR layer, the film thicknesses of the high refractive index Al _0.1 Ga _0.9 As layer and the low refractive index Al _0.9 Ga _0.1 As layer are such that each optical path length in these media is approximately 1/4 of the oscillation wavelength. It is set to become.

  Next, form a circular dielectric mask with a diameter of 20 μm so that the central axis coincides with the circular buried tunnel junction formed in step 2, and p-GaAs contact until the surface of the first DBR layer 202 is exposed. The layer 214 and the second DBR layer 213 and below are dry-etched (step 6). Thereby, a cylindrical structure 215 having a diameter of 20 μm is formed, and the side surface of the oxide layer forming layer 208 is exposed.

  Next, an electrode is formed on the exposed first DBR layer 202 around the cylindrical structure 215 as follows. First, a photoresist is applied to the entire surface of the wafer, and then the photoresist is removed only at a portion where an electrode is to be formed by lithography. After vapor deposition of Au / Ge / Ni, an electrode 216 is formed on a part of the first DBR layer 202 by removing the photoresist and lifting off the Au / Ge / Ni on the photoresist (step) 7).

Next, heating is performed at a temperature of about 420 ° C. for about 30 minutes in a furnace in a steam atmosphere (step 8). As a result, only the oxide layer forming layer 208 whose side surface is exposed in step 6 is selectively oxidized simultaneously in an annular shape. The reason why the Al composition x of the oxide layer forming layer Al _x Ga _1-x As is set to a value larger than 0.9 is that if it is 0.9 or less, almost no oxidation occurs, and the oxidation rate must be faster than the DBR part. Because there is.

  Subsequently, the p-side electrode is formed as follows. First, a photoresist is applied on the wafer and patterned by mask exposure. Then, Ti / Pt / Au is deposited, the photoresist is removed, and Ti / Pt / Au on the photoresist is lifted off. As shown, a p-side electrode 217 is formed (step 9).

  Next, after filling a mesa with polyimide 218 as shown in FIG. 4D, the columnar structure 215 formed in step 7 and the polyimide on the electrode 216 formed in step 7 are removed by lithography (step 10). Next, pad electrodes 219 and 220 are formed on the polyimide. Each of these pad electrodes is connected to each of the electrode 216 formed in step 6 and the p-side electrode 217 formed in step 9 (step 10: see FIG. 4E).

  The VCSELs thus fabricated on the GaAs substrate can be cut out and used one by one or in a desired array (for example, 1 × 10, 100 × 100, etc.).

  In this embodiment, an oxide layer is used as the current confinement structure. Usually, a flat layer is formed as the oxide layer formation layer, and the current confinement diameter is adjusted by controlling the oxidation time. However, since this is affected by variations in the surface condition and composition of the side surface of the oxide layer forming layer, it is difficult to obtain a designed current confinement diameter with good reproducibility and uniformity.

On the other hand, in this embodiment, as described above, the oxide layer forming layer 208 has a convex shape reflecting the convex structure formed in the p-Al _0.1 Ga _0.9 As layer 206 on the lower side. For this reason, as shown in FIG. 4B, a slope portion that is not parallel to the substrate appears near the center. Due to the difference in crystal plane orientation, the oxidation rate differs between the inclined surface portion and the portion parallel to the substrate outside thereof. Specifically, the oxidation rate becomes slower on the slope portion. In other words, the oxidation rate decreases around 6 μm, which is the diameter of the cylinder on which the p-Al _0.1 Ga _0.9 As layer 206 is formed. Therefore, the designed current confinement diameter can be obtained with good uniformity and reproducibility. However, when such a convex structure is used, optical confinement increases due to this.

  Further, when the crystal is grown on the convex structure, the growth rate is different between the upper surface of the convex part and the flat part next to the convex part and the slope connecting it, so that the raw material can move between the two. For this reason, the growth rate differs from the case where the entire surface is grown on a flat substrate, and the rate of change in the rate changes as the growth progresses and the level difference of the convex portion changes. This is disadvantageous for DBR growth that requires precise layer thickness control. In this embodiment, these problems are solved by performing planarization in step 4.

  The configuration of the semiconductor light emitting device of this example will be described. Here, it is assumed that the present invention is applied to a surface emitting laser having an oscillation wavelength of 1.3 μm formed on an InP substrate. The current confinement structure of the semiconductor light emitting device of this example is a current block structure.

  FIG. 5 is a schematic cross-sectional view showing a configuration example of the surface emitting laser according to the present embodiment.

As shown in FIG. 5, the surface emitting laser of the present example includes a first DBR layer 302, an n-type InP cladding layer 303, an active layer 304, a p-type InP cladding layer 305, on an n-type InP substrate 301. In this configuration, an n-type InP layer 306, a p-type InP layer 307, a p-type In _0.8 Ga _0.2 As _0.44 P _0.56 layer 308, a p-type InP layer 309, and a second DBR layer 311 are sequentially stacked.

  As shown in FIG. 5, the n-type InP layer 306 has a distribution of sites with and without a pattern, and a concave shape is formed. The p-type InP layer 307 formed on the n-type InP layer 306 also reflects the concave shape.

The p-type In _0.8 Ga _0.2 As _0.44 P _0.56 layer 308 and the p-type InP layer 309 on the p-type InP layer 307 have a layer thickness distribution opposite to that of the n-type InP layer 306. The concave shape of the p-type InP layer 307 is absorbed by the downward convex shape of the p-type In _0.8 Ga _0.2 As _0.44 P _0.56 layer 308 and the p-type InP layer 309. With this structure, the height of the upper surface of the p-type InP layer 307 and the upper surface of the p-type InP layer 309 coincide with each other, and the surfaces thereof are flat.

  Next, a method for manufacturing the surface emitting laser according to this embodiment will be described.

  6A to 6E are schematic cross-sectional views for explaining a method of manufacturing the surface emitting laser shown in FIG.

First, as shown in FIG. 6A, a plurality of DBRs (n-type semiconductor mirror layers) having a basic unit of a pair of an n-type InP layer and an n-type AlGaInAs layer lattice-matched to InP are stacked on an n-type InP substrate 301. First DBR layer 302, n-type InP cladding layer 303, active layer 304 comprising non-doped Al _0.15 Ga _0.15 In _0.7 As quantum well and Al _0.34 Ga _0.22 In _0.44 As barrier layer, p-type InP cladding layer 305, n-type InP Layers 306 are sequentially stacked (step 1).

  Next, a resist mask having an open circular portion having a diameter of about 7 μm is formed by photolithography, and the n-type InP layer 306 in a portion not covered with the resist mask is removed by etching, and then the photoresist is removed (process) 2).

Next, again using the MOCVD method, as shown in FIG. 6B, a p-type InP layer 307, a p-type In _0.8 Ga _0.2 As _0.44 P _0.56 layer 308, and a p-type InP layer 309 are sequentially stacked on the wafer (step 3). Next, a resist is applied on the p-type InP layer 309, and a circular resist mask 310 having a diameter of about 7 μm is formed by a photolithography technique so that the center axis coincides with the 7 μm diameter recess formed in step 2. .

Next, using a selective etchant, the p-type InP layer 309 and the p-type In _0.8 GaAs _0.44 P layer 308 at portions not covered with the resist mask 310 are sequentially removed (step 4). As a result, the surface is flattened as shown in FIG. 6C. Thereafter, the resist mask 310 is removed.

The relationship between the etched p-type In _0.8 GaAs _0.44 P layer 308 and the underlying p-type InP layer 307 in Step 4 is the same as the relationship between the n-InGaP layer 110 and the n-GaAs layer 109 in Example 1. It is the same. Therefore, also in the present embodiment, the same effects as those of the first embodiment can be obtained because the composition of the constituent elements of these buried layers is different. As a result, the upper surface of the p-type InP layer 307 and the upper surface of the remaining p-type InP layer 309 coincide with each other, and the surface is flattened as described above.

Subsequently, as shown in FIG. 6D, a _second DBR (dielectric mirror layer) having a basic unit consisting of a pair of an SiO ₂ layer and an amorphous Si (a-Si) layer is stacked on the wafer by sputtering. The DBR layer 311 is formed (step 5).

The film thicknesses of the SiO ₂ layer and the a-Si layer are set so that the respective optical path lengths in these media are approximately 1/4 of the oscillation wavelength. Next, unnecessary portions of the second DBR layer 311 are removed leaving a circular portion having a diameter of about 10 μm coaxially with the circular tunnel junction formed in step 2 by photolithography and etching (step 6). Next, mesa etching is performed using the same procedure as in Example 1 to form a cylindrical structure 312 having a diameter of about 30 μm that reaches the surface of the first DBR layer 302 (Step 7).

  Next, an electrode is formed on the first DBR layer 302 exposed by the mesa etching. First, after applying a photoresist on the wafer, only a portion where an electrode is to be formed is removed by lithography. After depositing Ti / Pt / Au, the photoresist is removed and Ti / Pt / Au on the photoresist is lifted off to form an electrode 313 on a part of the first DBR (step 8). .

  Next, after filling the mesa with polyimide 314, the polyimide on the electrode formed in step 8 is removed by lithography (step 9). Subsequently, an electrode is formed as follows. First, a photoresist is applied on the wafer and patterned by mask exposure. Then, Ti / Pt / Au is deposited, the photoresist is removed, and Ti / Pt / Au on the photoresist is lifted off to form the ring electrode 315. Then, a pad electrode 316 connected thereto is formed. At the same time, a pad electrode 317 is formed on the polyimide 314 and connected to the electrode 313 on the first DBR layer 302 formed in step 8 (step 10: see FIG. 6E).

  The VCSELs thus produced on the InP substrate can be cut out and used one by one or in a desired array (for example, 1 × 10, 100 × 100, etc.).

  In this embodiment, since the n-type InP layer 306 is formed between the p-type InP layer 305 and the p-type InP layer 307 except for the circular portion of the center 7 μm, this functions as a current blocking layer, and the current is circular. It is narrowed to a part.

  However, in order to form this current block structure, it is necessary to remove the n-type InP layer 306 in the circular portion in Step 2, thereby forming a recess. For this reason, the optical path length sandwiched between the mirrors on both sides is smaller in the circular portion than in the surrounding portion. In this case, contrary to Example 1, the equivalent refractive index is smaller in the circular portion, so that a so-called reverse waveguide structure is formed, and laser oscillation is difficult. For this reason, there is a possibility that problems such as an increase in the threshold current and a lack of oscillation may occur. On the other hand, in this embodiment, these problems are solved by performing flattening in step 4.

  The configuration of the semiconductor light emitting device of this example will be described. Here, it is assumed that the present invention is applied to a surface emitting laser having an oscillation wavelength of 1.15 μm formed on a GaAs substrate. The current confinement structure of the semiconductor light emitting device of this example is a buried tunnel junction.

  FIG. 7 is a schematic cross-sectional view showing a configuration example of the surface emitting laser according to the present embodiment.

As shown in FIG. 7, the surface emitting laser of the present example has a first DBR layer 402, an oxide layer forming layer 403, an n-type Al _0.2 Ga _0.8 As cladding layer 404, an active layer on an n-type GaAs substrate 401. Layer 405, p-type Al _0.3 Ga _0.7 As cladding layer 406, p-GaAs layer 407, p-Al _0.3 Ga _0.7 As layer 408, p-GaAs layer 409, p ⁺ -GaAs _0.9 Sb _0.1 layer 410, n ⁺ -In _{In this configuration, a 0.15} Ga _0.85 As layer 411, an n-GaAs layer 412, an n-GaAs layer 413, an n-InGaP layer 414, and a second DBR layer 416 are sequentially stacked.

p ⁺ -GaAs _0.9 Sb _0.1 layer _{^{410, n + - In 0.15 Ga}} 0.85 As layer 411 and n-GaAs layer 412 has a configuration same pattern are laminated, each have the same layer thickness distribution . These layers have a distribution of sites with and without a pattern. p ⁺ -GaAs _0.9 Sb _0.1 layer _{^{410, n + - In 0.15 Ga}} 0.85 As layer 411 and n-GaAs layer 412 constituting a tunnel junction at the site with a pattern.

  The tunnel junction portion is embedded in the n-GaAs layer 413, and the n-InGaP layer 414 formed on the n-GaAs layer 413 has a layer thickness distribution opposite to that of the tunnel junction portion. The convex shape of the tunnel junction is absorbed by the concave shape of the n-InGaP layer 414. With this structure, the upper surface of the n-InGaP layer 414 and the exposed surface of the n-GaAs layer 413 have the same height, and their surfaces are flat.

  Next, a method for manufacturing the surface emitting laser according to this embodiment will be described.

  8A to 8E are schematic cross-sectional views for explaining a method of manufacturing the surface emitting laser shown in FIG.

First, as shown in FIG. 8A, a plurality of DBRs (n-type semiconductor mirror layers) having a basic unit of a pair of an n-type GaAs layer and an n-type Al _0.9 Ga _0.1 As layer are stacked on an n-type GaAs substrate 401. 1 DBR layer 402, oxide layer forming layer 403 of n _- type Al _x Ga _1-x As (where 0.9 <x <1), n-type Al _0.2 Ga _0.8 As cladding layer 404, non-doped In _0.35 Ga _0.65 As quantum well Active layer 405 comprising a GaAs barrier layer, p-type Al _0.3 Ga _0.7 As cladding layer 406, p-GaAs layer 407, p-Al _0.3 Ga _0.7 As layer 408, p-GaAs layer 409, p ⁺ -GaAs _0.9 Sb _0.1 layer 410, n ⁺ -In _0.15 Ga _0.85 As layer 411, and n-GaAs layer 412 are sequentially deposited by metal organic chemical vapor deposition (MOCVD) (step 1).

Here, C is used as the p-type dopant of the p ⁺ -GaAs _0.9 Sb _0.1 layer 410, Si is used as the n-type dopant of the n ⁺ -In _0.15 Ga _0.85 As layer 411, and the p doping concentration is 1 × 10 ²⁰ cm ^−3. The n doping concentration was 2 × 10 ¹⁹ cm ⁻³ . The thickness of each layer was 5 nm for the p ⁺ -GaAs _0.9 Sb _0.1 layer 410 and 10 nm for the n ⁺ -In _0.15 Ga _0.85 As layer 411.

Next, a circular resist mask having a diameter of about 6 μm is formed on the wafer by photolithography, and then the n-GaAs layer 412 and the n ⁺ -In _0.15 Ga _0.85 As layer 411 in a portion not covered with the resist by etching. The p ⁺ -GaAs _0.9 Sb _0.1 layer 410 layer is removed (step 2). Thereafter, the photoresist is removed (step 3).

Next, as shown in FIG. 8B, an n-GaAs layer 413 and an n-InGaP layer 414 are sequentially stacked on the wafer again by using the MOCVD method (step 4). In this structure, the p ⁺ -GaAs _0.9 Sb _0.1 layer 410 and the n ⁺ -In _0.15 Ga _0.85 As layer 411 form a tunnel junction. A part of this is removed and then buried with a semiconductor, and a current flows only through the remaining tunnel junction.

  The tunnel junction is disposed at a node of a standing wave whose interface is between the first DBR layer 402 and a second DBR layer described later, and reduces light absorption. In addition, a step in the semiconductor is produced by etching in step 2. At this time, the thickness of the n-GaAs layer 412 is set so that the optical path length from the convex surface to the tunnel junction interface is almost 1/4 of the oscillation wavelength. ing. The layer thicknesses of the n-GaAs layer 413 and the n-InGaP layer 414 are set so that the optical path length of each layer is an integral multiple of 1/4, such as approximately 1/2 or 1/4 of the oscillation wavelength.

  Next, a resist is applied on the n-InGaP layer 414, and a resist mask 415 whose center is opened in a circular shape so that the center axis coincides with the 6 μm diameter tunnel junction formed in step 2 is formed by photolithography. To do. Then, the n-InGaP layer 414 in the opening of the resist mask 415 is etched using selective etching (step 5).

  The relationship between the n-InGaP layer 414 as the etching target film and the n-GaAs layer 413 as the underlying film in the step 5 is the same as the relationship between the n-InGaP layer 110 and the n-GaAs layer 109 in the first embodiment. Therefore, also in the present embodiment, the same effects as those of the first embodiment can be obtained because the composition of the constituent elements of these buried layers is different. Therefore, the height of the upper surface of the n-InGaP layer 414 and the exposed surface of the n-GaAs layer 413 coincide.

  8C, the n-InGaP layer 414 can have a thickness distribution opposite to the convex portion of the tunnel junction, as shown in FIG. 8C. The convex shape is eliminated and the surface can be flattened. Thereafter, the resist mask 415 is removed.

Next, a second DBR layer 416 in which a plurality of DBRs (dielectric mirror layers) having a basic unit of a pair of an SiO ₂ layer and an amorphous Si (a-Si) layer is formed on the wafer by sputtering is formed. To do. The film thicknesses of the SiO ₂ layer and the a-Si layer are set so that the optical path lengths in these media are approximately 1/4 of the oscillation wavelength (step 6).

  Next, as shown in FIG. 8D, unnecessary portions of the second DBR layer 416 are removed leaving a circular portion having a diameter of about 10 μm coaxially with the circular tunnel junction formed in Step 2 by photolithography and etching ( Step 7).

  Next, a resist is applied on the wafer, a circular resist mask having a diameter of about 20 μm is formed coaxially with the circular tunnel junction formed in step 2 by photolithography, and then the surface of the first DBR layer 402 Etching (mesa etching) is performed until a columnar structure 417 is formed (step 8). Thereafter, the resist is removed.

  Next, an electrode is formed on the first DBR layer 402 exposed by the mesa etching as follows. First, after applying a photoresist on the wafer, the photoresist is removed only at a portion where an electrode is to be formed by lithography. After depositing Au / Ga / Ni, the photoresist is removed, and Au / Ga / Ni on the photoresist is lifted off to form an electrode 418 on a part of the first DBR layer 402 (step) 9).

Then after forming the SiO ₂ layer 419 is removed SiO ₂ layer 419 on the electrode 418 formed in the step 9 by lithography (step 10). Subsequently, an electrode is formed as follows. First, a photoresist is applied on the wafer and patterned by mask exposure. Then, Au / Ge / Ni is evaporated, the photoresist is removed, and Au / Ge / Ni on the photoresist is lifted off. As shown, an electrode 420 and a pad electrode 421 connected thereto are formed. At the same time, a pad electrode 422 is formed on the SiO ₂ layer 419 and connected to the electrode 418 on the first DBR layer 402 formed in the above step 9 (step 11: see FIG. 8E).

  The VCSELs thus fabricated on the GaAs substrate can be cut out and used one by one or in a desired array (for example, 1 × 10, 100 × 100, etc.).

  Also in this embodiment, the surface is flattened in step 5 in the same manner as in embodiment 1, and even when the buried layer is thin, the generation of higher-order modes can be suppressed and the radiation angle can be reduced.

  In this example, the optical path length from the tunnel junction interface to the second DBR layer is 3/4 of the oscillation wavelength at the upper part of the tunnel junction, and the n-GaAs layer 413 and the n-InGaP layer 414 are optical paths of the respective layers. The lengths are approximately 1/2 and 1/4 of the oscillation wavelength, respectively. Since the refractive index of InGaP is smaller than that of GaAs, the reflection at the interface between the n-GaAs layer 413 and the n-InGaP layer 414 is almost in phase with the reflected wave from the second DBR layer. For this reason, the reflectance of the portion where the surrounding InGaP layer 414 exists is slightly lower than the reflectance of the upper part of the tunnel junction. As a result, a so-called mode filter effect is produced, which has an advantage that higher-order modes are further suppressed.

  As described above, the first to fourth embodiments have been described as embodiments of the present invention. However, the implementation method of the present invention is not limited to the above-described various forms, and various modifications can be made without departing from the scope of the present invention. Is possible. Regarding the wavelength and material of the semiconductor light emitting device, those other than those listed in the examples can be selected.

  In the semiconductor light emitting device of the present invention, since the second buried layer is formed with a layer thickness distribution opposite to that of the pattern layer through the first buried layer in the pattern layer forming direction, The concave portion or the convex portion is absorbed by the second buried layer. In addition, since the composition of the constituent elements of the first and second buried layers is different, the amount of scraping of the first buried layer serving as a base film is suppressed when the second buried layer is etched. Can do. Therefore, the surface can be flattened with good reproducibility and uniformity, and the optical length of the resonator can be accurately controlled.

  In the method for manufacturing a semiconductor light emitting device of the present invention, since two or more kinds of buried layers having different constituent element compositions are used, a technique such as selective etching using any one of the buried layers as an etching target film is used. Is possible. As a result, an embedding layer having a convex shape opposite to the concave portion in the resonator is formed, or an embedding layer having a concave shape opposite to the convex portion in the resonator is formed to flatten the surface. Easy to do.

  According to the present invention, since the surface of the resonator can be flattened even if the buried layer is thinner than the conventional one, the optical confinement factor can be adjusted to an appropriate value without increasing the resonator length. Can do. Therefore, the problem due to the trade-off relationship between the radiation angle and the modulation speed, which was a problem of the prior art, can be solved, and a device capable of low-radiation angle and high-speed modulation can be realized. Contributes greatly to improvement.

  In the present invention, two or more types of buried layers are used to planarize the resonator surface. However, as described above, it is preferable that selective etching can be performed on a predetermined buried layer. In order to perform surface flattening by selective etching, it is desirable that one or more buried layers be provided between a layer having a layer thickness distribution and a layer having a thickness distribution opposite thereto. In addition, since the purpose of planarization is to suppress the generation of higher-order modes of the laser light, it is necessary to planarize the portion where the light is distributed, and there are concave and convex portions in the portion where the light does not reach. It doesn't matter.

  In addition, the upper mirror of the layer having a thickness distribution is mainly a semiconductor DBR or a dielectric DBR. In the case of a dielectric DBR, the refractive index difference between the two layers constituting the DBR is large, so that resonance occurs. The difference in the optical path length in the chamber greatly affects the equivalent refractive index difference and thus the optical confinement. For this reason, flattening of the resonator surface is particularly important, and the present invention is effective.

  In addition, a layer having a thickness distribution is often used for producing a current confinement structure, and the present invention is particularly effective for flattening this.

  In addition, for a low radiation angle, it is desirable that the flatness of the resonator surface be 10 nm or less on the upper surface of the region where light is distributed.

  Furthermore, in order to reduce the difference in equivalent refractive index due to the refractive index difference of the buried layer, it is desirable that the refractive index of each buried layer be within 10% at the laser oscillation wavelength.

3 is a schematic cross-sectional view showing a configuration example of a surface emitting laser according to Example 1. FIG. FIG. 3 is a schematic cross-sectional view for explaining the method for manufacturing the surface emitting laser according to the first embodiment. FIG. 3 is a schematic cross-sectional view for explaining the method for manufacturing the surface emitting laser according to the first embodiment. FIG. 3 is a schematic cross-sectional view for explaining the method for manufacturing the surface emitting laser according to the first embodiment. FIG. 3 is a schematic cross-sectional view for explaining the method for manufacturing the surface emitting laser according to the first embodiment. FIG. 3 is a schematic cross-sectional view for explaining the method for manufacturing the surface emitting laser according to the first embodiment. 6 is a schematic cross-sectional view showing a configuration example of a surface emitting laser according to Example 2. FIG. 6 is a schematic cross-sectional view for explaining the method for manufacturing the surface-emitting laser according to Example 2. FIG. 6 is a schematic cross-sectional view for explaining the method for manufacturing the surface-emitting laser according to Example 2. FIG. 6 is a schematic cross-sectional view for explaining the method for manufacturing the surface-emitting laser according to Example 2. FIG. 6 is a schematic cross-sectional view for explaining the method for manufacturing the surface-emitting laser according to Example 2. FIG. 6 is a schematic cross-sectional view for explaining the method for manufacturing the surface-emitting laser according to Example 2. FIG. 6 is a schematic cross-sectional view illustrating a configuration example of a surface emitting laser according to Example 3. FIG. 10 is a schematic cross-sectional view for explaining the method for manufacturing the surface-emitting laser according to Example 3. FIG. 10 is a schematic cross-sectional view for explaining the method for manufacturing the surface-emitting laser according to Example 3. FIG. 10 is a schematic cross-sectional view for explaining the method for manufacturing the surface-emitting laser according to Example 3. FIG. 10 is a schematic cross-sectional view for explaining the method for manufacturing the surface-emitting laser according to Example 3. FIG. 10 is a schematic cross-sectional view for explaining the method for manufacturing the surface-emitting laser according to Example 3. FIG. 6 is a schematic cross-sectional view showing a configuration example of a surface emitting laser according to Example 4. FIG. 10 is a schematic cross-sectional view for explaining the method for manufacturing the surface-emitting laser according to Example 4. FIG. 10 is a schematic cross-sectional view for explaining the method for manufacturing the surface-emitting laser according to Example 4. FIG. 10 is a schematic cross-sectional view for explaining the method for manufacturing the surface-emitting laser according to Example 4. FIG. 10 is a schematic cross-sectional view for explaining the method for manufacturing the surface-emitting laser according to Example 4. FIG. 10 is a schematic cross-sectional view for explaining the method for manufacturing the surface-emitting laser according to Example 4. FIG. It is a figure for demonstrating one structural example of the conventional embedding structure. It is a figure for demonstrating another structural example of the conventional embedding structure.

Explanation of symbols

101, 201, 401 n-type GaAs substrate 102, 202, 302, 402 First DBR layer 103, 203 n-type Al _0.3 Ga _0.7 As cladding layer 104, 204, 304, 405 Active layer 105, 205 p-type Al _0.3 Ga _0.7 As cladding layer 108 p ⁺ -In _0.15 Ga _0.85 As layer 109 n-GaAs layer 110 n-InGaP layer 111 n-GaAs layer 113, 213, 311, 416 Second DBR layer 206, 209 p-Al _0.1 Ga _0.9 As layer 210 p-Al _0.35 Ga _0.65 As layer 211 p-GaAs layer 301 n-InP substrate 303 n-InP cladding layer 305 p-InP cladding layer 306 n-InP layer 307 p-InP layer 308 p-type In _0.8 Ga _0.2 As _0.44 P _0.56 layer 309 p-InP layer 404 n-type Al _0.2 Ga _0.8 As cladding layer 406 p-type Al _0.3 Ga _0.7 As cladding layer 411 n ⁺ -In _0.15 Ga _0.85 As layer 412, 413 n-GaAs layer 414 n- InGaP layer

Claims (12)

A semiconductor light emitting device having a resonator sandwiched between two reflecting mirrors,
A pattern layer having a predetermined layer thickness distribution, constituting a part of the resonator;
A first embedded layer provided on the patterning layer side of the pattern layer with respect to the pattern layer;
A second buried layer provided in contact with the first buried layer, having a composition different from that of the first buried layer and having a layer thickness distribution opposite to that of the pattern layer;
A semiconductor light emitting device having:   The semiconductor light emitting element according to claim 1, wherein the first and second buried layers are provided between the two reflecting mirrors.   2. The semiconductor light emitting element according to claim 1, wherein the first and second buried layers are provided in a region where laser light is distributed.   4. The semiconductor light emitting element according to claim 1, wherein the pattern layer forms part of a current confinement structure. 5.   The relationship between the first buried layer and the second buried layer is an etching selectivity ratio between the first buried layer and the second buried layer under the etching conditions for the second buried layer. The semiconductor light-emitting element according to claim 1, wherein the ratio is 1: 2 or more.   6. The semiconductor light emitting element according to claim 1, wherein the first buried layer is provided in contact with the pattern layer.   The semiconductor light-emitting device according to claim 1, wherein the current confinement structure is a tunnel junction.   The semiconductor light emitting element according to claim 1, wherein a dielectric is included in a part of the two reflecting mirrors.   9. The semiconductor light emitting device according to claim 1, wherein the flatness of the upper surface of the laminated structure including the first and second buried layers is 10 nm or less.   10. The semiconductor light emitting device according to claim 1, wherein an optical path length of at least one of the first and second buried layers is an integral multiple of ¼ of an oscillation wavelength.   11. The semiconductor light emitting device according to claim 1, wherein a difference in refractive index between the first and second buried layers at a laser oscillation wavelength is within 10%. Forming a first reflecting mirror on the substrate;
Forming a first clad layer, an active layer and a second clad layer in order on the first reflecting mirror;
Forming a pattern layer having a predetermined layer thickness distribution constituting a part of the current confinement structure above the second cladding layer;
Forming a first buried layer on the pattern layer;
Forming a second buried layer having a constituent element composition different from that of the first buried layer on the first buried layer;
Forming a layer thickness distribution opposite to the pattern layer in the second buried layer by selective etching;
A method of manufacturing a semiconductor light emitting device, wherein a second reflecting mirror is formed above the second buried layer.

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