JP2008159927A - Group III nitride semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a trench on a surface of a group III nitride semiconductor region containing a first conductivity type impurity, and to fill the trench with a group III nitride semiconductor region containing a second conductivity type impurity. In a semiconductor device, an electric field is prevented from being concentrated locally, and a high breakdown voltage of the semiconductor device is realized.
Trenches, 12, and 4 are formed on the surface side of a first group III nitride semiconductor region 30 containing an impurity of a first conductivity type. The trenches 12, 8, and 4 are filled with second group III nitride semiconductor regions 14, 10, and 6 containing impurities of the second conductivity type. The tangent line of the junction line extends over the entire length of the junction line between the first group III nitride semiconductor region 30 and the second group III nitride semiconductor region 14, 10, 6 exposed in the cross section of the trenches 12, 8, 4. There are no vertices whose slope changes discontinuously.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device using a group III nitride semiconductor used for a high voltage device or a high frequency device, and a manufacturing method thereof.

A semiconductor device that uses a group III nitride semiconductor, a trench formed on the surface, and a group III nitride semiconductor region containing n-type impurities (hereinafter referred to as an n-type group III nitride semiconductor region) And a group III nitride semiconductor region filling the trench and containing p-type impurities (hereinafter, sometimes referred to as a p-type group III nitride semiconductor region). An apparatus is disclosed in Patent Document 1. In the semiconductor device of Patent Document 1, the junction surface of the n-type group III nitride semiconductor region and the p-type group III nitride semiconductor region is exposed in the cross section of the trench. The junction line that is exposed in the cross section and forms the side surface of the trench extends in a direction perpendicular to the surface of the semiconductor substrate, and the junction line that forms the bottom surface of the trench is the surface of the semiconductor substrate. It extends in parallel with. The junction line connecting the side surface of the trench and the bottom surface of the trench is orthogonal, and the inclination of the junction line changes discontinuously at the intersection. That is, a horizontally extending bottom surface (inclination = 0) and a vertically extending side surface (inclination = infinity) form a corner at the intersection.
In a group III nitride semiconductor, a predetermined region of an n-type group III nitride semiconductor region cannot be made p-type by implanting p-type ions into the predetermined region of the n-type group III nitride semiconductor region. This is because it is difficult to activate the implanted p-type impurity. Therefore, in Patent Document 1, a protective film having a predetermined region opened on the surface of the n-type group III nitride semiconductor region is formed, and the n-type group III nitride semiconductor region is formed from the opening in which the protective film is not formed. The trench is formed by dry etching. When the trench is formed by dry etching, the line forming the side surface of the trench and the line forming the bottom surface of the trench are orthogonal to each other in the cross section of the trench. Since the p-type group III nitride semiconductor region is grown in the trench, the side surface of the trench is formed when the junction line between the n-type group III nitride semiconductor region and the p-type group III nitride semiconductor region is observed. The joining line to be formed and the joining line forming the bottom surface of the trench are orthogonal to each other. In the group III nitride semiconductor, in order to locally form the group III nitride semiconductor region of the second conductivity type in the group III nitride semiconductor region of the first conductivity type, the dry etching technique and the crystal growth technique are combined. The junction line of the first-conductivity-type group III nitride semiconductor region and the second-conductivity-type group III nitride semiconductor region is the apex (corner) where the side surface and the bottom surface are orthogonal and the inclination changes discontinuously. Part).

JP 2004-260140 A

The semiconductor device having the second conductivity type region filling the trench formed in the first conductivity type region of the group III nitride semiconductor region is exposed to the cross section of the trench because the manufacturing method thereof is limited. The junction line between the n-type group III nitride semiconductor region and the p-type group III nitride semiconductor region has a vertex (corner) whose inclination changes discontinuously. If the slope has a vertex that changes discontinuously, an electric field concentrates near the vertex when a reverse bias is applied to the semiconductor device. In the portion where the electric field is concentrated, the breakdown voltage of the semiconductor device becomes small. That is, the breakdown voltage of the semiconductor device is lowered.
In the present invention, a trench is formed on the surface of the group III nitride semiconductor region containing the first conductivity type impurity, and the trench is filled with the group III nitride semiconductor region containing the second conductivity type impurity. In a semiconductor device, the local concentration of the electric field is prevented, and the high breakdown voltage of the semiconductor device is realized.

When a portion with a high breakdown voltage and a portion with a low breakdown voltage coexist in the semiconductor device, the breakdown voltage of the semiconductor device is determined by the portion with the lowest breakdown voltage. In other words, the breakdown voltage of the semiconductor device can be increased by improving the breakdown voltage of the portion with a low breakdown voltage in the semiconductor device. In the present invention, the breakdown voltage of the semiconductor device is increased by reducing the concentration of the electric field in the portion where the breakdown voltage in the semiconductor device is low, that is, in the portion where the electric field is most likely to concentrate when a reverse bias is applied to the semiconductor device. .
The semiconductor device of the present invention includes a first group III nitride semiconductor region having a trench formed on the surface and containing an impurity of the first conductivity type, and filling the trench and a second conductivity type. A second group III nitride semiconductor region containing impurities is provided. A junction line between the first group III nitride semiconductor region and the second group III nitride semiconductor region is exposed in the cross section of the trench. In the semiconductor device of the present invention, there is no vertex at which the slope of the tangent of the junction line changes discontinuously over the entire length of the junction line exposed in the cross section of the trench.

In the semiconductor device described above, since the apex does not exist in the first group III nitride semiconductor region and the second group III nitride semiconductor region, an electric field is generated in a local portion when a reverse bias is applied to the semiconductor device. Concentration can be prevented. Since the low breakdown voltage portion in the semiconductor device can be improved, the breakdown voltage of the semiconductor device can be increased.
As a feature of the semiconductor device of the present invention, when a cross section of a trench formed in the first group III nitride semiconductor region is observed, the first group III nitride semiconductor region and the second group III nitride semiconductor It should not be evaluated that there are no vertices where the slope of the tangent of the joint line changes discontinuously over the entire length of the joint line of the region. As described above, in the group III nitride semiconductor, the second conductivity type impurity is ion-implanted into the first conductivity type semiconductor region, and the second conductivity type is implanted into the local region in the first conductivity type semiconductor region. A semiconductor region cannot be formed. This is because in the group III nitride semiconductor, it is difficult to activate the second conductivity type impurity even if the second conductivity type impurity is ion-implanted into the first conductivity type semiconductor region. That is, in the conventional group III nitride semiconductor device, the first group III nitride semiconductor is formed in order to form the second group III nitride semiconductor region in the local region in the first group III nitride semiconductor region. A method of etching a region to form a trench and crystal-growing a second group III nitride semiconductor inside the trench, or a second group III nitride on the entire surface of the first group III nitride semiconductor region And forming a trench by etching a predetermined range of the surface of the second group III nitride semiconductor region to reach the first group III nitride semiconductor region, and generating a trench from the inside of the trench. It is common sense to employ a method for crystal growth of the first group III nitride semiconductor so as to cover the surface of the group nitride semiconductor region. As long as this method is employed, it is inevitable that the slope of the tangent of the junction line between the first group III nitride semiconductor region and the second group III nitride semiconductor region has a discontinuous change.
The present invention is a technique for improving the breakdown voltage of a semiconductor device by overcoming the conventional technical common sense.

  In the semiconductor device of the present invention, at least one pair of trenches is formed on the surface of the first group III nitride semiconductor region, and the second group III nitride semiconductor region fills both of the pair of trenches. The bonding line forming the inner side surface of the pair of trenches extends in a direction orthogonal to the surface of the semiconductor substrate, and the bonding line forming the bottom surface of the pair of trenches is the surface of the semiconductor substrate. It is also effective when extending in parallel with. In this case, the joining line connecting the inner side surface of the trench and the bottom surface of the trench is a curved curve that protrudes toward the first group III nitride semiconductor region. This is also effective when the joint line forming the outer side surfaces of the pair of trenches extends in a direction perpendicular to the surface of the semiconductor substrate. In this case, a joining line connecting the outer side surface of the pair of trenches and the bottom surface of the trench is a curve that is convex toward the first group III nitride semiconductor region.

  According to the above semiconductor device, when a reverse bias is applied to the semiconductor device, the electric field is most likely to be concentrated among the junction lines of the first group III nitride semiconductor region and the second group III nitride semiconductor region. In the portion, electric field concentration in the portion can be reduced. When a reverse bias is applied to the semiconductor device, an electric field is generated at the junction line between the first group III nitride semiconductor region and the second group III nitride semiconductor region where the slope of the tangent line of the junction line changes greatly. Easy to concentrate. That is, the electric field tends to concentrate in the vicinity of a portion where a joint line extending in a direction perpendicular to the surface of the semiconductor substrate and a joint line extending in parallel with the surface of the semiconductor substrate intersect. In the present invention, it is possible to prevent the electric field from concentrating on a portion where the electric field tends to concentrate. The breakdown voltage of the semiconductor device can be increased.

  In a specific aspect of the semiconductor device of the present invention, a third group III nitride semiconductor region stacked in a range extending over a pair of trenches on the surface of the first group III nitride semiconductor region, A group III nitride semiconductor region formed on the surface of the group III nitride semiconductor region over the pair of trenches, and formed above the pair of trenches. A pair of low resistance regions on the front surface side that are electrically connected to the nitride semiconductor region and the fourth group III nitride semiconductor region, and a back surface side low current region formed on the back surface side of the first group III nitride semiconductor region. The semiconductor device includes a resistance region and can be embodied in a semiconductor device in which the band gap of the fourth group III nitride semiconductor region is wider than the band gap of the third group III nitride semiconductor region.

  According to the semiconductor device described above, a hetero bond is formed by the third group III nitride semiconductor region and the fourth group III nitride semiconductor region. A two-dimensional electron gas region is formed between the third group III nitride semiconductor region and the fourth group III nitride semiconductor region. By making the conductivity type of the fourth group III nitride semiconductor region the same conductivity type as the third group III nitride semiconductor region, or by making the conductivity type of the fourth group III nitride semiconductor region i-type A two-dimensional electron gas region is formed in the same conductivity type semiconductor region or i-type semiconductor region. Carrier movement resistance is reduced, and the on-resistance of the semiconductor device can be reduced.

It is preferable to have a gate electrode laminated via an insulating layer on the surface of the uppermost group III nitride semiconductor region located between the pair of low resistance regions on the surface side.
By applying a voltage to the gate electrode, a two-dimensional electron gas region can be formed on the heterojunction surface. A normally-off semiconductor device can be realized.

In the semiconductor device of the present invention, a trench is formed on the surface and the first group III nitride semiconductor region containing the first conductivity type impurity is included, and the trench makes a round of the cell area. The terminal guard ring is preferably formed by the second group III nitride semiconductor region filling the trench that goes around the cell area.
According to the semiconductor device described above, the depletion layer can be extended to the termination area when a reverse bias is applied to the semiconductor device. In the cross section of the terminal guard ring, the terminal guard ring has no apex, and the electric field concentration generated when the apex is present can be mitigated. The breakdown voltage of the semiconductor device can be increased.

  In the present invention, a method for manufacturing a semiconductor device can also be provided. The manufacturing method includes a step of forming a first protective film on the surface of the first group III nitride semiconductor region containing impurities of the first conductivity type, and a second protective film on a part of the surface of the first protective film. And forming the second protective film from a position where the second protective film is not present by isotropically etching the first protective film without etching the first group III nitride semiconductor region and the second protective film. When observing a cross section along a straight line extending toward the position where the film exists, the first group III nitride semiconductor region in contact with the first group III nitride semiconductor region from the end of the first protective film in contact with the second protective film is observed. A step of forming a curve having no vertex at which the slope of the tangent of the curve discontinuously changes over the entire length of the curve formed toward the end portion of the first protective film; and the second protective film is removed. Both the process, the first protective film and the first group III nitride semiconductor region, By anisotropically etching from the surface side, when the cross section along the straight line is observed, over the entire length of the curve forming the etched surface of the first group III nitride semiconductor region, A step of forming a curve having no apex where the slope of the tangent of the curve changes discontinuously, and a second III containing an impurity of the second conductivity type on the etched surface of the first group III nitride semiconductor region A group semiconductor region is formed.

  According to the above manufacturing method, there is an apex at which the slope of the tangent line of the junction line changes discontinuously over the entire length of the junction line of the first group III nitride semiconductor region and the second group III nitride semiconductor region. A non-existing semiconductor device can be manufactured. A semiconductor device that can suppress the concentration of an electric field in the vicinity of the junction line between the first group III nitride semiconductor region and the second group III nitride semiconductor region can be manufactured. A semiconductor device with high breakdown voltage can be manufactured.

In the manufacturing method of the present invention, after the second protective film is removed, the second protective film is formed prior to etching both the first protective film and the first group III nitride semiconductor region. A third protective film can be formed on the surface of one protective film.
When the third protective film is not formed, the distance from the unetched surface of the first group III nitride semiconductor region to the bottom surface of the trench is determined by the thickness of the first protective film. By forming the third protective film on the surface of the first protective film on which the second protective film has been formed, the distance from the unetched surface of the first group III nitride semiconductor region to the bottom surface of the trench can be freely controlled. can do.

  According to the present invention, when a reverse bias is applied to a semiconductor device, the electric field concentration at the portion where the electric field is most likely to be concentrated can be reduced in the junction surface of the semiconductor region of the different conductivity type. As a result, the breakdown voltage of the semiconductor device can be increased.

The main features of the examples are listed.
(First embodiment)
A trench is formed on the surface of the n ⁻ type group III nitride semiconductor region. The trench is filled with a p-type group III nitride semiconductor region.
(Second Embodiment)
An impurity diffusion preventing film 20 is formed on a predetermined portion of the surface of the p-type group III nitride semiconductor region 14.
(Third embodiment)
A termination area A2 that makes a round of the cell area A1 is formed. In the termination area A2, trenches 8 and 4 are formed on the surface of the n ⁻ type group III nitride semiconductor region. A p-type group III nitride semiconductor region 110Y is formed at the bottom of the trench 8, and a p ⁺ -type group III nitride semiconductor region 110X is formed on the surface of the group III nitride semiconductor region 110Y. A p-type group III nitride semiconductor region 106Y is formed at the bottom of the trench 4, and a p ⁺ -type group III nitride semiconductor region 106X is formed on the surface of the group III nitride semiconductor region 106Y.
(Fourth embodiment)
A termination area A2 that makes a round of the cell area A1 is formed. In the termination area A2, trenches 8 and 4 are formed on the surface of the n ⁻ type III group. A p ⁺ -type group III nitride semiconductor region 210X is formed on the cell area A1 side in the trench 8 and a p-type group III nitride semiconductor region 210Y is formed on the side opposite to the cell area A1 in the trench 8. Has been. A p ⁺ -type group III nitride semiconductor region 206X is formed on the cell area A1 side in the trench 4, and a p-type group III nitride semiconductor region 206Y is formed on the side opposite to the cell area A1 in the trench 4. Has been.

Embodiments will be described in detail below with reference to the drawings. In the embodiment, a semiconductor device in which a trench is formed on the surface of an n ⁻ type group III nitride semiconductor region and the trench is filled with a p type group III nitride semiconductor region will be described. In the group III nitride semiconductor, the mobility of electrons in the semiconductor region is several hundred to several thousand times larger than the mobility of holes in the semiconductor region. In other words, the semiconductor device can be operated at high speed by using carriers of the semiconductor device as electrons.
(First embodiment)
FIG. 1 schematically shows a cross section of a vertical group III nitride semiconductor device 1 having a heterojunction. FIG. 1 shows a cell area A1 and a termination area A2 of the semiconductor device 1. Arrows in the figure indicate coordinates. Hereinafter, the + Z direction may be referred to as the front surface side, and the −Z direction may be referred to as the back surface side. In the semiconductor device 1, the cell area A <b> 1 is actually repeatedly formed in the −X direction, and the termination area A <b> 2 is also formed at the end of the semiconductor device 1 in the −X direction. Although FIG. 1 is a cross-sectional view, some hatching is omitted for easy viewing of the drawing.
First, the cell area A1 of the semiconductor device 1 will be described.
A drain electrode 34 in which titanium (Ti) and aluminum (Al) are stacked is formed on the back surface of the semiconductor device 1. The drain electrode 34 is connected to the drain terminal D. On the surface of the drain electrode 34, an n ⁺ -type group III nitride semiconductor region 32 containing gallium nitride (GaN) as a main material is formed. The impurity concentration of the group III nitride semiconductor region 32 is adjusted to approximately 3 × 10 ¹⁸ cm ⁻³ .
An n ⁻ -type group III nitride semiconductor region (first group III nitride semiconductor region) 30 mainly composed of gallium nitride is formed on the surface of the group III nitride semiconductor region 32. The impurity concentration of group III nitride semiconductor region 30 is adjusted to approximately 1 × 10 ¹⁶ cm ⁻³ .

A pair of trenches 12 is formed on the surface side of the n ⁻ -type group III nitride semiconductor region 30. The trench 12 extends in the direction perpendicular to the paper surface. The trench 12 is filled with a p ⁺ -type group III nitride semiconductor region (second group III nitride semiconductor region) 14 mainly composed of gallium nitride. The n ⁻ type group III nitride semiconductor region 30 and the p ⁺ type group III nitride semiconductor region 14 are directly joined. The impurity concentration of the group III nitride semiconductor region 14 is adjusted to approximately 5 × 10 ¹⁸ cm ⁻³ . The pair of group III nitride semiconductor regions 14 are separated by a group III nitride semiconductor region 30. When viewed in plan, the group III nitride semiconductor region 14 extends long in the direction perpendicular to the paper surface of FIG. That is, a plurality of group III nitride semiconductor regions 14 are formed in a stripe shape.
FIG. 1 shows a cross section of the trench 12, and a bonding line 12 c that forms the side surfaces of the pair of trenches 12 extends in the ± Z direction of the semiconductor device 1. A joining line 12 a that forms the bottom surface of the trench 12 extends in the ± X direction of the semiconductor device 1. Junction line 12 b at the corner portion connecting the side surface and the bottom surface is a curve that is convex toward group III nitride semiconductor region 30. The slope of the tangent line of the joint line 12a is zero. The inclination of the tangent line of the joining line 12c is infinite. In the joint line 12b, the slope of the tangent line continuously changes between 0 and infinity, and there are no vertices that change discontinuously.

An impurity diffusion preventing film 20 mainly made of aluminum nitride (AlN) is formed on the inner part of the surface of the pair of group III nitride semiconductor regions 14. The impurity diffusion preventing film 20 is not formed at a portion where the source electrode 16 described later is in electrical contact with the group III nitride semiconductor region 14. The impurity diffusion preventing film 20 is made of a group III nitride semiconductor, silicon nitride (SiN), silicon oxide (SiO ₂ ), a composite film of silicon nitride and silicon oxide, etc. containing aluminum as a part of the composition instead of aluminum nitride. It can also be used. That is, the impurity diffusion preventing film 20 may be any material that does not diffuse the impurities contained in the group III nitride semiconductor region 14 into the group III nitride semiconductor region 28 described later.
On the surface of the group III nitride semiconductor region 30, an n ⁻ type group III nitride semiconductor region 28 (third group III nitride semiconductor region) mainly composed of gallium nitride is formed in a range extending over the pair of trenches 12, 12. ) Is formed. The group III nitride semiconductor region 28 is formed on the surfaces of the group III nitride semiconductor region 30 and the impurity diffusion prevention film 20. Silicon is used as an impurity in the III nitride semiconductor region 28. The impurity concentration of the III nitride semiconductor region 28 is adjusted to approximately 1 × 10 ¹⁶ cm ⁻³ .
An n ⁻ type group III nitride mainly composed of gallium aluminum nitride (Al _0.3 Ga _0.7 N) in a range extending from the pair of trenches 12 and 12 on the surface of the group III nitride semiconductor region 28. A semiconductor region 26 (fourth group III nitride semiconductor region) is formed. The impurity concentration of the group III nitride semiconductor region 26 is adjusted to approximately 1 × 10 ¹⁶ cm ⁻³ . The crystal structure forming the group III nitride semiconductor region 26 contains aluminum. The band gap of the group III nitride semiconductor region 26 is wider than the band gap of the group III nitride semiconductor region 28. That is, a heterojunction is formed between the group III nitride semiconductor region 28 and the group III nitride semiconductor region 26. The group III nitride semiconductor region 26 may be an i-type group III nitride semiconductor. It is sufficient that the band gap of the group III nitride semiconductor region 26 is wider than the band gap of the group III nitride semiconductor region 28.

Above the pair of trenches 12, 12, a pair of n ⁺ -type source regions 18, 18 connected to the group III nitride semiconductor region 28 and the group III nitride semiconductor region 26 are formed. The impurity concentration of the source region 18 is adjusted to approximately 3 × 10 ¹⁸ cm ⁻³ . On the surface of the source region 18 and the group III nitride semiconductor region 14, a source electrode 16 (a low resistance region on the surface side) in which titanium and aluminum are laminated is formed. The source electrode 16 is electrically connected to the group III nitride semiconductor region 14 and the source region 18. The source region 18 is electrically connected to the group III semiconductor region 26 and the group III nitride semiconductor region 28. That is, the source electrode 16 is electrically connected to the group III nitride semiconductor region 28, the group III nitride semiconductor region 26, and the group III nitride semiconductor region 14. When the semiconductor device 1 is viewed in plan, the source region 18 is not formed in a range where the group III nitride semiconductor region 30 and the group III nitride semiconductor region 28 are in contact with each other.
A gate insulating film 24 mainly composed of silicon oxide is formed on the surface of the group III nitride semiconductor region 26. The gate insulating film 24 is formed extending to part of the surface of the source regions 18 and 18.
On the surface of the gate insulating film 24, a gate electrode 22 containing nickel (Ni) as a main material is formed. The gate electrode 22 is formed so as to overlap with the inner end portion between the source regions 18 and 18 and is not in contact with the source electrode 16.

Next, the termination area A2 of the semiconductor device 1 will be described. The description of the same configuration as the cell area A1 is omitted.
Trenches 8 and 4 are formed on the surface side of group III nitride semiconductor region 30. The trenches 8 and 4 make a round around the cell area A1. The trench 8 is filled with a p ⁺ -type group III nitride semiconductor region (second group III nitride semiconductor region) 10 mainly composed of gallium nitride. The trench 4 is filled with a p ⁺ -type group III nitride semiconductor region (second group III nitride semiconductor region) 6 mainly composed of gallium nitride. The impurity concentration of group III nitride semiconductor regions 10 and 6 is adjusted to approximately 5 × 10 ¹⁸ cm ⁻³ . When the group III nitride semiconductor regions 10 and 6 are viewed in plan, the group III nitride semiconductor region 10 makes a round of the cell area A1. The group III nitride semiconductor region 6 makes a round of the group III nitride semiconductor region 10. By forming the group III nitride semiconductor regions 10 and 6, the depletion layer can be extended to the outside of the group III nitride semiconductors 10 and 6 when a reverse bias is applied to the semiconductor device 1. Concentration of the electric field on the junction line 12 between the group III nitride semiconductor 30 and the group III nitride semiconductor region 14 can be suppressed. Hereinafter, the group III nitride semiconductor regions 10 and 6 may be referred to as termination guard rings 10 and 6.

The joint line 8 c that forms the side surface of the trench 8 extends in the ± Z direction of the semiconductor device 1. A joint line 8 a that forms the bottom surface of the trench 8 extends in the ± X direction of the semiconductor device 1. The joint line 8 b at the corner portion connecting the side surface and the bottom surface is a curve that is convex toward the group III nitride semiconductor region 30. The inclination of the tangent line of the joint line 8a is zero. The inclination of the tangent line of the joint line 8c is infinite. In the joint line 8b, the slope of the tangent line continuously changes between 0 and infinity, and there are no vertices that change discontinuously.
The joint line 4 c that forms the side surface of the trench 4 extends in the ± Z direction of the semiconductor device 1. The joint line 4 a that forms the bottom surface of the trench 4 extends in the ± X direction of the semiconductor device 1. The joint line 4 b at the corner connecting the side surface and the bottom surface is a curved line that protrudes toward the group III nitride semiconductor region 30. The inclination of the tangent line of the joint line 4a is zero. The inclination of the tangent line of the joint line 4c is infinite. In the joint line 4b, the slope of the tangent line continuously changes between 0 and infinity, and there are no vertices that change discontinuously.
An insulating film 2 mainly composed of silicon oxide is formed on the surfaces of the group III nitride semiconductor region 30 and the termination guard rings 10 and 6.

The operation of the semiconductor device 1 will be described.
The p ⁺ type group III nitride semiconductor region 14 is opposed to the n type group III nitride semiconductor region 28 with the impurity diffusion prevention film 20 interposed therebetween. In a state where no voltage is applied to the gate electrode 22, a depletion layer is formed from the group III nitride semiconductor region 14 to the group III nitride semiconductor region 28. The depletion layer extends to the + Z side from the heterojunction surface of the group III nitride semiconductor region 28 and the group III nitride semiconductor region 26. When the heterojunction surface is depleted, the energy level of the conduction band of the heterojunction surface exists above the Fermi level. There cannot be a two-dimensional electron gas layer at the heterojunction surface. In a state where no voltage is applied to the gate electrode 22, electrons cannot travel on the heterojunction surface. The semiconductor device 1 is off. That is, the semiconductor device 1 performs a normally-off operation.

When the semiconductor device 1 is off, a bias charge is applied between the source electrode 16 and the drain electrode 34. A depletion layer is formed between group III nitride semiconductor region 14 and group III nitride semiconductor region 30. The electric field applied to the bonding line 12 is strongest in the vicinity of the portion where the bonding line 12a and the bonding line 12c intersect. In the semiconductor device 1, a bonding line 12 b that protrudes toward the group III nitride semiconductor region 30 exists at a corner portion where the bonding line 12 a and the bonding line 12 c intersect. The joining line 12b has a tangential slope that continuously changes, has a smooth overall shape, and does not have an angular apex. For this reason, it can prevent that an electric field concentrates locally. The breakdown voltage of a semiconductor device is determined by the breakdown voltage of the lowest breakdown voltage in the semiconductor device. That is, it is determined by the breakdown voltage of the portion where the electric field is highest when the semiconductor device is turned off. When the semiconductor device is turned off, the semiconductor device 1 can reduce the electric field applied to the portion where the electric field is normally high when the semiconductor device is turned off.
Similarly, there is a joining line 8b that extends smoothly between the joining line 8a and the joining line 8c. The electric field applied to the portion where the junction line 8a and the junction line 8c intersect can be reduced. A joining line 4b exists between the joining line 4a and the joining line 4c. Similarly, the electric field applied to the portion where the joining line 4a and the joining line 4c intersect can be reduced.

When a positive voltage is applied to the gate electrode, the depletion layer extending from the p ⁺ type group III nitride semiconductor region 14 to the group III nitride semiconductor region 26 disappears. A two-dimensional electron gas layer is formed at the junction line between the group III nitride semiconductor region 28 and the group III nitride semiconductor region 26. The energy level of the conduction band of the two-dimensional electron gas layer exists below the femil level. A two-dimensional electron gas layer exists in the potential well of the heterojunction plane. When a voltage is applied to the gate electrode 22, electrons can travel through the two-dimensional electron gas layer. That is, the semiconductor device 1 is turned on.
In a state where the semiconductor device 1 is turned on, electrons flow along the two-dimensional electron gas layer formed from the source region 18 to the heterojunction surface of the group III nitride semiconductor region 28 and the group III nitride semiconductor region 26. Run. When the electrons reach the region in which the group III nitride semiconductor region 30 is convex in the + Z direction (the region sandwiched between the pair of group III nitride semiconductor regions 14, 14), the electrons pass through the semiconductor device 1. -Flows in the Z direction. That is, electrons flow to the drain electrode 34 via the group III nitride semiconductor region 30 and the group III nitride semiconductor region 32. The source electrode 16 and the drain electrode 34 are electrically connected.

A method for manufacturing the semiconductor device 1 will be described with reference to FIGS. Note that the configuration of each part does not accurately represent the actual size scale. For ease of understanding, the scale of the drawing is changed as appropriate.
First, as shown in FIG. 2, a group III nitride semiconductor substrate 32 made mainly of n ⁺ -type gallium nitride is prepared. Group III nitride semiconductor substrate 32 has a thickness of about 200 μm.
Next, as shown in FIG. 3, an n ⁻ type group III nitride semiconductor region 30 is grown on the group III nitride semiconductor substrate 32 using MOCVD (Metal Organic Chemical Vapor Deposition). Group III nitride semiconductor region 30 has a thickness of 6 μm. Next, a protective film (first protective film) 36 containing SiO ₂ as a main material is formed on the surface of the group III nitride semiconductor region 30. Thereafter, a resist film (second protective film) 38 is formed in a predetermined region on the surface of the protective film 36. In the semiconductor device 1 shown in FIG. 1, the resist film 38 is formed so as to correspond to the range in which the group III nitride semiconductor region 30 protrudes in the + Z direction.

Next, as shown in FIG. 4, the protective film 36 is isotropically etched. In order to etch the protective film 36 isotropically, a method of etching only the protective film 36 without etching the resist film 38 and the group III nitride semiconductor region 30 is employed. For example, a wet etching method using hydrofluoric acid (HF) or the like can be used. A curved portion 36 a is formed in the protective film 36 by isotropically etching the protective film 36.
Next, as shown in FIG. 5, after removing the resist film 38, a protective film 40 containing SiO ₂ as a main material is formed. The protective film 40 is formed on the surface of the group III nitride semiconductor region 30 and the protective film 36 (see FIG. 4). That is, the protective film 40 is formed in a state having the curved portion 40 a on the surface of the group III nitride semiconductor region 30 while maintaining the shape of the curved portion 36 a of the protective film 36 described above. Thereafter, a resist film (third protective film) 42 is formed on the flat portion 40b of the protective film 40 located on the + Z side with respect to the curved portion 40a.

  Next, as shown in FIG. 6, the resist film 42 and the protective film 40 are anisotropically etched from both surfaces. In order to perform anisotropic etching, for example, dry etching such as RIE (Reactive Ion Etching) can be used. By adjusting the thickness of the resist film 42, the lengths of the bonding lines 12c, 8c, 4c (see FIG. 1) can be adjusted.

  Next, as shown in FIGS. 7A and 7B, the protective film 40 and the group III nitride semiconductor region 30 are anisotropically etched from the surface side of both. As shown in FIG. 7 (a), until the curvature portion 40a is etched and disappears, the curvature portion 40a is more than the portion of the group III nitride semiconductor region 30 covered by the curvature portion 40a. More portions of the group III nitride semiconductor region 30 that are not covered are etched. This phenomenon is caused by the difference in etching rate between gallium nitride and silicon oxide. For example, when an ICP (Inductively Coupled Plasma) apparatus is used, gallium nitride is etched at 0.15 μm / min, whereas silicon oxide is etched at 0.05 μm / min. That is, silicon oxide is etched at a slower rate than gallium nitride. Therefore, as shown in FIG. 7B, the radius of curvature of the curved portion 12 b formed in the group III nitride semiconductor region 30 is larger than the radius of curvature of the curved portion 40 a formed in the protective film 40.

The steps described in FIGS. 5 and 6 are not necessarily essential. In FIG. 1, the p ⁺ type III group semiconductor regions 14, 10, 6 can be appropriately employed depending on the depth in the −Z direction. 5 and FIG. 6, when the resist film 38 shown in FIG. 4 is removed, the group III nitride semiconductor region 30 and the protective film 36 are anisotropically etched from the surface side of both. do it. In that case, the joining lines 12c, 8c, and 4c in FIG. 1 are not formed. Horizontal joint lines 12 a, 8 a, 4 a and a joint line in which a curve that curves continuously outward from the lines intersects the surface of group III nitride semiconductor region 30 are formed.

Next, as shown in FIG. 8, using the MOCVD method, a p-type III is formed from the exposed surface of the group III nitride semiconductor region 30 to the unetched surface of the group III nitride semiconductor region 30. Group nitride semiconductor regions 14 and 10.6 are grown. Next, an impurity diffusion preventing film 20 containing AlN as a main material is formed on the surface of the group III nitride semiconductor region 14.
Next, as shown in FIG. 9, after the protective film 40 is removed, the surface of the group III nitride semiconductor region 30 and the group III nitride semiconductor region 10.6 in the termination area A2 (see FIG. 1) is oxidized. A protective film 42 of silicon is formed. Thereafter, gallium nitride 28 is grown on the exposed surface of the group III nitride semiconductor region 30 and the surface of the impurity diffusion preventing film 20. The amount of impurities in the gallium nitride region 28 for crystal growth is adjusted to the same amount as that of the group III nitride semiconductor region 30. That is, the crystal-grown gallium nitride region 28 and the group III nitride semiconductor region 30 can be evaluated as one continuous region. The thickness of the gallium nitride 28 formed on the surface of the group III nitride semiconductor region 30 is about 100 nm. Next, the group III nitride semiconductor region 26 is crystal-grown on the surface of the group III nitride semiconductor region 28. The thickness of the group III nitride semiconductor region 26 is 50 nm. Here, a heterojunction is formed between the group III nitride semiconductor region 28 and the group III nitride semiconductor region 26.

Next, as shown in FIG. 10, a protective film 44 of silicon oxide is formed on the surface of the group III nitride semiconductor region 26 using the CVD method. After the protective film 44 is formed on the entire surface of the group III nitride semiconductor region 26, a portion (see FIG. 1) where the source region 18 and the source electrode 16 are formed is removed by using a lithography technique and an etching technique. Is done. Thereafter, ion implantation is performed to form the source region 18. Ion implantation dose of nitrogen 1 × ¹⁰ 15 ^{cm -2,} was implanted at an acceleration voltage 35 eV and a dose of the silicon 1 × ¹⁰ 15 ^{cm -2,} it is implanted at an acceleration voltage of 65 eV. The arrows in FIG. 10 indicate the range where ion implantation is performed. Here, before the silicon is ion-implanted, nitrogen is ion-implanted, whereby the number of electrons in the source region 18 is increased and the resistance of the source region 18 is reduced. Next, after removing the protective film 44, a protective film 46 of silicon oxide (see also FIG. 11) is formed on the surfaces of the source region 18 and the group III nitride semiconductor region 26, and the temperature is increased at 1300 ° C. in a nitrogen atmosphere. Anneal for minutes. By annealing, the ion-implanted impurity (silicon) is activated.

Next, as shown in FIG. 11, the protective film 46, the source region 18, and the impurity diffusion prevention film 20 in the portion where the source electrode 16 is formed (see FIG. 1) are etched to form the group III nitride semiconductor region 14. Expose. Etching is performed using an RIE apparatus.
Next, as shown in FIG. 1, after the protective film 46 and the protective film 42 are removed, the gate insulating film 24 and the insulating film 2 are formed. The thickness of the gate insulating film 24 is adjusted to 50 nm. The thickness of the protective film 2 is also adjusted to 50 nm. Next, titanium 10 nm and aluminum 100 nm are deposited to form the source electrode 16 on the surface of the source region 18 and the surface of the group III nitride semiconductor region 14. Next, 10 nm of titanium and 100 nm of aluminum are deposited to form the drain electrode 34 on the back surface of the group III nitride semiconductor region 32.
Next, annealing is performed at 500 ° C. for 2 minutes in a nitrogen atmosphere. The contact resistance between the source electrode, the source region 18 and the group III nitride semiconductor region 14 can be lowered by annealing. Similarly, the contact resistance between the drain electrode 34 and the group III nitride semiconductor region 32 can be lowered. Through the above steps, the semiconductor device 1 shown in FIG. 1 can be obtained.

  In the semiconductor device 1 according to the first embodiment, in order to connect the side surface and the bottom surface of the trench 12, a curved joint line 12 b convex to the −Z side is formed on both sides (+ X side and −X side) of the trench 12. . However, the bonding line 12b may be formed on one side (+ X side or −X side) of the side surface of the trench 12, and the other side surface and the bottom surface may be orthogonal to each other. This phenomenon is the same for the trenches 8 and 4. In particular, in the case of the trenches 8 and 4 in the termination area, it is preferable that the joint lines 8b and 4b are formed outside. Further, the junction line 12 b is formed in the trench 12, and the junction lines 8 b and 4 b may not be formed in the trenches 8 and 4. In this case, the joining line 8a and the joining line 8c intersect at right angles. In the semiconductor device 1, it suffices if a curved junction line is formed in any of the trenches 12, 8, 4 toward the group III nitride semiconductor region 30.

(Second embodiment)
With reference to FIG. 12, the semiconductor device 101 of the present embodiment will be described. The semiconductor device 101 is a modification of the semiconductor device 1. Components substantially similar to those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
In the semiconductor device 101, group III nitride semiconductor regions 114, 110, and 106 containing p-type impurities are formed on the surface side of the n ⁻ type group III nitride semiconductor region 30. In the group III nitride semiconductor region 114, a group III semiconductor region 114X containing a p-type impurity deeply and a group III nitride semiconductor region 114Y containing a p-type impurity thinner than the group III nitride semiconductor region 114X are formed. Yes. In the group III nitride semiconductor region 110, a group III semiconductor region 110X containing a p-type impurity deeply and a group III nitride semiconductor region 110Y containing a p-type impurity thinner than the group III nitride semiconductor region 110X are formed. Yes. In the group III nitride semiconductor region 106, a group III semiconductor region 106X containing a p-type impurity deeply and a group III nitride semiconductor region 106Y containing a p-type impurity thinner than the group III nitride semiconductor region 106X are formed. Yes.
When a bias is applied to the semiconductor device, the electric field tends to concentrate at the corner where the side surface and the bottom surface of the trench intersect. Further, when the p-type group III nitride semiconductor region and the n-type group III nitride semiconductor region are directly joined, the electric field is more concentrated when the impurity concentration of the p-type group III nitride semiconductor region is high. easy. In the semiconductor device 101 of this embodiment, the group III nitride semiconductor regions 114, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110 are portions of the group III nitride semiconductor regions 114, 110, The impurity concentration of 106 is lowered. That is, in the junction line where the group III nitride semiconductor region 30 and the group III nitride semiconductor regions 114, 110, and 106 are joined, the electric field concentration at the portion where the inclination of the tangent of the junction line greatly changes is more effectively mitigated. be able to.

A method for manufacturing the semiconductor device 101 will be described.
The steps from FIG. 1 to FIG. 7B are the same as those of the semiconductor device 1, and thus the description thereof is omitted. Next, the group III nitride semiconductor regions 114Y, 110Y and 106Y are grown from the surface of the group III nitride semiconductor region 30 to a predetermined height. The impurity concentration of group III nitride semiconductor regions 114Y, 110Y, and 106Y is adjusted to 1 × 10 ¹⁸ cm ⁻³ . Next, the nitride semiconductor regions 114X, 110X, and 106X are crystal-grown from the surface of the group III nitride semiconductor regions 114Y, 110Y, and 106Y. The impurity concentration of the group III nitride semiconductor regions 114X, 110X, and 106X is adjusted to 5 × 10 ¹⁸ cm ⁻³ . The subsequent steps can be manufactured in the same manner as in Example 1.

(Third embodiment)
With reference to FIG. 13, the semiconductor device 201 of the present embodiment will be described. The semiconductor device 201 is a modification of the semiconductor device 1. Components substantially similar to those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
In the semiconductor device 201, group III nitride semiconductor regions 210 and 206 containing p-type impurities are formed on the surface side of the n ⁻ type group III nitride semiconductor region 30 in the termination area A2. In the group III nitride semiconductor region 210, a group III nitride semiconductor region 210X containing a p-type impurity deeply and a group III nitride semiconductor region 210Y containing a p-type impurity thinner than the group III nitride semiconductor region 210X are formed. Has been. Group III nitride semiconductor region 210 </ b> X forms the inside of group III nitride semiconductor region 210. Group III nitride semiconductor region 210 </ b> Y forms the outside of group III nitride semiconductor region 210. In the group III nitride semiconductor region 206, a group III nitride semiconductor region 206X containing a p-type impurity deeply and a group III nitride semiconductor region 206Y containing a p-type impurity thinner than the group III nitride semiconductor region 206X are formed. Has been. Group III nitride semiconductor region 206 </ b> X forms the inside of group III nitride semiconductor region 206. Group III nitride semiconductor region 206 </ b> Y forms the outside of group III nitride semiconductor region 206.
When a bias is applied to the semiconductor device, the electric field tends to concentrate on the side surface outside the semiconductor device (on the opposite side to the cell area A1) among the side surfaces of the trench. In the semiconductor device 201 of this example, the impurity concentration of the group III nitride semiconductor regions 210 and 206 in the portion where the electric field is likely to concentrate at the junction line between the group III nitride semiconductor region 30 and the group III nitride semiconductor regions 210 and 206. Is low. In other words, in the junction line where the group III nitride semiconductor region 30 and the group III nitride semiconductor regions 210 and 206 are joined, the electric field concentration at the portion where the inclination of the tangent of the junction line outside the semiconductor device greatly changes is more effectively achieved. Can be relaxed.

A method for manufacturing the semiconductor device 201 will be described.
The steps from FIG. 1 to FIG. Thereafter, the same method as in FIGS. 3 to 7B, that is, a first protective film is formed, and a second protective film is formed on the surface thereof. After the first protective film and the second protective film are isotropically etched and the second protective film is removed, the first protective film and the outer portions of the semiconductor regions 10 and 6 are anisotropically etched. The group III nitride semiconductor regions 10 and 6 that are not etched are the group III nitride semiconductor regions 210X and 210Y of FIG. Thereafter, group III nitride semiconductor regions 210Y and 206Y are crystal-grown from the exposed surface of group III nitride semiconductor region 30. The impurity concentration of group III nitride semiconductor regions 210X and 206Y is adjusted to 1 × 10 ¹⁸ cm ⁻³ .

(Fourth embodiment)
With reference to FIG. 14, the semiconductor device 401 of the present embodiment will be described. The semiconductor device 401 is not a semiconductor device having a heterojunction like the semiconductor devices 1, 101, 201, and 301. The semiconductor device 401 is a diode in which different conductivity type group III nitride semiconductors are in contact with each other. First, the cell area A1 of the semiconductor device 401 will be described.
A cathode electrode 434 in which titanium (Ti) and aluminum (Al) are stacked is formed on the back surface of the semiconductor device 401. On the surface of the cathode electrode 434, an n ⁺ -type group III nitride semiconductor region 432 mainly composed of gallium nitride (GaN) is formed. An n ⁻ -type group III nitride semiconductor region (first group III nitride semiconductor region) 430 made mainly of gallium nitride is formed on the surface of group III nitride semiconductor region 432.
A trench 412 is formed on the surface side of the group III nitride semiconductor region 430. The trench 412 extends in the direction perpendicular to the paper surface. The trench 412 is filled with a p-type group III nitride semiconductor region (second group III nitride semiconductor region) 414 made mainly of gallium nitride. A bonding line 412 c that forms the side surface of the trench 412 extends in the ± Z direction of the semiconductor device 401. A bonding line 412 a that forms the bottom surface of the trench 412 extends in the ± X direction of the semiconductor device 401. The joint line 412b at the corner portion connecting the side surface and the bottom surface is a curve that is convex toward the group III nitride semiconductor region 430. The slope of the tangent line of the joint line 412a is zero. The inclination of the tangent line of the joining line 412c is infinite. In the joint line 412b, the slope of the tangent line continuously changes between 0 and infinity, and there are no vertices that change discontinuously.
In the group III nitride semiconductor region 414, a group III semiconductor region 414X containing a p-type impurity deeply and a group III nitride semiconductor region 414Y containing a p-type impurity thinner than the group III nitride semiconductor region 414X are formed. Yes.
An insulating film 402 is formed on part of the surface of group III nitride semiconductor region 414. An anode electrode 416 is connected to a portion of the surface of group III nitride semiconductor region 414 where insulating film 402 is not formed. Although the anode electrode 416 is also formed above the group III nitride semiconductor region 430, the anode electrode 416 and the group III nitride semiconductor region 430 are electrically separated by the insulating film 402. The anode electrode 416 is formed by stacking nickel (Ni) and gold (Au).

Next, the termination area A2 will be described. The description of the same configuration as the cell area A1 is omitted.
Trenches 408 and 404 are formed on the surface side of group III nitride semiconductor region 430. The trenches 408 and 404 go around the cell area. A joint line 408 c that forms the side surface of the trench 408 extends in the ± Z direction of the semiconductor device 401. A joint line 408 a that forms the bottom surface of the trench 408 extends in the ± X direction of the semiconductor device 401. The joint line 408b at the corner portion connecting the side surface and the bottom surface is a curve that protrudes toward the group III nitride semiconductor region 430. The slope of the tangent line of the joint line 408a is zero. The slope of the tangent line of the joint line 408c is infinite. In the joint line 408b, the slope of the tangent line continuously changes between 0 and infinity, and there are no vertices that change discontinuously. A bonding line 404 c that forms the side surface of the trench 404 extends in the ± Z direction of the semiconductor device 401. A bonding line 404 a that forms the bottom surface of the trench 404 extends in the ± X direction of the semiconductor device 401. Junction line 404b at the corner portion connecting the side surface and the bottom surface is a convex curve toward group III nitride semiconductor region 430. The slope of the tangent line of the joint line 404a is zero. The inclination of the tangent line of the joining line 404c is infinite. In the joint line 404b, the slope of the tangent line continuously changes between 0 and infinity, and there are no vertices that change discontinuously.
The trench 408 is filled with a p-type group III nitride semiconductor region (second group III nitride semiconductor region) 410 made mainly of gallium nitride. In group III nitride semiconductor region 410, group III semiconductor region 410X containing p-type impurities deeply and group III nitride semiconductor region 410Y containing p-type impurities thinner than group III nitride semiconductor region 410X are formed. Yes. The trench 404 is filled with a p-type group III nitride semiconductor region (second group III nitride semiconductor region) 406 mainly composed of gallium nitride. In group III nitride semiconductor region 406, group III semiconductor region 406X containing p-type impurities is formed, and group III nitride semiconductor region 410Y containing p-type impurities thinner than group III nitride semiconductor region 406X is formed. Yes.
In the semiconductor device 401 of this embodiment, there is a joining line 412b that extends smoothly between the joining line 412a and the joining line 412c. The electric field applied to the portion where the joining line 412a and the joining line 412c intersect can be reduced. Similarly, the electric field applied to the portion where the joining line 408a and the joining line 408c intersect can be reduced. The electric field applied to the portion where the joining line 404a and the joining line 404c intersect can also be reduced.
In the semiconductor device 401 of this embodiment, the impurity concentration of the group III nitride semiconductor regions 414, 410, and 406 where the electric field tends to concentrate is further reduced. That is, in the junction line where the group III nitride semiconductor region 430 and the group III nitride semiconductor regions 414, 410, and 406 are joined, the electric field concentration at the portion where the inclination of the tangent of the junction line greatly changes is more effectively mitigated. be able to.

Specific examples of the present invention have been described above in detail, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
In the above embodiment, two termination guard rings are formed in the termination area. However, the number of termination guard rings is not limited to two. One end guard ring may be provided, or three or more end guard rings may be formed. Moreover, the termination guard ring may not be formed.
In the fourth embodiment, the group III nitride semiconductor region containing p-type impurities is formed on the surface side of the trench formed in the n-type group III nitride semiconductor region, and is formed on the bottom side of the trench. A group III nitride semiconductor region containing a thin p-type impurity is formed. However, as shown in the third embodiment, a group III nitride semiconductor region containing a high concentration of p-type impurities is formed on the cell area side, and a group III nitride containing a thin p-type impurity on the side opposite to the cell area. A physical semiconductor region may be formed.
Further, the technical elements described in the present specification or drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in the present specification or the drawings can achieve a plurality of objects at the same time, and has technical utility by achieving one of the objects.

Sectional drawing of the semiconductor device of 1st Example is shown. The manufacturing process of the semiconductor device of 1st Example is shown. The manufacturing process of the semiconductor device of 1st Example is shown. The manufacturing process of the semiconductor device of 1st Example is shown. The manufacturing process of the semiconductor device of 1st Example is shown. The manufacturing process of the semiconductor device of 1st Example is shown. The manufacturing process of the semiconductor device of 1st Example is shown. The manufacturing process of the semiconductor device of 1st Example is shown. The manufacturing process of the semiconductor device of 1st Example is shown. The manufacturing process of the semiconductor device of 1st Example is shown. The manufacturing process of the semiconductor device of 1st Example is shown. Sectional drawing of the semiconductor device of 2nd Example is shown. Sectional drawing of the semiconductor device of 3rd Example is shown. Sectional drawing of the semiconductor device of 4th Example is shown.

Explanation of symbols

4, 8, 12: Trench 6, 10, 106, 110, 206, 210: Termination guard ring (second group III nitride semiconductor region)
14,114: p ⁺ type group III nitride semiconductor region (second group III nitride semiconductor region)
16: Source electrode 18: Source region 20: Impurity diffusion preventing film 22: Gate electrode 24: Gate insulating film 30: n ⁻ type group III nitride semiconductor region (first group III nitride semiconductor region)
34: Drain electrode

Claims (8)

A first group III nitride semiconductor region having a trench formed on the surface and containing a first conductivity type impurity;
A second group III nitride semiconductor region filling the trench and containing an impurity of a second conductivity type;
An apex at which the inclination of the tangent line of the junction line changes discontinuously over the entire length of the junction line of the first group III nitride semiconductor region and the second group III nitride semiconductor region exposed in the cross section of the trench. There is no semiconductor device. At least one pair of trenches is formed in the surface of the first group III nitride semiconductor region;
The second group III nitride semiconductor region fills both of the pair of trenches,
The joint line forming the inner side surface of the pair of trenches extends in a direction perpendicular to the surface of the semiconductor substrate,
The joint line forming the bottom surface of the pair of trenches extends parallel to the surface of the semiconductor substrate,
2. The semiconductor device according to claim 1, wherein the bonding line connecting the side surface and the bottom surface is a curved line projecting toward the first group III nitride semiconductor region. At least one pair of trenches is formed in the surface of the first group III nitride semiconductor region;
The second group III nitride semiconductor region fills both of the pair of trenches,
The joint line forming the outer side surface of the pair of trenches extends in a direction perpendicular to the surface of the semiconductor substrate;
The joint line forming the bottom surface of the pair of trenches extends parallel to the surface of the semiconductor substrate,
2. The semiconductor device according to claim 1, wherein the bonding line connecting the side surface and the bottom surface is a curved line projecting toward the first group III nitride semiconductor region. A third group III nitride semiconductor region stacked in a range extending over the pair of trenches on the surface of the first group III nitride semiconductor region;
A fourth group III nitride semiconductor region stacked in a range extending over the pair of trenches on the surface of the third group III nitride semiconductor region;
A pair of low resistance regions on the surface side formed above the pair of trenches and connected to the third group III nitride semiconductor region and the fourth group III nitride semiconductor region;
A low resistance region on the back side formed on the back side of the first group III nitride semiconductor region,
4. The semiconductor device according to claim 2, wherein the band gap of the fourth group III nitride semiconductor region is wider than the band gap of the third group III nitride semiconductor region.   5. A gate electrode stacked on an upper surface of a group III nitride semiconductor region located between a pair of low resistance regions on the surface side with an insulating layer interposed therebetween. Any of the semiconductor devices. The trench makes a round of the cell area,
2. The semiconductor device according to claim 1, wherein a termination guard ring is formed by the second group III nitride semiconductor region filling the trench that goes around the cell area. Forming a first protective film on the surface of the first group III nitride semiconductor region containing a first conductivity type impurity;
Forming a second protective film on a portion of the surface of the first protective film;
The position where the second protective film exists from the position where the second protective film does not exist by etching the first protective film isotropically without etching the first group III nitride semiconductor region and the second protective film. Of the first protective film in contact with the first group III nitride semiconductor region from the end of the first protective film in contact with the second protective film when a cross section along a straight line extending toward the surface is observed Forming a curve having no vertices where the slope of the tangent of the curve discontinuously changes over the entire length of the curve formed toward the part;
Removing the second protective film;
When the cross section along the straight line is observed by anisotropically etching both the first protective film and the first group III nitride semiconductor region from the surface side of both, the first group III Forming a curve having no vertices where the slope of the tangent of the curve discontinuously changes over the entire length of the curve forming the etched surface of the nitride semiconductor region;
A method of manufacturing a semiconductor device, comprising: forming a second group III semiconductor region containing a second conductivity type impurity on the etched surface of the first group III nitride semiconductor region.   After removing the second protective film, prior to etching both the first protective film and the first group III nitride semiconductor region, the second protective film is formed on the surface of the first protective film on which the second protective film has been formed. The method according to claim 7, wherein three protective films are formed.

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