JP2008159650A - Semiconductor device, and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To attain a semiconductor device provided with a split gate MONOS memory in which a control gate and a memory gate are not easily shorted in each memory cell even when the memory cell is divided into fine pieces. <P>SOLUTION: An electrically insulated part 18 is provided on the memory gate 15 of the split gate MONOS memory 40 forming the semiconductor device 50, covering an upper part in the side of the control gate 13 in the memory gate. Thereby, a distance between the upper surfaces of both control gate and memory gate can be set longer than that corresponding to a thickness of the ONO film 17 provided between the above two gates. Accordingly it is possible to prevent generation of a short-circuit between the control gate and memory gate that may be caused by residues of metal layer used to form each control gate and memory gate through formation of silicide of polysilicon layer. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device provided with a split gate type MONOS (Metal Oxide Nitride Oxide Silicon) memory and a method for manufacturing the semiconductor device.

  A MONOS memory, which is a non-volatile rewritable semiconductor memory that stores charges at discrete trap centers of a silicon nitride film, is widely used as a storage medium for digital devices such as digital cameras and portable music players. In recent years, with the increase in digital devices with short product cycles and digital devices that require a variety of products, there is a demand for microcomputers with built-in semiconductor memory (so-called “flash microcomputers”) that can be rewritten on-board. The MONOS memory has come to be used as a program storage memory of the flash microcomputer.

  The MONOS memory can be classified into several types according to its structure, but today, a split gate type is attracting attention because it is difficult to excessively erase stored data. FIG. 9 is a cross-sectional view schematically showing a memory cell in a split gate type conventional MONOS memory. In the memory cell 120 shown in the figure, a control gate 113 is disposed on a semiconductor substrate 110 on which a predetermined impurity diffusion region (not shown) is formed, with a gate insulating film 111 interposed therebetween. The memory gate 115 is disposed in the memory. An ONO film 117 extends in a region from between the control gate 113 and the memory gate 115 to between the memory gate 115 and the semiconductor substrate 110. Further, a sidewall spacer 119a is formed so as to be in contact with one side surface of the control gate 113 in the line width direction, and a sidewall spacer 119b is formed so as to be in contact with the outer surface of the memory gate 115 in the line width direction. ing.

  The control gate 113 includes a polysilicon region 113a formed on the gate insulating film 111 and a silicide region 113b formed by siliciding the polysilicon layer that is the source of the polysilicon region 113a from the upper surface side. And have. Similarly, the memory gate 115 is formed by siliciding a polysilicon region 115a located on the semiconductor substrate 110 via the ONO film 117 and a polysilicon layer that is a source of the polysilicon region 115a from the upper surface side. Silicided region 115b.

  The ONO film 117 is a laminated film having a three-layer structure formed by laminating an oxide film, a nitride film, and an oxide film in this order. As the oxide film, a silicon oxide film or a nitrided film is used. A silicon nitride film is often used as the material film. The ONO film 117 is formed so as to cover the entire one side surface in the line width direction of the control gate 113 and partially cover the upper surface of the semiconductor substrate 110. Therefore, the ONO film 117 has an L-shaped vertical sectional shape. A region of the ONO film 117 interposed between the control gate 113 and the memory gate 115 is used as an electrical insulating film that electrically separates the two gates, and is interposed between the memory gate 115 and the semiconductor substrate 110. The intervening area is used as an area for storing logical data.

  The split gate type MONOS memory having such a structure is always required to have a high storage density. Accordingly, the memory cells are being miniaturized and the electrical resistances of the control gate and the memory gate are reduced. Is planned. The electrical resistance of the control gate and the memory gate can be reduced by forming these gates from a single metal, but in general, the control gate and the memory are partially or entirely silicided by a polysilicon layer. This is achieved by forming each of the gates. Then, in the silicidation of the polysilicon layer, a desired metal layer such as cobalt (Co) or nickel (Ni) is formed so as to cover the polysilicon layer, and the metal layer and the polysilicon layer below the metal layer are formed. It is performed by reacting with each other by heating. The remaining metal layer that did not contribute to the reaction is removed in a later step.

  Today, the miniaturization of memory cells in the split gate type MONOS memory has progressed to the extent that the ONO film 117 shown in FIG. 9 has a thickness of about 20 nm. In other words, the miniaturization is progressing to the extent that the distance between the control gate and the memory gate in each memory cell is about 20 nm. For this reason, when a low electrical resistance control gate and memory gate are formed by siliciding the polysilicon layer, a short circuit occurs between the control gate and the memory gate due to the residue of the metal layer used in the silicidation reaction. It becomes easy to do.

  The present invention has been made in view of the above circumstances, and a semiconductor device including a split gate type MONOS memory in which a short circuit between a control gate and a memory gate in each memory cell hardly occurs even if the memory cell is miniaturized. The purpose is to obtain.

  Another object of the present invention is to obtain a method of manufacturing a semiconductor device having a split gate type MONOS memory in which a short circuit between a control gate and a memory gate in each memory cell does not easily occur even if the memory cell is miniaturized. And

  In one embodiment of the semiconductor device of the present invention, at least the upper part of each of the control gate and the memory gate constituting the memory cell in the split gate type MONOS memory is silicided, and the upper part on the control gate side in the memory gate is formed by an electric insulating part. Covered.

  In one embodiment of the method for manufacturing a semiconductor device of the present invention, in forming a split gate type MONOS memory, a first polysilicon layer that is a source of a control gate, a second polysilicon layer that is a source of a memory gate, And forming a NO film covering the upper portion of the second polysilicon layer on the first polysilicon layer side, and then siliciding each of the first polysilicon layer and the second polysilicon layer to form a control gate, a memory gate, Get.

  In the semiconductor device of the above aspect according to the present invention, the upper portion of the memory gate on the control gate side is covered with the electrical insulating portion, which corresponds to the thickness of the ONO film interposed between the control gate and the memory gate. The distance between the upper surfaces of the two gates is longer than the distance. Therefore, even if each of the control gate and the memory gate is formed by siliciding the desired polysilicon layer and the memory cell is miniaturized, the control is caused by the residue of the metal layer used in the silicidation described above. It is unlikely that the gate and the memory gate are short-circuited. Therefore, in this semiconductor device, even if the memory cell in the split gate type MONOS memory is miniaturized to increase its storage density, it is easy to obtain a highly reliable one, and as a result, the performance of the semiconductor device is improved. easy.

  Hereinafter, embodiments of the semiconductor device of the present invention and the method of manufacturing the semiconductor device of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the embodiments described below.

  FIG. 1 is a cross-sectional view schematically showing an example of a semiconductor device of the present invention. A semiconductor device 50 shown in the figure includes a semiconductor substrate 10 and a split gate type MONOS memory 40 (hereinafter abbreviated as “MONOS memory 40”) formed on the semiconductor substrate 10. The MONOS memory 40 is a NOR-type storage element having a large number of memory cells arranged in a matrix. In FIG. 1, four of the memory cells constituting one memory cell row (partially appearing) Memory cells 30, 30, 30, 30 appear.

  As the semiconductor substrate 10, for example, a single crystal silicon substrate, an SOI (Silicon on Insulator) substrate, or the like is used. The semiconductor substrate 10 has an active region (well) having a predetermined conductivity type and shape, and a predetermined shape. An element isolation region is formed. In FIG. 1, only one P-type well 5 appears.

  The individual memory cells 30 constituting the MONOS memory 40 include a control gate 13 disposed on the semiconductor substrate 10 via a gate insulating film 11, a memory gate 15 disposed on the side of the control gate 13, and a control gate. An ONO film 17 extending in a region between the gate 13 and the memory gate 15 and between the memory gate 15 and the semiconductor substrate 10, and an electrical insulating portion 18 provided on the memory gate 15 are included. . Further, a side wall spacer 19a disposed so as to contact one side surface of the control gate 13 in the line width direction and a side wall spacer 119b disposed so as to contact the outer side surface of the memory gate 115 in the line width direction are provided. Have.

  The control gate 13 includes a polysilicon region 13a formed on the gate insulating film 11 and a silicide region 13b formed by siliciding the polysilicon layer that is the source of the polysilicon region 13a from the upper surface side. And have. Similarly, the memory gate 15 includes a polysilicon region 15a located on a region of the ONO film 17 that protrudes from the upper surface of the semiconductor substrate 10, and a polysilicon layer that is the source of the polysilicon region 15a. And a silicide region 15b formed by silicidation from the side.

  The ONO film 17 is a laminated film having a three-layer structure formed by laminating an oxide film, a nitride film, and an oxide film in this order, and covers the entire one side surface of the control gate 13 in the line width direction. Thus, it is formed so as to partially cover the upper surface of the semiconductor substrate 10, and its vertical cross-sectional shape is L-shaped. In FIG. 1, the ONO film 17 is drawn as a single layer for convenience.

  The electrical insulating portion 18 covers the upper part of the memory gate 15 on the control gate 13 side, and makes the distance between the upper surface of the silicide region 13b and the upper surface of the silicide region 15b longer than the distance corresponding to the film thickness of the ONO film 17. ing.

  FIG. 2 is a schematic view showing the above-described electrical insulating portion 18 in an enlarged manner. As shown in the figure, the electrical insulating portion 18 is a film having a stacked structure including a lower electrical insulating film 18a in contact with the memory gate 15 and an upper electrical insulating film 18b stacked on the lower electrical insulating film 18a. . The upper part of the uppermost oxide film 17c in the ONO film 17 formed by stacking the oxide film 17a, the nitride film 17b, and the oxide film 17c in this order is on the control gate 13 side in the memory gate 15. The upper electrical insulating film 18a is formed by projecting the upper part of the nitride film 17b in the ONO film 17 to the upper part of the memory gate 15 on the control gate 13 side. ing. 2 that are the same as those shown in FIG. 1 are assigned the same reference numerals as those used in FIG. 1, and descriptions thereof are omitted.

  The total number of masks (etching mask and ion implantation mask) required for manufacturing the memory cell 30 having the electrical insulating portion 18 having the above-described structure is that the electrical insulating portion 18 is not provided, as will be described later. This is the same as the total number of masks required when forming a memory cell having the same structure as the memory cell 30.

  In the memory cell 30 shown in FIGS. 1 and 2, the control gate 13 and the memory gate 15 are electrically separated by a region of the ONO film 17 interposed between the control gate 13 and the memory gate 15. In the ONO film 17, a region interposed between the memory gate 15 and the semiconductor substrate 10 is used as a region for storing logic data. For this purpose, each memory cell 30 has a predetermined impurity diffusion region formed in the semiconductor substrate 10.

  For example, as shown in FIG. 1, the memory cell 30 is mainly controlled when viewed in plan and the source region 21 formed in the semiconductor substrate 10 so as to be located mainly on the side of the memory gate 15 when viewed in plan. And a drain region 25 formed in the semiconductor substrate 10 so as to be located on the side of the gate 13. Further, the first extension region 22 extending from the source region 21 to the lower side of the memory gate 15, the first channel doped region 23 extending from the lower side of the memory gate 15 to the lower side of the control gate 13, and the control from the drain region 25. A second extension region 26 extending below the gate 13 and a second channel doped region 28 positioned below the control gate 13 are included.

The source region 21 includes an N ⁺ -type impurity diffusion region 21a and a silicide region 21b formed on the N ⁺ -type impurity diffusion region 21a, and is arranged one by one in two memory cell columns. The drain region 25 includes an N ⁺ -type impurity diffusion region 25a and a silicide region 25b formed on the N ⁺ -type impurity diffusion region 25a, and is arranged one by one in two memory cells 30 adjacent in the row direction. Has been. Each of the first extension region 22, the first channel dope region 23, the second extension region 26, and the second channel dope region 28 is disposed in one memory cell. The arrangement direction of the memory cells 30 in each memory cell column is substantially parallel to a bit line (not shown).

  In the MONOS memory 40 shown in FIG. 1, the logic data is written into each memory cell 30 by, for example, setting the control gate 13, the memory gate 15, and the source region 21 to a high potential and setting the drain region 25 to a low potential. Thus, hot electrons are injected into the ONO film 17 under the memory gate 15 through the first extension region 22. For example, the logical data stored in the memory cell 30 is erased by setting the control gate 13 and the drain region 21 to a high potential, the memory gate 15 to a negative potential, and the source region 21 to a ground potential. This is done by injecting hot holes into the ONO film 17 under the memory gate 15 via the channel doped region 23.

  In the semiconductor device 50 (see FIG. 1) having the above-described configuration, the upper portion of the memory gate 15 in each memory cell 30 constituting the MONOS memory 40 is partially covered by the electrical insulating portion 18, and As described above, the distance between the upper surface of the control gate 13 and the upper surface of the memory gate 15 is longer than the distance corresponding to the film thickness of the ONO film 17.

  For this reason, in the semiconductor device 50, even if the memory cell 30 of the MONOS memory 40 is miniaturized, a short circuit between the control gate 13 and the memory gate 15 is less likely to occur than in the case where the electrical insulating portion 18 is not provided. That is, even if each of the control gate 13 and the memory gate 15 is formed by siliciding a desired polysilicon layer and the memory cell 30 is miniaturized, it is caused by the residue of the metal layer used in the silicidation described above. Therefore, it is difficult for the control gate 13 and the memory gate 15 to be short-circuited.

  Therefore, even if the MONOS memory 40 is miniaturized and its storage density is increased in the semiconductor device 50, it is easy to obtain a highly reliable one, and as a result, it is easy to improve the performance of the semiconductor device 50. The semiconductor device 50 may have only a function as a memory element, or may have a function as a memory element and other functions, for example, a MONOS memory 40 and a USB (Universal Serial Bus) connector ( Or a flash microcomputer provided with a MONOS memory 40 and a microcontroller (not shown).

  The semiconductor device 50 having the above-described technical effect can be manufactured by the manufacturing method of the present invention including, for example, a laminated structure preparation process, a patterning process, and a silicidation process described below. Hereinafter, each step will be described in detail with reference to the reference numerals used in FIG.

<Laminated structure preparation process>
In the stacked structure preparation step, a gate insulating film 11 (see FIG. 1), a first polysilicon layer that is a source of the control gate 13 (see FIG. 1), a cap layer wider than the first polysilicon layer, Are stacked in this order on the semiconductor substrate 10 (see FIG. 1), and a stacked structure in which an ONO film, an NO film, and a polysilicon film are formed in a predetermined form on the semiconductor substrate 10 is prepared.

  An impurity diffusion region serving as a source of the second channel dope region 28 (see FIG. 1) is formed in advance at a predetermined portion of the semiconductor substrate 10. The ONO film is a film that is the basis of the ONO film 17 shown in FIGS. 1 and 2, and the ONO film is formed on the upper surface of the semiconductor substrate 10, each side surface of the gate insulating film 11, and the first poly film. It is formed so as to cover each side surface of the silicon layer. The NO film is a laminated film in which a nitride film and an oxide film are laminated in this order. For example, a silicon nitride film is used as the nitride film, and a silicon oxide film is used as the oxide film. Used. This NO film is formed so as to cover the outer surface of the cap layer. The polysilicon film is formed so as to cover the above-described ONO film (ONO film that is the origin of the ONO film 17) and the NO film.

  Such a laminated structure may be produced by itself, or a product produced elsewhere may be purchased. For example, by performing the following first to fourth sub-steps in this order, the above laminated structure can be produced by itself.

  As shown in FIG. 3A, in the first sub-process, the semiconductor substrate 10 in which the predetermined active region (well) and the impurity diffusion region 28a that is the source of the second channel dope region 28 (see FIG. 1) are formed. On top of this, an electrical insulating film 11a that is the source of the gate insulating film 11, a polysilicon film 13P that is the source of the control gate 13, and the inorganic film 60a that is the source of the cap layer described above are stacked in this order. In FIG. 3A, only one P-type well 5 appears in the active region (well) formed in the semiconductor substrate 10.

As the electrical insulating film 11a, a silicon oxide film, a silicon oxynitride film, a high dielectric constant dielectric film, or the like can be used. The formation method (film formation method) is the same as the material of the electrical insulating film 11a. Accordingly, a thermal oxidation method, a physical vapor deposition method (PVD method), a chemical vapor deposition method (CVD method), or the like is appropriately selected. The polysilicon film 13P is formed by the PVD method or the CVD method. As the inorganic film 60a, a film having an etching characteristic different from that of the polysilicon film 13P, such as a silicon oxide film, is used, and the inorganic film 60a is also formed by the PVD method or the CVD method. When a silicon oxide film is formed by a CVD method, if oxygen (O ₂ ) gas and TEOS (tetraethyl orthosilicate; (C ₂ H ₅ O) ₄ Si) gas are used as source gases, silicon having good film quality It is easy to obtain an oxide film.

  In the second sub-process, an etching mass having a predetermined shape is formed on the inorganic film 60a, and then the inorganic film 60a is selectively etched to form the cap layer. FIG. 3-2 is a cross-sectional view schematically illustrating an example of a cap layer. As shown in the figure, the cap layer 60 is formed on the polysilicon film 13P so as to cover the impurity diffusion region 28a in plan view. At this time, the polysilicon film 13P is not substantially etched.

  In the third sub-process, the polysilicon film 13P is etched using the cap layer 60 as an etching mask to form a first polysilicon layer serving as the source of the control gate 13 (see FIG. 1). Further, after the first polysilicon layer is formed, the above-described electrical insulating film 11a is etched using the first polysilicon layer as an etching mask to obtain the gate insulating film 11 (see FIG. 1). In obtaining the first polysilicon layer, in other words, the polysilicon film 13P is over-etched so that the line width of the first polysilicon layer is narrower than the line width of the cap layer 60. Then, the etching conditions are selected.

  FIG. 3C is a cross-sectional view schematically showing the first polysilicon layer and the gate insulating film obtained as described above. As shown in the figure, the first polysilicon layer 13L is formed on the semiconductor substrate 10 via the gate insulating film 11, and the cap layer 60 is located on the first polysilicon layer 13L. The line width of the gate insulating film 11 is narrower than the width of the impurity diffusion region 28a, and the line width of the gate insulating film 11 and the line width of the first polysilicon layer 13L are substantially the same. Further, the line width of the cap layer 60 is wider than the line width of the first polysilicon layer 13L, and the cap layer 60 protrudes at approximately equal distances on both sides of the first polysilicon layer 13L in the line width direction.

  In the fourth sub-process, an ion implantation mask having a predetermined shape is provided on the semiconductor substrate 10 to form an impurity diffusion region that is a source of the first channel doped region 23 (see FIG. 1), and then the upper surface of the semiconductor substrate 10, the gate An ONO film that covers each side surface of the insulating film 11 and each side surface of the first polysilicon layer 13L and an NO film that covers the outer surface of the cap layer 60 are formed. Further, a polysilicon film that covers the ONO film and the NO film is formed by, for example, a CVD method.

  The above ONO film can be obtained, for example, by performing formation of a silicon oxide film by a thermal oxidation method, formation of a silicon nitride film by a CVD method, and formation of a silicon oxide film by a CVD method in this order. . When the ONO film is formed in this way, the silicon oxide film is not formed on the cap layer 60 when the silicon oxide film is formed by the thermal oxidation method, but the silicon nitride film is also formed on the cap layer 60 when the silicon nitride film is formed. Since the material film is formed and the silicon oxide film is also formed on the cap layer 60 when the silicon oxide film is subsequently formed, the above-described NO film is naturally obtained.

  FIG. 3-4 is a cross-sectional view schematically showing the impurity diffusion region, the ONO film, the NO film, and the polysilicon film described above. As shown in the figure, the impurity diffusion region 23a that is the source of the first channel dope region 23 (see FIG. 1) extends to one side in the line width direction of the first polysilicon layer 13L in plan view. Thus, the P-type well 5 is formed. The ONO film 17A covers the upper surface of the semiconductor substrate 10, each side surface of the gate insulating film 11, and each side surface of the first polysilicon layer 13L, and the upper end thereof reaches the lower surface of the cap layer 60. The NO film 18A covers the outer surface of the cap layer 60, and the polysilicon film 15P covers the ONO film 17A and the NO film 18A, respectively. The polysilicon film 15P is a film that becomes the source of the memory gate 15 (see FIG. 1). By forming the polysilicon film 15P, the laminated structure 70 described above is obtained.

<Patterning process>
In the patterning step, first, the polysilicon film 15P described above is patterned, and the memory gate 15 (see FIG. 1) is arranged on one side of the first polysilicon layer 13L (see FIG. 3-4) in the line width direction. A second polysilicon layer is formed.

  In this patterning, for example, the polysilicon film 15P is selectively etched back by anisotropic etching, for example, and the first polysilicon layer 13L is formed on both sides in the line width direction as schematically shown in FIG. After forming the second polysilicon layer 15L, the unnecessary second polysilicon layer 15L can be selectively removed by, for example, dry etching.

  Here, the “unnecessary second polysilicon layer 15L” means the second polysilicon layer 15L that is not used as a material of the memory gate 15 (see FIG. 1). In the example shown in FIG. 4A, the second polysilicon layer 15L formed on the left side of the first polysilicon layer 13L corresponds to the “unnecessary second polysilicon layer 15L”. In selectively removing the unnecessary second polysilicon layer 15L, an etching mask having a predetermined shape is used to protect the necessary second polysilicon layer 15L. As schematically shown in FIG. 4B, the second polysilicon layer 15L is left only above the impurity diffusion region 23a.

  Next, the ONO film 17A and the NO film 18A (see FIG. 3-4) are respectively patterned, and the ONO film 17A is formed between the second polysilicon layer 15L and the first polysilicon layer 13L and the second polysilicon layer 15L. The NO film 18A is left only between the semiconductor substrate 10 and the upper portion of the second polysilicon layer 15L on the first polysilicon layer 13L side.

  The patterning of the ONO film 17A is performed by selectively removing, by isotropic etching, a region of the uppermost oxide film constituting the ONO film 17A that is not in contact with the second polysilicon layer 15L. After selectively removing the exposed nitride film by isotropic etching, the region exposed by removing the nitride film in the lowermost oxide film is removed by isotropic etching or anisotropic etching. This is done by selective removal.

  The NO film 18A is patterned in the process of patterning the ONO film 17A as described above. That is, in the oxide film in the NO film 18A, the region located on the upper surface of the cap layer 60 (see FIG. 4-2) and the region located on the side surface of the cap layer 60 are the uppermost layers in the ONO film 17A. When the oxide film is selectively removed, the oxide film is removed together. Of the nitride film in the NO film 18A, the region located on the upper surface of the cap layer 60 (see FIG. 4-2) and the region located on the side surface of the cap layer 60 are the same as the nitride film in the ONO film 17A. Thus, they are removed together when selectively removed.

  As schematically shown in FIG. 4C, by patterning the ONO film 17A as described above, the second polysilicon layer 15L and the semiconductor are interposed between the second polysilicon layer 15L and the first polysilicon layer 13L. An ONO film 17 extending between the substrate 10 and the substrate 10 is obtained. Further, by patterning the NO film 18A as described above, the electrical insulating portion 18 that covers the upper portion of the second polysilicon layer 15L on the first polysilicon layer 13L side is obtained.

<Silication process>
In the silicidation step, the first polysilicon layer 13L and the second polysilicon layer 15L described above are silicidized. However, prior to the silicidation, each of the first extension region 22, the first channel doped region 23, and the second extension region 26 (see FIG. 1) is formed in the semiconductor substrate 10, and further, the source region 21 (see FIG. 1). Each of the impurity diffusion region serving as the source of the reference and the impurity diffusion region serving as the source of the drain region 25 (see FIG. 1) is formed in the semiconductor substrate 10.

  The formation of the first extension region 22, the first channel dope region 23, the second extension region 26, and each of the impurity diffusion regions can be regarded as a sub-process in the silicidation process, and is different from the silicidation process. It can also be regarded as a process.

  In forming each of the first extension region 22, the first channel doped region 23, the second extension region 26, the impurity diffusion region that is the source of the source region 21, and the impurity diffusion region that is the source of the drain region 25, FIG. As shown in FIG. 5, first, an impurity diffusion region 22 a that is a source of the first extension region 22 and an impurity diffusion region 26 a that is a source of the second extension region 26 are formed.

  These impurity diffusion regions 22a and 26a are formed on the semiconductor substrate 10 by using, for example, the first polysilicon layer 13L, the ONO film 17, the electrical insulating portion 18, and the second polysilicon layer 15L as ion implantation masks. The impurity ions are implanted, and the impurity ions are activated by heat treatment. By forming the impurity diffusion regions 22a and 26a in the semiconductor substrate 10, the first channel doped region 23 can be obtained from the impurity diffusion region 23a (see FIG. 4-3). Further, the second channel dope region 28 is obtained from the impurity diffusion region 28a (see FIG. 4-3).

  Next, sidewall spacers 19a and 19b (see FIG. 1) are formed so as to cover the upper surface of the semiconductor substrate 10, the first polysilicon layer 13L, the ONO film 17, the electrical insulating portion 18, and the second polysilicon layer 15L, respectively. A base film, for example, a silicon oxide film is formed. Then, this film is etched back by anisotropic etching to form sidewall spacers 19a and 19b as shown in FIG.

  Thereafter, desired impurity ions are formed on the semiconductor substrate 10 using the first polysilicon layer 13L, the ONO film 17, the electrical insulating portion 18, the second polysilicon layer 15L, and the sidewall spacers 19a and 19b as ion implantation masks. And the impurity ions are activated by heat treatment. By performing the activation, as shown in FIG. 7, the impurity diffusion region 21A that is the source of the source region 21 (see FIG. 1) and the impurity diffusion region 25A that is the source of the drain region 25 (see FIG. 1) Is formed on the semiconductor substrate 10. Accordingly, the first extension region 22 is formed from the impurity diffusion region 22a (see FIG. 6), and the second extension region 26 is formed from the impurity diffusion region 26a.

  The silicidation of each of the first polysilicon layer 13L and the second polysilicon layer 15L is performed after the impurity diffusion regions 21A and 25A are formed as described above. As shown in FIG. 8, when siliciding the first polysilicon layer 13L and the second polysilicon layer 15L, first, cobalt (Co) or nickel (Ni) is formed so as to cover the polysilicon layers 13L and 15L. ) Or the like is formed on the semiconductor substrate 10 by, for example, the PVD method.

  Next, a heat treatment at a predetermined temperature corresponding to the composition of the metal film 65 is performed to cause the metal film 65 to react with the polysilicon layers 13L and 15L. By this reaction, each of first polysilicon layer 13L and second polysilicon layer 15L is silicided from the upper surface side to a predetermined depth. As a result, the control gate 13 and the memory gate 15 shown in FIG. 1 are obtained. The impurity diffusion regions 21A and 25A are also silicided from the upper surface side to a predetermined depth, and the source region 21 and the drain region 25 shown in FIG. 1 are obtained.

  Thereafter, the remainder of the metal film 65 that has not been consumed by the above reaction is removed by, for example, wet etching. By removing the remaining metal film 65, the MONOS memory 40 (see FIG. 1) is formed on the semiconductor substrate 10.

  In the case where the MONOS memory 40 is formed in this manner, the cap layer 60 (see FIG. 3-2) and the MONOS memory without the electrical insulating portion 18 (see FIG. 1) are formed. The number of steps for forming the inorganic film 60a (see FIG. 3-1) to be increased. However, since the first polysilicon layer 13L (see FIG. 3-3) is formed by patterning the polysilicon film 13P using the cap layer 60 as an etching mask, a mask (etching mask) necessary for forming the MONOS memory 40 is formed. The total number of ion implantation masks) is the same as the total number of masks necessary for forming a MONOS memory having the same structure as that of the MONOS memory 40 except that the electrical insulating portion 18 is not provided. For this reason, the manufacturing cost does not increase so much.

  In addition, after performing the silicidation process mentioned above, the process of forming a predetermined | prescribed multilayer wiring on the semiconductor substrate 10 (refer FIG. 1) is performed. Further, when a semiconductor device having a function as a memory element and other functions is to be manufactured, according to the function to be provided in the semiconductor device, the above-described stacked structure preparation step, patterning step, and In addition to the silicidation process, a desired process is added.

  The semiconductor device and the method for manufacturing the semiconductor device according to the present invention have been described in detail with reference to the embodiments. However, the present invention is not limited to the above-described embodiments. For example, the MONOS memory in the semiconductor device of the present invention is not limited to the NOR type, and may be a NAND type or an AND type.

  In addition, the electrical insulating portion covering the upper part of the memory gate in the MONOS memory on the control gate side can be formed by an electrical insulating film having a single layer structure or formed by an electrical insulating film having a laminated structure of three or more layers. It is also possible to do. The electrical insulating portion can be formed as a member different from the ONO film that electrically separates the control gate and the memory gate. However, from the viewpoint of suppressing an increase in manufacturing cost, it is preferable to form the above-described electrical insulating portion by projecting the upper part of the film constituting the ONO film on the memory gate as in the above-described method. Each of the semiconductor device and the semiconductor device manufacturing method of the present invention can be variously modified, modified, combined, and the like in addition to the above.

It is sectional drawing which shows an example of the semiconductor device of this invention roughly. It is the schematic which expands and shows the electrical-insulation part shown in FIG. It is sectional drawing which shows roughly an example of the laminated film formed on a semiconductor substrate at the 1st sub process in the laminated structure preparation process in the manufacturing method of the semiconductor device of this invention. It is sectional drawing which shows roughly an example of the cap layer formed at the 2nd sub process in the laminated structure preparation process in the manufacturing method of the semiconductor device of this invention. It is sectional drawing which shows roughly an example of each of the 1st polysilicon layer and gate insulating film which are formed at the 3rd sub process in the laminated structure preparation process in the manufacturing method of the semiconductor device of this invention. It is sectional drawing which shows roughly an example of each of the impurity diffusion area | region, ONO film | membrane, NO film | membrane, and polysilicon film | membrane formed at the 4th sub process in the laminated structure preparation process in the manufacturing method of the semiconductor device of this invention. . It is sectional drawing which shows roughly an example of the 2nd polysilicon layer each formed in the line | wire width direction both sides of a 1st polysilicon layer at the patterning process in the manufacturing method of the semiconductor device of this invention. It is sectional drawing which shows roughly an example of the 2nd polysilicon layer left on the one side of the line | wire width direction of a 1st polysilicon layer at the patterning process in the manufacturing method of the semiconductor device of this invention. It is sectional drawing which shows roughly an example of each of the ONO film | membrane and NO film | membrane formed at the patterning process in the manufacturing method of the semiconductor device of this invention. It is sectional drawing which shows roughly an example of the impurity diffusion area | region formed in a semiconductor substrate before siliciding a polysilicon layer in the silicidation process in the manufacturing method of the semiconductor device of this invention. It is sectional drawing which shows roughly an example of the side wall spacer formed prior to siliciding a polysilicon layer at the silicidation process in the manufacturing method of the semiconductor device of this invention. It is sectional drawing which shows roughly an example of the other impurity diffusion area | region formed in a semiconductor substrate prior to siliciding a polysilicon layer at the silicidation process in the manufacturing method of the semiconductor device of this invention. It is sectional drawing which shows roughly an example of the metal film used for silicidation of a polysilicon layer at the silicidation process in the manufacturing method of the semiconductor device of this invention. It is sectional drawing which shows roughly the memory cell in the split gate type conventional MONOS memory.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 11 Gate insulating film 13 Control gate 13a Polysilicon area | region 13b Silicide area | region 13L 1st polysilicon layer 15 Memory gate 15a Polysilicon area | region 15b Silicide area | region 15L 2nd polysilicon layer 17, 17A ONO film | membrane 17a ONO film | membrane Lower oxide film 17b Nitride film with ONO film 17c Uppermost oxide film with ONO film 18 Electrical insulating portion 18a Lower electrical insulating film 18b Upper electrical insulating film 18A NO film 30 Memory cell 40 Split gate type MONOS memory 50 Semiconductor device 60 Cap layer 65 Metal film

Claims (3)

A split gate type MONOS memory having a plurality of memory cells formed on a semiconductor substrate, each of the plurality of memory cells,
A control gate disposed on the semiconductor substrate via a gate insulating film and silicidized at least at the top;
A memory gate disposed laterally in the line width direction of the control gate and silicidized at least at the top;
The memory gate and the control gate are interposed between the memory gate and the control gate to electrically isolate the memory gate, and the memory gate and the semiconductor substrate are interposed between the memory gate and the semiconductor substrate. An ONO film,
An electrical insulating portion covering an upper portion of the memory gate on the control gate side;
A semiconductor device comprising: The electrical insulating portion has a lower electrical insulating film in contact with the memory gate, and an upper electrical insulating film laminated on the lower electrical insulating film,
The upper part of the uppermost oxide film in the ONO film protrudes to the upper part on the control gate side in the memory gate to form the lower electrical insulating film,
The upper part of the nitride film in the ONO film protrudes to the upper part on the control gate side in the memory gate to form the upper electrical insulating film.
The semiconductor device according to claim 1. A gate insulating film, a first polysilicon layer serving as a source of a control gate, and a cap layer wider than the first polysilicon layer are stacked in this order on the semiconductor substrate, and the upper surface of the semiconductor substrate, An ONO film covering each side surface of the gate insulating film and each side surface of the first polysilicon layer; an NO film covering the outer surface of the cap layer; and a polysilicon film covering each of the ONO film and the NO film And a laminated structure preparing step for obtaining a laminated structure in which each is formed,
The polysilicon film, the ONO film, and the NO film are respectively patterned to form a second polysilicon layer serving as a memory gate on the side of the first polysilicon layer in the line width direction, The ONO film is left between the second polysilicon layer and the first polysilicon layer and between the second polysilicon layer and the semiconductor substrate, and the NO film is the first polysilicon layer in the second polysilicon layer. A patterning process that remains only on the upper part of the polysilicon layer side;
A silicidation step of siliciding each of the first polysilicon layer and the second polysilicon layer;
A method of manufacturing a semiconductor device comprising a split gate type MONOS memory, comprising:

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