JP2008021333A - Non-volatile memory system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance the rate of relieving a writing errors occurring in a non-volatile memory system over time. <P>SOLUTION: The non-volatile memory system comprises a plurality of non-volatile memory devices (FLS1-FLS16) and a control device (CTR). The control device, when it detects the writing error in the non-volatile memory being operated, may make a setting for, in an area for the non-volatile memory device that is associated with an error, substitutive information of between chips indicating that the control device substitutes a memory area associated with the error for a memory area within one of the other non-volatile memory devices, and may change the other non-volatile memory device indicated by the substitutive information of between the chips as an object for operations when it obtains the substitutive information of between chips from the non-volatile memory being operated on. Thus, the control device may substitute a chip for the other chips in order to relieve the writing errors occurred in one of the non-volatile memory devices. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a technique for relieving a storage area defect in a nonvolatile storage device that occurs over time in a nonvolatile storage system having a plurality of nonvolatile storage devices, for example, an ATA (AT attachment) memory card equipped with a flash memory. The present invention relates to a technology that is effective when applied to a memory card.

  An electrically rewritable nonvolatile memory device such as a flash memory stores information with a threshold voltage corresponding to the amount of electrons or holes injected into the floating gate of the memory cell. The threshold voltage characteristics of such a memory cell deteriorate with time as the number of rewrites increases. When the characteristic deterioration progresses, a write error occurs in the verify operation at the time of data rewriting. Conventionally, there has been provided a relief technique for replacing a storage error when a write error occurs in a part of the storage area.

  For example, in an ATA memory card as a file memory, a storage area of a nonvolatile storage device is divided into a data block area and a data block replacement area for relief, etc., and each functional area is divided into a data block and its management area in units of sectors. Defined as a set of Each data block is assigned a unique physical address on the memory. When a write error occurs in the data block area, an information flag indicating failure is set in the unit area, and the physical address of the data block area used to replace it in the data block replacement area is set as the replacement address. Write data related to the write error is written to the data block of the alternative address. After that, when an access is made instructing the defective data block address, the data block in the data block alternative area specified by the alternative address is accessed by recognizing the defect of the data block by the defective flag in the management area. Is done.

  However, if replacement of a defective data block is limited to a non-volatile memory device, if there is a bias in the defect occurrence rate, any one of the write defects exceeding the repair capability of the data block replacement area will occur as soon as possible. The inventor has revealed that there is a problem that the entire memory card must be defective.

  In this regard, conventionally, a technique for providing a backup nonvolatile memory for backup is provided in Japanese Patent Laid-Open Nos. 3-25798 and 3-25798, and a defective nonvolatile memory is replaced. A required data processing method is disclosed in Japanese Patent Laid-Open No. 9-200366.

Japanese Patent Laid-Open No. 3-25798 Japanese Patent Laid-Open No. 3-25798 Japanese Patent Laid-Open No. 9-200466

  In the conventional technology, it is assumed that a non-volatile storage device that has become defective is replaced or that a redundant (spare) non-volatile memory is used. However, the storage area of each nonvolatile storage device has not been used without waste.

  An object of the present invention is to provide a non-volatile storage system that can improve the remedy efficiency against a write failure that occurs over time without replacing a non-volatile storage device that has caused a failure or using a spare non-volatile memory. It is to provide.

  Another object of the present invention is to replace a defective nonvolatile storage device or use a spare nonvolatile memory even when replacement of a defective data block becomes impossible in some nonvolatile storage devices. It is an object of the present invention to provide a non-volatile storage system that can avoid the entire failure without any problems.

  Still another object of the present invention is to provide a nonvolatile storage system that can use the storage area of each nonvolatile storage device without waste instead of a defective data block.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  [1] << Inter-chip replacement >> A nonvolatile memory system according to the present invention controls a plurality of nonvolatile memory devices that can be read, erased, and written, and the operation of the nonvolatile memory device in response to an external request. And a control device. When the control device detects a write error in the nonvolatile storage device to be operated among the plurality of nonvolatile storage devices, the control device allocates a storage area related to the write error to another nonvolatile storage device in the plurality of nonvolatile storage devices. It is possible to set the inter-chip replacement information indicating that the storage area of the volatile storage device is replaced in the nonvolatile storage device of the storage area related to the error, and from the nonvolatile storage device to be operated to the inter-chip When the replacement information is obtained, another nonvolatile memory device indicated by the inter-chip replacement information can be changed to an operation target. In this specification, a write error refers to a state in which a required threshold voltage cannot be obtained as a result of applying (programming) and program verifying a write voltage to a nonvolatile memory cell, or the write target has already been replaced. When the alternative destination address cannot be acquired in the confirmation process of whether the alternative destination address can be acquired before the program and program verification are started.

  As described above, inter-chip replacement using a storage area of another nonvolatile storage device is possible for relieving a write error generated in one nonvolatile storage device. As a result, even if it becomes impossible to replace a defective data block in some nonvolatile storage devices, the entire nonvolatile storage device can be replaced without replacing the defective nonvolatile storage device or using a spare nonvolatile memory. You can escape defects.

  When a write error occurs in a non-volatile storage device in which the remaining number of storage areas that can be replaced becomes less than a predetermined number, inter-chip replacement may be allowed. Thereby, inter-chip replacement can be performed so as to eliminate waste of data blocks as much as possible. That is, since the inter-chip replacement is started before the non-volatile memory device that has been replaced until the in-chip replacement becomes completely impossible, the remaining of the newly replaceable area is unlikely to be largely biased. Thus, the number of processing cycles for inter-chip substitution and intra-chip substitution can be minimized. If there is a large bias in the remaining area that can be replaced between non-volatile storage devices, the number of non-volatile storage devices that can be used as a replacement destination decreases, and a non-volatile storage device that can be used as a replacement destination between chips is reduced. This is because the number of search retries for searching increases.

  In order to perform inter-chip replacement so as to eliminate waste of data blocks as much as possible, inter-chip replacement is allowed for write errors that occur in non-volatile storage devices where the number of storage areas that can be used as replacement destinations is less than a predetermined number You just have to do it.

  A write error that occurs in the non-volatile storage device in the substitution-permitted state may be dealt with by on-chip substitution. For example, when a write error occurs in a non-volatile storage device in which more than a predetermined number of substitutable storage areas remain, the control device stores the storage area related to the write error in another storage of the same non-volatile storage device. When the in-chip replacement information indicating that the area has been replaced is set in the nonvolatile storage device of the storage area related to the error, and the in-chip replacement information is obtained from the operation target nonvolatile storage device, the in-chip replacement information The storage area indicated by the information can be changed to an operation target.

  This makes it possible to improve the remedy efficiency against write failures that occur over time without replacing a defective nonvolatile storage device or using a spare nonvolatile memory. The storage area of the nonvolatile storage device can be used without waste.

  Needless to say, the storage area used for inter-chip replacement or intra-chip replacement is different from the redundant storage area used for defect relief in the device process.

  As a non-volatile storage device as a replacement destination by inter-chip replacement, a non-volatile storage device in which more than a predetermined number of storage areas that can be used as a replacement destination remain can be adopted as a candidate. When the candidate that can be adopted does not exist, a nonvolatile storage device having a predetermined number or less of storage areas that can be adopted as an alternative destination may be adopted as another candidate. When writing the data related to the write error to the area that replaces the storage area related to the write error, it is desirable that the operation does not conflict with the operation of writing other data, in order to eliminate such contention. This can be possible when writing to the non-volatile storage device in which the write error has occurred is best.

  [2] << Interleaved writing >> In the above nonvolatile storage system, in response to a data write request from the outside, the control device sequentially writes a plurality of different nonvolatile data while shifting write operation timing in units of a predetermined amount of data. When the interleave writing to be written to the storage device is controllable, when the write error is detected during the interleave writing operation, the nonvolatile memory that has caused the write error is replaced with another nonvolatile storage device that replaces the storage area related to the write error. This excludes a non-volatile storage device that is a target of a series of interleave writing including a volatile storage device.

  Thereby, when writing data related to a write error in the alternative area, it is possible to eliminate contention with an interleave operation for writing other divided data. Alternatively, such competition elimination can be easily realized with high probability.

  According to another more detailed aspect focusing on interleaved writing, when the control device detects a write error during an interleaved write operation, the control device can perform interleaving as another nonvolatile storage device that replaces the storage area related to the write error. The first candidate may be selected from non-volatile storage devices that are separated by a predetermined number or more with respect to the order.

  When the first candidate cannot be selected, the control device can be adopted as an alternative destination from among the non-volatile storage devices positioned behind the interleave order out of the selection range of the first candidate May be selected as the second candidate.

  When the selection of the second candidate is impossible, the control device substitutes the storage area using the nonvolatile storage device that has caused the write error as the third candidate.

  When the third candidate cannot be selected, the control device can be used as an alternative destination from among the non-volatile storage devices ahead of the interleaving order direction out of the selection range of the first candidate. Select as the fourth candidate.

  [3] << Parallel writing >> When adopting parallel writing instead of interleave writing, the control device responds to a data write request from the outside, and a plurality of non-volatile storage devices in which write data is different by a predetermined data amount unit Can be controlled in parallel, and when a write error is detected during a parallel write operation, the nonvolatile memory that has caused the write error can be used as another nonvolatile storage device that replaces the storage area related to the write error. The first candidate is selected from the range excluding the nonvolatile storage device that is the target of parallel writing including the volatile storage device.

  [4] The nonvolatile memory device according to the present invention will be described from still another viewpoint. The nonvolatile storage system includes a control device and a plurality of nonvolatile storage devices. The control device receives data and address information from the outside, stores the data received from the outside in the plurality of nonvolatile storage devices, reads data stored in the nonvolatile storage device, or the nonvolatile The nonvolatile storage device controls each operation of erasing data stored in the storage device, and each nonvolatile storage device stores data for the data supplied from the control device in response to an operation instruction from the control device. Each of the read operation, the read operation for reading the stored data and supplying it to the control device, or the erase operation for erasing the stored data is performed. The control device divides the data received from the outside into a predetermined size, and supplies the first data of the divided data to the first nonvolatile storage device together with a write operation instruction, An interleaving operation for supplying second data to the second nonvolatile memory device together with a write instruction is performed while the writing operation is continued in the first nonvolatile memory device, and all the divided data are stored in the plurality of nonvolatile memories. Sequentially supply to the device. When a write error occurs in a predetermined data write operation in one of the plurality of nonvolatile storage devices, the write operation is performed when the control device detects the write error. With respect to the nonvolatile storage device being performed and other nonvolatile storage devices other than the nonvolatile storage device to which the divided data is to be written after the occurrence of the write error, the control device together with the write operation instruction Data storage control for supplying the predetermined data is performed.

  Each of the nonvolatile memory devices has a plurality of memory cells, a plurality of word lines, and a plurality of bit lines. Each of the plurality of memory cells is disposed at an intersection of a corresponding word line and bit line. The memory cells connected to the respective word lines are classified into, for example, a first group and a second group, and the memory cells of the first group are used for storing data supplied from the control device. The second group of memory cells are used to store predetermined information. The predetermined information includes information on whether or not a write error has occurred when storing the predetermined data in a memory cell connected to the word line in the write operation, and the write error has occurred. In the case, the information includes information indicating a nonvolatile storage device storing the predetermined data.

  The predetermined size of the divided data is, for example, the size of data that can be stored in the memory cells of the first group. The write operation, read operation, and erase operation are performed, for example, for each word line.

  Each of the memory cells stores data, for example, as a threshold voltage corresponding to the data to be stored, and the write operation is a threshold corresponding to the data to store the threshold voltage of each memory cell. A first operation for changing to a value voltage, and a second operation for checking whether or not the threshold voltage of each memory cell has changed to a corresponding threshold voltage, the first operation and the second The operation is repeated a predetermined number of times. At this time, the write error is detected after the first operation and the second operation are repeated a predetermined number of times, and the threshold voltage of at least one memory cell is not the corresponding threshold voltage. It is to be.

  When the non-volatile storage device detects the write error in the write operation, the non-volatile storage device notifies the control device of the occurrence of the write error, and the control device detects the write error by the notification. Before the write operation instruction to the other nonvolatile storage device, the nonvolatile storage device in which a write error occurred was a write operation target when the write error occurred A write operation is performed by designating a word line different from the word line.

  When the nonvolatile storage device is remedied by redundant means at the device process stage, when the write error occurs via the redundant means before notifying the controller of the occurrence of the write error The write operation is performed by designating a word line different from the word line that was the target of the write operation.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  In other words, it is possible to realize a nonvolatile storage system that can improve the remedy efficiency with respect to writing failures that occur over time without replacing a defective nonvolatile storage device or using a spare nonvolatile memory. it can.

  Even if it becomes impossible to replace a defective data block in some nonvolatile storage devices, the entire failure can be avoided without replacing the defective nonvolatile storage device or using a spare nonvolatile memory. A non-volatile storage system can be provided.

  In the non-volatile storage system, the storage area of each non-volatile storage device can be used without waste to replace the defective data block.

  << ATA Memory Card >> FIG. 1 shows a block configuration of a flash memory built-in ATA memory card (also simply referred to as an ATA memory card) as an example of a nonvolatile storage system according to the present invention. The memory card 1 shown in the figure is a flash memory FLS1 to FLS16 (any one flash memory FLSi is an example of a plurality of nonvolatile storage devices that can be read, erased, and written on a card substrate (not shown). And a card controller CTR as an example of a control device that controls the operation of the plurality of flash memories in response to a request from the outside. Although the flash memories FLS1 to FLS16 and the card controller CTR are not particularly limited, they are commonly connected to the bus 2, and the flash memories FLS1 to FLS16 are each provided with their own chip enable signals CE1 to CE16 (any one is referred to as a chip enable signal CEi). The operation is selected by the following. The bus (I / O bus) 2 is used for exchanging addresses, data, access strobe signals, and commands.

  FIG. 2 shows an example of the flash memory FLSi. In the figure, the memory array 3 has a memory mat, a data latch circuit, and a sense latch circuit. This memory mat has a large number of electrically erasable and writable nonvolatile memory cell transistors. A memory cell transistor (also referred to as a flash memory cell) is formed through a tunnel oxide film in a channel region between a source and a drain formed in a semiconductor substrate or well, and between the source and drain, although not particularly shown. A floating gate, and a control gate superimposed on the floating gate via an interlayer insulating film. The control gate is connected to the word line 6, the drain is connected to the bit line 5, and the source is connected to a source line (not shown). The threshold voltage of the memory cell transistor increases when electrons are injected into the floating gate, and the threshold voltage decreases when electrons are extracted from the floating gate. The memory cell transistor stores information corresponding to the level of the threshold voltage with respect to the word line voltage (control gate applied voltage) for reading data. Although not particularly limited, in this specification, a state in which the threshold voltage of the memory cell transistor is low is referred to as an erased state, and a state in which the threshold voltage is high is referred to as a written state.

  The external input / output terminals I / O0 to I / O7 of the flash memory 1 connected to the bus 2 are also used as address input terminals, data input terminals, data output terminals, and command input terminals. The X address signal input from the external input / output terminals I / O 0 to I / O 7 is supplied to the X address buffer 8 via the multiplexer 7. X address decoder 9 decodes the internal complementary address signal output from X address buffer 8 to drive the word line.

  A sense latch circuit is provided on one end side of the bit line 5, and a data latch circuit is provided on the other end. The bit line 5 is selected by the Y gate array circuit 13 based on the selection signal output from the Y address decoder 11. The Y address signal input from the external input / output terminals I / O0 to I / O7 is preset in the Y address counter 12, and the address signal sequentially incremented from the preset value is supplied to the Y address decoder 11.

  The bit line selected by the Y gate array circuit 13 is conducted to the input terminal of the output buffer 15 during the data output operation, and is conducted to the output terminal of the data control circuit 16 via the input buffer 17 during the data input operation. The connection between the output buffer 15 and the input buffer 17 and the input / output terminals I / O 0 to I / O 7 is controlled by the multiplexer 7. Commands supplied from the input / output terminals I / O 0 to I / O 7 are supplied to the mode control circuit 18 through the multiplexer 7 and the input buffer 17.

  The control signal buffer circuit 19 is supplied with a chip enable signal CEi, an output enable signal OEi, a write enable signal WEi, a serial clock signal SC, a reset signal RESi, and a command enable signal CDEi as access control signals. The mode control circuit 18 controls the signal interface function with the outside according to the state of these signals, and controls the internal operation according to the input command. In the case of command input or data input to the input / output terminals I / O0 to I / O7, the signal CDEi is asserted. If the command is input, the signal WEi is further asserted. If the data is input, WEi is negated. If it is an address input, the signal CDEi is negated and the signal WEi is asserted. As a result, the mode control circuit 18 can distinguish commands, data, and addresses that are multiplexed and input from the external input / output terminals I / O0 to I / O7. The mode control circuit 18 can inform the outside of the state by asserting the ready / busy signal R / Bi during the erase or write operation.

  An internal power supply circuit (internal voltage generation circuit) 20 generates an operation power supply 21 that is various internal voltages for writing, erasing, verifying, reading, and the like, and supplies the operation power supply 21 to the X address decoder 9 and the memory cell array 3. .

  The mode control circuit 18 controls the flash memory FLSi as a whole according to the input command. The operation of the flash memory FLSi is basically determined by commands. The commands of the flash memory 1 include commands such as read, erase, and write.

  The flash memory FLSi has a status register 24 to indicate its internal state, and the contents can be read from the input / output terminals I / O0 to I / O7 by asserting the signal OEi.

  The flash memory FLSi has, for example, a redundancy program circuit 8R, a redundancy X address decoding logic 9R, and a redundancy memory array 3R as redundancy means for relieving a defective memory cell transistor that has been clarified in the device manufacturing stage, and is in a word line unit. Relief is made possible. The redundant program circuit 8R outputs a detection signal to the X address decoder 9 when a defective X address to be remedied is programmed and an input of an X address that matches the programmed defective X address is detected. When the detection signal is activated, the X address decoder 9 deactivates the normal X address decoding logic, activates the redundant X address decoding logic 9R instead, and assigns the defective address at that time to relief. A redundant address is input from the redundant program circuit 8R and decoded, and a redundant word line is selected in the redundant memory array 3R.

  FIG. 3 shows an example of the card controller CTR. The card controller CTR has a host interface (HIF) 30 connected to a host device, and a memory interface (MIF) 31 connected to the flash memories FLS1 to FLS16 via the bus 2, between which a control logic circuit 32 is provided. A central processing unit (CPU) 33, a read only memory (ROM) 34, and a random access memory (RAM) 35 are connected to the control logic circuit 32. The CPU 33 executes a program stored in the ROM 34 in response to an access request or the like given from the host device to control the interface with the host device and the interface with the flash memory. The RAM 35 is used for a CPU work area and a control table area for interface control. The control logic circuit 32 is dedicated hardware for realizing a host interface function, a memory interface function, an error detection / correction function, and a data transfer control function for sharing a part of software processing possible by the CPU 33. is there.

  As typical functions of the card controller CTR, an access control function for operating the flash memories FLS1 to FLS16 as file memories in accordance with the ATA interface specification, and a defect related to data writing to the flash memory FLSi, for example, a part of the storage area There is an alternative control function of the storage area for defects occurring in the system. Since the access control function is compatible with the IDE disk interface specification and is already known, its detailed description is omitted here. Hereinafter, the alternative control function will be described in detail.

  << Alternative Control Function >> FIG. 4 illustrates an address map of a memory mat in the flash memory FLSi. This address map is a local address map in each flash memory FLSi, and is roughly divided into a data area 40, an alternative area 41, and a defect registration table area 42. Each area is not particularly limited, but unit areas BLK · CNT having a format in which 32 bytes of management information CNT are added to a unit block BLK having 32 bytes of ECC code in 2048 (512 × 4) bytes for 4 sectors. Have. For example, the data area 40 has 15649 unit areas, the replacement area 41 has 673 unit areas BLK · CNT, and the defect registration table area 42 has 62 unit areas BLK · CNT. Each unit area BLK / CNT is provided with a redundant relief storage area that is part of the redundant mat 3R for relieving defects generated in the device process stage of the flash memory FLSi. Is performed, it is mapped to an address to be relieved, and address mapping is not performed unless it is used for relieving.

  The data area 40 is, for example, a data area that is open to the user. When a write error occurs in the data area 40 or the like over time, the replacement area 41 is used to replace the unit area BLK / CNT such as the data area 40 in which the error has occurred. An alternative unit has a unit area BLK · CNT as a minimum unit. The replacement area 41 is used for inter-chip replacement for substituting the data area 40 and the like of another flash memory as well as for in-chip replacement for substituting the data area 40 and the like in the same flash memory. The defect registration table area 42 is an area in which the replacement-destination flash memory and the address of the replacement-destination replacement area are registered when intra-chip replacement and inter-chip replacement are performed.

  FIG. 5 illustrates a defect registration data format in the defect registration table area 42. Although not particularly limited, the defect registration data for one unit area BLK / CNT is 4 bytes, the chip number area 50 for specifying the replacement destination flash memory, and the replacement destination address area for specifying the address of the replacement destination unit area 51 is provided. The ECC code is arranged for each 11-bit information. The replacement destination address is not particularly limited, but is an offset address from the replacement area head address.

  The correspondence between the defect registration data for every 4 bytes and the unit areas BLK · CNT is not particularly limited, but is one-to-one correspondence. Therefore, by performing address calculation based on the physical address of the unit area BLK · CNT, it is possible to obtain the corresponding defect registration data for every 4 bytes. Such an address calculation is performed by the card controller CTR.

  FIG. 6 illustrates an information format of the management information CNT. The management information CNT includes a substitution flag 60, a block address 61, an identification code 62, other management information 64, and an ECC code 65. The substitution flag 60 indicates that the corresponding unit area BLK · CNT is not substituted by a predetermined code. When all the bits are “1”, the corresponding unit area BLK · CNT is substituted by the substitution area 41. It shows that. The block address means a local memory address (physical address) assigned to the unit area BLK · CNT. The identification code is a code indicating whether the unit block BLK is data or control information. Other management information includes, for example, the physical address of the replacement source (error generation source) unit area in the replacement destination unit area BLK / CNT.

  An alternative control of the unit areas BLK / CNT by the card controller will be described.

  The card controller CTR recognizes a specific address of the alternative area 41, for example, the physical address “3E2C′H” (the symbol “H” represents a hexadecimal number) as the inter-chip alternative determination block address. That is, the card controller CTR reads the management information CNT when accessing the unit area. If the physical address of the read management information CNT is lower than “3E2C′H”, in other words, it can still be replaced with the replacement area 41. If more than a predetermined number of storage areas remain, control is performed to perform in-chip replacement when a write error occurs in the unit area BLK · CNT. In the substitution control, the substitution flag 60 of the management information in the unit area BLK · CNT in which the write error has occurred is set to “1”, and the area 50 is used as defect registration data for every 4 bytes corresponding to the unit area BLK · CNT. Is written with the chip number of the replacement destination (in this case, the chip number of the flash memory in which a write error has occurred because it is an in-chip replacement), and the replacement destination address is written in the area 51. The information written in the areas 50 and 51 and the flag 60 in this way is an on-chip replacement indicating that the unit area BLK · CNT related to the write error is replaced with another unit area BLK · CNT of the same flash memory. Make information.

  If the physical address of the read management information CNT is higher than “3E2C′H”, in other words, the card controller CTR has less than a predetermined number of storage areas that can be newly replaced in the replacement area 41. For example, when a write error occurs in the unit area BLK / CNT, control is performed to perform inter-chip replacement. In this substitution control, the substitution flag 60 of the management information in the unit area BLK · CNT in which the write error has occurred is set to all bits “1”, and the defect registration data for every 4 bytes corresponding to the unit area BLK · CNT 50 is written with the chip number of the replacement destination (in this case, the chip number of another flash memory different from the flash memory that caused the write error because it is inter-chip replacement), and the replacement destination address is written in the area 51. Is included. The information written in the areas 50 and 51 and the flag 60 in this way includes inter-chip replacement information indicating that the unit area BLK · CNT related to the write error is replaced with the unit area BLK · CNT of a different flash memory. Make it.

  When the card controller CTR reads the management information CNT of the unit area BLK / CNT designated by the address from the flash memory to be accessed, and recognizes the replacement (all bits “1”) from the flag 60 of the read management information CNT. Then, the defect registration data for every 4 bytes corresponding to the unit area BLK / CNT is read, and the alternative destination address in the flash memory of the chip number designated in the areas 50 and 51 is changed to the access target to perform access control. .

  Needless to say, the replacement area used for inter-chip replacement or intra-chip replacement is different from the redundant storage area such as the redundant array 3R used for defect relief in the device process. Relief according to the program content of the redundant program circuit is automatically redundant according to the flash memory hardware if redundant repair is performed, regardless of whether inter-chip replacement or intra-chip replacement is performed. Will be replaced.

  As is clear from the description of the replacement control function, inter-chip replacement using the replacement area 41 of another flash memory is possible for relieving a write error occurring in one flash memory. Therefore, even if it becomes impossible to replace the defective portion of the data storage area 40 with a replacement area in some flash memories, the defective nonvolatile storage device can be replaced or a spare nonvolatile memory can be installed. Without using it, the whole defect can be avoided.

  When a write error occurs in the flash memory where the remaining storage area that can be replaced is less than the specified number, inter-chip replacement is allowed for it, so inter-chip replacement is performed to eliminate waste of data blocks as much as possible. It can be performed. In other words, since the inter-chip replacement is started before the flash memory that has been replaced until the in-chip replacement becomes completely impossible, it becomes difficult to cause a large bias in the rest of the newly replaceable area, It is possible to minimize the number of processing cycles for inter-chip substitution and intra-chip substitution. If there is a large bias in the remaining area that can be replaced between flash memories, the number of flash memories that can be used as an alternative destination decreases, and the number of search retries for searching for flash memory that can be used as an alternative destination increases. Because it will end up.

  As a result, it is possible to improve the remedy efficiency with respect to write failures that occur over time, without replacing defective flash memories or using spare flash memories. The storage area can be used without waste.

  << Alternative control function when interleave writing is supported >> Next, an alternative control function when interleave writing is employed will be described.

  FIG. 7 shows an example of the interleave writing method. In interleave writing, in response to a data write request from the host device, the card controller CTR writes the write data to a plurality of different flash memories sequentially in a predetermined data amount unit, for example, 2080 byte units while shifting the write operation timing. It is a method. In FIG. 7, the operation described as “transfer” is an operation for transferring a command and write data from the card controller to the flash memory, and the operation described as “flash program” means a write and write verify operation for the flash memory. To do. As is apparent from the figure, the flashon memory ChipNo. 0-ChipNo. In step 3, commands and write data are sequentially transferred in series, and the write operation according to the transferred command is started at a timing that is sequentially shifted.

  As illustrated in FIG. 8, the logical address in units of sectors of write data by such interleaved writing is a plurality of flash memories ChipNo. 0-ChipNo. Will be distributed over three. In FIG. 8, the numbers 0, 1, 2, and 3 mean the logical addresses in sector data units.

  FIGS. 9 to 12 illustrate a method for selecting a replacement destination flash memory in the inter-chip replacement process when interleave writing is employed. In the figure, it is assumed that 64 flash memories, Chip 0 to Chip 63, are mounted. In each figure, it is assumed that a write error has occurred in the flash memory Chip 1 indicated by ◎ and the necessity of inter-chip replacement has occurred (inter-chip replacement generation chip). The flash memory (1) is a flash memory that itself requires inter-chip replacement and cannot respond to inter-chip replacement from another flash memory (chip that cannot accept inter-chip replacement). ○ is a flash memory that can be dealt with by on-chip replacement itself, and can respond to inter-chip replacement from other flash memories (chip that can accept inter-chip replacement). □ is a series of interleave target flash memories that may include the inter-chip replacement chip (interleave target prediction chip). Here, the number of interleave target flash memories is six. (2) means a flash memory that is the interleave target prediction chip and is an inter-chip substitution request rejection chip.

  FIG. 9 illustrates an alternative approach where there is an interchip alternative acceptable chip. When the card controller CTR detects a write error in the flash memory Chip1 during the interleave write operation, a series of interleave writes including the flash memory Chip1 in which the write error has occurred as another flash memory that replaces the storage area related to the write error Excluding the target flash memories Chip1 to Chip6 and Chip60 to Chip63, the first candidate as the replacement target is selected from the chips that can accept the inter-chip replacement indicated by a circle. It is desirable that the selection algorithm for selecting the first candidate from among the chips that can accept inter-chip replacement is as random as possible. For example, in the selectable range, a chip number corresponding to the number of remainders of A / (BC) or The closest flash memory may be selected as the first candidate. A is the number of blocks 15649 in the data area 40, B is the number of flash memory chips, and the chip number of the flash memory that requires inter-chip replacement.

  As described above, when writing data related to a write error in the alternative area, it is possible to eliminate contention with an interleave operation for writing other divided data. Alternatively, such competition elimination can be easily realized with high probability.

  FIG. 10 illustrates an alternative approach where there is no interchip alternative acceptable chip. When the first candidate cannot be selected, the card controller CTR can replace the flash memory chips 60 to 63 that are located behind the interleaving order out of the selection range of the first candidate. Select as 2 candidates.

  FIG. 11 illustrates an alternative method when the second candidate cannot be selected. When the selection of the second candidate is impossible, the card controller CTR selects the flash memory Chip1 in which the write error has occurred as the third candidate.

  FIG. 12 illustrates an alternative method when the third candidate cannot be selected. When the selection of the third candidate is impossible, the card controller CTR is one out of the selection ranges of the first candidate that can be substituted from the flash memories Chip2 to Chip6 ahead of the interleaving order direction. Select as 4 candidates.

  FIG. 13 illustrates an inter-chip replacement processing procedure by the card controller CTR for realizing the selection method described in FIGS. 9 to 12.

  When a write error is detected (S1), the replacement status of the flash memory is determined based on the failure registration table area 42 of the flash memory related to the write error, the corresponding management information CNT, etc. (S2). It is determined whether or not the inter-chip substitution determination block described in (1) has been reached, that is, whether or not to process with intra-chip substitution or with inter-chip substitution (S3). If the inter-chip substitution determination block has not been reached, an in-chip substitution process is performed (S4).

  If it is determined in step S3 that the inter-chip replacement determination block has been reached, it is first determined whether there is an inter-chip replacement acceptable chip in order to perform inter-chip replacement processing (S5). . When there is a chip that can accept inter-chip replacement, the processing of TR1 described in FIG. 9 is performed. That is, a replacement destination chip candidate is selected (S6), and the replacement status of the flash memory to be a candidate is determined based on the defect registration table area 42 in the selected candidate flash memory, the corresponding management information CNT, and the like (S7). 4) It is determined whether or not intra-chip replacement has reached the inter-chip replacement determination block described with reference to FIG. 4, in other words, whether or not processing should be performed by intra-chip replacement or inter-chip replacement (S8). If the inter-chip substitution determination block has not been reached, an in-chip substitution process is performed (S9). Otherwise, the process returns to step S5.

  If it is determined in step S5 that there is no chip that can accept inter-chip replacement, the process TR2 described in FIG. 10 is performed. First, a chip being interleaved is selected (S10). In short, a flash memory in which the interleaving order precedes the flash error occurrence flash memory is selected. One of the selected flash memories is selected as a candidate (S11), and an alternative status of the flash memory to be a candidate is determined based on the failure registration table area 42 and the corresponding management information CNT in the selected flash memory (S12). 4) It is determined whether or not intra-chip replacement has reached the inter-chip replacement determination block described with reference to FIG. 4, in other words, whether or not processing should be performed with intra-chip replacement or inter-chip replacement (S13). If the inter-chip substitution determination block has not been reached, an in-chip substitution process is performed (S14). Otherwise, if the process has not been completed for all candidates selected in S10, the process returns to step S11 (S15).

  When an appropriate candidate cannot be selected in the TR2 process, the process TR3 described in FIG. 11 is performed. First, a replacement destination is designated as a write error generating chip (S16), and it is determined whether or not there is a substantially empty data block in the replacement area 41 of the flash memory (S17). The substantial vacancy mentioned here may mean that the substitution has progressed beyond the inter-chip substitution determination block 3, in other words, if the substitution area has not been used up for substitution, it is determined that there is a vacancy. To do. If there is a vacancy, substitution within the chip is performed (S18).

  If it is determined in step S17 that there is no substantial space, the process TR4 described in FIG. 12 is performed. First, the alternative candidate is set to the next chip in the interleaving direction (S19), and it is determined whether or not there is a substantially empty data block in the alternative area 41 of the flash memory (S20). The substantial vacancy here is the same as in S17. If there is a vacancy, inter-chip replacement is performed (S21). If all of the mounted chips cannot be used as alternative destination candidates (S22), the alternative processing is impossible and error processing is performed to end the series of processing (S23).

  FIG. 14 illustrates an alternative destination calculation flow. This process corresponds to the process of step S5. That is, it is determined whether there is a chip that can accept an inter-chip substitute (S30). If there is a chip that can accept an inter-chip substitute, a substitute destination chip is calculated from the block address where the write error occurred (S31). The calculation method is obtained, for example, by adding the remainder obtained by dividing the block address by the number of chips outside the interleave range to the minimum chip number of chips outside the interleave range. More specifically, chips outside the interleave range are designated as ChipN0.7 to ChipNo. 59, and the error generating chip is Chip No. 1 and the error occurrence block address is 10'H and the number of mounted chips is 64, the remainder of 16 ÷ 53 is 16, and the out-of-range minimum ChipNo. 7 is 7 + 16 = 23, the candidate chip for the inter-chip replacement chip is ChipNo. 23.

  FIG. 15 illustrates an alternative processing flow. This process corresponds to an alternative process such as steps S4 and S9. An empty block is searched from an alternative area of the flash memory that can be an alternative candidate (S40), and the presence or absence of an empty block is determined (S41). If there is no empty block, the substitution error ends, and if there is a blank block, substitution is executed (S42). In the replacement execution, the data related to the error is written to the replacement destination, and if there is no write error (S43), processing such as setting the flag of the corresponding management area and setting the replacement destination address of the corresponding defect registration table data is performed. (S45), the different diamond processing is terminated. If there is a write error, the next bored block is searched (S44), and the process returns to step S41.

  FIGS. 16 to 23 show specific examples of alternative situations realized by the alternative control function at the time of interleave writing support. 16 to 22 show that the flash memory is Chip No. 0-ChipN0. 16 are mounted. FIG. 22 shows that the flash memory is ChipNo. It is assumed that six of 0 to Chip N0.5 are installed.

  16 to 19 assume a case where the occurrence of an error becomes apparent before starting the program process for the flash memory cell. That is, before applying the write voltage (programming) to the nonvolatile memory cell and performing program verification, the management information must be confirmed first. At this time, if the data block to be written has already been replaced, it is necessary to check whether the replacement destination address can be acquired before starting the above program and program verification. However, if the read is impossible due to an EEC error or the like, the alternative destination address cannot be acquired, and a write error occurs. Assume that such a write error occurs.

  In FIG. An error has occurred in the g flash memory of No. 5. At this time, ChipNo. B-ChipNo. Substitution processing may be performed using any one of F. This corresponds to the processing result according to FIG.

  FIG. 17 shows ChipNo. B-ChipNo. An alternative destination in the case where the flash memory of F is inappropriate as an alternative destination is shown. A flash memory of 0 is used as an alternative destination. This corresponds to the processing result according to FIG.

  In the case of FIG. 18, ChipNo. 0, as well as ChipNo. When the flash memory up to 4 cannot be replaced at all, an error occurs in the ChipNo. 5 is the alternative. This corresponds to the processing result according to FIG.

  In the case of FIG. 19, the ChipNo. 5 cannot be substituted, the previous interleave target ChipNo. 6 flash memories are used as alternatives. In this case, the interleaving operation is hindered. This corresponds to the processing result according to FIG.

  20 to 22 assume a case where the occurrence of an error becomes clear at the end of writing.

  In FIG. An error has occurred in the g flash memory of No. 5. At this time, except for the flash memory that is being interleaved at that time and the target of the next interleave operation, for example, ChipNo. 0-ChipNo. Any one of 4 may be used to perform the substitute process.

  21 shows the Chip No. selected as a candidate in FIG. 0-ChipNo. 4 shows an alternative destination when the flash memory is inappropriate as an alternative destination, and the flash memory, for example, ChipNo. 6 is an inter-chip replacement target.

  In the case of FIG. 22, when the flash memory whose operation has been completed in FIG. 5 is the alternative. The ChipNo. If all the alternative areas are used up, the inter-chip alternative destination is newly searched from the entire mounted chip.

  FIG. 23 shows an example when the number of mounted chips is small. When the number of mounted chips is small, there is less room for inter-chip replacement without interleaving.

  << Alternative Control Function when Supporting Parallel Writing >> FIG. 24 illustrates an example of inter-chip replacement when parallel writing is employed.

  When adopting parallel writing instead of the interleave writing, the card controller CTR writes the write data in parallel to a plurality of different flash memories in a predetermined data amount unit in response to an external data write request. Can be controlled. In the example of FIG. 24, writing is performed by operating six flash memories in parallel. When a write error is detected during a parallel write operation, other flash memories that replace the storage area related to the write error are excluded from the range excluding the flash memory subject to parallel write including the flash memory in which the write error has occurred. It is desirable to select one candidate. In the example of FIG. When an error occurs in the flash memory of No. 5, ChipNo. C-ChipNo. One of F is a candidate for inter-chip replacement.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the selection procedure of the inter-chip replacement target candidate is not limited to the above-described specific example, and if the candidate is selected so as not to disturb the writing operation that has already started or is expected to start after that, as much as possible. Well, various changes are possible.

  Redundant relief may be used in combination with relief on the bit line side. The present invention is not limited to an ATA memory card, and can be widely applied to other storage format nonvolatile memories, memory cards conforming to other standards, and the like. The number of mounted flash memories is not limited to the above.

1 is a block diagram of a flash memory built-in ATA memory card that is an example of a nonvolatile storage system according to the present invention. FIG. It is a block diagram which shows an example of flash memory. It is a block diagram which shows an example of a card controller. It is explanatory drawing which illustrates the address map of the memory mat in flash memory. It is explanatory drawing which illustrates the defect registration data format of a defect registration table area | region. It is explanatory drawing which illustrates the information format of management information. It is explanatory drawing which shows the concept of the interleave writing system. It is explanatory drawing which illustrates the state in which the logical address of the sector unit of the write data by interleaved writing is disperse | distributed to several flash memory. It is explanatory drawing which shows the alternative method when there exists a chip | tip which can accept an inter-chip alternative as an example of the selection method of the inter-chip alternative destination flash memory in the case of adopting interleave writing. It is explanatory drawing which shows the alternative method when there is no chip | tip which can accept an inter-chip alternative as another example of the selection technique of the inter-chip alternative destination flash memory in the case of adopting interleave writing. FIG. 11 is an explanatory diagram showing an alternative method when the second candidate in FIG. 10 cannot be selected as still another example of the inter-chip replacement destination flash memory selection method when interleave writing is employed. FIG. 12 is an explanatory diagram showing an alternative method when the third candidate in FIG. 11 cannot be selected as still another example of the inter-chip replacement destination flash memory selection method in the case of employing interleaved writing. FIG. 13 is a flowchart illustrating an inter-chip replacement processing procedure by the card controller for realizing the selection method described in FIGS. It is a flowchart which illustrates the process of alternative destination calculation. It is a flowchart which illustrates an alternative process. FIG. 10 is a timing chart showing a case where an error occurrence is clarified at an early stage after the start of writing as a specific example of the alternative situation realized by the alternative control function at the time of interleave writing support, corresponding to the processing result of FIG. FIG. 11 is a timing chart showing a case where an error occurrence is clarified at an early stage after the start of writing as a specific example of an alternative situation realized by the alternative control function at the time of interleave writing support, corresponding to the processing result of FIG. FIG. 12 is a timing chart showing a case where an error occurrence is clarified at an early stage after the start of writing as a specific example of an alternative situation realized by the alternative control function at the time of interleave writing support, corresponding to the processing result shown in FIG. FIG. 13 is a timing chart showing a case where an error occurrence is clarified at an early stage after the start of writing as a specific example of an alternative situation realized by the alternative control function at the time of interleave writing support, corresponding to the processing result of FIG. It is a timing chart which shows the case where an error occurrence becomes clear at the time of completion of writing as a specific example of the alternative situation realized by the alternative control function at the time of interleave writing support. It is another timing chart which shows the case where error occurrence becomes clear at the time of completion | finish of writing as a specific example of the alternative condition implement | achieved by the alternative control function at the time of interleave writing support. It is another timing chart which shows the case where an error occurrence becomes clear at the time of completion of writing as a specific example of the alternative situation realized by the alternative control function at the time of interleave writing support. It is a timing chart which shows the case where the number of mounted chips is small as a specific example of the alternative situation realized by the alternative control function at the time of interleave writing support. It is a timing chart which illustrates the mode of substitution between chips at the time of adopting parallel writing.

Explanation of symbols

1 ATA memory card 2 bus CTR card controller FLS1 to FLS16 flash memory CE1 to CE16 chip enable signal 3 memory array 3R redundant memory array 8 X address buffer 8R redundant program circuit 9 X address decoder 9R redundant X address decoding logic 33 CPU
34 ROM
35 RAM
40 Data area 41 Alternative area 42 Defect registration table area BLK unit block CNT management information BLK / CNT unit area 50 Chip number area 51 Alternative address area 60 Alternative flag 61 Block address

Claims (6)

A plurality of non-volatile storage devices capable of reading, erasing and writing; and a control device for controlling the operation of the non-volatile storage device in response to an external request;
When the control device detects a write error with respect to an operation target nonvolatile storage device of the plurality of storage devices, the control device allocates a storage area related to the write error to another nonvolatile storage device of the plurality of storage devices. It is possible to set inter-chip replacement information indicating that the storage area has been replaced in the nonvolatile storage device of the storage area related to the error, and obtain inter-chip replacement information from the nonvolatile storage device to be operated. The non-volatile storage system is characterized in that the other non-volatile storage device indicated by the inter-chip replacement information can be changed to an operation target.   2. The nonvolatile memory according to claim 1, wherein the inter-chip replacement is made possible for a write error that occurs in a nonvolatile storage device in which a storage area that can be used as a replacement destination is equal to or less than a predetermined number. Sexual memory system.   For the write error that occurs in the non-volatile storage device in which more than a predetermined number of storage areas that can be used as alternatives remain, the control device separates the storage area related to the write error from the same non-volatile storage device. It is possible to set in-chip replacement information indicating that the storage area has been replaced to the non-volatile storage device of the storage area related to the error, and to replace the in-chip replacement information from the non-volatile storage device to be operated. 3. The nonvolatile storage system according to claim 2, wherein when obtained, the storage area indicated by the in-chip alternative information can be changed to an operation target.   The control device can employ, as a candidate, a non-volatile storage device in which more than a predetermined number of storage areas that can be used as a replacement destination remain as a replacement non-volatile storage device by inter-chip replacement. The non-volatile storage system according to claim 3.   The control device can employ a non-volatile storage device having a predetermined number or less of storage areas that can be employed as an alternative destination as another candidate when the candidate that can be employed does not exist. Item 5. The nonvolatile storage system according to Item 4.   In response to an external data write request, the controller is capable of controlling parallel writing in which write data is written in parallel to a plurality of different nonvolatile storage devices in units of a predetermined amount of data. When a write error is detected, as another nonvolatile storage device that replaces the storage area related to the write error, from the range excluding the nonvolatile storage device that is the target of parallel writing including the nonvolatile storage device that has caused the write error The nonvolatile storage system according to claim 1, wherein a first candidate is selected.

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