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JP2008072148A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2008072148A
JP2008072148A JP2007312500A JP2007312500A JP2008072148A JP 2008072148 A JP2008072148 A JP 2008072148A JP 2007312500 A JP2007312500 A JP 2007312500A JP 2007312500 A JP2007312500 A JP 2007312500A JP 2008072148 A JP2008072148 A JP 2008072148A
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JP
Japan
Prior art keywords
conductor wiring
protruding electrode
semiconductor element
electrode
conductor
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Pending
Application number
JP2007312500A
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Japanese (ja)
Inventor
Hiroyuki Imamura
博之 今村
Nobuyuki Koya
信之 幸谷
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Priority to JP2007312500A priority Critical patent/JP2008072148A/en
Publication of JP2008072148A publication Critical patent/JP2008072148A/en
Pending legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731Location prior to the connecting process
    • H01L2224/73101Location prior to the connecting process on the same surface
    • H01L2224/73103Bump and layer connectors
    • H01L2224/73104Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81192Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of securing a sufficient area size in which an electrode pad of the semiconductor device faces a bump electrode even when the location of the bump electrode formed on a conductor wiring on a wiring board is shifted to the longitudinal direction of the conductor wiring. <P>SOLUTION: A semiconductor device is provided with a wiring board having an insulating substrate 1, a plurality of conductor wiring 2 installed in line on the insulating substrate, and a bump electrode formed on each of a plurality of conductor wirings, and a semiconductor element mounted thereon. The bump electrode is electrically connected with an electrode pad of the semiconductor element. A distance between a center line of the semiconductor element and electrode pad is larger than the distance d between a center line C2 of a mounting part of the semiconductor element on the wiring board and the conductor wiring. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、チップオンフィルム(COF)に用いられるテープキャリア基板のような配線基板、特に導体配線上に突起電極が形成された配線基板上に半導体素子が搭載された半導体装置の構造に関する。   The present invention relates to a structure of a semiconductor device in which a semiconductor element is mounted on a wiring substrate such as a tape carrier substrate used for a chip-on-film (COF), particularly a wiring substrate in which a protruding electrode is formed on a conductor wiring.

フィルム基材を使用したパッケージモジュールの一種として、COF(Chip On Film)が知られている。図14は、COFの一例の一部を示す断面図である。COFは、柔軟な絶縁性のテープキャリア基板20の上に半導体素子21が搭載され、封止樹脂22により保護された構造を有し、フラットパネルディスプレイの駆動用ドライバーとして主に使用されている。テープキャリア基板20は、主たる要素として、絶縁性のフィルム基材23とその面上に形成された導体配線24を含む。必要に応じて導体配線24上には、金属めっき被膜25および絶縁樹脂であるソルダーレジスト26の層が形成される。一般的に、フィルム基材23としてはポリイミドが、導体配線24としては銅が使用される。   COF (Chip On Film) is known as a kind of package module using a film substrate. FIG. 14 is a cross-sectional view showing a part of an example of a COF. The COF has a structure in which a semiconductor element 21 is mounted on a flexible insulating tape carrier substrate 20 and is protected by a sealing resin 22, and is mainly used as a driver for driving a flat panel display. The tape carrier substrate 20 includes, as main elements, an insulating film base material 23 and conductor wiring 24 formed on the surface thereof. If necessary, a layer of a metal plating film 25 and a solder resist 26 that is an insulating resin is formed on the conductor wiring 24. Generally, polyimide is used as the film base 23 and copper is used as the conductor wiring 24.

また、テープキャリア基板20上の導体配線24と半導体素子21上の電極パッド27は、突起電極28を介して接続されている。この突起電極28は、あらかじめテープキャリア基板20上の導体配線24に対して形成しておく方法と、半導体素子21上の電極パッド27に対して形成しておく方法のいずれかにより設けられる。   In addition, the conductor wiring 24 on the tape carrier substrate 20 and the electrode pad 27 on the semiconductor element 21 are connected via a protruding electrode 28. The protruding electrode 28 is provided by either a method in which the protruding electrode 28 is previously formed on the conductor wiring 24 on the tape carrier substrate 20 or a method in which the protruding electrode 28 is formed on the electrode pad 27 on the semiconductor element 21.

テープキャリア基板20上の導体配線24に対して突起電極28を形成するためには、例えば特許文献1に記載されたような方法が用いられる。その製造方法の工程について、図15を参照して説明する。図15(a1)〜(f1)は、従来例の製造工程におけるフィルム基材の一部を示す平面図である。図15(a2)〜(f2)は、各々図15(a1)〜(f1)に対応する断面図である。各断面図は、図15(a1)のC−Cに対応する位置で示されている。この製造工程は、金属めっきにより突起電極を形成する場合の例である。   In order to form the protruding electrode 28 on the conductor wiring 24 on the tape carrier substrate 20, for example, a method described in Patent Document 1 is used. The steps of the manufacturing method will be described with reference to FIG. 15 (a1) to (f1) are plan views showing a part of a film substrate in the manufacturing process of the conventional example. 15 (a2) to (f2) are cross-sectional views corresponding to FIGS. 15 (a1) to (f1), respectively. Each cross-sectional view is shown at a position corresponding to CC in FIG. This manufacturing process is an example in the case where bump electrodes are formed by metal plating.

まず、導体配線24が形成されたフィルム基材23(図15(a1))に対し、フォトレジスト29を全面に形成する(図15(b1))。次に、突起電極形成用の露光マスク30を用い、その光透過領域30aを通してフォトレジスト29を露光する(図15(c1))。次に、フォトレジスト29を現像して開口パターン29aを形成し(図15(d1))、開口パターン29aを通して金属めっきを施す(図15(e1))。フォトレジスト29を剥離すれば、図15(f1)に示すように、導体配線24に突起電極28が形成されたテープキャリア基板20が得られる。突起電極28は、図15(f1)に示すように、長方形のフィルム基材1の4辺に沿って配置されているのが一般的であるが、各辺に対して一列ではなく、複数列に配列されている場合もある。   First, a photoresist 29 is formed on the entire surface of the film base material 23 (FIG. 15A1) on which the conductor wiring 24 is formed (FIG. 15B1). Next, the photoresist 29 is exposed through the light transmission region 30a by using the exposure mask 30 for forming the protruding electrodes (FIG. 15 (c1)). Next, the photoresist 29 is developed to form an opening pattern 29a (FIG. 15 (d1)), and metal plating is performed through the opening pattern 29a (FIG. 15 (e1)). If the photoresist 29 is peeled off, the tape carrier substrate 20 in which the protruding electrodes 28 are formed on the conductor wiring 24 is obtained as shown in FIG. As shown in FIG. 15 (f1), the protruding electrodes 28 are generally arranged along the four sides of the rectangular film substrate 1, but a plurality of rows instead of one row for each side. In some cases, they are arranged.

以上のようにテープキャリア基板20の導体配線24に突起電極28を形成する場合、フィルム基材1の特性上、露光マスク30の位置合わせが困難である。露光マスク30の位置合わせにずれがあると良好な突起電極28を形成することができないため、一般的には、半導体素子21上の電極パッド27に突起電極28を形成する。一方、テープキャリア基板20上の導体配線24に突起電極28を形成する方法は、半導体素子21上の電極パッド27に突起電極18を形成する方法に比べ、工程数を低減し製造コストを低減できる利点がある。
特開2001−168129号公報
As described above, when the protruding electrode 28 is formed on the conductor wiring 24 of the tape carrier substrate 20, the alignment of the exposure mask 30 is difficult due to the characteristics of the film base 1. If the alignment of the exposure mask 30 is misaligned, a good protruding electrode 28 cannot be formed. Therefore, the protruding electrode 28 is generally formed on the electrode pad 27 on the semiconductor element 21. On the other hand, the method of forming the protruding electrode 28 on the conductor wiring 24 on the tape carrier substrate 20 can reduce the number of steps and the manufacturing cost compared to the method of forming the protruding electrode 18 on the electrode pad 27 on the semiconductor element 21. There are advantages.
JP 2001-168129 A

しかしながら、上述のような従来例の方法により形成された突起電極28は、その形状が良好ではなかった。図16に、上述の製造工程により作製されたテープキャリア基板の断面図を示す。図16(a)は、導体配線24の長手方向の断面図であり、図15(f2)と同様の図である。図16(b)は、(a)のD−D断面、すなわち導体配線24を横切る方向の断面を示す。   However, the shape of the protruding electrode 28 formed by the conventional method as described above was not good. FIG. 16 shows a cross-sectional view of a tape carrier substrate manufactured by the above-described manufacturing process. FIG. 16A is a cross-sectional view in the longitudinal direction of the conductor wiring 24, which is the same as FIG. 15F2. FIG. 16B shows a DD cross section in FIG. 16A, that is, a cross section in a direction crossing the conductor wiring 24.

図16に示されるように、突起電極28は、導体配線24の上面に接合された状態に形成される。したがって突起電極28は、導体配線24上面の微小な面積の接合のみにより保持されている。そのため、横方向の力が加わると、突起電極28が導体配線24の上面から剥離し易い。例えば、半導体素子21上の電極パッド27(図14参照)と接続された状態で、半導体素子21とテープキャリア基板20との間に横方向の力が加わると、突起電極28が導体配線24から剥離する惧れがあり、半導体素子の実装後の接続状態の安定性に問題がある。   As shown in FIG. 16, the protruding electrode 28 is formed in a state of being bonded to the upper surface of the conductor wiring 24. Therefore, the protruding electrode 28 is held only by bonding of a small area on the upper surface of the conductor wiring 24. Therefore, when a lateral force is applied, the protruding electrode 28 is easily peeled off from the upper surface of the conductor wiring 24. For example, when a lateral force is applied between the semiconductor element 21 and the tape carrier substrate 20 while being connected to the electrode pad 27 (see FIG. 14) on the semiconductor element 21, the protruding electrode 28 is removed from the conductor wiring 24. There is a risk of peeling, and there is a problem in the stability of the connection state after mounting the semiconductor element.

また、突起電極28は、図15(d1)に示した微小な面積の開口パターン29aを通して、導体配線24の上面のみにめっきにより形成されるので、突起電極28の上面は平坦になる。突起電極28の上面が平坦であると、以下のように、半導体素子21上の電極パッド27との接続を行う際に障害を生じる。   Further, since the protruding electrode 28 is formed by plating only on the upper surface of the conductor wiring 24 through the opening pattern 29a having a minute area shown in FIG. 15D1, the upper surface of the protruding electrode 28 becomes flat. If the upper surface of the protruding electrode 28 is flat, a failure occurs when connecting to the electrode pad 27 on the semiconductor element 21 as described below.

第1に、突起電極28と電極パッド27との位置合わせにずれがあると、突起電極28は、接続されるべき電極パッド27に隣接する電極パッド27と位置が重なり易いことである。その結果、不適当な電極パッド27と接続される惧れがある。   First, if there is a misalignment between the protruding electrode 28 and the electrode pad 27, the protruding electrode 28 is likely to overlap with the electrode pad 27 adjacent to the electrode pad 27 to be connected. As a result, there is a risk of connection with an inappropriate electrode pad 27.

第2に、電極パッド27との接続に際して、電極パッド27の表面に形成されている自然酸化膜の破砕が困難なことである。通常、電極パッド27の酸化膜を突起電極28の当接により破砕して、酸化されていない金属部分との電気的接続を得るが、突起電極28の上面が平坦であると、酸化膜の破砕が困難である。   Secondly, when the electrode pad 27 is connected, it is difficult to crush the natural oxide film formed on the surface of the electrode pad 27. Usually, the oxide film of the electrode pad 27 is crushed by the contact of the protruding electrode 28 to obtain an electrical connection with an unoxidized metal portion. However, if the upper surface of the protruding electrode 28 is flat, the oxide film is crushed. Is difficult.

第3に、図17に示すように半導体素子21とテープキャリア基板20の間に樹脂層22を介在させた状態で、突起電極28と電極パッド27とを接続する処理が困難なことである。すなわち、半導体素子21の実装に際して、突起電極28の頂面により樹脂層22を排除して、突起電極28と電極パッド27を接触させるが、突起電極28の上面が平坦であると、樹脂層22を排除する作用が十分に働かない。   Third, as shown in FIG. 17, it is difficult to connect the protruding electrode 28 and the electrode pad 27 with the resin layer 22 interposed between the semiconductor element 21 and the tape carrier substrate 20. That is, when the semiconductor element 21 is mounted, the resin layer 22 is eliminated by the top surface of the protruding electrode 28 and the protruding electrode 28 and the electrode pad 27 are brought into contact. However, if the upper surface of the protruding electrode 28 is flat, the resin layer 22 The action to eliminate is not enough.

さらに、図15に示した従来例の方法により突起電極28を形成する場合、突起電極形成用の露光マスク30と導体配線24の位置合わせ精度が悪いと、フォトレジスト29に形成された開口パターン29aが導体配線24に重なり合う面積が小さくなる。その結果、図18に示すように、導体配線24上に形成された突起電極28について、設計したサイズを確保することができない。このような突起電極28のサイズ不良は、今後のCOFの多出力化に伴う電極バッド27の狭ピッチ化によって、さらに、深刻な問題となる。   Further, when the protruding electrode 28 is formed by the method of the conventional example shown in FIG. 15, if the alignment accuracy of the exposure mask 30 for forming the protruding electrode and the conductor wiring 24 is poor, the opening pattern 29a formed in the photoresist 29 is formed. The area overlapping the conductor wiring 24 is reduced. As a result, as shown in FIG. 18, the designed size cannot be ensured for the protruding electrode 28 formed on the conductor wiring 24. Such a defective size of the protruding electrode 28 becomes a more serious problem due to the narrowing of the pitch of the electrode pad 27 accompanying the increase in the output of COF in the future.

なお、以上に説明した問題はテープキャリア基板の場合に顕著であるが、各種の配線基板に共通の問題である。   The problem described above is remarkable in the case of a tape carrier substrate, but is a problem common to various wiring substrates.

以上の問題を考慮して本発明は、導体配線上に形成された突起電極が、横方向に加わる力に対して実用的に十分な強さで保持され、半導体素子実装後に十分な接続の安定性が得られる半導体装置を提供することを目的とする。   In view of the above problems, the present invention is such that the protruding electrode formed on the conductor wiring is held with a practically sufficient strength against the force applied in the lateral direction, and sufficient connection stability is achieved after mounting the semiconductor element. An object of the present invention is to provide a semiconductor device capable of obtaining high performance.

本発明の半導体装置は、絶縁性基材、前記絶縁性基材上に整列して設けられた複数本の導体配線、及び前記複数本の導体配線の各々に形成された突起電極を備えた配線基板と、前記配線基板上に搭載された半導体素子とを備え、前記突起電極と前記半導体素子の電極パッドとが電気的に接続され、前記半導体素子の中心線と前記電極パッドとの間の距離が、前記配線基板の前記半導体素子の搭載部の中心線と前記導体配線との間の距離よりも大きいことを特徴とする。   A semiconductor device according to the present invention includes an insulating base material, a plurality of conductor wirings arranged in alignment on the insulating base material, and a wiring including a protruding electrode formed on each of the plurality of conductor wirings A distance between the center line of the semiconductor element and the electrode pad, wherein the protruding electrode and the electrode pad of the semiconductor element are electrically connected to each other; and a semiconductor element mounted on the wiring board. Is larger than the distance between the center line of the mounting portion of the semiconductor element of the wiring board and the conductor wiring.

本発明の半導体装置によれば、配線基板にの導体配線に形成された突起電極の位置が、導体配線の長さ方向にずれても、半導体素子の電極パッドと突起電極が対向する面積を十分な大きさに確保可能である。   According to the semiconductor device of the present invention, even if the position of the protruding electrode formed on the conductor wiring on the wiring board is shifted in the length direction of the conductive wiring, the area where the electrode pad of the semiconductor element and the protruding electrode are opposed is sufficient. It is possible to secure a large size.

以下、本発明の実施の形態について、図面を参照して具体的に説明する。なお、以下の実施の形態ではテープキャリア基板の場合を例として説明するが、他の配線基板の場合にも同様に各実施の形態の思想を適用可能である。   Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings. In the following embodiments, the case of a tape carrier substrate will be described as an example. However, the idea of each embodiment can be applied to other wiring substrates as well.

(実施の形態1)
図1および図2を参照して、実施の形態1におけるテープキャリア基板の構造について説明する。図1は、テープキャリア基板の一部を示す斜視図である。図2(a)はテープキャリア基板の一部を示す平面図、(b)は断面で示した正面図、(c)は(b)におけるA−A断面図である。
(Embodiment 1)
The structure of the tape carrier substrate in the first embodiment will be described with reference to FIGS. FIG. 1 is a perspective view showing a part of a tape carrier substrate. 2A is a plan view showing a part of the tape carrier substrate, FIG. 2B is a front view showing a section, and FIG. 2C is a sectional view taken along line AA in FIG.

図1に示すように、フィルム基材1の上には、複数本の導体配線2が整列して設けられ、各導体配線2上に突起電極3が形成されている。突起電極3の平面形状は、図2(a)に示すように、導体配線2を横切って導体配線2の両側の領域に亘っている。導体配線2の幅方向における突起電極3の断面形状は、図2(c)に示すように、導体配線2の上面および両側面に接合され、中央部が両側よりも高くなった中高形状である。また突起電極3は、導体配線2の両側部でフィルム基材1の面に接するように形成されている。導体配線2の長さ方向における突起電極3の断面は、図2(b)に示すように、実質的に長方形である。   As shown in FIG. 1, a plurality of conductor wirings 2 are arranged on a film substrate 1 and a protruding electrode 3 is formed on each conductor wiring 2. As shown in FIG. 2A, the planar shape of the protruding electrode 3 extends across the conductor wiring 2 and on both sides of the conductor wiring 2. As shown in FIG. 2C, the cross-sectional shape of the protruding electrode 3 in the width direction of the conductor wiring 2 is a medium-high shape that is joined to the upper surface and both side surfaces of the conductor wiring 2 and whose center is higher than both sides. . Further, the protruding electrode 3 is formed so as to be in contact with the surface of the film base 1 at both sides of the conductor wiring 2. The cross section of the protruding electrode 3 in the length direction of the conductor wiring 2 is substantially rectangular as shown in FIG.

突起電極3を上述のような形状とすることにより、突起電極3は、実用的に十分な強さで導体配線2上に保持される。すなわち、突起電極3は、導体配線2の上面だけではなく両側面にも接合されているので、横方向に加わる力に対する安定性が十分である。   By forming the protruding electrode 3 as described above, the protruding electrode 3 is held on the conductor wiring 2 with a practically sufficient strength. That is, since the protruding electrode 3 is joined not only to the upper surface of the conductor wiring 2 but also to both side surfaces, the stability against the force applied in the lateral direction is sufficient.

また、突起電極3の上面が平坦ではなく中高であることにより、半導体素子の電極パッドとの接続に好適である。第1に、突起電極3と電極パッドとの位置合わせにずれがあっても、上面が平坦である場合と比べて、突起電極3は隣接する不適当な電極パッドと接続され難い。第2に、電極パッドとの接続に際して、電極パッドの表面に形成された酸化膜を、突起電極3の凸状の上面により容易に破砕することができ、酸化されていない内部と良好な電気的接続が得られる。第3に、半導体素子とテープキャリア基板の間に樹脂層を介在させた状態で、突起電極3と電極パッドとを接続する際に、突起電極3の頂面により樹脂層を容易に排除することができる。   In addition, since the upper surface of the protruding electrode 3 is not flat but medium and high, it is suitable for connection to the electrode pad of the semiconductor element. First, even if there is a misalignment in the alignment between the protruding electrode 3 and the electrode pad, the protruding electrode 3 is less likely to be connected to the adjacent inappropriate electrode pad as compared with the case where the upper surface is flat. Second, when connecting to the electrode pad, the oxide film formed on the surface of the electrode pad can be easily crushed by the convex upper surface of the protruding electrode 3, and the interior not oxidized and good electrical property can be obtained. A connection is obtained. Third, when the bump electrode 3 and the electrode pad are connected with the resin layer interposed between the semiconductor element and the tape carrier substrate, the resin layer is easily removed by the top surface of the bump electrode 3. Can do.

なお、以上の効果を得るためには、突起電極3が導体配線2の両側部でフィルム基材1の面に接するように形成されていることは、必須ではない。但し、そのような構成を有する場合に、横方向に加わる力に対して最も安定して導体配線2に保持される。また、導体配線2の長さ方向における突起電極3の断面が実質的に長方形であることも必須ではないが、そのような構造は、半導体素子の電極パッドとの接続性能が最も良好であり、しかも製造が容易である。   In addition, in order to acquire the above effect, it is not essential that the protruding electrode 3 is formed so as to be in contact with the surface of the film base 1 at both sides of the conductor wiring 2. However, when it has such a structure, it is hold | maintained to the conductor wiring 2 most stably with respect to the force added to a horizontal direction. Further, it is not essential that the cross section of the protruding electrode 3 in the length direction of the conductor wiring 2 is substantially rectangular, but such a structure has the best connection performance with the electrode pad of the semiconductor element, Moreover, it is easy to manufacture.

図2(c)に示すように、突起電極3の導体配線2の上面からの厚みは、導体配線2の側面からの横方向の厚みよりも大きい。このような形状は必須ではないが、テープキャリア基板6のうねり等による導体配線2と半導体素子21との間のショートを抑制し、かつ、隣接する導体配線2上の突起電極3とのショートを回避するために効果的である。この形状は、後述のめっきを用いた製造方法により形成される。   As shown in FIG. 2C, the thickness of the protruding electrode 3 from the upper surface of the conductor wiring 2 is larger than the thickness in the lateral direction from the side surface of the conductor wiring 2. Although such a shape is not essential, a short circuit between the conductor wiring 2 and the semiconductor element 21 due to the undulation of the tape carrier substrate 6 is suppressed, and a short circuit with the protruding electrode 3 on the adjacent conductor wiring 2 is prevented. It is effective to avoid. This shape is formed by a manufacturing method using plating described later.

フィルム基材1としては、一般的な材料であるポリイミドを用いることができる。他の条件に応じて、PET、PEI等の絶縁フィルム材料を用いても良い。導体配線2は、通常、厚みが3〜20μmの範囲で、銅を用いて形成する。必要に応じて、フィルム基材1と導体配線2の間に、エポキシ系の接着剤を介在させてもよい。   As the film substrate 1, polyimide which is a general material can be used. Depending on other conditions, an insulating film material such as PET or PEI may be used. The conductor wiring 2 is usually formed using copper in a thickness range of 3 to 20 μm. If necessary, an epoxy-based adhesive may be interposed between the film base 1 and the conductor wiring 2.

突起電極3の厚みは通常、3〜20μmの範囲である。突起電極3の材料としては、例えば銅を用いることができる。銅を用いる場合、突起電極3と導体配線2に金属めっきを施すことが望ましい。例えばニッケルめっきを内層とし、金めっきを外層として施す。あるいは、錫、(ニッケル+パラジウム)、ニッケルのみ、金のみのめっきを施す場合もある。突起電極3と導体配線2に金属めっきを施す場合、突起電極3と導体配線2の間にはめっきを施さない。突起電極3に金属めっきを施さない場合は、突起電極3として、例えば金、あるいはニッケルを用い、突起電極3と導体配線2の間にニッケルめっきを施す。   The thickness of the protruding electrode 3 is usually in the range of 3 to 20 μm. As a material of the protruding electrode 3, for example, copper can be used. When copper is used, it is desirable to apply metal plating to the protruding electrode 3 and the conductor wiring 2. For example, nickel plating is used as an inner layer and gold plating is applied as an outer layer. Alternatively, tin, (nickel + palladium), nickel only, or gold only may be applied. When metal plating is performed on the protruding electrode 3 and the conductor wiring 2, no plating is performed between the protruding electrode 3 and the conductor wiring 2. When metal plating is not applied to the protruding electrode 3, for example, gold or nickel is used as the protruding electrode 3, and nickel plating is performed between the protruding electrode 3 and the conductor wiring 2.

(実施の形態2)
図3を参照して、実施の形態2におけるテープキャリア基板の製造方法について説明する。図3(a1)〜(f1)は、テープキャリア基板における突起電極を形成する製造工程を示し、半導体素子搭載部の平面図である。図3(a2)〜(f2)は各々、図3(a1)〜(f1)の拡大断面図である。各断面図は、図3(a1)におけるB−Bに相当する位置での断面を示す。
(Embodiment 2)
With reference to FIG. 3, the manufacturing method of the tape carrier substrate in Embodiment 2 is demonstrated. FIGS. 3A1 to 3F1 are plan views of a semiconductor element mounting portion, showing a manufacturing process for forming protruding electrodes on the tape carrier substrate. 3 (a2) to (f2) are enlarged sectional views of FIGS. 3 (a1) to (f1), respectively. Each cross-sectional view shows a cross-section at a position corresponding to BB in FIG.

まず、図3(a1)に示すように、複数の導体配線2が表面に整列して形成されたフィルム基材1を用意する。このフィルム基材1の全面に、図3(b1)に示すように、フォトレジスト4を形成する。次に図3(c1)に示すように、フィルム基材1に形成されたフォトレジスト4の上部に、突起電極形成用の露光マスク5を対向させる。露光マスク5の光透過領域5aは、複数の導体配線2の整列方向に、複数の導体配線2を横切るように連続した長孔形状を有する。   First, as shown in FIG. 3 (a1), a film substrate 1 on which a plurality of conductor wirings 2 are formed on the surface is prepared. A photoresist 4 is formed on the entire surface of the film substrate 1 as shown in FIG. Next, as shown in FIG. 3 (c1), an exposure mask 5 for forming protruding electrodes is opposed to the upper portion of the photoresist 4 formed on the film substrate 1. The light transmission region 5 a of the exposure mask 5 has a long hole shape that is continuous across the plurality of conductor wirings 2 in the alignment direction of the plurality of conductor wirings 2.

露光マスク5の光透過領域5aを通して露光し、現像することにより、図3(d1)に示すように、フォトレジスト4に、導体配線2を横切る長孔状パターン4aが開口される。それにより長孔状パターン4a中に、導体配線2の一部が露出する。次に、フォトレジスト4の長孔状パターン4aを通して、導体配線2の露出した部分に金属めっきを施して、図3(e1)に示すように突起電極3を形成する。次に、フォトレジスト4を除去すれば、図3(f1)に示すように、導体配線2に突起電極3が形成されたテープキャリア基板6が得られる。   By exposing and developing through the light transmission region 5a of the exposure mask 5, a long hole pattern 4a across the conductor wiring 2 is opened in the photoresist 4 as shown in FIG. 3 (d1). Thereby, a part of the conductor wiring 2 is exposed in the long hole pattern 4a. Next, the exposed portion of the conductor wiring 2 is subjected to metal plating through the long hole pattern 4a of the photoresist 4 to form the protruding electrode 3 as shown in FIG. 3 (e1). Next, if the photoresist 4 is removed, as shown in FIG. 3 (f1), the tape carrier substrate 6 in which the protruding electrodes 3 are formed on the conductor wiring 2 is obtained.

以上のように、フォトレジスト4に形成された長孔状パターン4aを通して導体配線2
の露出した部分に金属めっきを施すことにより、図2に示したような形状の突起電極3を、容易に形成することができる。これは、図3(e1)の工程で、導体配線2の上面のみでなく側面も露出しており、導体配線2の露出面全体に亘ってめっきが形成されるからである。
As described above, the conductor wiring 2 passes through the long hole pattern 4a formed in the photoresist 4.
By performing metal plating on the exposed portion, the protruding electrode 3 having a shape as shown in FIG. 2 can be easily formed. This is because not only the upper surface of the conductor wiring 2 but also the side surfaces are exposed in the step of FIG. 3 (e1), and plating is formed over the entire exposed surface of the conductor wiring 2.

フォトレジスト4の長孔状パターン4aは、図3(d1)に示されるように複数本の導体配線2に跨って連続した形状でなくともよい。すなわち、少なくとも導体配線2の両側の所定範囲の領域を含む形状であれば、複数の導体配線2にそれぞれ対応する長孔が離散的に配置されたパターンを用いることもできる。但し、複数本の導体配線2に跨って連続した長孔状パターンであれば、露光マスク5の光透過領域5aを、図3(c1)に示したような連続した長孔とすることができるので、作成が容易である。長孔状パターン4aは、各々の導体配線2の両側に亘る範囲に形成される限り、その長手方向が導体配線2に対して多少の角度を持っていても問題ないが、導体配線2の長手方向に対して直交していることが最も合理的である。   The long hole pattern 4a of the photoresist 4 does not have to have a continuous shape across a plurality of conductor wirings 2 as shown in FIG. That is, a pattern in which long holes corresponding to the plurality of conductor wirings 2 are discretely arranged can be used as long as the shape includes at least a predetermined range of regions on both sides of the conductor wiring 2. However, in the case of a long hole pattern continuous across a plurality of conductor wirings 2, the light transmission region 5a of the exposure mask 5 can be a continuous long hole as shown in FIG. 3 (c1). So it is easy to create. As long as the long hole pattern 4a is formed in a range extending over both sides of each conductor wiring 2, there is no problem even if the longitudinal direction has a slight angle with respect to the conductor wiring 2. It is most reasonable to be orthogonal to the direction.

また、フォトレジスト4に長孔状パターン4aを形成して金属めっきを施すことにより、導体配線2に対する突起電極3の位置精度を、容易に確保することができる。すなわち、導体配線2に対する長孔状パターン4aの位置ずれが許容範囲内であれば、導体配線2と長孔状パターン4aが必ず交わり、導体配線2が露出するからである。金属めっきは導体配線2の上面および側面に成長するので、長孔状パターン4aの位置ずれにかかわらず、一定の形状・寸法に形成され、設計された条件を満足することができる。したがって、露光マスク5の位置合わせに厳密な精度を必要とせず、調整が容易である。   Further, by forming the long hole pattern 4 a on the photoresist 4 and performing metal plating, the positional accuracy of the protruding electrode 3 with respect to the conductor wiring 2 can be easily ensured. That is, if the positional deviation of the long hole pattern 4a with respect to the conductor wiring 2 is within an allowable range, the conductor wiring 2 and the long hole pattern 4a always intersect and the conductor wiring 2 is exposed. Since the metal plating grows on the upper surface and the side surface of the conductor wiring 2, it is formed in a fixed shape and size regardless of the positional deviation of the long hole pattern 4a, and the designed conditions can be satisfied. Accordingly, the alignment of the exposure mask 5 does not require strict accuracy and adjustment is easy.

突起電極3を銅で形成する場合、金属めっきの一例としては、めっき液として硫酸銅を用い、0.3〜5A/dm2の条件で電解めっきを行う。電解めっきは、突起電極3を図
2(c)に示したような断面形状で十分な厚みで形成するために好適である。
When the protruding electrode 3 is formed of copper, as an example of metal plating, copper sulfate is used as a plating solution, and electrolytic plating is performed under conditions of 0.3 to 5 A / dm2. Electrolytic plating is suitable for forming the protruding electrode 3 with a sufficient thickness with a cross-sectional shape as shown in FIG.

次に、本実施の形態の製造方法を実施する際に発生する、露光マスク5の位置ずれに起因する問題を解決する方法について説明する。まず、半導体素子の電極パッドとテープキャリア基板6の導体配線2の相互の配置関係について、図4〜図6を参照して説明する。   Next, a method for solving the problem caused by the positional deviation of the exposure mask 5 that occurs when the manufacturing method of the present embodiment is performed will be described. First, the mutual arrangement relationship between the electrode pads of the semiconductor element and the conductor wiring 2 of the tape carrier substrate 6 will be described with reference to FIGS.

図4は、半導体素子の一例を示す平面図である。半導体素子21の面に形成された電極パッドの配置が示される。半導体素子7の長辺方向に配列された電極パッドを8aで示し、短辺方向に配列された電極パッドを8bで示す。電極パッド8aは、電極パッド8bに比べて多数、高密度に配置されている。C1は、半導体素子7の中心(半導体素子中心と記す)を示す。Dは、電極パッド8aの端縁とC1との間の距離である。S1は、電極パッド8aの端縁と電極パッド8bの側縁の間の間隔である。L1は電極パッド8aの長さ、W1は電極パッド8aの幅である。   FIG. 4 is a plan view showing an example of a semiconductor element. The arrangement of the electrode pads formed on the surface of the semiconductor element 21 is shown. An electrode pad arranged in the long side direction of the semiconductor element 7 is indicated by 8a, and an electrode pad arranged in the short side direction is indicated by 8b. A large number of electrode pads 8a are arranged at a higher density than the electrode pads 8b. C1 indicates the center of the semiconductor element 7 (referred to as the semiconductor element center). D is the distance between the edge of the electrode pad 8a and C1. S1 is the distance between the edge of the electrode pad 8a and the side edge of the electrode pad 8b. L1 is the length of the electrode pad 8a, and W1 is the width of the electrode pad 8a.

図5は、テープキャリア基板の製造に用いられる、導体配線2が形成されたフィルム基材1の一部を示す平面図である。C2は、半導体素子7が搭載されるべき領域の中心(半導体素子搭載部中心と記す)を示す。dは、導体配線2の端縁と半導体素子搭載部中心C2の間の距離である。   FIG. 5 is a plan view showing a part of the film base material 1 on which the conductor wiring 2 is formed, which is used for manufacturing the tape carrier substrate. C2 indicates the center of the region where the semiconductor element 7 is to be mounted (referred to as the center of the semiconductor element mounting portion). d is the distance between the edge of the conductor wiring 2 and the semiconductor element mounting portion center C2.

図6は、本実施の形態の製造方法により、導体配線2上に突起電極3が形成されたテープキャリア基板6の半導体搭載部を示す平面図である。この図における突起電極3は、図3(c1)における露光マスク5が導体配線2に対して位置ずれの無い状態で形成された場合を示す。L2は突起電極3の長さ、W2は突起電極3の幅である。   FIG. 6 is a plan view showing a semiconductor mounting portion of the tape carrier substrate 6 in which the protruding electrode 3 is formed on the conductor wiring 2 by the manufacturing method of the present embodiment. The protruding electrode 3 in this figure shows a case where the exposure mask 5 in FIG. 3C1 is formed with no positional deviation with respect to the conductor wiring 2. L2 is the length of the protruding electrode 3, and W2 is the width of the protruding electrode 3.

導体配線2の長さ方向への露光マスク5の位置ずれを考慮すると、半導体素子中心C1
から電極パッド8aまでの距離Dよりも、半導体素子搭載部中心C2から導体配線2までの距離dを短くすることが望ましい。また、電極パッド8aの長さL1よりも、突起電極3の長さL2を長くすることが望ましい。そうすれば、露光マスク5の位置ずれに起因して、形成された突起電極3の位置が導体配線2の長さ方向にずれても、電極パッド8aと突起電極3が対向する面積を十分な大きさに確保可能である。
Considering the positional shift of the exposure mask 5 in the length direction of the conductor wiring 2, the semiconductor element center C1
It is desirable to make the distance d from the semiconductor element mounting portion center C2 to the conductor wiring 2 shorter than the distance D from the electrode pad 8a. Further, it is desirable to make the length L2 of the protruding electrode 3 longer than the length L1 of the electrode pad 8a. Then, even if the position of the formed protruding electrode 3 is shifted in the length direction of the conductor wiring 2 due to the displacement of the exposure mask 5, the area where the electrode pad 8a and the protruding electrode 3 face each other is sufficient. The size can be secured.

また、図7は、図6と同様、本実施の形態の製造方法により、導体配線2上に突起電極3が形成されたテープキャリア基板6の半導体搭載部を示す平面図である。この図における突起電極3は、図3(c1)における露光マスク5が導体配線2に対してフィルム基材1の短辺方向に位置ずれした状態で形成された場合を示す。S2は、フィルム基材1の長辺方向に配列された導体配線2上の突起電極3の端縁と、短辺方向に配列された導体配線2の側縁の間の間隔である。   7 is a plan view showing a semiconductor mounting portion of the tape carrier substrate 6 in which the protruding electrodes 3 are formed on the conductor wiring 2 by the manufacturing method of the present embodiment, as in FIG. The protruding electrode 3 in this figure shows a case where the exposure mask 5 in FIG. 3 (c 1) is formed in a state of being displaced in the short side direction of the film substrate 1 with respect to the conductor wiring 2. S2 is the distance between the edge of the protruding electrode 3 on the conductor wiring 2 arranged in the long side direction of the film substrate 1 and the side edge of the conductor wiring 2 arranged in the short side direction.

図7に示す状態の場合、突起電極3の大きさは全て設計した寸法を満足できるが、導体配線2と露光マスク5の位置ずれの方向に起因して、図4に示す間隔S1と図7に示す間隔S2に相違を生じている。つまり、露光マスク5がフィルム基材1の短辺方向に位置ずれした場合、フィルム基材1の長辺方向に配置された導体配線2上では、突起電極3の位置が導体配線2の長手方向に移動するのに対して、フィルム基材1の短辺方向に配置された導体配線2上では、突起電極3の位置が移動しないからである。この問題を解決する方法を図8および9に示す。   In the state shown in FIG. 7, the size of the protruding electrode 3 can satisfy all the designed dimensions. However, due to the direction of positional deviation between the conductor wiring 2 and the exposure mask 5, the distance S1 shown in FIG. There is a difference in the interval S2 shown in FIG. That is, when the exposure mask 5 is displaced in the short side direction of the film substrate 1, the position of the protruding electrode 3 is the longitudinal direction of the conductor wire 2 on the conductor wire 2 arranged in the long side direction of the film substrate 1. This is because the position of the protruding electrode 3 does not move on the conductor wiring 2 arranged in the short side direction of the film substrate 1. A method for solving this problem is shown in FIGS.

図8は、図3(c1)の工程で用いる露光マスク5のパターンを変更した露光マスク9を示す。この露光マスク9は、フィルム基材1の長辺に対応する部分の光透過領域9aが連続した長孔形状を有すのに対して、短辺に対応する部分の光透過領域9bは、個別の開口が配置された離散的形状を有する。併せて、図9に示すように導体配線10a、10bが形成されたフィルム基材1を用いる。この形態では、フィルム基材1の長辺方向に配列された導体配線10aに比べて、短辺方向に配列された導体配線10bは幅が広い。   FIG. 8 shows an exposure mask 9 in which the pattern of the exposure mask 5 used in the step of FIG. The exposure mask 9 has a long hole shape in which the light transmission region 9a corresponding to the long side of the film substrate 1 is continuous, whereas the light transmission region 9b corresponding to the short side is individually formed. Have a discrete shape with a plurality of openings arranged therein. In addition, as shown in FIG. 9, a film substrate 1 on which conductor wirings 10a and 10b are formed is used. In this embodiment, the conductor wiring 10b arranged in the short side direction is wider than the conductor wiring 10a arranged in the long side direction of the film substrate 1.

上述の露光マスク9を用いて、上述の導体配線10a、10bの上にフォトレジストの開口パターンを形成し金属めっきを施せば、設計したサイズの突起電極3が得られ、かつ図4に示す間隔S1と図7に示す間隔S2を同一にできる。すなわち、図8の露光マスク9がフィルム基材1の短辺方向に位置ずれした場合、図9のフィルム基材1の短辺方向に配置された導体配線10b上では、露光マスク9の光透過領域9bが幅方向に移動し、形成される突起電極3の位置が図9に示すように移動する。しかも、導体配線10bが幅広に形成されているので、移動量が許容範囲内であれば、所定のサイズで突起電極3が形成される。その移動量は、フィルム基材1の長辺方向に配置された導体配線10a上で、突起電極3の位置が導体配線10aの長手方向に移動する量と同等である。その結果、S1とS2が同一になる。   By using the above-described exposure mask 9 to form a photoresist opening pattern on the above-described conductor wirings 10a and 10b and performing metal plating, the projected electrodes 3 having the designed size can be obtained, and the intervals shown in FIG. The interval S2 shown in FIG. 7 can be made the same as S1. That is, when the exposure mask 9 in FIG. 8 is displaced in the short side direction of the film substrate 1, the light transmission of the exposure mask 9 is performed on the conductor wiring 10b arranged in the short side direction of the film substrate 1 in FIG. The region 9b moves in the width direction, and the position of the protruding electrode 3 to be formed moves as shown in FIG. Moreover, since the conductor wiring 10b is formed wide, the protruding electrode 3 is formed with a predetermined size if the movement amount is within an allowable range. The amount of movement is equivalent to the amount by which the position of the protruding electrode 3 moves in the longitudinal direction of the conductor wiring 10a on the conductor wiring 10a arranged in the long side direction of the film substrate 1. As a result, S1 and S2 are the same.

図10は、図3(c1)に示した工程に対応し、別の形態の露光マスク11を用いる場合を示す。この形態では、露光マスク11には、図3(c1)における露光マスク5の光透過領域5aに対応する位置に、光遮断領域11aが形成されている。この露光マスク11は、フォトレジスト4がネガ型の場合に適用する。露光マスク11に関する他の条件は、図3(c1)の露光マスク5と同様である。   FIG. 10 corresponds to the step shown in FIG. 3C1, and shows a case where an exposure mask 11 of another form is used. In this embodiment, a light blocking area 11a is formed in the exposure mask 11 at a position corresponding to the light transmission area 5a of the exposure mask 5 in FIG. This exposure mask 11 is applied when the photoresist 4 is a negative type. Other conditions regarding the exposure mask 11 are the same as those of the exposure mask 5 in FIG.

(実施の形態3)
図11を参照して、実施の形態3におけるテープキャリア基板の構造およびその製造方法について説明する。本実施の形態では、フィルム基材1上に形成された導体配線12は、先端部12aが他の基端部12bよりも細くなった形状を有する。これは、以下の理由による。
(Embodiment 3)
With reference to FIG. 11, the structure of the tape carrier substrate and the manufacturing method thereof in the third embodiment will be described. In this Embodiment, the conductor wiring 12 formed on the film base material 1 has the shape where the front-end | tip part 12a became thinner than the other base end part 12b. This is due to the following reason.

すなわち、図3(e)に示した電解金属めっきによる突起電極3の形成時には、導体配線2の幅方向にも銅めっき層が成長する。そのため、隣接する導体配線2から幅方向に成長する銅めっき層どうしが短絡する惧れがある。それを回避するために導体配線2の相互間隔を広くすれば、導体配線2の密度が低下し、半導体装置の小型化の障害となる。   That is, a copper plating layer grows also in the width direction of the conductor wiring 2 when the protruding electrode 3 is formed by electrolytic metal plating shown in FIG. For this reason, there is a possibility that the copper plating layers grown in the width direction from the adjacent conductor wiring 2 may be short-circuited. If the interval between the conductor wirings 2 is increased in order to avoid this, the density of the conductor wirings 2 is lowered, which becomes an obstacle to miniaturization of the semiconductor device.

そこで本実施の形態のように、導体配線12の先端部12aを細くし、この細い部分に突起電極3を形成すれば、導体配線12の幅方向に銅めっき層が成長した際に、隣接する銅めっき層間で短絡が発生する惧れが軽減される。   Therefore, if the tip end portion 12a of the conductor wiring 12 is thinned and the protruding electrode 3 is formed on this thin portion as in this embodiment, the copper plating layer is adjacent when the copper plating layer grows in the width direction of the conductor wiring 12. The possibility of short circuit between copper plating layers is reduced.

(実施の形態4)
図12を参照して、実施の形態4における半導体装置およびその製造方法について説明する。テープキャリア基板8は、上述の実施の形態に記載されたように、フィルム基材1の上に配置された複数本の導体配線2に各々突起電極3が形成され、突起電極3は図2に示したような形状を有する。すなわち、導体配線2を横切って導体配線2の両側の領域に亘り、導体配線2の幅方向における断面形状が、導体配線2の上面および両側面に接合された形状である。また、導体配線2の幅方向における断面形状は、中央部が両側よりも高くなった中高である。テープキャリア基板8上に実装された半導体素子21は、その電極パッド27に突起電極3が接続され、テープキャリア基板8と半導体素子21の間には、封止樹脂22が充填されている。
(Embodiment 4)
With reference to FIG. 12, the semiconductor device and the manufacturing method thereof in the fourth embodiment will be described. As described in the above-described embodiment, the tape carrier substrate 8 is formed with the protruding electrodes 3 on the plurality of conductor wirings 2 arranged on the film base 1, and the protruding electrodes 3 are shown in FIG. It has the shape as shown. That is, the cross-sectional shape in the width direction of the conductor wiring 2 is a shape joined to the upper surface and both side surfaces of the conductor wiring 2 over the regions on both sides of the conductor wiring 2 across the conductor wiring 2. Moreover, the cross-sectional shape in the width direction of the conductor wiring 2 is a medium height with the center portion being higher than both sides. The protruding element 3 is connected to the electrode pad 27 of the semiconductor element 21 mounted on the tape carrier substrate 8, and a sealing resin 22 is filled between the tape carrier substrate 8 and the semiconductor element 21.

この半導体装置の製造に際しては、上述の実施の形態における製造方法により作製されたテープキャリア基板8上に半導体素子21を搭載し、ボンディングツール13により押圧する。その際、ボンディングツール13を介して超音波を印加することが望ましい。それにより、突起電極3の凸状に形成された先端が、電極パッド27の表面層の酸化膜に当接して振動するための、酸化膜を破砕する効果が顕著になる。   In manufacturing this semiconductor device, the semiconductor element 21 is mounted on the tape carrier substrate 8 manufactured by the manufacturing method in the above-described embodiment and pressed by the bonding tool 13. At that time, it is desirable to apply ultrasonic waves through the bonding tool 13. As a result, the effect of crushing the oxide film is prominent because the tip of the protruding electrode 3 formed in a convex shape abuts against the oxide film on the surface layer of the electrode pad 27 and vibrates.

また、図13に示すような方法により、半導体素子21をテープキャリア基板8上に実装することもできる。すなわち図13(a)に示すように、テープキャリア基板8の突起電極3が形成された領域を覆って封止樹脂14を充填する。次に、半導体素子21とテープキャリア基板8を対向させ、両者を互いに向かって押圧して、図13(b)に示すように、電極パッド27に突起電極3を当接させる。その際、中高で凸状である突起電極3の上面により、封止樹脂14が両脇に効果的に排除されて、突起電極3と電極パッド27を容易に当接させることができる。   Further, the semiconductor element 21 can be mounted on the tape carrier substrate 8 by a method as shown in FIG. That is, as shown in FIG. 13A, the sealing resin 14 is filled so as to cover the region of the tape carrier substrate 8 where the protruding electrodes 3 are formed. Next, the semiconductor element 21 and the tape carrier substrate 8 are opposed to each other and pressed toward each other, so that the protruding electrode 3 is brought into contact with the electrode pad 27 as shown in FIG. At that time, the sealing resin 14 is effectively removed on both sides by the upper surface of the protruding electrode 3 having a medium and high convex shape, and the protruding electrode 3 and the electrode pad 27 can be easily brought into contact with each other.

本発明の半導体素子によれば、半導体素子の電極パッドと突起電極が対向する面積を十分な大きさに確保可能であるので、チップオンフィルム(COF)に用いられるテープキャリア基板として有用である。   According to the semiconductor element of the present invention, the area where the electrode pad and the protruding electrode of the semiconductor element are opposed to each other can be secured to a sufficient size, so that it is useful as a tape carrier substrate used for a chip-on-film (COF).

実施の形態1におけるテープキャリア基板の一部を示す斜視図The perspective view which shows a part of tape carrier board | substrate in Embodiment 1. FIG. (a)は同テープキャリア基板の一部を示す平面図、(b)は断面で示した正面図、(c)は(b)におけるA−A断面図(A) is a plan view showing a part of the tape carrier substrate, (b) is a front view shown in cross section, (c) is a cross-sectional view taken along line AA in (b). 実施の形態2におけるテープキャリア基板の製造方法を示し、(a1)〜(f1)は、突起電極を形成する製造工程における、フィルム基材上の半導体素子搭載部の平面図、(a2)〜(f2)は各々、(a1)〜(f1)の拡大断面図The manufacturing method of the tape carrier board | substrate in Embodiment 2 is shown, (a1)-(f1) is a top view of the semiconductor element mounting part on a film base material in the manufacturing process which forms a protruding electrode, (a2)-( f2) are enlarged sectional views of (a1) to (f1), respectively. 半導体素子の一例を示す平面図Plan view showing an example of a semiconductor element テープキャリア基板の製造に用いられる、導体配線が形成されたフィルム基材を示す平面図The top view which shows the film base material in which the conductor wiring was formed used for manufacture of a tape carrier substrate 実施の形態2の製造方法により製造されたテープキャリア基板の一例の半導体搭載部を示す平面図The top view which shows the semiconductor mounting part of an example of the tape carrier substrate manufactured by the manufacturing method of Embodiment 2 実施の形態2の製造方法により製造されたテープキャリア基板の他の例の半導体搭載部を示す平面図The top view which shows the semiconductor mounting part of the other example of the tape carrier board manufactured by the manufacturing method of Embodiment 2. FIG. 実施の形態2における露光マスクの一例を示す平面図Plan view showing an example of an exposure mask in the second embodiment 実施の形態2における変形例の導体配線が設けられたテープキャリア基板を示す平面図The top view which shows the tape carrier board | substrate with which the conductor wiring of the modification in Embodiment 2 was provided 実施の形態2における他の例の露光マスクを用いる露光工程を示し、(a)は平面図、(b)は拡大断面図The exposure process using the exposure mask of the other example in Embodiment 2 is shown, (a) is a top view, (b) is an expanded sectional view 実施の形態3におけるテープキャリア基板を示す平面図FIG. 9 is a plan view showing a tape carrier substrate in the third embodiment. 実施の形態4における半導体装置を示す断面図Sectional drawing which shows the semiconductor device in Embodiment 4 実施の形態4における半導体装置の製造方法の他の例を示す断面図Sectional drawing which shows the other example of the manufacturing method of the semiconductor device in Embodiment 4. FIG. 従来例のCOFの一部を示す断面図Sectional drawing which shows a part of COF of a prior art example 従来例のテープキャリア基板の製造工程を説明するための図であり、(a1)〜(f1)はフィルム基材の一部を示す平面図、(a2)〜(f2)は各々その断面図It is a figure for demonstrating the manufacturing process of the tape carrier board | substrate of a prior art example, (a1)-(f1) is a top view which shows a part of film base material, (a2)-(f2) is each sectional drawing. 図15の製造工程により作製されたテープキャリア基板の一部を示す断面図Sectional drawing which shows a part of tape carrier board produced by the manufacturing process of FIG. 図16のテープキャリア基板に半導体素子を実装する様子を示す断面図Sectional drawing which shows a mode that a semiconductor element is mounted in the tape carrier substrate of FIG. 図15の製造工程の課題を説明するためにテープキャリア基板の一部を示す平面図FIG. 15 is a plan view showing a part of a tape carrier substrate for explaining the problem of the manufacturing process of FIG.

符号の説明Explanation of symbols

1、23 フィルム基材
2、12、24 導体配線
3、28 突起電極
4、29 フォトレジスト
4a 長孔状パターン
5、9、11、30 露光マスク
5a、9a、11a、30a 光透過領域
6、20 テープキャリア基板
7、21 半導体素子
8a、8b 電極パッド
10a、10b 導体配線
12a 先端部
12b 基端部
13 ボンディングツール
14、22 封止樹脂
25 金属めっき被膜
26 ソルダーレジスト
27 電極パッド
29a 開口パターン
1, 23 Film substrate 2, 12, 24 Conductor wiring 3, 28 Protruding electrode 4, 29 Photoresist 4a Elongated pattern 5, 9, 11, 30 Exposure mask 5a, 9a, 11a, 30a Light transmission region 6, 20 Tape carrier substrate 7, 21 Semiconductor element 8a, 8b Electrode pad 10a, 10b Conductor wiring 12a Tip portion 12b Base end portion 13 Bonding tool 14, 22 Sealing resin 25 Metal plating film 26 Solder resist 27 Electrode pad 29a Opening pattern

Claims (1)

絶縁性基材、前記絶縁性基材上に整列して設けられた複数本の導体配線、及び前記複数本の導体配線の各々に形成された突起電極を備えた配線基板と、前記配線基板上に搭載された半導体素子とを備え、
前記突起電極と前記半導体素子の電極パッドとが電気的に接続され、前記半導体素子の中心線と前記電極パッドとの間の距離が、前記配線基板の前記半導体素子の搭載部の中心線と前記導体配線との間の距離よりも大きいことを特徴とする半導体装置。
Insulating substrate, a plurality of conductor wirings arranged in alignment on the insulating substrate, and a wiring board comprising projecting electrodes formed on each of the plurality of conductor wirings, and on the wiring substrate With a semiconductor element mounted on the
The protruding electrode and the electrode pad of the semiconductor element are electrically connected, and the distance between the center line of the semiconductor element and the electrode pad is such that the center line of the mounting portion of the semiconductor element on the wiring board A semiconductor device characterized by being larger than a distance between the conductor wiring.
JP2007312500A 2007-12-03 2007-12-03 Semiconductor device Pending JP2008072148A (en)

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Application Number Priority Date Filing Date Title
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JP2004136009A Division JP4108641B2 (en) 2004-04-30 2004-04-30 Wiring substrate manufacturing method and semiconductor device manufacturing method

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Publication Number Publication Date
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05206204A (en) * 1991-04-17 1993-08-13 Oki Electric Ind Co Ltd Mounting method of electronic parts onto board using conductive particles
JPH10308414A (en) * 1997-03-05 1998-11-17 S I I R D Center:Kk Mounting structure
JP2001127102A (en) * 1999-10-25 2001-05-11 Sony Corp Semiconductor device and manufacturing method thereof
JP2001168129A (en) * 1999-12-10 2001-06-22 Sony Chem Corp Method for producing contact structure

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05206204A (en) * 1991-04-17 1993-08-13 Oki Electric Ind Co Ltd Mounting method of electronic parts onto board using conductive particles
JPH10308414A (en) * 1997-03-05 1998-11-17 S I I R D Center:Kk Mounting structure
JP2001127102A (en) * 1999-10-25 2001-05-11 Sony Corp Semiconductor device and manufacturing method thereof
JP2001168129A (en) * 1999-12-10 2001-06-22 Sony Chem Corp Method for producing contact structure

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