JP2008042038A - Electronic apparatus and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To miniaturize an electronic apparatus with a semiconductor device mounted therein by reducing a mount area of the semiconductor device. <P>SOLUTION: An RF power module PM1 includes a wiring board 101, a semiconductor chip CHP1 and a passive component 102 mounted on the wiring board 101, and a sealing resin 103 covering them. Within the semiconductor chip CHP1, an LDMOSFET is formed which constitutes a power amplification circuit of the RF power module PM1, and mounted on an upper face of the wiring board 101 by a flip chip. A bump electrode 108 formed on a surface 107a of the semiconductor chip CHP1 is electrically connected with a conductor pattern 105a on the upper face of the wiring board 101. The bump electrode 108 includes the bump electrodes 108 for the drain, gate and source of the LDMOSFET constituting the power amplification circuit. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an electronic device and a semiconductor device, and more particularly to a technology effective when applied to a power amplification module mounted on a mobile communication device and a semiconductor device used therefor.

  In recent years, mobile communication devices (so-called mobile phones) represented by communication methods such as GSM (Global System for Mobile Communications), PCS (Personal Communication Systems), PDC (Personal Digital Cellular), and CDMA (Code Division Multiple Access) Phone) is widespread worldwide.

  In general, this type of mobile communication device includes an antenna that emits and receives radio waves, a high-frequency power amplifier (RF power module) that amplifies a power-modulated high-frequency signal and supplies the signal to the antenna, and a high-frequency signal received by the antenna. A receiving unit that performs signal processing, a control unit that performs these controls, and a battery (battery) that supplies a power supply voltage thereto are configured.

In WO 2005/024931 A1 pamphlet (Patent Document 1), the drift (offset drain) region interposed between the gate electrode of the power MOSFET and the n ⁺ -type drain region has a double offset structure. By making the impurity concentration in the near n ⁻ -type drift (offset drain) region relatively low and making the impurity concentration in the n-type drift (offset drain) region separated from the gate electrode relatively high, there is conventionally a trade-off between them. A technique for reducing both the on-resistance and the feedback capacitance, which are related, is described.

In addition, International Publication No. 2005/015636 A1 pamphlet (Patent Document 2) describes power amplifier circuits of different systems constituting the RF power module of a dual-type digital mobile phone capable of handling high frequency signals in two frequency bands. Are arranged in the same IC chip, a power amplifying circuit is arranged around the IC chip, and a peripheral circuit is arranged between the power amplifying circuits.
International Publication No. 2005/024931 A1 Pamphlet International Publication No. 2005/015636 A1 Pamphlet

  According to the study of the present inventor, the following has been found.

  In recent years, along with demands for downsizing, thinning, and high performance of mobile communication devices, electronic devices such as RF power modules mounted thereon are also required to be downsized, thinned, and high performance. Yes. The RF power module has a structure in which an electronic component such as a semiconductor amplifying element chip or a passive component is mounted on a wiring board, and it is desired to reduce the size and thickness of each electronic component.

  However, there is a limit to downsizing the electronic components mounted on the wiring board, and it is not efficient to reduce the size of the RF power module only by downsizing the electronic components.

  On the other hand, in the RF power module, a semiconductor amplifying element chip is mounted on a wiring board, and the electrodes of the semiconductor amplifying element chip are electrically connected to terminals of the wiring board via bonding wires.

  When a semiconductor amplifying element chip is mounted on a wiring board and the electrodes of the semiconductor amplifying element chip and the terminals of the wiring board are wire-bonded, in addition to the area of the semiconductor amplifying element chip itself, the area required for arranging bonding wires Must be secured around the mounted semiconductor amplifying element chip, the mounting area of the semiconductor amplifying element chip is increased, and the planar dimension of the wiring board constituting the RF power module is increased. This hinders miniaturization of electronic devices such as RF power modules.

  An object of the present invention is to provide a technique capable of downsizing an electronic device.

  Another object of the present invention is to provide a technique capable of reducing the mounting area of a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The present invention is an electronic device having a power amplifier circuit, comprising: a wiring board; and a semiconductor chip on which an LDMOSFET element constituting the power amplifier circuit is formed and flip-chip mounted on the main surface of the wiring board. Is.

  The present invention also includes a semiconductor device including an LDMOSFET element constituting a power amplifier circuit and having a plurality of bump electrodes formed on a surface thereof, the semiconductor substrate and a semiconductor layer formed on the main surface of the semiconductor substrate And a source region and a drain region of the LDMOSFET element formed in the first active region for forming the LDMOSFET element of the semiconductor layer, and a gate insulating film on the first active region of the semiconductor layer. In addition, the gate electrode of the LDMOSFET element, a first punched layer formed in the first active region of the semiconductor layer, and a second active region formed in a second active region different from the first active region of the semiconductor layer. A plurality of bump electrodes including a source bump electrode, and the wiring structure includes the source layer; and a wiring layer formed on the semiconductor layer. A first source wiring electrically connected to the bump electrode, wherein the source region is electrically connected to the semiconductor substrate via the first punching layer, and the semiconductor substrate is electrically connected to the second punching layer. The second punched layer is electrically connected to the first source wiring.

  The present invention also provides a semiconductor device including an LDMOSFET element constituting a power amplifier circuit and having a plurality of bump electrodes formed on a surface thereof, and a semiconductor substrate and a first active region for forming the LDMOSFET element on the semiconductor substrate. A source region and a drain region of the LDMOSFET element formed on the semiconductor substrate, and a gate electrode of the LDMOSFET element formed on the first active region of the semiconductor substrate via a gate insulating film. A drain bump electrode electrically connected to the drain region; a gate bump electrode electrically connected to the gate electrode; and a source bump electrode electrically connected to the source region. The drain bump electrode and the source bump electrode are arranged at a planar position facing each other through the first active region. It is one in which the gate bump electrode is arranged between a and near to become planar position of the first active region between the source bump electrode and the drain bump electrode.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  The electronic device can be downsized.

  In addition, the mounting area of the semiconductor device can be reduced.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view or a perspective view may be hatched to make the drawing easy to see.

(Embodiment 1)
In this embodiment, for example, a power amplification module (electronic) such as an RF (Radio Frequency) power module used (installed) in a digital cellular phone (mobile communication device) that transmits information using a network such as the GSM system. Device) and a semiconductor chip (semiconductor device) used (mounted).

  Here, GSM (Global System for Mobile Communication) refers to one or standard of a wireless communication method used for digital mobile phones. GSM has three frequency bands of radio waves to be used: 900 MHz band (824 to 915 MHz) is GSM900 or simply GSM, 1800 MHz band (1710 to 1910 MHz) is GSM1800 or DCS (Digital Cellular System) 1800 or PCN, 1900 MHz band Is called GSM1900, DCS1900 or PCS (Personal Communication Services). GSM1900 is mainly used in North America. In North America, GSM850 in the 850 MHz band may also be used. The RF power module PM1 of the present embodiment is an RF power module used in these frequency bands (high frequency bands), for example.

  FIG. 1 shows a circuit block diagram of an RF power module (high-frequency power amplifier, power amplifier module, power amplifier module, semiconductor device, electronic device) PM1 of the present embodiment. In this figure, for example, two frequency bands of GSM900 and DCS1800 can be used (dual band system), and GMSK (Gaussian filtered Minimum Shift Keying) modulation system and EDGE (Enhanced Data GSM Environment) modulation system in each frequency band. The circuit block diagram (amplifier circuit) of the RF power module which can use two communication systems is shown. Note that the GMSK modulation method is a method used for communication of audio signals, and is a method of shifting the phase of a carrier wave according to transmission data. The EDGE modulation method is a method used for data communication and is a method in which an amplitude shift is further added to the phase shift of GMSK modulation.

  As shown in FIG. 1, the circuit configuration of the RF power module PM1 includes two power amplifier circuits (high frequency power amplifier circuits) AMP1 and AMP2, bias circuits BAC1 and BAC2, power supply circuits PSC1 and PSC2, and a matching circuit. AJC1, AJC2, AJC3, AJC4, detection circuits DEC1, DEC2, and the like are included. Therefore, the RF power module PM1 is an electronic device having the power amplifier circuits AMP1 and AMP2.

  The power amplifier circuit AMP1 is a power amplifier circuit for GSM900, and has a multi-stage configuration in which a plurality of amplifier circuits (amplifier stages), here, three amplifier stages (amplifier circuits) AMP11, AMP12, and AMP13 are connected in multistage. Yes. The power amplifier circuit AMP2 is a power amplifier circuit for the DCS 1800, and has a multistage configuration in which a plurality of amplifier circuits (amplifier stages), here, three amplifier stages (amplifier circuits) AMP21, AMP22, and AMP23 are connected in multistage. Yes.

  The bias circuit BAC1 is a bias circuit that applies a bias voltage to each of the amplification stages AMP11 to AMP13 of the power amplifier circuit AMP1. The bias circuit BAC2 is a bias circuit that applies a bias voltage to each of the amplification stages AMP21 to AMP23 of the power amplifier circuit AMP2.

  The power supply circuit PSC1 is a power supply circuit that generates a power supply voltage to be applied to the drain terminal of the output LDMOSFET of each amplification stage AMP11 to AMP13 of the power amplifier circuit AMP1. The power supply circuit PSC2 is a power supply circuit that generates a power supply voltage that is applied to the drain terminal of the output LDMOSFET of each of the amplification stages AMP21 to AMP23 of the power amplifier circuit AMP2.

  The matching circuit AJC1 is a matching circuit (input matching circuit) between the input terminal IPT1 for GSM900 and the power amplification circuit AMP1 (first amplification stage AMP11) for GSM900. The matching circuit AJC3 is a matching circuit (output matching circuit) between the output terminal OPT1 for GSM900 and the power amplification circuit AMP1 (third amplification stage AMP13) for GSM900. The matching circuit AJC2 is a matching circuit (input matching circuit) between the input terminal IPT2 for DCS1800 and the power amplifier circuit AMP2 (first amplification stage AMP21) for DCS1800. The matching circuit AJC4 is a matching circuit (output matching circuit) between the output terminal OPT2 for DCS1800 and the power amplifier circuit AMP2 (third amplifier stage AMP23) for DCS1800. Each matching circuit is a circuit that performs impedance matching.

  The detection circuit DEC1 is a detection circuit for detecting an output (output signal, output power) from the power amplification circuit AMP1 for GSM900. The detection circuit DEC2 is a detection circuit for detecting an output (output signal, output power) from the power amplification circuit AMP2 for DCS1800.

  Among these circuits, the power amplification circuit AMP1 (amplification stages AMP11 to AMP13) for GSM900, the power amplification circuit AMP2 (amplification stages AMP21 to AMP23) for DCS1800, the bias circuits BAC1 and BAC2, and the detection circuits DEC1 and DEC2 are: One semiconductor chip (semiconductor amplification element chip, high frequency power amplification element chip, semiconductor device) is formed in CHP1.

  Although not shown, a matching circuit (interstage matching circuit) may be provided between the amplification stages AMP12 to AMP13 and between the amplification stages AMP21 to AMP23. Although not shown, a GSM900 low-pass filter may be provided between the matching circuit AJC3 and the GSM900 output terminal OPT1, and a DCS1800 low-pass filter is provided between the matching circuit AJC4 and the DCS1800 output terminal OPT2. Can also be provided. The low-pass filter is a circuit that attenuates harmonics.

  The RF input signal input to the input terminal IPT1 for GSM900 of the RF power module PM1 is input to the semiconductor chip CHP1 through the matching circuit AJC1, and the power amplifier circuit AMP1 in the semiconductor chip CHP1, that is, the three amplification stages AMP11 to AMP13. Is output from the semiconductor chip CHP1 and output as an RF output signal from the output terminal OPT1 for GSM900 via the matching circuit AJC3.

  The RF input signal input to the input terminal IPT2 for DCS 1800 of the RF power module PM1 is input to the semiconductor chip CHP1 through the matching circuit AJC2, and the power amplifier circuit AMP2 in the semiconductor chip CHP1, that is, the three amplification stages AMP21 to AMP23. And output from the semiconductor chip CHP1 and output as an RF output signal from the output terminal OPT2 for DCS1800 through the matching circuit AJC4.

  The bias control signal input to the bias control signal input terminal BIT1 for GSM900 of the RF power module PM is input to the bias circuit BAC1, and is applied to the amplification stages AMP11 to AMP13 of the power amplifier circuit AMP1 based on the bias control signal. The bias voltage is controlled.

  The bias control signal input to the bias control signal input terminal BIT2 for DCS 1800 of the RF power module PM is input to the bias circuit BAC2, and is applied to the amplification stages AMP21 to AMP23 of the power amplifier circuit AMP2 based on the bias control signal. The bias voltage is controlled.

  The output (output signal, output power) from the power amplifier circuit AMP1 for GSM900 is detected by the detection circuit DEC1, and the detection signal (output power detection signal) detected by the detection circuit DEC1 is for GSM900 of the RF power module PM. The output detection signal is output from the output terminal OPT3.

  The output (output signal, output power) from the power amplifier circuit AMP2 for DCS1800 is detected by the detection circuit DEC2, and the detection signal (output power detection signal) detected by the detection circuit DEC2 is for the DCS1800 of the RF power module PM. The output detection signal is output from the output terminal OPT4.

  Each of the power amplifier circuits AMP1 and AMP2 includes three n-channel LDMOSFETs (Laterally Diffused Metal-Oxide-Semiconductor Field Effect Transistors, lateral diffusion MOSFETs) as the three amplification stages AMP11 to AMP13 and AMP21 to AMP23. ) Are sequentially connected in cascade (multi-stage connection). That is, each amplification stage AMP11, AMP12, AMP13, AMP21, AMP22, AMP23 is formed by an n-channel LDMOSFET element. Then, three n-channel LDMOSFETs (that is, an n-channel LDMOSFET constituting the amplification stage AMP11, an n-channel LDMOSFET constituting the amplification stage AMP12, and an n-channel LDMOSFET constituting the amplification stage AMP13) are sequentially connected (multistage connection). ) To form a power amplifier circuit AMP1. Further, three n-channel LDMOSFETs (that is, an n-channel LDMOSFET constituting the amplification stage AMP21, an n-channel LDMOSFET constituting the amplification stage AMP22, and an n-channel LDMOSFET constituting the amplification stage AMP23) are sequentially connected (multi-stage connection). ) To form a power amplifier circuit AMP2. In the present embodiment, three amplification stages are connected (multi-stage connection) to form each power amplifier circuit AMP1, AMP2. However, as another form, two amplification stages or four or more stages are used. It is also possible to connect the amplifier stages (multi-stage connection) to form the power amplifier circuits AMP1 and AMP2. In this case, each power amplifier circuit AMP1 and AMP2 is subordinate to two or four or more n-channel LDMOSFETs. Connected circuit configuration.

  Next, FIG. 2 shows an example of a digital cellular phone system DPS using the RF power module PM1 of the present embodiment. Reference numeral ANT in FIG. 2 is an antenna for transmitting and receiving signal radio waves, reference numeral 151 is a front-end module, reference numeral 152 is a voice signal converted into a baseband signal, a received signal is converted into a voice signal, and a modulation system switching signal. And a baseband circuit for generating a band switching signal, 153 is a modulation / demodulation circuit for down-converting and demodulating the received signal to generate a baseband signal and modulating the transmitted signal, and FLT1 and FLT2 are received from the received signal This filter removes noise and interference. The filter FLT1 is for GSM, and the filter FLT2 is for DCS. The baseband circuit 152 includes a plurality of semiconductor integrated circuits such as a DSP (Digital Signal Processor), a microprocessor, and a semiconductor memory. The front end module 151 includes switch circuits 154a and 154b, capacitors C5 and C6, and a duplexer 156. The switch circuits 154a and 154b are switch circuits for switching between transmission and reception, the capacitors C5 and C6 are elements for cutting a DC component from the received signal, and the demultiplexer 156 is a circuit for demultiplexing a signal in the GSM900 band and a signal in the DCS1800 band These circuits and elements are mounted on one wiring board to form a module. The switching signals CNT1 and CNT2 of the switch circuits 154a and 154b are supplied from the baseband circuit 152. Also, the switch circuits 154a and 154b can be provided in the RF power module PM1.

  FIG. 3 is a conceptual perspective view showing the structure of the RF power module PM1 of the present embodiment. FIG. 4 is a conceptual top view (plan view) of the RF power module PM1 of the present embodiment. FIG. 5 is a conceptual cross-sectional view (side cross-sectional view) of the RF power module PM1 of the present embodiment. 3 and 4 show a state in which the sealing resin 103 is seen through. 5 corresponds to a sectional view (side sectional view), but shows a conceptual structure of the RF power module PM1, and is completely different from a section obtained by cutting the structure of FIGS. 3 and 4 at a predetermined position. Does not match. FIGS. 3 and 4 are a perspective view and a plan view, respectively, but in order to make the drawings easy to see, the conductor pattern 105a on the upper surface 101a of the wiring board 101 is hatched with a satin (dot). .

  The RF power module PM1 of the present embodiment shown in FIGS. 3 to 5 includes a wiring board (multilayer board, multilayer wiring board, module board) 101 and a semiconductor chip (semiconductor) mounted (mounted) on the wiring board 101. Element, active element) CHP1, a passive component (passive element, chip component) 102 mounted (mounted) on the wiring substrate 101, and a sealing resin that covers the upper surface of the wiring substrate 101 including the semiconductor chip CHP1 and the passive component 102 (Sealing resin portion) 103. The semiconductor chip CHP1 and the passive component 102 are electrically connected to the conductor layer (transmission line) of the wiring board 101. Further, the RF power module PM1 can be mounted on, for example, an external circuit board (not shown) or a mother board.

The wiring board 101 is, for example, a multilayer wiring board (multilayer board) in which a plurality of insulator layers (dielectric layers) 104 and a plurality of conductor layers or wiring layers (not shown) are stacked and integrated. 3 and 5, the five insulating layers 104 are laminated to form the wiring board 101. However, the number of the laminated insulating layers 104 is not limited to this, and can be variously changed. . As a material for forming the insulator layer 104 of the wiring substrate 101, for example, a ceramic material such as alumina (aluminum oxide, Al ₂ O ₃ ) can be used. In this case, the wiring substrate 101 is a ceramic multilayer substrate. The material of the insulator layer 104 of the wiring board 101 is not limited to a ceramic material, and can be variously changed. For example, a glass epoxy resin may be used.

  Between the upper surface (front surface, main surface) 101a and lower surface (back surface, main surface) 101b of the wiring substrate 101 and between the insulator layers 104, there is a conductive layer (wiring layer, wiring pattern, conductive pattern) for wiring formation. Is formed. A conductor pattern (terminal, board side terminal, electrode, transmission line, wiring pattern) 105a made of a conductor is formed on the upper surface 101a of the wiring board 101 by the uppermost conductor layer of the wiring board 101, and the lowermost layer of the wiring board 101. The conductor layer forms an external connection terminal (terminal, external connection terminal, electrode, module electrode) 105b made of a conductor on the lower surface 101b of the wiring board 101. The conductor pattern 105a has a terminal portion to which the bump electrode 108 of the semiconductor chip CHP1 and the electrode of the passive component 102 are connected, and a wiring portion that connects the terminal portions.

  The external connection terminal 105b corresponds to, for example, the input terminals IPT1 and IPT2, the output terminals OPT1 and OPT2, the bias control signal input terminals BIT1 and BIT2, the output detection signal output terminals OPT3 and OPT4 in FIG. A conductor layer (wiring layer, wiring pattern, conductor pattern) is also formed inside the wiring substrate 101, that is, between the insulator layers 104, but is not shown in FIG. 5 for simplification. Of the wiring patterns formed by the conductor layer of the wiring substrate 101, a wiring pattern for supplying a reference potential (for example, the reference potential supplying terminal 105 c on the lower surface 101 b of the wiring substrate 101) is used for forming the wiring of the insulator layer 104. The wiring pattern for the transmission line can be formed as a belt-like pattern so as to cover the most area of the surface.

  Each conductor layer (wiring layer) constituting the wiring substrate 101 is electrically connected through a conductor or a conductor film in a via hole (through hole) 106 formed in the insulator layer 104 as necessary. Therefore, the conductor pattern 105a on the upper surface 101a of the wiring substrate 101 is formed by using the upper surface 101a of the wiring substrate 101 and / or an internal wiring layer (wiring layer between the insulator layers 104), a conductor film in the via hole 106, or the like. Via the external connection terminal 105b on the lower surface 101b of the wiring board 101.

  The semiconductor chip CHP1 is a semiconductor chip on which a semiconductor integrated circuit corresponding to a circuit configuration surrounded by a dotted line indicating the semiconductor chip CHP1 in the circuit block diagram of FIG. 1 is formed. Accordingly, in the semiconductor chip CHP1 (or the surface layer portion), LDMOSFET elements (LDMOSFET circuits 131A to 131C and 132A, which will be described later) as semiconductor amplifier elements constituting the amplification stages AMP11 to AMP13 and AMP21 to AMP23 of the power amplifier circuits AMP1 and AMP2. , 132C). In addition, elements (semiconductor elements or passive elements) constituting the bias circuits BAC1 and BAC2 and the detection circuits DEC1 and DEC2 are also formed in the semiconductor chip CHP1.

  Further, in the present embodiment, the LDMOSFET elements constituting the power amplifier circuits AMP1 and AMP2 (the amplification stages AMP11 to AMP13 and AMP21 to AMP23) are all formed in one semiconductor chip CHP1, thereby the RF power. The RF power module PM1 can be downsized by reducing the number of semiconductor chips used in the module PM1.

  A plurality of bump electrodes (projection electrodes) 108 are formed on the surface (main surface on the semiconductor element formation side) 107a of the semiconductor chip CHP1. The bump electrode 108 is, for example, a solder bump. Gold bumps or the like can also be used as the bump electrodes 108. The bump electrode 108 is electrically connected to an element (semiconductor element or passive element) formed on the semiconductor chip CHP1 or a semiconductor integrated circuit. The bump electrode 108 corresponds to the bump electrode 40 described later.

  The semiconductor chip CHP1 is formed by forming a semiconductor integrated circuit on a semiconductor substrate (semiconductor wafer) made of single crystal silicon or the like, and then grinding the back surface of the semiconductor substrate as necessary, and then dicing or the like to each semiconductor chip CHP1. It is separated. The manufacturing process and structure of the semiconductor chip CHP1 will be described later in detail.

  The semiconductor chip CHP1 is flip-chip connected (flip-chip mounted) on the upper surface 101a (main surface) of the wiring substrate 101. That is, the semiconductor substrate CHP1 has the back surface (main surface opposite to the main surface on the semiconductor element formation side) 107b facing upward and the front surface 107a facing the upper surface 101a of the wiring substrate 101. Is mounted (mounted) on the upper surface 101a. Accordingly, the semiconductor chip CHP1 is face-down bonded to the upper surface 101a of the wiring substrate 101. The bump electrodes 108 on the surface 107a of the semiconductor chip CHP1 are joined (mounted and connected) to and electrically connected to the conductor pattern 105a (terminal portion thereof) on the upper surface 101a of the wiring substrate 101. Therefore, an element (semiconductor element or passive element) or a semiconductor integrated circuit formed on the semiconductor chip CHP1 is electrically connected to the conductor pattern 105a (the terminal portion thereof) on the upper surface 101a of the wiring substrate 101 via the bump electrode 108. Has been.

  The passive component 102 includes a passive element such as a resistance element (for example, a chip resistor), a capacitance element (for example, a chip capacitor), or an inductor element (for example, a chip inductor), and includes, for example, a chip component. The passive component 102 is, for example, a passive component (passive component for the matching circuit of the power amplifier circuits AMP1 and AMP2) that constitutes the matching circuits (input matching circuits) AJC1 and AJC2, the matching circuits (output matching circuits) AJC3 and AJC4, and the like. . The passive component 102 is mounted (bonded or connected) to the conductive pattern 105a (terminal portion thereof) on the upper surface 101a of the wiring board 101 by a bonding material having good conductivity such as solder 109. In addition, a passive element constituting a matching circuit (an interstage matching circuit) between the amplification stages AMP12 to AMP13 and between the amplification stages AMP21 to AMP23 can also be constituted by the passive component 102. In addition, an interstage matching circuit can be configured by passive elements formed in the semiconductor chip CHP1. Further, the inductor element used for each matching circuit can be configured by the passive component 102, but can also be configured by a microstrip line formed by the conductor pattern of the wiring substrate 101 in addition to the passive component 102.

  Between the conductive patterns 105a (terminal portions thereof) on the upper surface 101a of the wiring substrate 101 to which the semiconductor chip CHP1 or the passive component 102 is electrically connected, the upper surface 101a of the wiring substrate 101 or an internal wiring layer or via hole 106 is provided as necessary. The wiring is connected via an inner conductor film or the like, and is electrically connected to the external connection terminal 105 b on the lower surface 101 b of the wiring substrate 101.

  The sealing resin 103 is formed on the upper surface 101a of the wiring substrate 101 so as to cover the semiconductor chip CHP1 and the passive component 102. The sealing resin 103 is made of, for example, a resin material such as an epoxy resin, and can contain a filler.

  FIG. 6 is a side view schematically showing a state where the RF power module PM1 of the present embodiment is mounted on a mounting board (wiring board) 111. FIG.

  As shown in FIG. 6, the RF power module PM1 and other components 112 (for example, passive components) are mounted on the upper surface 111a of the mounting substrate 111. At this time, the external connection terminal 105b of the RF power module PM1 is joined and electrically connected to the terminal 113 of the mounting substrate 111 via the solder 114 or the like, and the electrode of the component 112 is connected to the terminal 113 of the mounting substrate 111. And are electrically connected through solder 114 or the like. In addition, the reference potential supply terminal 105c of the RF power module PM1 is joined and electrically connected to the reference potential supply terminal 113c of the mounting substrate 111 via the solder 114 or the like. Therefore, the reference potential can be supplied from the reference potential supply terminal 113c of the mounting substrate 111 to the RF power module PM1 via the solder 114 and the reference potential supply terminal 113c.

  FIG. 7 is a perspective view showing an RF power module PM201 of a comparative example, and corresponds to FIG. Like FIG. 3 above, FIG. 7 also shows a state where the sealing resin is seen through, and in order to make the drawing easy to see, a satin (dot) hatching is applied to the conductor pattern 205a on the upper surface of the wiring board 201. It is attached.

  The RF power module PM201 of the comparative example shown in FIG. 7 has a semiconductor chip CHP201 (corresponding to CHP1 of the present embodiment) on the upper surface of the wiring substrate 201 (corresponding to the wiring substrate 101 of the present embodiment). A passive component 202 (corresponding to the passive component 102 of the present embodiment) is mounted, and a sealing resin (not shown) is formed so as to cover them.

  However, unlike the present embodiment, in the RF power module PM201 of the comparative example, the semiconductor chip CHP201 is die-bonded face-up on the upper surface of the wiring substrate 201, and the pad electrode on the surface of the semiconductor chip CHP201 is bonded to the bonding wire ( It is electrically connected to a conductor pattern 205a (corresponding to the conductor pattern 105a of the present embodiment) on the upper surface of the wiring board 201 via a metal wire 203. Further, the back electrode formed on the back surface of the semiconductor chip CHP201 is connected to the conductor pattern 205a on the top surface of the wiring board 201.

  In the RF power module PM201 of the comparative example, the bonding wire 203 is used for the connection between the electrode of the semiconductor chip CHP201 and the conductor pattern 205a of the wiring board 201. In order to perform wire bonding using a bonding tool, a certain distance (for example, about several hundred μm) is required from the side surface of the semiconductor chip CHP201 to the connection portion between the conductor pattern 205a of the wiring board 201 and the bonding wire 203. In the wiring substrate 201, an extra region 210 is formed around the semiconductor chip CHP201 mounting region. The extra area 210 of the wiring board 201 is not necessary in terms of electric circuit, but is necessary for arranging the area (or bonding wire 203) necessary for wire bonding the semiconductor chip CHP201 and the wiring board 201. Area). This extra area 210 increases the planar dimension of the wiring board 201 and enlarges the planar dimension of the RF power module PM201. On the other hand, when trying to narrow the extra region 210 (that is, trying to shorten the distance from the side surface of the semiconductor chip CHP201 to the connection portion between the conductor pattern 205a of the wiring board 201 and the bonding wire 203), the connection of the bonding wire 203 is performed. Defects may occur, which reduces the manufacturing yield of the RF power module PM201.

  On the other hand, in the RF power module PM1 of the present embodiment, as described above, the semiconductor chip CHP1 is face-down bonded to the wiring board 101 and flip-chip mounted, and the bump electrodes 108 of the semiconductor chip CHP1 are attached to the wiring board 101. Since it is connected to the conductor pattern 105a (the terminal portion thereof), it is not necessary to provide a portion corresponding to the extra area 210 described above. That is, since the conductor pattern 105a for connecting the bump electrode 108 is disposed below the semiconductor chip CHP1, and the bump electrode 108 of the semiconductor chip CHP1 is connected thereto, the bump electrode 108 of the semiconductor chip CHP1 and the conductor pattern 105a of the wiring board 101 are connected. Is located below the semiconductor chip CHP1, and an area corresponding to the extra area 210 does not occur around the semiconductor chip CHP1 mounting area. For this reason, the RF power module PM1 of the present embodiment has a mounting area (area required for mounting) of the semiconductor chip (semiconductor device) CHP1 on the wiring substrate 101 as compared with the RF power module PM201 of the comparative example using wire bonding. Can be reduced. Therefore, compared with the RF power module PM201 of the comparative example in which the semiconductor chip CHP201 and the wiring board 201 are connected by the bonding wires 203, the RF power module PM1 of the present embodiment has the wiring area corresponding to the unnecessary area 210. The planar dimension of the substrate 101 can be reduced, and the planar dimension of the RF power module PM1 can be reduced. Further, compared with the RF power module PM201 of the comparative example in which the semiconductor chip CHP201 and the wiring board 201 are connected by the bonding wire 203, the RF power module PM1 of the present embodiment is sealed by the amount of the bonding wire loop height. The thickness of the resin 103 can be reduced, and the thickness (height) of the RF power module PM1 can be reduced (lower). Therefore, an electronic device such as the RF power module PM1 can be reduced in size.

  FIG. 8 is a plan view (plan layout diagram) of the semiconductor chip CHP1 of the present embodiment, and shows an example of circuit arrangement of the semiconductor chip CHP1. Although FIG. 8 is a plan view, the LDMOSFET circuits 131A to 131C and 132A to 132C and the pad electrode PD are hatched for easy understanding of the drawing.

  As shown in FIG. 8, the semiconductor chip CHP1 of the present embodiment includes LDMOSFET circuits (LDMOSFET circuit region, LDMOSFET formation region, and high frequency amplification corresponding to the amplification stages AMP11, AMP12, AMP13, AMP21, AMP22, and AMP23, respectively. Transistor region, amplification element formation region) 131A, 131B, 131C, 132A, 132B, 132C. Further, the semiconductor chip CHP1 has an element formation region 133 in which a capacitor element, a resistance element, a control MOSFET, or the like is formed. Each element formed in the element formation region 133 corresponds to an element constituting the bias circuits BAC1, BAC2, the detection circuits DEC1, DEC2, and the like. A plurality of pad electrodes PD are formed on the surface of the semiconductor chip CHP1. The bump electrode 108 is formed on each pad electrode PD.

  The pad electrode PD is a drain pad electrode PDD1, PDD2, PDD3, PDD4, PDD5, PDD6 which is a drain pad electrode, a source pad PDS1, PDS2, PDS3, PDS4, PDS5, PDS6 which is a source pad electrode, and a gate electrode Gate pads PDG1, PDG2, PDG3, PDG4, PDG5 and PDG6. In addition, the pad electrode PD includes a pad electrode PD1 for use in inputting a control signal, outputting a detection signal, and the like.

  The gate pad PDG1 is an input pad electrode (pad electrode for inputting an RF signal via the matching circuit AJC1) electrically connected to the gate electrode of the LDMOSFET circuit 131A (corresponding to the amplification stage AMP11).

  The drain pad PDD1 is an output pad electrode (pad electrode for outputting an RF signal amplified by the LDMOSFET circuit 131A) electrically connected to the drain of the LDMOSFET circuit 131A (corresponding to the amplification stage AMP11).

  The source pad PDS1 is a pad electrode that is electrically connected to the source of the LDMOSFET circuit 131A (corresponding to the amplification stage AMP11).

  The gate pad PDG2 is an input pad electrode (pad electrode for inputting an RF signal via the interstage matching circuit) electrically connected to the gate electrode of the LDMOSFET circuit 131B (corresponding to the amplification stage AMP12). .

  The drain pad PDD2 is an output pad electrode (pad electrode for outputting an RF signal amplified by the LDMOSFET circuit 131B) electrically connected to the drain of the LDMOSFET circuit 131B (corresponding to the amplification stage AMP12).

  The source pad PDS2 is a pad electrode that is electrically connected to the source of the LDMOSFET circuit 131B (corresponding to the amplification stage AMP12).

  The gate pad PDG3 is an input pad electrode (pad electrode for inputting an RF signal via the interstage matching circuit) electrically connected to the gate electrode of the LDMOSFET circuit 131C (corresponding to the amplification stage AMP13). .

  The drain pad PDD3 is an output pad electrode (pad electrode for outputting an RF signal amplified by the LDMOSFET circuit 131C) electrically connected to the drain of the LDMOSFET circuit 131C (corresponding to the amplification stage AMP13).

  The source pad PDS3 is a pad electrode electrically connected to the source of the LDMOSFET circuit 131C (corresponding to the amplification stage AMP13).

  The gate pad PDG4 is an input pad electrode (pad electrode for inputting an RF signal via the matching circuit AJC2) electrically connected to the gate electrode of the LDMOSFET circuit 132A (corresponding to the amplification stage AMP21).

  The drain pad PDD4 is an output pad electrode (pad electrode for outputting an RF signal amplified by the LDMOSFET circuit 132A) electrically connected to the drain of the LDMOSFET circuit 132A (corresponding to the amplification stage AMP21).

  The source pad PDS4 is a pad electrode electrically connected to the source of the LDMOSFET circuit 132A (corresponding to the amplification stage AMP21).

  The gate pad PDG5 is an input pad electrode (pad electrode for inputting an RF signal via the interstage matching circuit) electrically connected to the gate electrode of the LDMOSFET circuit 132B (corresponding to the amplification stage AMP22). .

  The drain pad PDD5 is an output pad electrode (pad electrode for outputting an RF signal amplified by the LDMOSFET circuit 132B) electrically connected to the drain of the LDMOSFET circuit 132B (corresponding to the amplification stage AMP22).

  The source pad PDS5 is a pad electrode electrically connected to the source of the LDMOSFET circuit 132B (corresponding to the amplification stage AMP22).

  The gate pad PDG6 is an input pad electrode (pad electrode for inputting an RF signal via the interstage matching circuit) electrically connected to the gate electrode of the LDMOSFET circuit 132C (amplification stage AMP23).

  The drain pad PDD6 is an output pad electrode (pad electrode for outputting an RF signal amplified by the LDMOSFET circuit 132C) electrically connected to the drain of the LDMOSFET circuit 132C (corresponding to the amplification stage AMP23).

  The source pad PDS6 is a pad electrode electrically connected to the source of the LDMOSFET circuit 132C (corresponding to the amplification stage AMP23).

  Further, in the semiconductor chip CHP1, the regions where the LDMOSFET circuits 131A, 131B, 131C, 132A, 132B, 132C are formed and the element forming regions 133 are element isolations composed of buried oxide films formed between the areas. Each region (corresponding to an element isolation region 5 described later) is electrically isolated from other regions. Further, the LDMOSFET circuits 131A, 131B, 131C, 132A, 132B, 132C and the element formation region 133 and the pad electrode PD are electrically connected to each other by internal wiring of the semiconductor chip CHP1 as necessary. ing.

  FIG. 9 is a plan view (planar layout diagram) of the semiconductor chip CHP201 of the comparative example used in the RF power module PM201 of the comparative example of FIG. 7, and corresponds to FIG.

  A semiconductor chip CHP201 of the comparative example shown in FIG. 9 includes LDMOSFET circuits 231A, 231B, 231C, 232A, 232B, and 232C corresponding to the amplification stages AMP11, AMP12, AMP13, AMP21, AMP22, and AMP23, respectively, and the element formation region. And an element formation region 233 corresponding to 133. Further, the semiconductor chip CHP201 of the comparative example is formed with drain pads PDD201 to PDD206, gate pads PDG201 to PDG206, and pad electrodes PD201 used for control signal input and detection signal output on the surface. The bonding wire 203 is connected to the electrode.

  The drain pads PDD201 to PDD206 are output pad electrodes electrically connected to the drains of the LDMOSFET circuits 231A to 231C and 232A to 232C, respectively. The gate pads PDG201 to 206 are input pad electrodes electrically connected to the gate electrodes of the LDMOSFET circuits 231A to 231C and 232A to 232C, respectively. A source pad electrode is not formed on the surface of the semiconductor chip CHP201 of the comparative example, and a source back electrode (not shown here) is formed on the back surface of the semiconductor chip CHP201. As shown in FIG. 7, the semiconductor chip CHP201 to which wire bonding is applied is die-bonded to the wiring substrate 201 face up. For this reason, the semiconductor chip CHP201 is joined to the conductor pattern 205a on the upper surface of the wiring substrate 201 with a conductive adhesive, so that the source back electrode for the source of the semiconductor chip CHP201 is electrically connected to the conductor pattern 205a on the upper surface of the wiring substrate 201. The source potential (reference potential) can be supplied from the back electrode for the source of the semiconductor chip CHP201 to the sources of the LDMOSFET circuits 231A to 231C and 232A to 232C.

  On the other hand, in the RF power module PM1 of the present embodiment, as shown in FIGS. 3 to 5, the semiconductor chip CHP1 is flip-chip mounted on the wiring substrate 101 by face-down bonding, and the surface 107a of the semiconductor chip CHP1 is mounted. The bump electrode 108 provided on the wiring board 101 is connected to the conductor pattern 105 a (the terminal portion thereof) of the wiring board 101. Therefore, in the semiconductor chip CHP1 of the present embodiment, the drain pads PDD1 to PDD6, the gate pads PDG1 to PDG6, and the source pads PDS1 to PDS6 are provided on the surface 107a of the semiconductor chip CHP1, and the drain pads PDD1 to PDD6 and the gate pads PDG1 to PDG1. The bump electrodes 108 provided on the PDG 6 and the source pads PDS1 to PDS6 are connected to the conductor pattern 105a of the wiring board 101.

  Also in the semiconductor chip CHP1 to which the flip chip mounting is applied, unlike the present embodiment, the source back electrode is formed on the back surface 107b, and the semiconductor chip CHP1 is flip-chip mounted on the wiring substrate 101 and then the semiconductor chip. It is also conceivable to cover the CHP 1 with a metal cap, connect the metal cap to the source back electrode, and supply the source potential (reference potential) to the source back electrode via the metal cap. However, in this case, even if the semiconductor chip CHP1 is flip-chip mounted to reduce the mounting area of the semiconductor chip CHP1 on the wiring substrate 101, the semiconductor chip CHP1 is covered with a metal cap. It is necessary to secure an area necessary for mounting the cap, and the planar size of the RF power module is increased by the area required for mounting the metal cap. Moreover, since it is necessary to mount a metal cap, the number of manufacturing steps increases and the manufacturing cost (member cost) increases.

  Therefore, in the semiconductor chip CHP1 of the present embodiment, not only the drain pads PDD1 to PDD6 and the gate pads PDG1 to PDG6 but also the source pads PDS1 to PDS6 are provided on the surface 107a side, and the drain pads PDD1 to PDD6 and the gate pads PDG1 to PDG6 are provided. The bump electrodes 108 provided on the source pads PDS1 to PDS6 are connected to the conductor pattern 105a of the wiring board 101. For this reason, source potentials (reference potentials) can be supplied from the conductor pattern 105a of the wiring substrate 101 to the source pads PDS1 to PDS6 of the semiconductor chip CHP1 via the bump electrodes 108, whereby the LDMOSFET circuits 131A to 131C and 132A to 132C are supplied. A source potential (reference potential) can be supplied to the source. Therefore, no back electrode (metal electrode layer) is formed on the back surface 107b of the semiconductor chip CHP1. This eliminates the need for wire bonding or mounting of a metal cap, and eliminates the area required for them, so that the planar dimensions of the RF power module PM1 can be reduced. Further, since the mounting of the metal cap is unnecessary, the number of manufacturing steps can be reduced, and the manufacturing cost (member cost) can be reduced.

  Next, a method of manufacturing the LDMOSFET (the LDMOSFET circuits 131A, 131B, 131C, 132A, 132B, and 132C) formed in the semiconductor chip (semiconductor device) CHP1 will be described in the order of steps with reference to FIGS.

10 to 19 are fragmentary cross-sectional views or fragmentary plan views of the semiconductor device of the present embodiment (corresponding to the semiconductor chip CHP1) during the manufacturing process. 10 to 19, FIGS. 10, 12, 14, 15, 18, and 19 are cross-sectional views of main parts, of which FIGS. 10, 12, 14, 15, and 18 are illustrated. Cross-sectional views of different process steps in the same region are shown in the order of processes, and FIG. 19 is a cross-sectional view of regions different from those. 10 to 19, FIGS. 11, 13, 16, and 17 are main part plan views, among which FIGS. 11 and 16 are plan views of different process steps in the same region. FIG. 13 and FIG. 17 show plan views of different process steps in the same region. The region shown in FIGS. 13 and 17 is a region corresponding to region RG1 in FIGS. Therefore, FIGS. 13 and 17 correspond to enlarged views of a region corresponding to the region RG1 of FIGS. 11 and 16, the bump electrodes 40D, 40G, and 40S are not formed yet, but the bump electrodes 40D, 40G, and 40S are later formed in order to clarify the positional relationship between the components. The formed position is indicated by a dotted line. Further, the Y direction shown in the plan views (FIGS. 11, 13, 16, and 17) indicates the gate electrode 9 and drain region (n ⁻ type drift region 10, n) of the LDMOSFET formed in the active region 6 described later. Corresponding to the extending direction of the type drift region 13 and the n ⁺ type drain region 14) and the source region (n ⁻ type source region 11 and n ⁺ type source region 15), and the X direction intersects the Y direction (preferably orthogonal) ) Direction. The same applies to the following plan views regarding the X direction and the Y direction. 10, 12, 14, 15 and 18, the LDMOSFET formation region 1A and the source corresponding to any of the LDMOSFET circuits 131A, 131B, 131C, 132A, 132B, 132C are drawn out. A source extraction region 1B, which is a (removal) region, is shown. Further, the bump electrode forming region 1C is shown in the cross-sectional view of FIG. 11 and FIG. 16 and the BB line in FIG. 13 correspond to the same position, and FIG. 10, FIG. 12, FIG. 14, FIG. 15 and FIG. A cross-sectional view of a position corresponding to the line BB is shown.

In order to manufacture the semiconductor chip CHP1, first, as shown in FIG. 10, a low resistance substrate made of, for example, p ⁺ type silicon (Si) single crystal and having a resistivity (specific resistance) of, for example, about 1 to 10 mΩcm. A semiconductor substrate (hereinafter simply referred to as a substrate) 1 is prepared. Then, using a known epitaxial growth method on the main surface of the substrate (semiconductor substrate, semiconductor wafer) 1, an epitaxial layer made of p-type single crystal silicon having a resistivity (specific resistance) of about 20 Ωcm and a thickness of about 2 μm, for example. (Semiconductor layer) 2 is formed. Although the epitaxial layer 2 is a semiconductor layer, the impurity concentration of the epitaxial layer 2 is lower than the impurity concentration of the substrate 1, and the resistivity of the epitaxial layer 2 is higher than the resistivity of the substrate 1.

  Next, a part (punched layer forming region) of the epitaxial layer 2 is etched (removed) by using a photolithography technique and a dry etching technique to form grooves 3 and 3 a reaching the substrate 1. At this time, the trench 3 is formed in the LDMOSFET formation region 1A, and the trench 3a is formed in the source lead region 1B. Then, p-type polycrystalline silicon in which a p-type impurity (for example, boron (B)) is doped on the substrate 1 (on the epitaxial layer 2) including the inside of the grooves 3 and 3a by using a CVD (Chemical Vapor Deposition) method or the like. After the film is deposited so as to fill the trenches 3 and 3a, the p-type polycrystalline silicon film outside the trenches 3 and 3a is removed by an etch back method or the like. As a result, p-type punched layers (punched layer, reach-through layer, p-type semiconductor region, p-type semiconductor layer) 4 and 4a made of a p-type polycrystalline silicon film are formed inside the grooves 3 and 3a. The p-type punching layer 4 (first punching layer) is made of a p-type polycrystalline silicon film embedded in the groove 3 and is formed in the LDMOSFET formation region 1A, and the p-type punching layer 4a (second punching layer). Is made of a p-type polycrystalline silicon film embedded in the trench 3a, and is formed in the source lead region 1B.

  The p-type punching layers 4 and 4 a penetrate the epitaxial layer 2, and the bottoms of the p-type punching layers 4 and 4 a reach the substrate 1. Thus, by embedding the p-type polycrystalline silicon film doped with impurities at a high concentration in the trenches 3 and 3a, the p-type punching layers 4 and 4a having a low parasitic resistance can be formed. Therefore, the impurity concentration of the p-type punched layers 4 and 4a is higher than the impurity concentration of the epitaxial layer 2, and the specific resistance (resistivity) of the p-type punched layers 4 and 4a is the specific resistance (resistivity) of the epitaxial layer 2. Lower than. It is also possible to form a punching layer with a smaller parasitic resistance by embedding a metal film inside the grooves 3 and 3a instead of the polycrystalline silicon film.

  Next, an element isolation region 5 made of an insulator is formed on the main surface of the epitaxial layer 2 by, for example, an STI (Shallow Trench Isolation) method or a LOCOS (Local Oxidization of Silicon) method. For example, the isolation region 5 can be formed in the epitaxial layer 2 by forming a groove in the epitaxial layer 2 by etching and embedding an insulating film such as a silicon oxide film in the groove. By forming the element isolation region 5, as shown in FIG. 11, an active region (first active region) 6 in which an LDMOSFET cell is formed on the main surface of the substrate 1 (main surface of the epitaxial layer 2), An active region (second active region) 6a for extracting a source is defined. The active region 6 and the active region 6 a are each surrounded by the element isolation region 5. Therefore, the active region 6 and the active region 6a are separated (electrically separated) by the element isolation region 5. The region where the active region 6 is formed substantially corresponds to the LDMOSFET formation region 1A, and the region where the active region 6a for source extraction is formed substantially corresponds to the source extraction region 1B. Therefore, an element isolation region 5 is formed between the LDMOSFET formation region 1A (active region 6) and the source lead region 1B (active region 6a). In addition, although FIG. 11 is a top view (principal part top view), in order to make drawing easy to see, the active regions 6 and 6a are hatched. Further, as described above, the cross section taken along the line AA in FIG. 11 substantially corresponds to FIG. Further, a region 6b composed of a group of active regions 6 and 6a (a region surrounded by a two-dot chain line in FIG. 11) will later become one of the LDMOSFET circuits 131A, 131B, 131C, 132A, 132B, and 132C. It becomes the corresponding area. Therefore, FIG. 11 shows one of the LDMOSFET circuits 131A, 131B, 131C, 132A, 132B, and 132C, a drain pad (upper bump electrode) connected to the LDMOSFET circuit, and a gate pad (upper bump electrode). ) And the source pad (upper bump electrode).

  Next, as shown in FIG. 12, a p-type impurity such as boron (B) is ion-implanted into a part of the epitaxial layer 2 using a photoresist pattern (not shown) as an ion implantation blocking mask. A p-type well (p-type base region, p-type semiconductor region) 7 for a punch-through stopper is formed. The p-type well 7 functions as a punch-through stopper that suppresses the extension of the depletion layer from the drain to the source of the LDMOSFET. The p-type well 7 is formed in a part of the LDMOSFET formation region 1A, and is mainly formed in the LDMOSFET source formation region and the channel formation region of the LDMOSFET formation region 1A. The p-type well 7 is also used for adjusting the threshold value of the LDMOSFET. A p-type well 7 can also be formed in the source lead region 1B.

  Next, after cleaning the surface of the epitaxial layer 2 with hydrofluoric acid or the like, the substrate 1 is subjected to a heat treatment (thermal oxidation treatment) at about 800 ° C., for example, so that silicon oxide having a thickness of about 11 nm is formed on the surface of the epitaxial layer 2. A gate insulating film 8 made of a film or the like is formed. The gate insulating film 8 may be a silicon oxide film containing nitrogen, a so-called oxynitride film, instead of the thermal oxide film. Alternatively, a silicon oxide film may be deposited on the thermal oxide film by a CVD method, and the gate insulating film 8 may be constituted by these two oxide films.

  Next, a gate electrode 9 is formed on the gate insulating film 8 in the LDMOSFET formation region 1A. In order to form the gate electrode 9, for example, an n-type polycrystalline silicon film (doped polysilicon film) is deposited on the main surface of the epitaxial layer 2 (that is, on the gate insulating film 8) by CVD or the like, and photolithography is performed. The n-type polycrystalline silicon film is patterned using a technique and a dry etching technique. Thus, a gate electrode 9 made of a patterned n-type polycrystalline silicon film is formed on the surface of the p-type well 7 in the LDMOSFET formation region 1A (active region 6) via the gate insulating film 8.

Next, an n-type impurity such as phosphorus (P) is ion-implanted into a part of the epitaxial layer 2 in the LDMOSFET formation region 1A using a photoresist pattern (not shown) as an ion implantation blocking mask. ⁻ Type drift region (n ⁻ type offset drain region) 10 is formed. Since the n ⁻ type drift region 10 is formed in a self-aligned manner with respect to the gate electrode 9, the n ⁻ type drift region 10 is formed at the lower portion of the side wall of the gate electrode 9 so that the end thereof is in contact with the channel formation region. Terminate. By reducing the impurity concentration of the n ⁻ type drift region 10, a depletion layer spreads between the gate electrode 9 and the drain, so that a feedback capacitance formed between them (parasitic between the drain and the gate electrode). Capacity, Cgd) is reduced.

Next, an n-type impurity such as arsenic (As) is ion-implanted into the surface of the p-type well 7 in the LDMOSFET formation region 1A using a photoresist pattern (not shown) as an ion implantation blocking mask. ^A -type source region 11 is formed. Since the n ⁻ type source region 11 is formed in a self-aligned manner with respect to the gate electrode 9, the n ⁻ type source region 11 terminates at the lower portion of the side wall of the gate electrode 9 so that the end thereof is in contact with the channel forming region. By performing ion implantation with low acceleration energy, the n ⁻ -type source region 11 is formed shallow, so that the spread of impurities from the source to the channel formation region can be suppressed, so that a decrease in threshold voltage can be suppressed. it can.

n ^- After formation of source region 11, such as by the p-type impurity such as boron (B) on the surface of the p-type well 7 of LDMOSFET formation region 1A is ion-implanted (e.g. oblique ion implantation), n ^- -type source A p-type halo region (not shown) may be formed below the region 11. The p-type halo region is not necessarily formed. However, when the p-type halo region is formed, the spread of impurities from the source to the channel formation region is further suppressed, and the short channel effect is further suppressed. Can be further suppressed.

  Next, a side wall spacer (side wall insulating film) 12 made of an insulating film such as a silicon oxide film is formed on the side wall of the gate electrode 9. The sidewall spacer 12 can be formed, for example, by depositing a silicon oxide film (insulating film) on the substrate 1 by CVD or the like and then anisotropically etching the silicon oxide film (insulating film).

Next, using a photoresist pattern (not shown) having an opening above the drain formation region as an ion implantation blocking mask, phosphorus (P) or the like is formed in a part of the n ⁻ type drift region 10 of the LDMOSFET formation region 1A. An n-type impurity is ion-implanted. Thereby, an n-type drift region (n-type offset drain region, drain) is formed in a part of the n ⁻ -type drift region 10 in a self-aligned manner with respect to the sidewall spacer 12 formed on the drain-side sidewall of the gate electrode 9. High concentration region) 13 is formed.

Since the impurity implanted when the n-type drift region 13 is formed is an impurity (P) having the same conductivity type as that implanted when the n ⁻ -type drift region 10 is formed, the impurity concentration of the n-type drift region 13 is n ⁻ -type drift. It becomes higher than the impurity concentration of the region 10. That is, since the n-type drift region 13 has a lower resistance than the n ⁻ -type drift region 10, the on-resistance (Ron) can be reduced.

Further, the n ⁻ type drift region 10 is formed in a self-aligned manner with respect to the gate electrode 9, whereas the n-type drift region 13 is self-aligned with respect to the sidewall spacer 12 on the side wall of the gate electrode 9. Therefore, the n-type drift region 13 is formed away from the gate electrode 9 by an amount corresponding to the film thickness of the sidewall spacer 12 along the gate length direction. Therefore, even if the impurity concentration of the n-type drift region 13 is increased, the influence on the feedback capacitance (Cgd) is small.

In addition, since the acceleration energy of ion implantation when forming the n-type drift region 13 is the same as the acceleration energy of ion implantation when forming the n ⁻ -type drift region 10, the junction depth of the n-type drift region 13 is n ⁻ -type drift. It becomes substantially the same as the junction depth of the region 10.

  Next, using a photoresist pattern (not shown) having an opening in a part of the n-type drift region 13 in the LDMOSFET formation region 1A and the p-type well 7 in the source formation region as an ion implantation blocking mask, An n-type impurity such as arsenic (As) is ion-implanted into a part of the n-type drift region 13 in the LDMOSFET formation region 1A and the p-type well 7 in the source formation region.

By the ion implantation, ⁿ the part of the n-type drift region 13 of the LDMOSFET formation region 1A has a higher impurity concentration than the n-type drift region 13, and spaced from the further channel forming region than the n-type drift region 13 ⁺ A type drain region (drain high concentration region) 14 is formed. At this time, the n ⁺ -type drain region 14 having a high impurity concentration is formed shallower than the n-type drift region 13 and the n ⁻ -type drift region 10 having a low impurity concentration. Capacity) can be reduced.

Also, by this ion implantation, the p-type well 7 of LDMOSFET formation region 1A, n ^- impurity concentration higher than type source region 11 and n ^- deep ^{n +} -type source position of the bottom portion than -type source region 11 Region 15 is formed. The n ⁺ -type source region 15 is formed in a self-aligned manner with respect to the sidewall spacer 12 on the side wall of the gate electrode 9, and is formed in contact with the n ⁻ -type source region 11. Therefore, the n ⁺ -type source region 15 is formed away from the channel formation region by an amount corresponding to the film thickness of the sidewall spacer 12 along the gate length direction.

Thus, the drift region (LDD region, offset drain region) interposed between the gate electrode 9 and the n ⁺ type drain region 14 has a double offset structure, and the n ⁻ type drift region 10 closest to the gate electrode 9 The impurity concentration is relatively low, and the impurity concentration of the n-type drift region 13 spaced from the gate electrode 7 is relatively high. As a result, a depletion layer spreads between the gate electrode 9 and the drain, and as a result, the feedback capacitance (Cgd) formed between the gate electrode 9 and the n ⁻ type drift region 10 in the vicinity thereof is reduced. Further, since the impurity concentration of the n-type drift region 13 is high, the on-resistance (Ron) is also reduced. Since the n-type drift region 13 is formed at a position separated from the gate electrode 9, the influence on the feedback capacitance (Cgd) is small. For this reason, since both the on-resistance (Ron) and the feedback capacitance (Cgd) can be reduced, the power added efficiency of the amplifier circuit can be improved.

By the steps so far, the drain (drain region) including the n ⁻ type drift region 10, the n type drift region 13 and the n ⁺ type drain region 14, and the n ⁻ type source region 11 and the n ⁺ type source region 15 are formed. An LDMOSFET having a source (source region) and a gate electrode 9 is formed on the main surface (active region 6) of the epitaxial layer 2 in the LDMOSFET formation region 1A. In this embodiment and the following embodiments, the MOSFET is not only a MISFET (Metal Insulator Semiconductor Field Effect Transistor) using an oxide film (silicon oxide film) as a gate insulating film, but also an oxide film (silicon oxide). It also includes a MISFET using an insulating film other than (film) as a gate insulating film.

  The LDMOSFET is a MISFET element having the following characteristics.

As a first feature, the LDMOSFET has an LDD (Lightly doped drain) region formed on the drain side of the gate electrode 9 in order to enable a high voltage operation with a short channel length. That is, the drain of the LDMOSFET has a high impurity concentration n ⁺ -type region (here, the n ⁺ -type drain region 14) and a lower impurity concentration LDD region (here, the n ⁻ -type drift region 10 and the n-type drift region). 13), and the n ⁺ -type region (n ⁺ -type drain region 14) is formed apart from the gate electrode 9 (or the channel formation region under the gate electrode 9) via the LDD region. Thereby, a high breakdown voltage can be realized. The amount of charge (impurity concentration) in the LDD region on the drain side, and the distance along the plane (main surface of the epitaxial layer 2) between the end of the gate electrode 9 and the n ⁺ -type drain region (drain high concentration region) 14 Must be optimized to maximize the breakdown voltage of the LDMOSFET.

As a second feature, the LDMOSFET has a p-type well (p-type base region) for a punch-through stopper in a source-side source formation region (n ⁻ -type source region 11 and n ⁺ -type source region 15) and a channel formation region. ) 7 is formed. On the drain side (drain formation region) of the LDMOSFET, the p-type well 7 is not formed, or is formed only in contact with a part of the drain formation region on the side close to the channel region.

As a third feature, the LDMOSFET has a source (here, a source region composed of an n ⁻ type source region 11 and an n ⁺ type source region 15) and a drain (here n ⁻ type drift region 10, n type drift region 13 and n ^{And a} drain region made up of the ⁺ type drain region 14) have an asymmetric structure with respect to the gate electrode 9.

Next, using a photoresist pattern (not shown) having an opening above the p-type punching layers 4 and 4a as an ion implantation blocking mask, boron fluoride (BF ₂ ) is formed on the surface of the p-type punching layers 4 and 4a. The p ⁺ type semiconductor regions 16 and 16a are formed in the upper region of the p type punching layers 4 and 4a by ion implantation of p type impurities such as. The p ⁺ type semiconductor region 16 is formed on the p type punching layer 4 in the LDMOSFET formation region 1A, and the p ⁺ type semiconductor region 16a is formed on the p type punching layer 4a in the source lead region 1B. By forming the p ⁺ type semiconductor regions 16 and 16a in the upper region of the p type punching layers 4 and 4a, the resistance of the surface of the p type punching layers 4 and 4a can be reduced.

The structure shown in FIG. 12 is obtained through the steps up to here. FIG. 13 is a fragmentary plan view corresponding to the process step of FIG. FIG. 13 shows a planar layout of the p-type punching layers 4, 4 a, the active regions 6, 6 a, the gate electrode 9 and the n ⁺ -type source region 15, and other components are not shown. In FIG. 13, in order to make the drawing easy to see, the n ⁺ -type source region 15 is indicated by a dotted line and the others are indicated by a solid line. As described above, the region shown in FIG. 13 is a region substantially corresponding to the region RG1 in FIG. Further, as described above, the BB line in FIG. 13 and the AA line in FIG. 11 show the same position, and the cross section shown in FIGS. 10 and 12 is the BB line in FIG. It is sectional drawing of the position corresponding to (AA line of FIG. 11).

As shown in FIG. 13, the gate electrode 9 of the LDMOSFET extends in the Y direction. Although not shown in FIG. 13, the drain region (n ⁻ type drift region 10, n type drift region 13 and n ⁺ type drain region 14) of the LDMOSFET is a region between the adjacent gate electrodes 9 in the active region 6. Formed in the Y direction. Further, the source region (n ⁻ type source region 11 and n ⁺ type source region 15) of the LDMOSFET is formed in a region between the other adjacent gate electrodes 9 in the active region 6 and extends in the Y direction. Yes. Although not shown in FIG. 13, the p ⁺ type semiconductor region 16 is formed in a region between the n ⁺ type source regions 15 of adjacent LDMOSFETs and extends in the Y direction.

In the LDMOSFET formation region 1A (active region 6), the structure of the unit cell (LDMOSFET unit cell, basic cell, unit region, unit LDMOSFET element) 20 shown in FIGS. 12 and 13 is repeated in the X direction. Yes. That is, a plurality of unit cells 20 (unit LDMOSFET elements) are arranged in the X direction. In the plurality of unit cells 20 (unit LDMOSFET elements) formed in the active region 6 of the region 6b, the gate electrodes 9 are electrically connected to each other via gate wirings 25G, 31G, and 35G and plugs 24 and 28, which will be described later. The connected drain regions (n ⁺ -type drain regions 14) are electrically connected to each other via drain wirings 25D, 31D, and 35D and plugs 24 and 28, which will be described later. In the plurality of unit cells 20 (unit LDMOSFET elements) formed in the active region 6 of the region 6b, the source regions (n ⁺ type source regions 15) are electrically connected to each other via the p-type punching layer 4 and the substrate 21. Connected.

  Therefore, the LDMOSFET elements constituting the amplification stages AMP11 to AMP13 and AMP21 to AMP23 of the power amplifier circuits AMP1 and AMP2 are configured by connecting a plurality of unit LDMOSFET elements (unit LDMOSFET elements composed of the unit cells 20) in parallel. Has been.

Next, as shown in FIG. 14, a metal silicide layer 21 made of, for example, cobalt silicide is formed on the surface (upper surface, upper part) of the n ⁺ type source region 15 and the p ⁺ type semiconductor region 16 of the LDMOSFET formation region 1A. To do.

To form the metal silicide layer 21, n ⁺ -type source region 15 and p ⁺ -type semiconductor region 16 than in the area from the covered with a photoresist layer, n ⁺ -type source region 15 and p using the photoresist layer as a mask The oxide film on the surface of the ⁺ type semiconductor region 16 is removed by etching. Then, a metal film such as a cobalt (Co) film is deposited on the substrate 1 using the photoresist layer as a mask. This metal film is in contact with the n ⁺ type source region 15 and the p ⁺ type semiconductor region 16 on the main surface of the epitaxial layer 2, but is not in contact with other regions because the photoresist layer is interposed. Thereafter, heat treatment is performed so that the metal film and silicon constituting the epitaxial layer 1 are reacted, so that the surfaces (upper parts) of the n ⁺ type source region 15 and the p ⁺ type semiconductor region 16 are made of cobalt silicide or the like. A metal silicide layer 21 can be formed.

  Next, an insulating film (interlayer insulating film) 22 made of a laminated film of a relatively thin silicon nitride film and a relatively thick silicon oxide film thereon is formed on the substrate 21 using a CVD method or the like. Accordingly, the surface is planarized by using a CMP (Chemical Mechanical Polishing) method or the like. A single film such as a silicon oxide film can also be used as the insulating film 22.

Next, by using the photoresist pattern (not shown) as an etching mask, the insulating film 22 is dry etched to form contact holes (openings, through holes, through holes) 23 in the insulating film 22. The contact hole 23 includes the p-type punching layer 4 (p ⁺ -type semiconductor region 16), the source (n ⁺ -type source region 15) and the drain (n ⁺ -type drain region 14), the gate electrode 9 and the p-type punching layer 4a (p ^{A +} type semiconductor region 16a) is formed on each upper part.

  Next, a plug (conductor portion) 24 mainly composed of a tungsten (W) film is embedded in the contact hole 23. For example, after a barrier film (for example, a titanium nitride film) is formed on the insulating film 22 including the inside (on the bottom and side walls) of the contact hole 23, the contact hole 23 is filled on the barrier film by CVD or the like. The plug 24 can be formed by removing the unnecessary tungsten film and barrier film on the insulating film 22 by CMP method or etch back method.

  Next, a wiring (first layer wiring) 25 made of a conductor film (tungsten film) mainly composed of tungsten (W) is formed on the insulating film 22 in which the plugs 24 are embedded. The wiring 25 can be formed, for example, by forming a tungsten film on the insulating film 22 in which the plug 24 is embedded by sputtering or the like, and patterning the tungsten film by using a photolithography method and a dry etching method. . At this time, a laminated film of a thin tungsten nitride (WN) film and a thicker tungsten (W) film formed thereon can be used instead of the single tungsten film. Further, the wiring 25 is not limited to the tungsten wiring, and may be a wiring using other metal material such as an aluminum wiring.

The wiring 25 includes a source wiring 25S1 electrically connected to the n ⁺ -type source region 15 and the p ⁺ -type semiconductor region 16 (the upper metal silicide layer 21) via the plug 24, and an n ⁺ -type drain via the plug 24. A drain wiring 25D electrically connected to the region 14, a gate wiring 25G electrically connected to the gate electrode 9 via the plug 24, and a source electrically connected to the p ⁺ type semiconductor region 16a via the plug 24 It has wiring 25S2. The gate wiring 25G is not shown in the cross-sectional view of FIG. 14, but is shown in FIG.

  Next, as shown in FIG. 15, an insulating film (interlayer insulating film) 26 made of a silicon oxide film or the like is formed on the insulating film 22 so as to cover the wiring 25 by a CVD method or the like.

  Next, the insulating film 26 is dry-etched using a photoresist pattern (not shown) as an etching mask, thereby forming a through hole (opening, through hole) 27 in the insulating film 26. At the bottom of the through hole 27, the wiring 25 is exposed. Then, a plug 28 mainly composed of a tungsten (W) film is embedded in the through hole 27. The plug 28 can be formed in substantially the same manner as the plug 24.

  Next, a conductor film mainly composed of an aluminum (Al) alloy film is formed on the insulating film 26 in which the plugs 28 are embedded, and the conductor film is patterned using a photolithography method and a dry etching method. Thus, a wiring (second layer wiring) 31 made of the patterned conductor film is formed. Examples of the conductor film for forming the wiring 31 include a barrier film (for example, a laminated film of a titanium film and a titanium nitride film), an aluminum film (or an aluminum alloy film), and a barrier film (for example, a laminated film of a titanium film and a titanium nitride film). ) And the like can be used.

  The wiring 31 includes a drain wiring 31D electrically connected to the drain wiring 25D via the plug 28, a gate wiring 31G electrically connected to the gate wiring 25G via the plug 28, and a source wiring 25S2 via the plug 28. And a source wiring 31S2 electrically connected to. The drain wiring 25D and the drain wiring 31D are formed with the same planar pattern, the gate wiring 25G and the gate wiring 31G are formed with the same planar pattern, and the source wiring 25S2 and the source wiring 31S2 are formed with the same planar pattern. Note that the gate wiring 31G is not shown in the sectional view of FIG. 15, but is shown in FIG.

  The structure shown in FIG. 15 is obtained through the steps up to here.

  16 and 17 are main part plan views corresponding to the process steps of FIG. 15, and regions corresponding to FIGS. 11 and 13 are shown, respectively. That is, an enlarged view of the region RG1 in FIG. 16 corresponds to FIG. FIG. 16 shows a planar layout of wirings (that is, source wiring 25S1, drain wiring 31D, gate wiring 31G and source wiring 31S2) that can be seen through each insulating film from above, and other components are shown in FIG. Omitted. FIG. 17 shows a planar layout of the active regions 6 and 6a, the source wiring 25S1, the drain wirings 25D and 31D, the gate wirings 25G and 31G, the source wirings 25S2 and 31S2, the contact hole 23, the through hole 27, and the gate electrode 9. The other components are not shown. In FIG. 17, the active regions 6 and 6a and the gate electrode 9 are indicated by dotted lines, and the contact hole 23 and the through hole 27 are indicated by two-dot chain lines.

  Next, as shown in FIG. 18, an insulating film (interlayer insulating film) 32 made of a silicon oxide film or the like is formed on the insulating film 26 so as to cover the wiring 31 by a CVD method or the like.

  Next, the insulating film 32 is dry-etched using a photoresist pattern (not shown) as an etching mask to form a through hole (opening, through hole) 33 in the insulating film 32. At the bottom of the through hole 33, the wiring 31 is exposed.

  Next, a conductor film mainly composed of an aluminum (Al) alloy film is formed on the insulating film 32 including the inside of the through hole 33, and this conductor film is patterned by using a photolithography method and a dry etching method. Then, a wiring (third layer wiring) 35 made of a patterned conductor film is formed. Examples of the conductor film for forming the wiring 35 include a barrier film (for example, a laminated film of a titanium film and a titanium nitride film), an aluminum film (or an aluminum alloy film), and a barrier film (for example, a laminated film of a titanium film and a titanium nitride film). ) And the like can be used.

  The wiring 35 extends on the insulating film 32, partially fills the through hole 33, and is electrically connected to the wiring 31 at the bottom of the through hole 33. Accordingly, in the wiring 35, a wiring portion extending on the insulating film 32 and a via portion filling the through hole 33 are integrally formed.

  The wiring 35 is electrically connected to the drain wiring 31D that is electrically connected to the drain wiring 31D via the via portion (the portion that fills the through hole 33), and to the gate wiring 31G via the via portion (the portion that fills the through hole 33). And a source wiring 35S2 electrically connected to the source wiring 31S2 via a via portion (a portion filling the through hole 33).

  Further, after forming the through hole 33, a plug is formed in the through hole 33 by the same method as the plugs 24 and 28, and then a conductor film for forming a wiring is formed on the insulating film 32 in which the plug is embedded, The conductive film can be patterned to form the wiring 35. In this case, the wiring 35 is electrically connected to the wiring 31 through a plug.

  Next, an insulating film (surface protective film) 36 is formed on the insulating film 32 so as to cover the wiring 35. This insulating film is made of, for example, a laminated film of a silicon oxide film and a silicon nitride film thereon, and can be formed by a CVD method or the like.

  Next, an opening is formed in the insulating film 36, and an equivalent of the bump electrode 18 is formed on the exposed wiring 35. However, no bump electrode is formed on the cross section of FIG. This will be described with reference to FIG. 19 showing a cross section of 1C.

  After the insulating film 36 is formed, the insulating film 36 is etched using a photoresist pattern (not shown) as an etching mask, so that openings (through holes, through holes) are formed in the insulating film 36 as shown in FIG. Hole) 37 is formed. The opening 37 reaches the wiring 35, and a part of the wiring 35 (drain wiring 35D, gate wiring 35G, and source wiring 35S2) is exposed at the bottom of the opening 37. The wiring 35 exposed at the opening 37 becomes the pad electrode 38, and this pad electrode 38 becomes the pad electrode PD. Accordingly, the drain pads PDD1 to PDD6 are formed by the drain wiring 35D exposed from the opening 37, and the gate pads PDG1 to PDG6 are formed by the gate wiring 35G exposed from the opening 37, and the source pads PDS1 to PDS6. Is formed by the source wiring 35S2 exposed from the opening 37.

  Next, an UBM (Under Bump Metal) film made of a conductor is formed on the insulating film 36 including the side wall and bottom of the opening 37 (that is, on the insulating film 36 including the wiring 35 exposed at the bottom of the opening 37). (Bump base metal layer, electrode base film, conductor film, terminal surface film) 39 is formed. The UBM film 39 is formed of, for example, a laminated film of a palladium (Pd) film and a titanium (Ti) film or a laminated film of a chromium (Cr) film, a nickel (Ni) -based alloy film, and a gold (Au) film. It can be formed by the method.

  Next, a bump electrode 40 is formed on the UBM film 39 on the wiring 35 exposed at the opening 36. The bump electrode 40 corresponds to the bump electrode 108. The bump electrode 40 is made of, for example, a solder bump. For example, the solder bump (bump electrode 40) is a spherical solder bump (bump) on the UBM film 39 by printing a solder paste on the UBM film 39 and then performing a reflow (solder reflow process) on the semiconductor substrate (substrate 1). An electrode 40) can be formed.

  The bump electrode 40 includes a drain bump electrode 40D formed on the drain wiring 35D (part of the pad electrode 38) via the UBM film 39, and a UBM film on the gate wiring 35G (part of the pad electrode 38). And a bump electrode 40G for gate formed through the UBM film 39 on the source wiring 35S2 (part of the pad electrode 38).

  Thereafter, the substrate 1 is cut by dicing or the like and separated into individual semiconductor chips (semiconductor devices) CHP1, but detailed description thereof will be omitted here. Moreover, the back surface grinding of the board | substrate 1 can also be performed before dicing. Note that no back electrode (metal electrode layer) is formed on the main surface of the substrate 1 opposite to the side on which the epitaxial layer 2 is formed (corresponding to the back surface 107b of the semiconductor chip CHP1). The separated semiconductor chip CHP1 is flip-chip mounted on the wiring substrate 101 to manufacture the RF power module PM1.

  20 and 21 are main part plan views of the manufactured semiconductor chip CHP1, and regions corresponding to FIGS. 11 and 13 are shown, respectively. That is, an enlarged view of the region RG1 in FIG. 20 corresponds to FIG. FIG. 20 shows a planar layout of the wirings (that is, the source wiring 25S1, the drain wiring 35D, the gate wirings 31G and 35G, and the source wiring 35S2) and the bump electrodes 40 that can be seen through each insulating film from above the semiconductor chip CHP1. The other components are not shown. FIG. 21 shows a planar layout of the active regions 6 and 6a, the source wiring 25S1, the drain wirings 25D, 31D, and 35D, the gate wirings 25G, 31G, and 35G, the source wirings 25S2, 31S2, and 35S2, and the through hole 33. The other components are not shown. In FIG. 21, the active regions 6 and 6a and the first and second layer wirings (that is, the wirings 25 and 31) that are the lower layer wirings are indicated by dotted lines, and the third layer wiring that is the uppermost layer wiring (that is, the wiring 35). Is shown by a solid line, and the through hole 33 is shown by a two-dot chain line. Further, the CC cross section, the DD line cross section, and the EE line cross section of FIG. 20 all have substantially the same structure as FIG.

  As described above, in the semiconductor chip CHP1, the LDMOSFET elements constituting the power amplifier circuits AMP1, AMP2 (the amplification stages AMP11, AMP12, AMP13, AMP21, AMP22, AMP23) are respectively connected to the epitaxial layer 2 on the main surface of the substrate 1. In the active region 6 (LDMOSFET formation region 1A), a wiring structure (multilayer wiring structure) composed of wirings 25, 31, and 35 is formed on the epitaxial layer 2.

In the semiconductor chip CHP1, as shown in FIG. 15 to FIG. 17 and the like, the semiconductor chip CHP1 is electrically formed in the drain region (n ⁺ type drain region 14) of the LDMOSFET formed in the active region 6 (LDMOSFET formation region 1A). Drain wirings 25 </ b> D and 31 </ b> D are formed on the drain region of the active region 6. The drain wiring 25D and the drain wiring 31D are formed in the same pattern (planar pattern), and the drain wiring 25D and the drain wiring 31D formed in the same plane position are electrically connected to each other through the plug 24. . Since the drain region extends in the Y direction in the active region 6, the drain wirings 25 </ b> D and 31 </ b> D also extend in the Y direction on the active region 6, but on the element isolation region 5 between the active regions 6. The drain wirings 25D and 31D are not formed. For this reason, the drain wirings 25D and 31D are isolated patterns formed only on each active region 6, but as shown in FIGS. It is electrically connected to the uppermost drain wiring 35 </ b> D extending in the direction via a via part (a part filling the through hole 33). The drain wiring 35D of the uppermost layer has an integrated pattern (comb-like pattern) in which the portions extending in the Y direction across the plurality of active regions 6 arranged in the Y direction in the region 6b are connected at the ends. The connecting portion becomes a large area pattern, which becomes the pad electrode 38, and the bump electrode 40D for drain is formed through the UBM film 39. Accordingly, in the active region 6 (LDMOSFET formation region 1A), the drain region (n ⁺ -type drain region 14) of each unit cell 20 is the uppermost layer via the plug 24, drain wiring 25D, plug 28 and drain wiring 31D. The drain wiring 35D is pulled up (drawn) to be electrically connected to each other, and a drain bump electrode 40D is formed on the drain wiring 35D.

Further, in the semiconductor chip CHP1, as shown in FIGS. 15 to 17 and the like, the semiconductor chip CHP1 is electrically formed in the source region (n ⁺ type source region 15) of the LDMOSFET formed in the active region 6 (LDMOSFET formation region 1A). The source wiring 25S1 thus formed is formed on the source region (n ⁺ type source region 15) and the p ⁺ type semiconductor region 16 of the active region 6. However, as shown in FIGS. 18, 20, 21, and the like, on the source wiring 25 </ b> S <b> 1, a source wiring in the same layer as the wiring 31 (the drain wiring 31 </ b> D, etc.) (a wiring electrically connected to the source wiring 25 </ b> S <b> 1). ) Is not formed. Accordingly, the source wiring 25S1 is formed on the active region 6, but the source wiring (wiring electrically connected to the source wiring 25S1) in the same layer as the wirings 31, 35 (drain wirings 31D, 35D, etc.). Is not formed on the active region 6. In the active region 6, since the source region extends in the Y direction, the source wiring 25 </ b> S <b> 1 also extends in the Y direction on the active region 6, but on the element isolation region 5 between the active regions 6. The source wiring 25S1 is not formed. Therefore, the source line 25S1 is an isolated pattern formed only on each active region 6. Accordingly, the source wiring 25S1 is not connected to the upper layer wiring (wiring in the same layer as the wirings 31 and 35), and is not connected to the bump electrode through the upper layer wiring.

Further, in the semiconductor chip CHP1, as shown in FIG. 15 to FIG. 17 and the like, the p-type punching layer 4a (upper p ⁺ type semiconductor region 16a) formed in the active region 6a (source lead region 1B) is electrically connected. Connected source lines 25S2 and 31S2 are formed on the active region 6a (on the p-type punching layer 4a and the p ⁺ -type semiconductor region 16a). The source wiring 25S2 and the source wiring 31S2 are formed in the same pattern (planar pattern) and are electrically connected to each other through the plug 24. The source wirings 25S2 and 31S2 are formed as a pattern having a wider and larger area than the drain wirings 25D and 31D. As shown in FIGS. 18, 20, 21, and the like, the source wirings 25S2 and 31S2 include the uppermost source wiring 35S2 extending above the source wirings 25S2 and 31S2 and the via portion (the portion that fills the through hole 33). ). Therefore, in the active region 6a (source lead region 1B), the substrate 1 is placed on the uppermost layer via the p-type punching layer 4a, the p ⁺ -type semiconductor region 16a, the plug 24, the source wiring 25S2, the plug 28 and the source wiring 31S2. The source wiring 35S2 is pulled up (drawn). As shown in FIGS. 19 and 20, the source wiring 35S2 is extended to the bump electrode formation region, and the source bump electrode 40S is formed there.

  FIG. 22 is a cross-sectional view of the main part of the gate contact portion of the semiconductor chip CHP1, and substantially corresponds to the cross section taken along line FF in FIG.

  As shown in FIGS. 16, 17, 21, 22, etc., the gate electrode 9 extends in the Y direction and is a portion located on the element isolation region 5 around or between the active regions 6. The gate line 25G is electrically connected to the gate line 25G via the plug 24 embedded in the line 23. The gate wiring 25G is electrically connected to the gate wiring 31G one layer above through the plug 28. The gate wiring 25G and the gate wiring 31G are formed in the same pattern (planar pattern), and the gate wirings 25G and 31G extend in the X direction around the active region 6 or between the element isolation regions 5. . Accordingly, the gate electrodes 9 extending in the Y direction are electrically connected to each other via the gate wirings 25G and 31G extending in the X direction. The through hole 27 for connecting the gate wiring 25G and the gate wiring 31G and the contact hole 23 for connecting the gate wiring 25G and the gate electrode 9 are formed on the element isolation region 5 around or between the active regions 6. Are formed at substantially the same plane position.

  The gate wiring 25G is a wiring in the same layer as the drain wiring 25D and the source wiring 25S1, and the gate wiring 31G is a wiring in the same layer as the drain wiring 31D, but the element isolation region between the active regions 6 as described above. 5, the drain wirings 25D and 31D and the source wiring 25S1 are not formed, and the gate wirings 25G and 31G extend in the X direction there. Accordingly, the drain wirings 25D and 31D and the source wiring 25S1 extending in the Y direction are arranged between the gate wirings 25G and 31G extending in the X direction.

  The gate wiring 31G extending in the X direction is electrically connected to the gate wiring 35G extending in the Y direction over the element isolation region 5 and the via portion (the portion filling the through hole 33) in the vicinity of the end portion. Thus, the gate wirings 31G extending in the X direction are electrically connected to each other via the gate wiring 35G extending in the Y direction. Accordingly, on the element isolation region 5 around or between the active regions 6, the gate electrode 9 of each unit cell 20 is pulled up to the gate wirings 25G and 31G via the plug 24, and the gate wirings 25G and 31G are pulled in the X direction. And is connected to the uppermost gate wiring 35G outside the active region 6 so as to be electrically connected to each other. Then, a part of the gate wirings 25G and 31G is extended so as to pass between the source wirings 25S2 and 31S2 adjacent in plan as shown in FIGS. 16 and 20, for example, and separated from the active region 6 The gate wiring 35G is electrically connected to the gate wiring 35G1 in the same layer as that of the gate wiring 35G via a via portion (a portion filling the through hole 33). As shown in FIGS. 19 and 20, the gate wiring 35G1 becomes a large area pattern, which becomes the pad electrode 38, and a bump electrode 40G for the gate is formed through the UBM film 39.

  FIG. 23 is a plan view of an essential part of the semiconductor chip CHP201 of the comparative example shown in FIG. 9, and corresponds to FIG. 20 of the present embodiment.

  As shown in FIG. 23, the semiconductor chip CHP201 of the comparative example includes a drain wiring 235D corresponding to the drain wiring 35D, gate wirings 225G, 231G, 235G corresponding to the gate wirings 25G, 31G, and 35G, and the source wiring 25S1. Source wiring 225S corresponding to the. However, the semiconductor chip CHP201 of the comparative example is a wire bonding semiconductor chip, and a source potential can be supplied from the back electrode of the semiconductor chip CHP201. For this reason, the drain and gate of the LDMOSFET are pulled up to the drain wiring 235D and the gate wiring 235G of the uppermost layer wiring, and a part of the drain wiring 235D and the gate wiring 235G is exposed, so that the drain pad 240D (above-mentioned) Drain pads PDD201 to PDD206) and gate pads 240G (corresponding to the gate pads PDG201 to 206) are formed. The semiconductor chip CHP201 of the comparative example does not need to pull up the source of the LDMOSFET to the source pad on the surface.

  On the other hand, the semiconductor chip CHP1 of the present embodiment is a flip-chip mounting semiconductor chip as shown in FIGS. Therefore, a plurality of bump electrodes 108 (that is, bump electrodes 40) are formed on the surface 107a side. As shown in FIG. 20, the bump electrode 108 formed on the surface 107a of the semiconductor chip CHP1, ie, the bump electrode 40, includes a drain bump electrode 40D, a gate bump electrode 40G, and a source bump electrode. 40S. That is, not only the drain and gate of the LDMOSFET are pulled up to the bump electrode 40D and bump electrode 40G on the surface of the semiconductor chip CHP1, but also the source of the LDMOSFET is pulled up to the bump electrode 40S on the surface of the semiconductor chip CHP1. Although not shown in FIG. 8, a drain bump electrode 40D is formed on each drain pad PDD1 to PDD6, and a gate bump electrode 40G is formed on each gate pad PDG1 to PDG6. Bump electrodes 40S for source are formed on pads PDS1 to PDS6.

  By forming not only the bump electrode 40D for drain and the bump electrode 40G for gate but also the bump electrode 40S for source on the surface of the semiconductor chip CHP1, when the semiconductor chip CHP1 is flip-chip mounted on the wiring substrate 101, A drain potential and a gate potential can be input or output to the drain and gate electrodes of the LDMOSFET circuits 131A, 131B, 131C, 132A, 132B, and 132C via the bump electrodes 40D and 40G, respectively, and the source bump electrode 40S can be output. The source potential (reference potential) can be supplied to the sources of the LDMOSFET circuits 131A, 131B, 131C, 132A, 132B, and 132C via the.

In the semiconductor chip CHP1, as shown in FIGS. 18 to 22, the drain (n ⁺ type drain region 14) of the LDMOSFET formed in the LDMOSFET formation region 1A (active region 6) is a plug 24 and a drain wiring 25D. The drain bump electrode 40D is electrically connected through the plug 28, the drain wiring 31D and the drain wiring 35D. The gate electrode 9 of the LDMOSFET formed in the LDMOSFET formation region 1A (active region 6) is a bump electrode for the gate through the plug 24, the gate wiring 25G, the plug 28, the gate wiring 31G and the gate wirings 35G and 35G1. It is electrically connected to 40G. The source (n ⁺ type source region 15) of the LDMOSFET formed in the LDMOSFET formation region 1A (active region 6) is the metal silicide layer 21 (and the plug 24 and the source wiring 25S1), the p ⁺ type semiconductor region 16, and the p ⁺ type semiconductor region 16. Electricity is supplied to the source bump electrode 40S via the die punching layer 4, the substrate 1, the p-type punching layer 4a, the p ⁺ type semiconductor region 16a, the plug 24, the source wiring 25S2, the plug 28, the source wiring 31S2 and the source wiring 35S2. Connected.

That is, in the semiconductor chip CHP1 of the present embodiment, the source (n ⁺ type source region 15) of the LDMOSFET formed in the LDMOSFET formation region 1A (active region 6) is electrically connected to the substrate 1 through the p-type punching layer 4. Connected. For this reason, the source regions (n ⁺ -type source regions 15) of the unit cell 20 are electrically connected to each other via the p-type punching layer 4 and the substrate 21. Since the element isolation region 5 is formed between the LDMOSFET formation region 1A (active region 6) and the source lead region 1B (active region 6a), the epitaxial layer 2 and the source of the LDMOSFET formation region 1A (active region 6) are formed. The isolation region 5 is electrically isolated from the epitaxial layer 2 in the extraction region 1B (active region 6a). However, in this embodiment, not only the p-type punching layer 4 is provided in the LDMOSFET formation region 1A (active region 6) but also the p-type punching layer 4a is provided in the source lead region 1B (active region 6a). The bottoms of the p-type punching layers 4 and 4 a reach the substrate 1, and the specific resistance of the punching layers 4 and 4 a is made lower than the specific resistance of the epitaxial layer 2, thereby reducing the p-type punching layers 4 and 4 a to the substrate 1. It is electrically connected with a resistor. The specific resistance of the substrate 1 is low, preferably 10 mΩcm or less. As a result, the p-type punching layer 4 in the LDMOSFET formation region 1A (active region 6) and the p-type punching layer 4a in the source lead region 1B (active region 6a) are interposed via the substrate 1 positioned below the element isolation region 5. Are electrically connected with a low resistance, and thereby, in the substrate 1 from the LDMOSFET formation region 1A (active region 6) to the source extraction region 1B (active region 6a) in the lateral direction (a direction parallel to the main surface of the substrate 1). ) So that the source current can be conducted.

As shown in FIG. 18 and the like, the p-type punching layer 4 in the LDMOSFET formation region 1A is provided with the source (n ⁺ ) of the LDMOSFET through the p ⁺ -type semiconductor region 16 and the metal silicide layer 21 (and the plug 24 and the source wiring 25S1). Electrically connected to the mold source region 15). The source lines 35S2, 31S2, and 25S2 (first source lines) are source lines (first source lines) that are electrically connected to the source bump electrode 40S as shown in FIGS. The p-type punching layer 4a is electrically connected via the plug 24 and the p ⁺ -type semiconductor region 16a.

For this reason, the source (n ⁺ -type source region 15) of the LDMOSFET formed in the LDMOSFET formation region 1A (active region 6) is electrically connected to the substrate 1 through the p-type punching layer 4 or the like. In the source lead region 1B (active region 6a), the p-type punching layer 4a, the p ⁺ type semiconductor region 16, the plugs 24 and 28, and the source wirings 25S2 and 31S2 are pulled up to the uppermost source wiring 35S2. The source wiring 35S2 of the uppermost layer is extended to the bump electrode formation position, and the source bump electrode 40S is formed there, so that only the drain and gate bump electrodes 40D and 40G are formed on the surface of the semiconductor chip CHP1. The bump electrode 40S for the source can also be formed.

Therefore, the source current conduction path (or source potential supply path) between the source (n ⁺ -type source region 15) of the LDMOSFET and the bump electrode 40S for the source is the metal silicide layer 21 (and the plug 24 and the source wiring 25S1). ), P ⁺ type semiconductor region 16, p type punching layer 4, substrate 1, p type punching layer 4a, p ⁺ type semiconductor region 16a, plug 24, source wiring 25S2, plug 28, source wiring 31S2 and source wiring 35S2. It becomes a route. Through this path, the source potential (reference potential) can be supplied from the source bump electrode 40S to the source (n ⁺ type source region 15) of the LDMOSFET formed in the LDMOSFET formation region 1A.

Further, in the present embodiment, as shown in FIGS. 18 to 20 and the like, the source current conduction path (or from the source bump electrode 40S to the source (n ⁺ -type source region 15) of the LDMOSFET formation region 1A) (or As a source potential supply path), the substrate 1 is conducted in the lateral direction (direction parallel to the main surface of the substrate 1) from the LDMOSFET formation region 1A to the source lead region 1B. For this reason, if the substrate 1 has a high resistance, the resistance of the path that conducts the substrate 1 in the lateral direction increases. Therefore, the substrate 1 preferably has a low resistance. Is preferably 10 mΩcm (10 milliohm centimeters) or less. As a result, the resistance of the conductive path from the source bump electrode 40S to the source (n ⁺ type source region 15) of the LDMOSFET formation region 1A can be reduced, and the source resistance can be reduced.

  Further, the length of the path that conducts in the lateral direction in the substrate 1 from the LDMOSFET formation region 1A to the source lead region 1B can be controlled by adjusting the planar layout of the active regions 6 and 6a. On the other hand, it is not easy to reduce the thickness of the substrate 1. For this reason, the semiconductor chip CHP1 of the present embodiment can reduce the source resistance as compared with the case where the source potential is supplied from the back electrode like the semiconductor chip CHP201.

  Further, in the present embodiment, the substrate 1 is punched by the p-type not by the LDMOSFET formation region 1A (active region 6) but by the source lead region 1B (active region 6a) separated from the LDMOSFET formation region 1A by the element isolation region 5. The source wiring 25S2 is pulled up to the lowermost source wiring 25S2 via the layer 4a and the plug 24, and the source wiring 25S2 is further pulled up to the upper layer source wiring 31S2 and the uppermost source wiring 35S2. Since the source bump electrode 40S is formed on a part of the source wiring 35S2 pulled up in the source lead-out region 1B, the source wiring 25S1 formed in the LDMOSFET formation region 1A (active region 6) extends to the uppermost layer wiring 35. There is no need to raise it.

Therefore, in the present embodiment, as shown in FIG. 18 and the like, in the LDMOSFET formation region 1A (active region 6), a wiring (first electrode) electrically connected to the source (n ⁺ type source region 15) of the LDMOSFET. 2 source wiring) is only the source wiring 25S1, and it is not necessary to form a source wiring in the same layer as the wirings 31 and 35 in the LDMOSFET formation region 1A (on the active region 6). That is, in the LDMOSFET forming region 1A (on the active region 6), the number of wiring layers (here, only one layer of the source wiring 25S1) for forming the source wiring (wiring electrically connected to the source of the LDMOSFET) is the drain wiring. It is smaller than the number of wiring layers (three layers of drain wirings 25D, 31D, and 35D in this case) forming the wiring (wiring electrically connected to the drain of the LDMOSFET). Thus, although the source wiring 25S1 adjacent to the drain wiring 25D is provided, but the source wiring adjacent to the drain wirings 31D and 35D is not provided, in the LDMOSFET formation region 1A (on the active region 6), Parasitic capacitance (output capacitance) with the source wiring can be reduced.

  In an LDMOSFET that is an amplifying element, the parasitic capacitance has a large effect on the high-frequency output characteristics. If the output capacitance increases, the impedance value decreases in the operation in the high-frequency band, so that the current flowing into the LDMOSFET increases. In addition, since the LDMOSFET also has a parasitic resistance, the loss (power consumed) caused by the parasitic resistance increases as the flowing current increases. For this reason, when the output capacitance increases, the power efficiency as the amplifying element decreases. However, in the present embodiment, the parasitic capacitance (output capacitance) between the drain wiring and the source wiring can be reduced as described above. Since the current flowing into the capacitor also becomes small, the power efficiency as an amplifying element can be improved.

  As described above, in this embodiment, since the semiconductor chip CHP1 is flip-chip mounted, it is difficult to take out the source electrode of the LDMOSFET from the back surface of the semiconductor chip CHP1, so that the source and the semiconductor chip CHP1 are similar to the gate and drain. Need to be taken out of the surface. Therefore, in the semiconductor chip CHP1, the source of the LDMOSFET is once connected to the low resistance substrate 1 through the punching layer 4, and then the punching layer 4a is formed in the active region 6a for extracting the source around the active region 6 for forming the LDMOSFET. Is connected to the substrate 1, and the source wirings 25S2, 31S2, and 35S2 (first source wiring) are electrically connected to the extraction layer 4a, whereby the source of the LDMOSFET is pulled up to the uppermost source wiring 35S2. Therefore, not only the gate and drain, but also the source can be taken out from the surface of the semiconductor chip CHP1, enabling the flip-chip mounting of the semiconductor chip CHP1, and the source wiring in the LDMOSFET formation region 1A (on the active region 6). The number of layers can be made smaller than the number of drain wiring layers. Therefore, in the LDMOSFET formation region 1A (region on the active region 6 for LDMOSFET), the parasitic capacitance between the source wiring and the drain wiring due to the adjacent source wiring and the drain wiring can be reduced, and the improvement in power efficiency can be improved. Can do.

In the present embodiment, as shown in FIGS. 14, 15, and 18, a metal silicide layer 21 is formed on the surfaces of the n ⁺ type source region 15 and the p ⁺ type semiconductor region 16. By providing the metal silicide layer 21, the n ⁺ -type source region 15 to the p ⁺ -type semiconductor region 16 can be provided via the metal silicide layer 21 without the source wiring 25 S 1 and the plug 24 connected to the source wiring 25 S 1. , A source current can flow from the p ⁺ type semiconductor region 16 to the p type punching layer 4 and from the p type punching layer 4 to the substrate 1. Therefore, in the LDMOSFET formation region 1A (on the active region 6), the formation of the source wiring 25S1 and the plug 24 connected to the source wiring 25S1 (and the contact hole 23 in which the plug 24 is embedded) can be omitted. . FIG. 24 is a cross-sectional view of the main part of a modification of the semiconductor chip CHP1 in which the source wiring 25S1, the plug 24 connected to the source wiring 25S1, and the contact hole 23 in which the plug 24 is embedded are omitted. This corresponds to FIG. As shown in FIG. 24, in the LDMOSFET formation region 1A (on the active region 6), the source wiring (the wiring electrically connected to the n ⁺ -type source region 15) does not exist, so that the drain wiring and The parasitic capacitance (output capacitance) between the source wiring and the source wiring can be further reduced, and the power efficiency of the LDMOSFET as an amplifying element can be further improved.

  However, when the formation of the metal silicide layer 21 is omitted, it is preferable to form the source wiring 25S1 and the plug 24 connected thereto. Even when the metal silicide layer 21 is formed, if the source wiring 25S1 and the plug 24 connected to the source wiring 25S1 are formed, the current density can be increased and more source current can flow. Reliability at a large current can be further improved.

Therefore, in the present embodiment, in the LDMOSFET formation region 1A (on the active region 6), the source wiring electrically connected to the source region (n ⁺ type source region 15) of the LDMOSFET is connected to the drain region (n ^{+ of the} LDMOSFET). The drain wiring (here, drain wiring 25D, 31D, 35D) electrically connected to the type drain region 14), or the number of layers is less than that of the LDMOSFET forming region 1A (on the active region 6) ) Is preferably not formed with a source wiring electrically connected to the source region (n ⁺ -type source region 15) of the LDMOSFET. Thereby, the parasitic capacitance (output capacitance) between the drain wiring and the source wiring can be reduced, and the power efficiency as an amplification element of the LDMOSFET can be improved.

Further, as shown in FIG. 17, (the width or dimension in the X-direction) width _W 1 of the source wiring 25S2,31S2 the same in the same layer drain wiring 25D, the width _W 2 (X-direction width or dimension) of 31D wider than _{(W 1> W} 2), as shown in FIG. 21, (the width or dimension in the X-direction) width _W 3 of the source wiring 35S2 is same width _W 4 (X direction of the drain line 35D in the same layer (W ₃ > W ₄ ). Thereby, source resistance can be reduced. Further, since the source wirings 25S2, 31S2, and 35S are formed not in the LDMOSFET formation region 1A (on the active region 6) but in the source lead region 1B (active region 6a), the width W of the source wirings 25S2, 31S2, and 35S is formed. ₁ and W ₃ can be easily widened, and even if the widths W ₁ and W ₃ of the source wirings 25S2, 31S2 and 35S are widened, the parasitic capacitance (output capacitance) between the drain wiring and the source wiring is increased. Can be prevented from increasing.

  Further, in the semiconductor chip CHP1 of the present embodiment, as shown in FIG. 11 and FIG. 20, the drain bump electrode 40D and the source bump are disposed at the planar positions opposed via the active region 6 (region 6b). The electrode 40S is arranged, and the bump electrode 40G for the gate is arranged between the drain bump electrode 40D and the bump electrode 40S for the source and at a planar position that is the periphery of the active region 6 (region 6b). Yes. By arranging the bump electrodes 40D, 40G, and 40S in such a manner, the number of drain bump electrodes 40D and source bump electrodes 40Sb arranged around the active region 6 (region 6b) is increased. In addition, the number of the drain bump electrodes 40D and the number of the source bump electrodes 40Sb can be easily made the same. Thereby, the characteristics of the LDMOSFET circuit can be improved. In addition, since a large current flows between the source and the drain in the final amplification stages AMP13 and AMP23 (that is, the LDMOSFET circuits 131C and 132C) of the power amplifier circuits AMP1 and AMP2, in particular, in the LDMOSFET circuits 131C and 132C, It is preferable to increase the number of bump electrodes 40D and source bump electrodes 40S, and it is preferable that the number of drain bump electrodes 40D and source bump electrodes 40Sb be the same.

In this embodiment, as shown in FIGS. 14, 15 and 18, a metal silicide layer 21 is provided, and the n ⁺ type source region 15 and the p ⁺ type semiconductor region of the LDMOSFET are provided via the metal silicide layer 21. 16 (p-type punching layer 4) is electrically connected. As another form, instead of providing the metal silicide layer 21, a metal film (for example, a tungsten film) is formed in the n ⁺ type source region 15 and the p ⁺ type semiconductor region 16 (p type punching layer 4), and the metal film is interposed therebetween. Thus, the n ⁺ type source region 15 and the p ⁺ type semiconductor region 16 (p type punching layer 4) of the LDMOSFET can be electrically connected.

  In the present embodiment, the three-layer wiring structure of the wirings 25, 31, and 35 is formed. However, as another form, one of the wiring 25 and the wiring 31 can be omitted. When the formation of one of the wiring 25 and the wiring 31 is omitted, the interlayer insulating film and the plug between the wiring 25 and the wiring 31 are not necessary, so that the formation of the insulating film 26 and the plug 28 is also omitted.

(Embodiment 2)
25 to 27 are main part plan views of the semiconductor chip CHP1a of the present embodiment, and correspond to FIGS. 20, 16, and 11 of the first embodiment, respectively. FIG. 28 is a main-portion cross-sectional view of the semiconductor chip CHP1a of the present embodiment and substantially corresponds to the cross-sectional view taken along the line GG in FIG.

  The semiconductor chip CHP1a in the present embodiment corresponds to the semiconductor chip CHP1 in the first embodiment. In the semiconductor chip CHP1 of the first embodiment, the source wiring 35S2 drawn in the source lead region 1B (active region 6a) is extended to a position away from the source lead region 1B (active region 6a), and then the source wiring The bump electrode 40S was formed. For this reason, the source bump electrode 40S is located away from the source lead region 1B (active region 6a) and above the element isolation region 5.

  On the other hand, as can be seen from FIGS. 25 to 28, the semiconductor chip CHP1a of the present embodiment has the source bump electrode 40S on the source wiring 35S2 drawn in the source lead region 1B (active region 6a). The source bump electrode 40S is formed so as to be positioned in the source lead region 1B (above the active region 6a). That is, in the semiconductor chip CHP1a, the source bump electrode 40D is disposed above (directly above) the punching layer 4a, and the punching layer 4a (and the active region 6a) is below (directly below) the source bump electrode 40D. Is provided. Then, a drain bump electrode 40D and a gate bump electrode 40G are arranged at a planar position facing each other through the active region 6, and the source bump electrode 40S is connected to the drain bump electrode 40D and the gate bump. The electrode 40G is disposed at a planar position on the active region 6a. In FIG. 25 to FIG. 27, the bump electrode 40S for the source is provided at a position facing the active region 6; however, the source bump electrode 40S may be provided on both sides as shown in FIG. A bump electrode 40S may be provided. Since the other configuration of the semiconductor chip CHP1a is substantially the same as that of the semiconductor chip CHP1 of the first embodiment, the description thereof is omitted here. Further, the configuration of the RF power module using the semiconductor chip CHP1a is substantially the same as that of the RF power module PM1 of the first embodiment, and therefore the description thereof is omitted here.

  In the present embodiment, the source bump electrode 40S is arranged in a different plane position from the source extraction region 1B by arranging the source bump electrode 40S in the source extraction region 1B (above the active region 6a). Compared to the case, the planar dimension of the semiconductor chip can be further reduced.

(Embodiment 3)
29 and 30 are main part plan views of the semiconductor chip CHP1b according to the present embodiment. FIG. 29 corresponds to FIG. 25 of the second embodiment, and is a wiring (that is, source wiring 25S1, drain wirings 35D and 51D, and gate wiring 31G that can be seen through each insulating film from above the semiconductor chip CHP1b. , 35G, 51G and the source wiring 51S2) and the bump electrodes 40D, 40G, 40S are shown, and the other components are not shown. 30 corresponds to a diagram in which the drain wiring 51D, the gate wiring 51G, the source wiring 51S2, and the bump electrodes 40D, 40G, and 40S, which are the uppermost layer wirings, are further removed (see through) from FIG. FIG. 31 is a main-portion cross-sectional view of the semiconductor chip CHP1b, and corresponds to a cross-sectional view taken along line GG or line HH in FIG.

  In the semiconductor chips CHP1 and CHP1a of the first and second embodiments, the bump electrode 40 is not disposed in the LDMOSFET forming region 1A (on the active region 6). However, in the semiconductor chip CHP1b of the present embodiment, the LDMOSFET is formed. Bump electrodes 40 (here, drain bump electrode 40D and gate bump electrode 40G) are arranged in region 1A (on active region 6).

  As can be seen from FIGS. 29 to 31, the semiconductor chip CHP1 b of the present embodiment has a wiring 51 as the uppermost wiring in addition to the wirings 25, 31, and 35. A bump electrode 40 is formed via the UBM film 39. Therefore, the wiring layer shown in FIG. 30 in which the wiring 51 is omitted is a wiring layer corresponding to FIG. 25 of the second embodiment. As shown in FIG. 30, the semiconductor chip CHP1b according to the present embodiment has a structure (wiring) up to the wiring 35 except that the drain wiring 35D and the gate wiring 35G are not provided with a large area pattern portion to be the pad electrode 38. 35 and the structure below the wiring 35) are substantially the same as those of the semiconductor chip CHP1a of the second embodiment.

  In the semiconductor chip CHP1b of the present embodiment, as shown in FIG. 31, an insulating film (interlayer insulating film) 36a made of a silicon oxide film or the like is formed on the insulating film 32 so as to cover the wiring 35. A through hole (not shown) exposing a part of the wiring 35 is formed in the film 36a, and a wiring (fourth layer wiring) 51 is formed on the insulating film 36a. The wiring 51 includes a drain wiring 50D that is electrically connected to the drain wiring 35D via a via portion (a portion that fills the through hole of the insulating film 36a), and a gate wiring that is electrically connected to the gate wiring 35G via the via portion. 50G and a source wiring 51S2 electrically connected to the source wiring 35S2 through a via portion. Further, an insulating film (surface protective film) 52 similar to the insulating film 36 is formed on the insulating film 36 a so as to cover the wiring 51, an opening 53 is formed in the insulating film 52, and exposed from the opening 53. A bump electrode 40 is formed on the formed wiring 51 via the UBM film 39. The bump electrode 40 formed on the drain wiring 51D is a drain bump electrode 40D, and the bump electrode 40 formed on the gate wiring 51G is a gate bump electrode 40G, which is formed on the source wiring 51S2. The bump electrode 40 is a source bump electrode 40S.

  In the semiconductor chips CHP1 and CHP1a of the first and second embodiments, the pad electrode 38 for forming the bump electrode is formed by the wiring 35. However, in the semiconductor chip CHP1b of the present embodiment, the wiring higher than the wiring 35 is formed. 51 is a pad electrode for forming a bump electrode, and a bump electrode 40 is formed there.

As shown in FIGS. 29 and 30, the source wiring 51S2 has a pattern (planar pattern) substantially the same as the source wiring 35S2. Although not shown here, the substrate 1 is placed in the uppermost layer via the p-type punching layer 4a, the p ⁺ -type semiconductor region 16, the plugs 24 and 28, and the source wirings 25S2, 31S2, and 35S in the source extraction region 1B (active region 6a). The source wiring 51S2 is pulled up to form a source bump electrode 40S on a part of the source wiring 51S2.

Further, in the semiconductor chip CHP1b of the present embodiment, as shown in FIGS. 29 to 31, in the LDMOSFET formation region 1A (active region 6), the drain region (n ⁺ -type drain region 14) of the LDMOSFET is plugged 24. , 28 and the drain wirings 25D, 31D are pulled up to the drain wiring 35D. This is the same as the semiconductor chips CHP1 and CHP1a of the first and second embodiments. In the semiconductor chip CHP1b of the present embodiment, the drain wiring 35D is electrically connected to the uppermost drain wiring 51D on the element isolation region 5 around the LDMOSFET formation region 1A (active region 6). 29 and 31 are extended to the LDMOSFET formation region 1A (on the active region 6), and a drain bump electrode 40D is formed there.

  Further, in the semiconductor chip CHP1b of the present embodiment, as in the semiconductor chips CHP1 and CHP1a of the first and second embodiments, the gate electrode 9 in the LDMOSFET formation region 1A (active region 6) is connected to the plugs 24 and 28 and the gate wiring 25G. , 31G to the gate wiring 35G. In the semiconductor chip CHP1b of the present embodiment, the gate wiring 35G is electrically connected to the uppermost gate wiring 51G on the element isolation region 5 around the LDMOSFET formation region 1A (active region 6). 29 and 31 are extended to the LDMOSFET formation region 1A (on the active region 6), and a gate bump electrode 40D is formed there.

  Since the other configuration of the semiconductor chip CHP1b is substantially the same as that of the semiconductor chip CHP1a of the second embodiment, the description thereof is omitted here. Further, the configuration of the RF power module using the semiconductor chip CHP1b is almost the same as that of the RF power module PM1 of the first embodiment, and therefore the description thereof is omitted here.

  As described above, the semiconductor chip CHP1b of the present embodiment includes at least one of the drain bump electrode 40D, the gate bump electrode 40G, and the source bump electrode 40S (here, the drain bump electrode 40D). And the bump electrode 40G for the gate are arranged in the LDMOSFET formation region 1A (on the active region 6). Thereby, the planar dimensions of the semiconductor chip can be further reduced as compared with the case where the bump electrodes 40D, 40S, and 40G are arranged outside the LDMOSFET formation region 1A (region on the active region 6).

  Moreover, since the number of wiring layers can be reduced in the semiconductor chips CHP1 and CHP1a of the first and second embodiments, the number of manufacturing steps can be reduced.

(Embodiment 4)
In the first to third embodiments, the source is drawn out and electrically applied to the source bump electrode 40S in the source lead region 1B (above the active region 6a) provided separately from the LDMOSFET formation region 1A (active region 6). I was connected. In the present embodiment, the source is drawn out in the LDMOSFET formation region 1A (active region 6), and the wiring (layout) of the wiring is devised to be electrically connected to the source bump electrode 40S.

  32 to 34 are main part plan views of the semiconductor chip CHP1c of the present embodiment, and correspond to FIGS. 11, 16, and 20 of the first embodiment, respectively. 35 to 37 are main-portion cross-sectional views of the semiconductor chip CHP1c of the present embodiment, and correspond to FIGS. 18, 19 and 22 of the first embodiment, respectively. 35 corresponds to a cross-sectional view taken along line KK in FIG. 33, and FIG. 36 is a cross-sectional view taken along line L1-L1, L2-L22, or L3-L3 in FIG. Correspondingly, FIG. 37 corresponds to a cross-sectional view of a position along the line MM in FIG.

In the semiconductor chip CHP1c of the present embodiment, as shown in FIG. 32, the active region 6 for forming the LDMOSFET is provided, but the active region 6a for extracting the source is not provided. Therefore, the p-type punching layer 4a, the p ⁺ -type semiconductor region 16, the plugs 24 and 28 (plugs 24 and 28 connected to the source wirings 25S2 and 31S2) and the source wiring formed in the source leading region 1B in the first embodiment. 25S2, 31S2, and 35S2 are not formed in the semiconductor chip CHP1c of the present embodiment. Instead, in the semiconductor chip CHP1 of the present embodiment, the wiring 31 has a source wiring 31S1, and the wiring 35 has a source wiring 35S1.

  In the semiconductor chip CHP1c of the present embodiment, the configuration of the LDMOSFET formed in the active region 6 for forming the LDMOSFET (that is, the LDMOSFET formation region 1A) is the same as that of the first embodiment, and therefore the description thereof is omitted here. . Also in the semiconductor chip CHP1c, the same source wiring S1 and drain wirings 25D1, 25D2 as those in the first embodiment and the plug 24 connected to them are formed.

Similar to the first embodiment, also in the semiconductor chip CHP1c of the present embodiment, as shown in FIGS. 32 to 37, in the active region 6 (LDMOSFET formation region 1A), the drain region of each unit cell 20 ( The n ⁺ -type drain region 14) is pulled up to the uppermost drain wiring 35D through the plug 24, the drain wiring 25D, the plug 28 and the drain wiring 31D, and is electrically connected to the drain wiring 35D. The bump electrode 40D is formed.

  As in the first embodiment, as shown in FIG. 33, drain wirings 25D and 31D (drain wiring 25D and drain wiring 31D are the same plane pattern) are isolated patterns formed only on each active region 6. However, as shown in FIG. 34 to FIG. 37, the drain wirings 25D and 31D are electrically connected via the uppermost drain wiring 35D extending in the Y direction and via portions (portions through which the through holes 33 are filled). It is connected to the. The uppermost drain wiring 35 </ b> D has an integral pattern (comb-like pattern) in which the portions extending in the Y direction across the plurality of active regions 6 arranged in the Y direction are connected at the ends. The connecting portion becomes a large area pattern, which becomes the pad electrode 38, and the bump electrode 40D for drain is formed through the UBM film 39. That is, the drain wirings 25D and 31D in the present embodiment have the same pattern as the drain wirings 25D and 31D in the first embodiment, and the drain wiring 35D in the present embodiment has no portion corresponding to the active region 6a. Except for this, the pattern is almost the same as the drain wiring 35D of the first embodiment.

  Therefore, the connection path from the drain region of the LDMOSFET formed in the active region 6 to the drain bump electrode 40D is substantially the same as in the first embodiment. However, the connection path from the source region of the LDMOSFET formed in the active region 6 to the source bump electrode 40S is different from that of the first embodiment.

That is, as shown in FIGS. 32 to 37, in the semiconductor chip CHP1c of the present embodiment, the source wiring 31S1 composed of the wiring 31 (that is, the source wiring 31S1 in the same layer as the drain wiring 31D) is formed in the LDMOSFET formation region 1A ( It is formed in the same pattern (planar pattern) as the source line 25S1 on the active region 6) and is electrically connected to the source line 25S1 through the plug 24. Furthermore, in the semiconductor chip CHP1c of the present embodiment, the source wiring 35S1 composed of the wiring 35 (that is, the source wiring 35S1 in the same layer as the drain wiring 35D) is formed in the LDMOSFET formation region 1A (on the active region 6). It is electrically connected to the source wiring 31S1 through a via part (a part filling the through hole 33). As a result, in the active region 6 (LDMOSFET formation region 1A), the source region (n ⁺ -type source region 15) of each unit cell 20 is the uppermost layer via the plug 24, the source wiring 25S1, the plug 28, and the source wiring 31S1. The source wiring 35S1 is pulled up to be electrically connected to each other, and a source bump electrode 40S is formed on the source wiring 35S1.

  As shown in FIG. 33, like the drain wirings 25D and 31D, the source wirings 25D and 31D are isolated patterns formed only on the active regions 6, but as shown in FIGS. The upper part of the source wirings 25D and 31D is electrically connected to the uppermost source wiring 35S1 extending in the Y direction via a via part (a part filling the through hole 33). The uppermost source wiring 35 </ b> S has an integral pattern (comb-like pattern) in which the portions extending in the Y direction across a plurality of active regions 6 arranged in the Y direction are connected at the ends. The connecting portion becomes a large area pattern, which becomes the pad electrode 38, and the bump electrode 40S for the source is formed through the UBM film 39.

  However, in the drain wiring 35D, the ends of the portions extending in the Y direction on the active region 6 and the ends of the portions extending in the Y direction on the active region 6 in the source wiring 35S are connected. Are connected to each other through the active region 6 (region 6b). That is, the drain wiring 35D and the source wiring 35S extending in the Y direction are alternately arranged on the active region 6, and the opposite ends of the drain wiring 35D and the source wiring 35S are connected to each other. For this reason, in the drain wiring 35D and the source wiring 35S, it is easy to secure a region for forming the bump electrode (a portion to become the pad electrode 38) by increasing the area of each connecting portion.

  Similarly to the first embodiment, also in the semiconductor chip CHP1c of the present embodiment, the gate electrode 9 extends in the Y direction and is located on the element isolation region 5 around or between the active regions 6 Thus, the gate wirings 25G and 31G (the drain wiring 25D and the drain wiring 31D are the same plane pattern) are electrically connected via the plugs 24 and 28. The gate wirings 25G and 31G extend in the X direction on the element isolation region 5 around or between the active regions 6. Therefore, the gate wirings 25G and 31G in the present embodiment have substantially the same pattern as the gate wirings 25G and 31G in the first embodiment except that the portion corresponding to the active region 6a is eliminated.

  The gate wiring 25G is a wiring in the same layer as the drain wiring 25D and the source wiring 25S1, and the gate wiring 31G is a wiring in the same layer as the drain wiring 31D and the source wiring 31S1, but between the active regions 6 as described above. The drain wirings 25D and 31D and the source wirings 25S1 and 31S1 are not formed on the element isolation region 5, and the gate wirings 25G and 31G extend in the X direction. Therefore, as shown in FIG. 33, the drain wirings 25D and 31D and the source wirings 25S1 and 31S1 extending in the Y direction are arranged between the gate wirings 25G and 31G extending in the X direction. Yes.

  The gate wiring 31G extending in the X direction is electrically connected to the gate wiring 35G extending in the Y direction around the element isolation region 5 around or between the active regions 6 and via portions (portions through which the through holes 33 are filled). As a result, the gate lines 31G extending in the X direction are electrically connected to each other via the gate line 35G extending in the Y direction. The gate wiring 35G located on the outermost side extends in a direction away from the active region 6 to form a large area pattern, which becomes a pad electrode 38, and a gate bump electrode 40G is formed via the UBM film 39. Yes. Therefore, on the element isolation region 5 around or between the active regions 6, the gate electrode 9 of each unit cell 20 is pulled up to the gate wirings 25G and 31G via the plugs 24 and 28, and the gate wirings 25G and 31G are connected. Extending in the X direction, connected to the uppermost gate wiring 35G outside the active region 6 so as to be electrically connected to each other, and a gate bump electrode 40G is formed on the gate wiring 35G. .

  Since the other configuration of the semiconductor chip CHP1c is substantially the same as that of the semiconductor chip CHP1 of the first embodiment, the description thereof is omitted here. Further, the configuration of the RF power module using the semiconductor chip CHP1c is substantially the same as that of the RF power module PM1 of the first embodiment, and the description thereof is omitted here.

  Thus, in the semiconductor chip CHP1c of the present embodiment, both the drain and source of the LDMOSFET formed in the LDMOSFET formation region 1A (active region 6) are used as the uppermost drain in the LDMOSFET formation region 1A (on the active region 6). The wiring 35D and the source wiring 35S1 are pulled up. Then, the drain wiring 35D and the source wiring 35S1 are extended to the outside opposite to the LDMOSFET formation region 1A (active region 6), the drain wirings 35D are connected to each other, and the drain pad electrode 40D is formed there. In addition, the source wirings 35S1 are connected to each other, and a source pad electrode 40S is formed there. The gate electrode 9 is pulled up to the gate wirings 25G and 31G on the element region 5. Since the gate wirings 25G and 31G are wirings lower than the drain wiring 35D and the source wiring 35S1, the gate wirings 25G and 31G extend to the outside of the active region 6 without being disturbed by the layout of the drain wiring 35D and the source wiring 35S1 on the active region 6. The gate wirings 25G and 31G can be pulled up to the uppermost gate wiring 35G on the element isolation region 5 outside the active region 6, and a gate bump electrode 40G can be formed on a part of the gate wiring 35G. Forming. By adopting such a wiring structure, a semiconductor chip CHP1c having a drain bump electrode 40D, a gate bump electrode 40G, and a source bump electrode 40S on the surface can be realized. Thereby, since the semiconductor chip CHP1c can be flip-chip mounted, the mounting area of the semiconductor chip CHP1c can be reduced.

  Further, in the semiconductor chip CHP1c of the present embodiment, as shown in FIGS. 32 to 34, the drain bump electrode 40D and the source bump electrode are disposed at planar positions facing each other through the active region 6 (region 6b). 40S, and the bump electrode 40G for the gate is disposed between the drain bump electrode 40D and the bump electrode 40S for the source and at a planar position around the active region 6 (region 6b). . If the wiring structure as described above is taken, the bump electrodes 40D, 40G, and 40S can be arranged as described above. By arranging the bump electrodes 40D, 40G, and 40S in such a manner, the number of drain bump electrodes 40D and source bump electrodes 40Sb arranged around the active region 6 (region 6b) is increased. In addition, the number of the drain bump electrodes 40D and the number of the source bump electrodes 40Sb can be easily made the same. Thereby, the characteristics of the LDMOSFET circuit can be improved. In addition, since a large current flows between the source and the drain in the final amplification stages AMP13 and AMP23 (that is, the LDMOSFET circuits 131C and 132C) of the power amplifier circuits AMP1 and AMP2, in particular, in the LDMOSFET circuits 131C and 132C, It is preferable to increase the number of bump electrodes 40D and source bump electrodes 40S, and it is preferable that the number of drain bump electrodes 40D and source bump electrodes 40Sb be the same.

In the present embodiment, the source region (n ⁺ type source region 15) of the LDMOSFET is electrically connected to the bump electrode 40S for the source via the plugs 24, 28 and the source wirings 25S1, 31S1, 35S1. The conductive path from the source region (n ⁺ type source region 15) of the LDMOSFET to the bump electrode 40S for source does not pass through the substrate 1. For this reason, in this embodiment, the substrate 1 does not have to be a low resistance substrate (a substrate having a low specific resistance). In the present embodiment, the LDMOSFET source region is connected to the substrate 1 because the substrate 1 does not pass through the conductive path from the LDMOSFET source region (n ⁺ -type source region 15) to the source bump electrode 40S. The formation of the p-type punching layer 4 can be omitted. In the present embodiment, the formation of the epitaxial layer 2 can be omitted, and the LDMOSFET can be formed not on the epitaxial layer 2 but on the substrate 1 itself.

(Embodiment 5)
FIGS. 38 and 39 are principal part plan views of the semiconductor chip CHP1d of the present embodiment, and correspond to FIGS. 29 and 30 of the third embodiment, respectively. FIG. 38 shows wirings (that is, source wirings 35S1 and 51S1, drain wirings 35D and 51D and gate wirings 31G, 35G, and 51G) and bump electrodes 40D, 40G, and 40S that can be seen through the respective insulating films from above the semiconductor chip CHP1d. The planar layout is shown, and the other components are not shown. FIG. 39 corresponds to a view in which the drain wiring 51D, the gate wiring 51G and the source wiring 51S1, which are the uppermost wiring, and the bump electrodes 40D, 40G, and 40S are further removed (see through) from FIG. 40 is a main-portion cross-sectional view of the semiconductor chip CHP1d, and corresponds to a cross-sectional view taken along line N1-N1 or N2-N2 in FIG.

  In the semiconductor chip CHP1c of the fourth embodiment, the bump electrode 40 is not disposed in the LDMOSFET formation region 1A (on the active region 6). However, in the semiconductor chip CHP1d of the present embodiment, the LDMOSFET formation region 1A (active A bump electrode 40 (here, a drain bump electrode 40D and a source bump electrode 40S) is disposed on the region 6.

  As can be seen from FIG. 38 to FIG. 40, the semiconductor chip CHP1d of the present embodiment further includes the wiring 51 as the uppermost wiring as in the third embodiment in addition to the wirings 25, 31, and 35. The bump electrode 40 is formed on the wiring 51 through the UBM film 39.

  That is, in the semiconductor chip CHP1d of the present embodiment, as shown in FIG. 38, an insulating film (interlayer insulating film) 36a made of a silicon oxide film or the like is formed on the insulating film 32 so as to cover the wiring 35. A through hole (not shown) exposing a part of the wiring 35 is formed in the insulating film 36a, and a wiring (fourth layer wiring) 51 is formed on the insulating film 36a. The wiring 51 includes a drain wiring 50D that is electrically connected to the drain wiring 35D via a via portion (a portion that fills the through hole of the insulating film 36a), and a gate wiring that is electrically connected to the gate wiring 35G via the via portion. 50G and a source wiring 51S1 electrically connected to the source wiring 35S1 through a via portion. Further, an insulating film (surface protective film) 52 similar to the insulating film 36 is formed on the insulating film 36 a so as to cover the wiring 51, an opening 53 is formed in the insulating film 52, and exposed from the opening 53. A bump electrode 40 is formed on the formed wiring 51 via the UBM film 39. The bump electrode 40 formed on the drain wiring 51D is a drain bump electrode 40D, and the bump electrode 40 formed on the gate wiring 51G is a gate bump electrode 40G, which is formed on the source wiring 51S1. The bump electrode 40 is a source bump electrode 40S.

  As shown in FIG. 38, the semiconductor chip CHP1d of the present embodiment has a wiring 35 except that the drain wiring 35D, the gate wiring 35G, and the source wiring 35S1 are not provided with a large area pattern portion that becomes the pad electrode 38. Since the structure up to this point (wiring 35 and the structure below the wiring 35) is substantially the same as that of the semiconductor chip CHP1d of the fourth embodiment, description thereof is omitted here.

In the semiconductor chip CHP1d of the present embodiment, as shown in FIGS. 38 to 40, in the LDMOSFET formation region 1A (active region 6), the drain region (n ⁺ -type drain region 14) of the LDMOSFET is plugged 24, 28. And it is pulled up to the drain wiring 35D via the drain wirings 25D and 31D. This is the same as the semiconductor chip CHPc of the fourth embodiment. The semiconductor chip CHP1b of the present embodiment electrically connects the drain wiring 35D to the uppermost drain wiring 51D on the element isolation region 5 around the LDMOSFET formation region 1A (active region 6). As shown in FIGS. 38 and 40, the wiring 51D extends to the LDMOSFET formation region 1A (on the active region 6), and a drain bump electrode 40D is formed there.

Further, as shown in FIGS. 38 to 40, in the semiconductor chip CHP1d of the present embodiment, the LDMOSFET source region (n ⁺ -type source region 15) is plugged in the LDMOSFET formation region 1A (active region 6). , 28 and the source wirings 25S1, 31S1 up to the source wiring 35S1. This is the same as the semiconductor chip CHPc of the fourth embodiment. The semiconductor chip CHP1b of the present embodiment electrically connects the source wiring 35S1 to the uppermost source wiring 51S1 on the element isolation region 5 around the LDMOSFET formation region 1A (active region 6). As shown in FIGS. 38 and 40, the wiring 51S1 extends to the LDMOSFET formation region 1A (on the active region 6), and the source bump electrode 40S is formed there.

  Further, in the semiconductor chip CHP1b of the present embodiment, the gate wiring 35G is electrically connected to the uppermost gate wiring 51G on the element isolation region 5, and this gate wiring 51G is shown in FIGS. 38 and 40. In addition, the bump electrode 40G for the gate is formed extending outside the LDMOSFET formation region 1A (on the active region 6).

  Since the other configuration of the semiconductor chip CHP1d of the present embodiment is substantially the same as that of the semiconductor chip CHP1d of the fourth embodiment, the description thereof is omitted here. Further, the configuration of the RF power module using the semiconductor chip CHP1d is substantially the same as that of the RF power module PM1 of the first embodiment, and therefore the description thereof is omitted here.

  As described above, the semiconductor chip CHP1d of the present embodiment includes at least one of the drain bump electrode 40D, the gate bump electrode 40G, and the source bump electrode 40S (here, the drain bump electrode 40D). And the bump electrode 40G for source are arranged in the LDMOSFET formation region 1A (on the active region 6). Thereby, the planar dimensions of the semiconductor chip can be further reduced as compared with the case where the bump electrodes 40D, 40S, and 40G are arranged outside the LDMOSFET formation region 1A (region on the active region 6).

  Further, since the number of wiring layers can be reduced in the semiconductor chip CHP1c of the fourth embodiment, the number of manufacturing steps can be reduced.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is suitable for application to, for example, a power amplification module mounted on a mobile communication device and a semiconductor device used therefor.

It is a circuit block diagram of RF power module of Embodiment 1 of the present invention. It is explanatory drawing which shows an example of the digital mobile telephone system using the RF power module of embodiment of this invention. It is a perspective view which shows the RF power module of one embodiment of this invention. FIG. 4 is a top view of the RF power module of FIG. 3. It is sectional drawing of the RF power module of FIG. It is a side view which shows the state which mounted the RF power module of FIG. 3 on the mounting board | substrate. It is a perspective view which shows the RF power module of a comparative example. It is a top view of the semiconductor chip of one embodiment of the present invention. It is a top view of the semiconductor chip of the comparative example used with the RF power module of the comparative example of FIG. It is principal part sectional drawing in the manufacturing process of the semiconductor device of one embodiment of this invention. FIG. 11 is an essential part plan view of the same semiconductor device as in FIG. 10 in manufacturing process. FIG. 11 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 10; FIG. 13 is an essential part plan view of the same semiconductor device as in FIG. 12 in manufacturing process. FIG. 13 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 12; FIG. 15 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 14; FIG. 16 is an essential part plan view of the same semiconductor device as in FIG. 15 in manufacturing process; FIG. 16 is an essential part plan view of the same semiconductor device as in FIG. 15 in manufacturing process; FIG. 18 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 17; FIG. 18 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 17; It is a principal part top view of the semiconductor device of one embodiment of this invention. It is a principal part top view of the semiconductor device of one embodiment of this invention. It is principal part sectional drawing of the semiconductor device of one embodiment of this invention. It is a principal part top view of the semiconductor chip of the comparative example of FIG. It is principal part sectional drawing of the semiconductor device of other embodiment of this invention. It is a principal part top view of the semiconductor device of other embodiment of this invention. It is a principal part top view of the semiconductor device of other embodiment of this invention. It is a principal part top view of the semiconductor device of other embodiment of this invention. It is principal part sectional drawing of the semiconductor device of other embodiment of this invention. It is a principal part top view of the semiconductor device of other embodiment of this invention. It is a principal part top view of the semiconductor device of other embodiment of this invention. It is principal part sectional drawing of the semiconductor device of other embodiment of this invention. It is a principal part top view of the semiconductor device of other embodiment of this invention. It is a principal part top view of the semiconductor device of other embodiment of this invention. It is a principal part top view of the semiconductor device of other embodiment of this invention. It is principal part sectional drawing of the semiconductor device of other embodiment of this invention. It is principal part sectional drawing of the semiconductor device of other embodiment of this invention. It is principal part sectional drawing of the semiconductor device of other embodiment of this invention. It is a principal part top view of the semiconductor device of other embodiment of this invention. It is a principal part top view of the semiconductor device of other embodiment of this invention. It is principal part sectional drawing of the semiconductor device of other embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 1A LDMOSFET formation region 1B Source extraction region 1C Bump electrode formation region 2 Epitaxial layer 3, 3a Groove 4, 4a p-type punching layer 5 Element isolation region 6, 6a Active region 6b region 7 P-type well 8 Gate insulating film 9 Gate Electrode 10 n ⁻ type drift region 11 n ⁻ type source region 12 Side wall spacer 13 n type drift region 14 n ⁺ type drain region 15 n ⁺ type source region 16, 16a p ⁺ type semiconductor region 21 Metal silicide layer 22 Insulating film 23 Contact hole 24 Plug 25, 31, 35, 51 Wiring 25D, 31D, 35D, 51D Drain wiring 25G, 31G, 35G, 51G Gate wiring 25S1, 25S2, 31S1, 31S2, 35S1, 35S2, 51S1 Source wiring 26 Insulating film 27 Through Hall 2 Plug 32 Insulating film 33 Through hole 36, 36a Insulating film 37 Opening 38 Pad electrode 39 UBM film 40, 40D, 40G, 40S Bump electrode 52 Insulating film 53 Opening 101 Wiring board 101a Upper surface 101b Lower surface 102 Passive component 103 Sealing resin 104 Insulator layer 105a Conductor pattern 105b External connection terminal 105c Reference potential supply terminal 106 Via hole 107a Front surface 107b Back surface 108 Bump electrode 109 Solder 111 Mounting substrate 111a Upper surface 112 Component 113 Terminal 114 Solder 131A to 131C, 132A to 132C LDMOSFET circuit 133 Element Formation area 151 Front end module 152 Baseband circuit 153 Modulation / demodulation circuit 154a Switch circuit 154b Switch circuit 156 Demultiplexer 201 Wiring board 202 Passive component 203 Bonding wire 205a Conductor pattern 210 Region 231A to 231C, 232A to 232C LDMOSFET circuit 233 Element formation region AJC1 to AJC4 Matching circuit AMP1, AMP2 Power amplification circuit AMP11 to AMP13, AMP21 to AMP23 Amplification stage BAC1, BAC2 Bias circuit BIT1, BIT2 Bias Control signal input terminals C5, C6 Capacitors CHP1, CHP1a, CHP1b, CHP1c, CHP1d, CHP201 Semiconductor chips CNT1, CNT2 Switching signal DEC1, DEC2 Detection circuit FLT1, FLT2 Filter IPT1, IPT2 Input terminals OPT1-OPT4 Output terminal PD Pad electrodes PDD1- PDD6, PDD201 to PDD206 Drain pads PDG1 to PDG6, PDG201 to PD G206 gate pad PDS1~PDS6 source pad PM1, PM201 RF power module PSC1, PSC2 power circuit RG1 regions _W 1 to _W-4 Width

Claims (20)

An electronic device having a power amplifier circuit,
A wiring board;
An LDMOSFET element that constitutes the power amplifier circuit is formed, and a semiconductor chip flip-chip mounted on the main surface of the wiring board;
An electronic device comprising: The electronic device according to claim 1.
An electronic device, wherein the wiring board is a multilayer wiring board. The electronic device according to claim 1.
An electronic device further comprising a passive component for a matching circuit of the power amplifier circuit mounted on the main surface of the wiring board. The electronic device according to claim 1.
The LDMOSFET element which comprises the said power amplifier circuit is all formed in the said one semiconductor chip, The electronic device characterized by the above-mentioned. The electronic device according to claim 1.
The power amplifier circuit has a multistage configuration in which a plurality of amplifier circuits are connected in multiple stages,
Each of the amplifier circuits is constituted by an LDMOSFET element,
An electronic device, wherein an LDMOSFET element constituting each of the amplifier circuits is formed on the semiconductor chip. The electronic device according to claim 5.
The LDMOSFET element constituting each of the amplifier circuits is configured by connecting a plurality of unit LDMOSFET elements in parallel. The electronic device according to claim 1.
The electronic device is a power amplification module for a mobile communication device. A semiconductor device including an LDMOSFET element constituting a power amplifier circuit and having a plurality of bump electrodes formed on a surface thereof,
A semiconductor substrate;
A semiconductor layer formed on the main surface of the semiconductor substrate;
A source region and a drain region of the LDMOSFET element formed in the first active region for forming the LDMOSFET element of the semiconductor layer;
A gate electrode of the LDMOSFET element formed on the first active region of the semiconductor layer via a gate insulating film;
A first stamped layer formed in the first active region of the semiconductor layer;
A second punched layer formed in a second active region different from the first active region of the semiconductor layer;
A wiring structure formed on the semiconductor layer;
Have
The plurality of bump electrodes include a source bump electrode;
The wiring structure includes a first source wiring electrically connected to the source bump electrode,
The source region is electrically connected to the semiconductor substrate via the first stamped layer;
The semiconductor substrate is electrically connected to the second punched layer;
The semiconductor device, wherein the second punched layer is electrically connected to the first source wiring. The semiconductor device according to claim 8.
The semiconductor device, wherein the source region is electrically connected to the source bump electrode through the first punched layer, the semiconductor substrate, the second punched layer, and the first source wiring. The semiconductor device according to claim 9.
The first punched layer and the second punched layer have bottoms reaching the semiconductor substrate,
The specific resistance of the first punched layer and the second punched layer is lower than the specific resistance of the semiconductor layer. The semiconductor device according to claim 8.
A specific resistance of the semiconductor substrate is 10 mΩcm or less. The semiconductor device according to claim 8.
It further has an element isolation region formed in the semiconductor layer,
The semiconductor device, wherein the first active region and the second active region are separated by the element isolation region. The semiconductor device according to claim 10.
A semiconductor device, wherein a back surface electrode is not formed on the main surface of the semiconductor substrate opposite to the side on which the semiconductor layer is formed. The semiconductor device according to claim 8.
A semiconductor device further comprising a metal silicide layer formed on a surface of the source region. The semiconductor device according to claim 8.
The wiring structure includes a drain wiring formed on the first active region and electrically connected to the drain region,
A second source wiring electrically connected to the source region is formed on the first active region with a number of layers smaller than the number of layers of the drain wiring, or on the first active region. The semiconductor device is characterized in that the second source wiring electrically connected to the source region is not formed. The semiconductor device according to claim 8.
The wiring structure includes a drain wiring formed on the first active region and electrically connected to the drain region,
The semiconductor device according to claim 1, wherein the width of the first source wiring is wider than the width of the drain wiring. The semiconductor device according to claim 8.
The semiconductor device according to claim 1, wherein the source bump electrode is disposed above the second punched layer. The semiconductor device according to claim 8.
The bump electrode further includes a drain bump electrode electrically connected to the drain region and a gate bump electrode electrically connected to the gate electrode,
At least one of the drain bump electrode, the gate bump electrode, and the source bump electrode is disposed above the first active region. The semiconductor device according to claim 8.
The bump electrode further includes a drain bump electrode electrically connected to the drain region and a gate bump electrode electrically connected to the gate electrode,
The drain bump electrode and the source bump electrode are arranged at planar positions facing each other through the first active region,
The semiconductor device according to claim 1, wherein the gate bump electrode is disposed between the drain bump electrode and the source bump electrode and at a planar position around the first active region. A semiconductor device including an LDMOSFET element constituting a power amplifier circuit and having a plurality of bump electrodes formed on a surface thereof,
A semiconductor substrate;
A source region and a drain region of the LDMOSFET element formed in a first active region for forming the LDMOSFET element of the semiconductor substrate;
A gate electrode of the LDMOSFET element formed on the first active region of the semiconductor substrate via a gate insulating film;
Have
The bump electrode includes a drain bump electrode electrically connected to the drain region, a gate bump electrode electrically connected to the gate electrode, and a source bump electrically connected to the source region. An electrode,
The drain bump electrode and the source bump electrode are arranged at planar positions facing each other through the first active region,
The semiconductor device according to claim 1, wherein the gate bump electrode is disposed between the drain bump electrode and the source bump electrode and at a planar position around the first active region.

Images