JP2007335547A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having embedded metal wiring of dual damascene structure wherein the unevenness is suppressed in the processed shape of the connection between lower layer metal wiring and a via hole. <P>SOLUTION: An interlayer dielectric is formed between the lower layer metal wiring 101 and upper layer metal wiring 113 as a three layer structure of a first insulating film 102, a second insulating film 103 whose etch rate is higher than that of the first insulating film 102 under the same etching condition, and a third insulating film 104 whose etch rate is higher than that of the second insulating film 103 under the same etching condition. The upper layer metal wiring 113 is embedded in a fourth insulating film 105 on the third insulating film 104. When the via hole 110 is formed passing through the first to the third insulating films 102 and 104, resist residue etc. are removed before the etching processing of the first insulating film 102, and the etching processing of the first insulating film 102 and the formation of a diffusion preventing metal film on the inner wall of the via hole 110 are successively carried out in the same vacuum apparatus. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a dual damascene structure embedded metal wiring and a method for manufacturing the same, and more specifically, a processing shape of a connecting portion between a lower metal wiring and a lower metal wiring of a contact connecting the upper metal wiring. The present invention relates to a semiconductor device in which variation is suppressed and a manufacturing method thereof.

  An embedded wiring technique is effective as a method for forming a multilayer metal wiring of a semiconductor integrated circuit device. In particular, after forming a wiring groove in which the upper metal wiring is formed and a contact via hole for electrically connecting the upper metal wiring and the lower metal wiring in the insulating film, the same metal film is embedded in the wiring groove and the via hole. Thus, the dual damascene technology in which the metal wiring and the contact are integrally formed has an advantage that the manufacturing cost can be significantly reduced by simplifying and speeding up the manufacturing process.

  Various proposals have been made for the structure and manufacturing method for the pattern formation of such embedded wiring. For example, two types of low dielectric constant insulating films are used, and an interlayer insulating film between an upper metal wiring and a lower metal wiring is formed. A method for forming a buried wiring having a hybrid structure is disclosed in Patent Document 1 below. Hereinafter, a conventional method for forming a buried wiring having an interlayer insulating film having a hybrid structure will be described with reference to the drawings.

  First, as shown in FIG. 4A, a first insulating film 202, a second insulating film 203, a third insulating film 204, and a fourth insulating film 205 are sequentially formed on the lower metal wiring 201. Then, a via pattern resist 206 having an opening corresponding to the via hole is formed thereon.

  Next, as shown in FIG. 4B, using the via pattern resist 206 as a mask, the fourth insulating film 205 to the second insulating film 203 are processed by dry etching, and the fourth insulating film 205 is exposed from the upper surface. A temporary via hole 207 reaching the upper surface of the insulating film 202 is formed, and then the via pattern resist 206 is removed by plasma ashing using an ashing gas such as oxygen.

  Next, as shown in FIG. 4C, the embedded film 208 is formed by embedding the via hole 207 using a material such as a photoresist, and this corresponds to a wiring groove in which the upper metal wiring is embedded thereon. A groove pattern resist 209 having an opening is formed.

Next, as shown in FIG. 4D, the fourth insulating film 205 and the third insulating film 204 are processed by dry etching using the groove pattern resist 209 as a mask, so that the second insulating film 205 is subjected to the second insulation. A wiring trench 210 reaching the upper surface of the film 203 is formed. Thereafter, the groove pattern resist 209 is removed by plasma ashing using an ashing gas such as oxygen. Thereafter, the first insulating film 202 exposed in the provisional via hole _207, using _{C x F y, C x H} x F z, O 2, N 2, an etching gas such as Ar, selectively A final via hole 207a reaching the upper surface of the lower metal wiring 201 is formed by removing by dry etching.

  Next, as shown in FIG. 5A, a wet cleaning process is performed to remove the CF polymer 211 remaining in the via hole 207a.

  Next, as shown in FIG. 5B, diffusion that prevents diffusion of the upper metal wiring and the conductive metal material for contact into the insulating film over the entire surface including the inner wall surfaces of the wiring groove 210 and the via hole 207a. A prevention metal film 214 is formed.

  Next, as shown in FIG. 5C, a conductive metal material 215 is deposited on the diffusion preventing metal film 214.

  Next, as shown in FIG. 5D, the conductive metal material 215 and the diffusion prevention metal film 214 are sequentially removed by CMP (Chemical Mechanical Polishing) method except for the inside of the wiring trench 210 and the via hole 207a. Then, the contact 216 is formed in the via hole 207a, and the upper metal wiring 217 is formed in the wiring groove 210, respectively.

JP 2005-5728 A

However, in the conventional method for forming embedded wiring, when the first insulating film 202 exposed in the temporary via hole 207 is removed by dry etching, the CF-based polymer 211 adheres in the via hole 207a, and the lower layer metal Due to the penetration of fluorine into Cu, which is the metal material of the wiring 201, a damage layer 212 mainly made of CuF _x is formed on the surface of the lower metal wiring 201. Thereafter, when the wet cleaning for removing CF-based polymer 211 in the via hole 207a, primarily by damage layer 212 made of CuF _x is removed, an undercut portion on the periphery below the via holes 207a of the lower metal interconnect 201 213 occurs. Due to the occurrence of the undercut 213, a favorable processed shape of the embedded wiring structure cannot be obtained, and the resistance variation of the lower layer metal wiring 201 increases.

  In general, a silicon nitride film, a SiCN film, or the like used for the first insulating film 202 has a high dielectric constant, which increases the capacitance between wirings. Further, after the removal of the first insulating film 202 in the via hole 207a, during the step of forming the diffusion preventing metal film 214 over the entire surface including the wiring trench 210 and the inner wall surface of the via hole 207a, the lower layer metal wiring 201 is formed. The metal surface is oxidized by the influence of exposure to the atmosphere. There is a risk that the performance, yield, or reliability of the semiconductor integrated circuit device may deteriorate due to the influence of the oxidation of the metal surface.

  The present invention has been made in view of the above problems, and an object of the present invention is to suppress variations in the processing shape of a connection portion between a lower metal wiring and a via hole in a semiconductor device having a dual damascene structure embedded metal wiring. A semiconductor device is provided.

  In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is in contact with each upper surface of a lower layer metal wiring formed on a semiconductor substrate and a lower insulating film filled laterally of the lower layer metal wiring, Depositing a first insulating film, depositing a second insulating film having a higher etching rate than the first insulating film under the same etching conditions on the upper surface of the first insulating film, and depositing on the upper surface of the second insulating film Depositing a third insulating film having a higher etching rate than the second insulating film under the same etching conditions; depositing a fourth insulating film made of a material different from the third insulating film on an upper surface of the third insulating film; Etching a part of the fourth insulating film until an upper surface of the third insulating film is exposed to form a groove for an upper metal wiring, and one of the exposed portions of the third insulating film by the groove. Part of the second insulating film Etching until the upper surface is exposed to form an upper part of a contact via hole that electrically connects the lower metal wiring and the upper metal wiring, and exposure of the second insulating film by the upper part of the via hole Etching the portion until the upper surface of the first insulating film is exposed to form an intermediate portion of the via hole; and exposing the portion of the first insulating film by the intermediate portion of the via hole to the upper surface of the lower metal wiring Etching until exposed to form a lower portion of the via hole, forming a diffusion prevention metal film on the entire surface including the via hole and the inner wall surface of the groove, and metal for the upper metal wiring and the contact Depositing a material on the diffusion-preventing metal film and filling the via hole and the groove, and outside the via hole and the groove. Removing the serial diffusion barrier metal film and the metal material, the contact is formed in the via hole, the first characterized by having the steps of forming the upper metal interconnect in said groove.

  Furthermore, in addition to the first feature, the method for manufacturing a semiconductor device according to the present invention includes performing a step of forming a lower portion of the via hole by a sputtering method in the same vacuum apparatus, and then, within the via hole and the groove portion. The second feature is that the step of forming the diffusion preventing metal film on the entire surface including the wall surface is continuously performed.

  Furthermore, in the semiconductor device manufacturing method according to the present invention, in addition to the first or second feature, following the step of depositing the fourth insulating film, the upper surface of the fourth insulating film is subjected to the same etching conditions. The method further includes depositing a fifth insulating film having an etching rate slower than that of the fourth insulating film, and in the step of forming the groove portion, a part of the fifth insulating film is exposed on an upper surface of the fourth insulating film. A third feature is that a hard mask for the groove is formed by etching until a part of the fourth insulating film is etched using the hard mask.

  Furthermore, in addition to the third feature, in the method of manufacturing a semiconductor device according to the present invention, at the time of forming the hard mask, at the same time as etching the part of the fourth insulating film in the step of forming the groove. A fourth feature is to remove the used resist film by etching.

  Furthermore, in addition to any one of the above features, the method of manufacturing a semiconductor device according to the present invention includes, in the step of forming the intermediate portion of the via hole, removing the resist film used when forming the upper portion of the via hole by etching. It is characterized by.

  Furthermore, in the method for manufacturing a semiconductor device according to the present invention, in addition to any of the above features, the first insulating film includes at least one of a silicon nitride film and a SiCN film, and the film thickness of the first insulating film is The sixth characteristic is that the thickness is 5 to 10 nm.

  Furthermore, in the semiconductor device manufacturing method according to the present invention, in addition to the sixth feature, the first insulating film is formed at a low temperature of 400 ° C. or lower by using an atomic layer deposition (ALD) method. The seventh feature is to form a film.

  Furthermore, the semiconductor device manufacturing method according to the present invention has, in addition to any of the above features, an eighth feature that the second insulating film is an organic low dielectric constant insulating film.

  Further, in the semiconductor device manufacturing method according to the present invention, in addition to any of the above features, the third insulating film may be a SiOF film, a SiOC film, a SiOCH film, a porous silica film, or other inorganic low dielectric constant. The ninth feature is that the insulating film is a high-efficiency insulating film.

  In order to achieve the above object, a semiconductor device according to the present invention includes a lower layer metal wiring formed on a semiconductor substrate and a lower layer insulating film filling a side of the lower layer metal wiring. 1 insulating film, a second insulating film having a higher etching rate than the first insulating film under the same etching conditions formed on the upper surface of the first insulating film, and the same etching conditions formed on the upper surface of the second insulating film A third insulating film having a higher etching rate than the second insulating film, a fourth insulating film made of a material different from the third insulating film formed on the upper surface of the third insulating film, and one of the fourth insulating films. Upper metal wiring formed by filling one or a plurality of layers of metal material into a groove portion that is open until the upper surface of the third insulating film is exposed, and a portion of the portion exposed by the groove portion of the third insulating film The second insulating film and the second A contact that electrically connects the lower metal wiring and the lower metal wiring by filling a via hole that penetrates through an insulating film until the upper surface of the lower metal wiring is exposed and is filled with the same metal material as the upper metal wiring The first feature is to include the above.

  Furthermore, in the semiconductor device according to the present invention, in addition to the first feature, the first insulating film includes at least one of a silicon nitride film and a SiCN film, and the film thickness of the first insulating film is 5 to 10 nm. This is the second feature.

  Furthermore, the semiconductor device according to the present invention has a third feature that, in addition to the first or second feature, the second insulating film is an organic low dielectric constant insulating film.

  Furthermore, in addition to any of the above features, the semiconductor device according to the present invention is characterized in that the third insulating film is a SiOF film, a SiOC film, a SiOCH film, a porous silica film, or other inorganic low dielectric constant insulating film. This is the fourth feature.

  According to the method of manufacturing a semiconductor device having the above characteristics, the interlayer insulating film between the upper metal wiring and the lower metal wiring is composed of three layers of the first to third insulating films, and the upper insulating film has the same etching conditions. Since it is deposited with a film material having a high etching rate, the interlayer insulating film is etched in order from the upper third insulating film, and a contact (conductive material) connecting the upper metal wiring and the lower metal wiring is filled. When forming the via hole, the lower insulating film functions as an etching stopper. Therefore, in the step of etching the second insulating film to form the middle portion of the via hole, the via hole processing resist film is simultaneously etched away, Before the via hole is completed by etching the lower first insulating film, the resist residue is completely removed and the first insulating film is clean. It can be etched. That is, since the CF-based polymer does not remain in the via hole with the surface of the lower metal wiring exposed after the etching of the first insulating film, fluorine enters the lower metal wiring and forms a damaged layer. Can prevent the occurrence of undercut. As a result, it is possible to provide a semiconductor device in which variation in the processing shape of the connection portion between the lower metal wiring and the via hole is suppressed, and the performance, yield, and reliability of the semiconductor device can be improved.

  In particular, according to the method for manufacturing a semiconductor device of the second feature, the diffusion barrier metal film is formed on the lower metal wiring surface without being exposed to the air after the completion of the via hole, and thus the better. The quality of the lower layer metal wiring is ensured.

  In particular, according to the semiconductor device manufacturing method of the seventh feature, since the first insulating film is as thin as about 5 to 10 nm and the film thickness uniformity is formed by the ALD method, the first insulating film is etched. Occurrence of the shape abnormality of the lower layer metal wiring due to the film residue after the removal or etching processing can be avoided.

  Further, according to the semiconductor device having the above characteristics, the interlayer insulating film between the upper metal wiring and the lower metal wiring is composed of three layers of the first to third insulating films, and the upper insulating film is etched at the same etching condition. Therefore, it can be manufactured by the method for manufacturing a semiconductor device having the above characteristics. Therefore, the effects of the semiconductor device manufacturing method of the above characteristics can be obtained, and a semiconductor device in which variation in the processing shape of the connection portion between the lower layer metal wiring and the via hole can be provided, and the performance of the semiconductor device, Yield and reliability can be improved.

  Embodiments of a semiconductor device and a method for manufacturing the same according to the present invention (hereinafter abbreviated as “the device of the present invention” and “the method of the present invention” as appropriate) will be described below with reference to the drawings.

  1 and 2 are process cross-sectional views schematically showing a method of forming a buried damascene metal wiring having a dual damascene structure according to the method of the present invention. FIG. 3 is a cross-sectional view schematically showing a cross-sectional structure of the device of the present invention formed by the method of the present invention. 1 and 2 show a dual damascene structure portion of the lower layer metal wiring of the device of the present invention, the upper layer metal wiring above it, and a contact for electrically connecting both metal wirings in the vertical direction. Description of transistor elements and the like below the lower metal wiring is omitted.

  First, with reference to FIG. 3, the overall schematic structure of the device 10 of the present invention manufactured using the method of the present invention will be described. As shown in FIG. 3, a MOS type transistor element is formed in the active region between the element isolation films 2 formed on the semiconductor substrate 1 by a known technique in a portion below the lower layer metal wiring 101 of the device 10 of the present invention. Yes. In FIG. 3, the MOS transistor element includes a source 4, a drain 5, and a gate 3 formed on a channel region between the source and drain via a gate insulating film. An interlayer insulating film 6 is formed between the MOS type transistor element and the lower layer metal wiring 101, and a first contact 7 for electrically connecting the drain 5 of the MOS type transistor element and the lower layer metal wiring 101 is formed. A diffusion preventing metal film for preventing diffusion of the metal material of the first contact 7 is provided on a side surface and a bottom surface of the first contact 7. Further, a diffusion preventing metal film for preventing diffusion of the metal material of the lower layer metal wiring 101 is provided on the side surface and the bottom surface of the lower layer metal wiring 101, and on the side of the lower layer metal wiring 101 above the interlayer insulating film 6. A lower insulating film 100 is formed. The first contact 7, the lower metal wiring 101, and the lower insulating film 100 are formed by a known method, and a detailed description of the formation method is omitted. For example, the lower metal wiring 101 can be formed by a damascene method similar to the upper metal wiring 113 described later.

  The first insulating film 102 is formed on the upper part of the lower metal wiring 101 of the device 10 of the present invention in contact with the upper surfaces of the lower metal wiring 101 and the lower insulating film 100, and further, the second insulating film 103 and A third insulating film 104, a fourth insulating film 105, and a fifth insulating film 106 are formed in order. The fourth insulating film 105 and the fifth insulating film 106 are formed with a groove 108 that is open until the upper surface of the third insulating film is exposed, and the first insulating film 102, the second insulating film 103, and the third insulating film 104 are formed. Is formed with a via hole 110 that is open until the upper surface of the lower metal wiring 101 is exposed. The groove portion 108 is a groove for embedding a metal material therein to form the upper metal wiring 113, and the via hole 110 is electrically embedded between the upper metal wiring 113 and the lower metal wiring 101 by embedding the metal material therein. This is a through hole for forming the second contact 114. A diffusion prevention metal film 111 for preventing diffusion of the metal material into the insulating film is formed on both inner wall surfaces of the groove 108 and the via hole 110, and the metal material is embedded therein so that the upper metal wiring 113 and the second contact 114 are embedded. However, it is formed by the so-called dual damascene method.

  In the present embodiment, the second insulating film 103 has a higher etching rate than the first insulating film 102 under the same etching conditions, and the etching selectivity with respect to the first insulating film 102 is high. In addition, the third insulating film 104 has a higher etching rate than the second insulating film 103 under the same etching conditions, and has a higher etching selectivity than the second insulating film 103. Specifically, the first insulating film 102 is formed of a silicon nitride film or a SiCN film, and the second insulating film 103 is an organic low dielectric constant insulating film such as a polyimide film or an amorphous carbon film implanted with fluorine. The third insulating film 104 is formed of an inorganic low dielectric constant insulating film such as a SiOF film, a SiOC film, a SiOCH film, or a porous silica film.

  Next, with reference to FIG. 1 and FIG. 2, the processing procedure of each process relating to the formation of the buried wiring above the lower metal wiring 101 of the device 10 of the present invention according to the method of the present invention will be described.

  First, as shown in FIG. 1A, a first insulating film 102 is formed to a thickness of 5 to 10 nm in contact with the upper surfaces of the lower metal wiring 101 and the lower insulating film 100, and further, the first insulating film On the second insulating film 103, the second insulating film 103 has a thickness of 50 to 100 nm, the third insulating film 104 has a thickness of 100 to 300 nm, the fourth insulating film 105 has a thickness of 100 to 300 nm, and the fifth insulating film. 106 are formed in order with a film thickness of 50 to 100 nm.

  In the present embodiment, the first insulating film 102 is a material whose etching rate is slower than that of the second insulating film 103 under the same etching conditions in order to serve as an etching stopper layer when forming the intermediate portion of the via hole 110 in the second insulating film 103. Further, for example, a silicon nitride film, a SiCN film, or the like is used because it is used as a diffusion prevention film that prevents the metal material of the lower layer metal wiring 101 from diffusing into the second insulating film 103. In addition, the first insulating film 102 is desirably formed thin using an atomic layer deposition (ALD) method while maintaining high film thickness uniformity at a low temperature of 400 ° C. or lower.

  The second insulating film 103 is made of a material having an etching rate slower than that of the third insulating film 104 under the same etching conditions in order to serve as an etching stopper layer when the upper portion of the via hole 110 is formed in the third insulating film 104. In order to reduce inter-wiring capacitance between the lower metal wiring 101 and the upper metal wiring 113, for example, an organic low dielectric constant insulating film such as a polyimide film having a relative dielectric constant lower than that of the first insulating film 102 or a fluorine-containing amorphous carbon film. Is used. The third insulating film 104 is the uppermost layer film of the interlayer insulating film in which the via hole 110 is formed. For example, the first insulating film 104 is used to reduce the inter-wiring capacitance between the lower metal wiring 101 and the upper metal wiring 113. An inorganic insulating film having a relative dielectric constant lower than that of the film 102, such as a silicon oxide film, a SiOF film, a SiOC film, or a porous silica film, is used. Here, since the first insulating film 102 has a higher dielectric constant than the second insulating film 103 and the third insulating film 104, three layers of first to third insulating films between the upper metal wiring 113 and the lower metal wiring 101 are used. By making the film thickness about 5% or less with respect to the total film thickness of the entire interlayer insulating film constituted by the above, the effect of reducing the inter-wiring capacitance between the lower layer metal wiring 101 and the upper layer metal wiring 113 can be more effectively exhibited. be able to.

  The fourth insulating film 105 is an interlayer insulating film in which a groove pattern is formed. Like the second insulating film 103, it is preferable to use an organic low dielectric constant insulating film in order to reduce the capacitance between wirings. The fifth insulating film 106 is a material having a slower etching rate than the fourth insulating film 105 under the same etching conditions, for example, a silicon oxide film, silicon, or the like, in order to serve as a hard mask when the groove 108 is etched in the fourth insulating film 105. An inorganic insulating film such as a nitride film, SiC film, SiON film, SiCN film, or SiOF film can be used. The organic low dielectric constant insulating film of the second insulating film 103 and the fourth insulating film 105 uses, for example, a spin coating method, and the inorganic insulating film of the third insulating film 104 and the fifth insulating film 106 uses, for example, CVD. Film formation is performed by a chemical vapor deposition method.

  Next, as shown in FIG. 1B, a groove pattern resist 107 having an opening at the same position as the groove 108 in which the upper metal wiring 113 is embedded is formed on the upper surface of the fifth insulating film 106 by a normal photolithography technique. To do. For example, the groove pattern resist 107 is formed by applying a photoresist composition on the upper surface of the fifth insulating film 106, and then performing exposure with an optimum exposure amount and focus using an ArF excimer laser scanner, followed by development. be able to. As the photoresist composition, for example, a chemically amplified positive photoresist composition containing a normal base resin, an acid generator and the like can be used.

Next, as shown in FIG. 1 (c), a groove pattern resist 107 as a _mask, using a _{C x F y, C x H} x F z, O 2, CO, etching gas such as Ar, the fourth insulating The fifth insulating film 106 is dry-etched until the upper surface of the film 105 is exposed, and then the fourth insulating film 105 and the groove pattern resist 107 are continuously etched using an etching gas such as H ₂ , N ₂ , and NH ₃ . By simultaneously performing dry etching until the upper surface of the third insulating film 104 is exposed, the groove 108 is formed.

  Next, as shown in FIG. 1D, the same portion as the via hole 110 in which the second contact 114 is embedded is opened on the upper surface of the fifth insulating film 106 and the entire surface of the substrate including the inner wall surface of the groove 108. A via pattern resist 109 is formed by the same formation method as the groove pattern resist 107.

Next, as shown in FIG. 2A, a third pattern is formed using an etching gas such as C _x F _y , C _x H _x F _z , O ₂ , N ₂ , Ar using the via pattern resist 109 as a mask. The upper portion of the via hole 110 is formed in the third insulating film 104 by dry etching the insulating film 104 selectively until the upper portion of the second insulating film 103 is exposed. At this time, since the etching selection ratio of the third insulating film 104 can be set as high as 5 to 10 with respect to the second insulating film 103, the etching can be stopped with high accuracy on the upper surface of the second insulating film 103. Subsequently, the second insulating film 103 and the via pattern resist 109 are dry-etched selectively using an etching gas such as H ₂ , N ₂ , and NH ₃ until the upper surface of the first insulating film 102 is exposed. As a result, an intermediate portion of the via hole 110 reaching the first insulating film 102 is formed. At this time, since the etching selectivity of the second insulating film 103 can be set as high as 10 or more with respect to the first insulating film 102, the etching can be stopped with high accuracy on the upper surface of the first insulating film 102. Thereafter, a resist residue or the like is removed by performing a wet cleaning process. Thereby, a substance that damages the lower layer metal wiring 101 such as CF polymer can be removed before the surface of the lower layer metal wiring 101 is exposed by the etching process of the first insulating film 102 in the next step.

  Next, as shown in FIG. 2B, the first insulating film 102 exposed on the bottom surface of the via hole 110 penetrating the third insulating film 104 and the second insulating film 103 is sputtered using Ar gas or the like. The via hole 110 penetrating the first insulating film 102 from the third insulating film 104 is completed by forming the lower portion of the via hole 110 by removing the first through the third insulating film 104, and then continuously in the same vacuum apparatus as in the sputtering step. A diffusion preventing metal film 111 is formed with a film thickness of 1 to 20 nm on the entire surface of the substrate including the inner wall surface 108 and the via pattern 110 by a sputtering method. At this time, since the first insulating film 102 is as thin as about 5 to 10 nm and has a good film thickness uniformity by the ALD method, the film residue after the removal of the first insulating film 102 by sputtering and the occurrence of shape abnormality by sputtering are generated. Can be avoided. Here, the diffusion preventing metal film 111 is formed using, for example, tantalum nitride, tungsten nitride, or the like. Further, the lower metal wiring 101 exposed on the bottom surface of the via hole 110 is exposed to the atmosphere by continuously performing the sputtering of the first insulating film 102 and the formation of the diffusion preventing metal film 111 in the same vacuum apparatus. Therefore, surface oxidation of the lower layer metal wiring 101 can be prevented.

  Next, as shown in FIG. 2C, copper is used as the conductive metal material 112 for the upper metal wiring 113 and the second contact 114 on the diffusion preventing metal film 111 by sputtering or plating. , Deposited with a film thickness of 500-1000 nm.

  Next, as shown in FIG. 2D, the metal material 112 and the diffusion-preventing metal film 111 deposited outside the trenches 108 and the via holes 110 are sequentially removed using a CMP (Chemical Mechanical Polishing) method. Then, the upper metal wiring 113 and the second contact 114 are formed as buried wirings in the trench 108 and the via hole 110, respectively.

  When the metal wiring is only the two-layer wiring of the lower metal wiring 101 and the upper metal wiring 113, the bonding pad 8 and the surface protective film 9 are formed by the existing method, and the device of the present invention shown in FIG. 3 is manufactured. .

  As described above, in the upper metal wiring 113 and the second contact 114 formed by the method of the present invention, the variation in the processing shape is suppressed in the lower metal wiring 101 below the via hole 110, so that the performance as a semiconductor device, the yield, and Reliability can be improved.

  Next, another embodiment of the present invention will be described.

  <1> In the above-described embodiment, a set of two-layer wiring structures between the lower metal wiring 101 and the upper metal wiring 113 has been described in detail. However, a multilayer wiring structure may be further formed by the same embedded wiring forming method. Is possible.

  <2> In the above embodiment, the film material, the film thickness, the film forming method, and the like have been described in detail for the first to fifth insulating films 102 to 106. These are for understanding the device of the present invention and the method of the present invention. It is illustrated for the sake of simplicity, and is not limited to the above film material, film thickness, film forming method, and the like.

  <3> In the above embodiment, the interlayer insulating film in which the groove 108 is formed has a two-layer structure of the fourth insulating film 105 and the fifth insulating film 106. However, the interlayer insulating film is not necessarily the two-layered structure of the above embodiment. It is not limited to the structure, and may be a one-layer or three-layer structure.

  The semiconductor device and the manufacturing method thereof according to the present invention can be used for a semiconductor device having a buried damascene metal wiring.

Process sectional drawing which shows typically a part of process procedure of the formation process of the embedded wiring in one Embodiment of the manufacturing method of the semiconductor device which concerns on this invention Process sectional drawing which shows typically another part of the process sequence of the formation process of the embedded wiring in one Embodiment of the manufacturing method of the semiconductor device which concerns on this invention Sectional drawing which shows the whole schematic structure in one Embodiment of the semiconductor device which concerns on this invention Process sectional view schematically showing the processing procedure of some processes in the conventional method for forming embedded wiring Process sectional drawing which shows typically the processing procedure of the other part process in the formation method of the conventional embedded wiring

Explanation of symbols

1: Semiconductor substrate 2: Element isolation film 3: Gate 4: Source 5: Drain 6: Interlayer insulating film 7: First contact 8: Bonding pad 9: Surface protective film 10: Semiconductor device according to the present invention 100: Lower layer insulation Film 101: Lower layer metal wiring 102: First insulating film 103: Second insulating film 104: Third insulating film 105: Fourth insulating film 106: Fifth insulating film 107: Groove pattern resist 108: Groove portion 109: Via pattern resist 110 : Via hole 111: Diffusion preventing metal film 112: Conductive metal material 113: Upper metal wiring 114: Second contact 201: Lower metal wiring 202: First insulating film 203: Second insulating film 204: Third insulating film 205: Fourth insulating film 206: Via pattern resist 207: Temporary via hole 207a: Via ho 208: buried film 209: groove pattern resist 210: wiring groove 211: CF-based polymer 212: damaged layer 213: undercut 214: diffusion barrier metal layer 215: conductive metallic material 216: contact 217: upper layer metal wiring

Claims (13)

A step of depositing a first insulating film in contact with each upper surface of a lower layer metal wiring formed on a semiconductor substrate and a lower layer insulating film filled laterally of the lower layer metal wiring;
Depositing a second insulating film having a higher etching rate than the first insulating film on the upper surface of the first insulating film under the same etching conditions;
Depositing a third insulating film having a higher etching rate than the second insulating film on the upper surface of the second insulating film under the same etching conditions;
Depositing a fourth insulating film of a material different from that of the third insulating film on an upper surface of the third insulating film;
Etching a part of the fourth insulating film until an upper surface of the third insulating film is exposed to form a groove for an upper metal wiring;
Etching is performed on a part of the exposed portion of the third insulating film by the groove until the upper surface of the second insulating film is exposed, and a contact for electrically connecting the lower metal wiring and the upper metal wiring. Forming the upper portion of the via hole;
Etching the exposed portion of the second insulating film by the upper part of the via hole until the upper surface of the first insulating film is exposed to form an intermediate portion of the via hole;
Etching the exposed portion of the first insulating film by the intermediate portion of the via hole until the upper surface of the lower layer metal wiring is exposed to form a lower portion of the via hole;
Forming a diffusion preventing metal film on the entire surface including the via hole and the inner wall surface of the groove;
Depositing the metal material for the upper layer metal wiring and the contact on the diffusion-preventing metal film and filling the via hole and the groove part;
Removing the diffusion preventing metal film and the metal material outside the via hole and the groove, forming the contact in the via hole, and forming the upper metal wiring in the groove. A method of manufacturing a semiconductor device.   In the same vacuum apparatus, after the step of forming the lower portion of the via hole is performed by a sputtering method, the step of forming a diffusion preventing metal film on the entire surface including the inner surface of the via hole and the groove portion is continuously performed. A method for manufacturing a semiconductor device according to claim 1. Subsequent to the step of depositing the fourth insulating film, the method further includes the step of depositing a fifth insulating film having an etching rate slower than that of the fourth insulating film under the same etching conditions on the upper surface of the fourth insulating film,
In the step of forming the groove, a part of the fifth insulating film is etched until an upper surface of the fourth insulating film is exposed to form a hard mask for the groove, and the hard mask is used to form the first 4. The method of manufacturing a semiconductor device according to claim 1, wherein a part of the four insulating films is etched.   4. The semiconductor device according to claim 3, wherein in the step of forming the groove portion, the resist film used at the time of forming the hard mask is removed by etching simultaneously with etching of a part of the fourth insulating film. Manufacturing method.   5. The method of manufacturing a semiconductor device according to claim 1, wherein, in the step of forming an intermediate portion of the via hole, the resist film used at the time of forming the upper portion of the via hole is removed by etching.   6. The method according to claim 1, wherein the first insulating film includes at least one of a silicon nitride film and a SiCN film, and the thickness of the first insulating film is 5 to 10 nm. The manufacturing method of the semiconductor device of description.   The method of manufacturing a semiconductor device according to claim 6, wherein the first insulating film is formed at a low temperature of 400 ° C. or lower by using an atomic layer deposition method.   The method for manufacturing a semiconductor device according to claim 1, wherein the second insulating film is an organic low dielectric constant insulating film.   9. The method according to claim 1, wherein the third insulating film is a SiOF film, a SiOC film, a SiOCH film, a porous silica film, or other inorganic low dielectric constant insulating film. The manufacturing method of the semiconductor device of description. A first insulating film formed on and in contact with each upper surface of a lower layer metal wiring formed on a semiconductor substrate and a lower layer insulating film filled laterally of the lower layer metal wiring;
A second insulating film having an etching rate faster than that of the first insulating film under the same etching conditions formed on the upper surface of the first insulating film;
A third insulating film having a higher etching rate than the second insulating film under the same etching conditions formed on the upper surface of the second insulating film;
A fourth insulating film made of a material different from the third insulating film formed on the upper surface of the third insulating film;
An upper-layer metal wiring formed by filling one or more layers of a metal material in a groove portion that is open until a part of the fourth insulating film is exposed until the upper surface of the third insulating film is exposed;
A portion of the portion of the third insulating film exposed by the groove portion passes through the second insulating film and the first insulating film, and a via hole is opened until the upper surface of the lower metal wiring is exposed. A semiconductor device comprising: the lower metal wiring filled with the same metal material; and a contact for electrically connecting the upper metal wiring.   11. The semiconductor device according to claim 10, wherein the first insulating film includes at least one of a silicon nitride film and a SiCN film, and the film thickness of the first insulating film is 5 to 10 nm.   12. The semiconductor device according to claim 10, wherein the second insulating film is an organic low dielectric constant insulating film.   The third insulating film according to any one of claims 10 to 12, wherein the third insulating film is a SiOF film, a SiOC film, a SiOCH film, a porous silica film, or another inorganic low dielectric constant insulating film. The semiconductor device described.