JP2007306245A - Vertical register driver of ccd imaging element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a vertical register driver of a CCD imaging element that can shorten a rise time and a fall time of a voltage for charge transfer by reducing the ON resistance of an output transistor while preventing the element size from increasing. <P>SOLUTION: Booster circuits 7 and 8 or a step-down circuit 6 is provided in front of output transistors 2 to 4 of the vertical register driver of the CCD imaging element. Consequently, gate voltages when the output transistors 2 to 4 are turned ON to increase current driving capabilities of the output transistors. In addition, a substrate potential switching circuit 9 is provided to convert a substrate potential when the output transistor 3 is ON. Control over them is performed by a control circuit 1 in a semiconductor integrated circuit driving vertical registers of the CCD imaging element. Consequently, the output transistors can be made to switch fast in response. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention is configured as a semiconductor integrated circuit device and drives a vertical register of a CCD (Charge Coupled Device) image sensor. A vertical register drive device for a CCD image sensor, that is, a so-called vertical driver, has high rise time and fall time of output voltage. It is related to conversion.

  A general semiconductor integrated circuit device around a vertical register driving device (vertical driver) of a CCD image pickup device has a configuration as shown in FIG. In FIG. 7, reference numeral 100 indicates an optical block, reference numeral 101 indicates a CCD image pickup device, reference numeral 102 indicates a mechanical shutter controller, reference numeral 103 indicates a vertical driver, and reference numeral 104 indicates a CDS (Correlated Double Sampling). (Sampling), AGC (Automatic Gain Control), a signal processing block having functions such as an AD (Analog-Digital) converter, 105 represents a timing generator, 106 represents an image processing block Yes.

  The CCD image pickup device 101 includes a photodiode that converts light from the optical block 100 into electric charges, and a vertical register and a horizontal register that transfer the converted electric charges to the signal processing block 104. In order to drive the vertical register and horizontal register of the CCD image sensor 101, it is necessary to generate a vertical drive pulse and a horizontal drive pulse, respectively. The vertical drive pulse is generated by the vertical driver 103 based on the timing signal voltage from the timing generator 105 and supplied to the CCD image sensor 101. Further, the timing signal voltage generated by the timing generator 105 is supplied as it is to the CCD image sensor 101 as a horizontal drive pulse. The signal output from the signal processing block 104 is sent to the image processing block 106. The image processing block 106 supplies a shutter control signal and a synchronization signal to the timing generator 105. The timing generator 105 controls the mechanical shutter controller 102 based on a signal from the image processing circuit 106 and supplies a signal voltage to the vertical driver 103 and the CCD image sensor 101.

  The vertical drive pulse requires a higher voltage than the horizontal drive pulse. This is because a high level voltage for transferring the charge accumulated in the pixel to the vertical register and a middle level voltage and a low level voltage for sequentially transferring the charge accumulated in the vertical register to the horizontal register are necessary. is there. A semiconductor integrated device that converts the signal voltage of the timing generator 105 into a voltage for driving the vertical register is called a vertical driver.

  FIG. 5 shows an example of the configuration of a conventional ternary vertical driver. In FIG. 5, reference numeral 1A denotes a control circuit that converts a signal voltage from the timing generator into a voltage for driving the vertical register. As shown in FIGS. 8A and 8B, the control circuit 1A has a low input voltage level of, for example, 0V, a high input voltage level of, for example, 3.3V, and a low level of the output voltage. Is, for example, −6V, and the high level of the output voltage is, for example, 12V.

  Reference numeral 2 denotes a P-channel output transistor for outputting a high level voltage of, for example, 12 V to the CCD image pickup device 5. Reference numeral 3 denotes an N-channel output transistor for outputting a middle level voltage of 0 V, for example, to the CCD image pickup device 5. Reference numeral 4 denotes an N-channel output transistor for outputting a low level voltage of, for example, -6 V to the CCD image pickup device 5.

  The high level, middle level, and low level voltages are selectively output by the control circuit 1A.

  Reference numerals 11 and 17 denote two input terminals of the vertical driver, and reference numeral 12 denotes an output terminal of the vertical driver. Reference signs Vin1 and CH1 indicate input voltages to the input terminal 11, and reference signs Vout1 indicate output voltages from the output terminal 12. The CCD image sensor 5 is connected to the output terminal 12 of the vertical driver. Reference numeral 13A denotes a ternary vertical driver block, which includes a control circuit 1A, a P-channel output transistor 2, and N-channel output transistors 3 and 4.

  Reference numerals 14 and 18 denote two input terminals of the vertical driver, and reference numeral 15 denotes an output terminal of the vertical driver. Symbols Vin2 and CH2 indicate input voltages to the input terminal 14, and symbol Vout2 indicates an output voltage from the output terminal 15. The CCD image pickup device 5 is also connected to an output terminal 15 of a vertical driver (not shown). Reference numeral 16A denotes a binary vertical driver block, which includes a control circuit and two N-channel output transistors. That is, the P-channel output transistor is omitted from the circuit of FIG. 5, and the internal circuit of the control circuit related thereto is omitted.

  FIG. 5 shows a ternary vertical driver block of a ternary output voltage that outputs a high level voltage, a middle level voltage, and a low level voltage, but a binary output that outputs a middle level voltage and a low level voltage. 2 shows a binary driver block of voltage binary system.

  FIGS. 9A and 9B show a ternary vertical driver block and a binary vertical driver block. The difference between the two is whether or not there is a P-channel output transistor for outputting a high level voltage. FIG. 9 also shows the relationship between the input voltages Vin1 and CH1 and the output voltage Vout1 in the ternary vertical driver block. Similarly, the relationship between the input voltage Vin2 and the output voltage Vout2 in the binary vertical driver block is also shown.

  As shown in FIG. 10, the vertical driver system for driving the CCD image sensor, that is, the vertical register drive system 50 for the CCD image sensor, has at least one ternary vertical driver block 51 and at least one binary. A vertical driver block 52 of the system is provided. Reference numeral 53 denotes a vertical driver input terminal, and reference numeral 54 denotes a vertical driver output terminal.

  The required number of ternary vertical driver blocks 51 and binary vertical driver blocks 52 differs depending on the structure or characteristics of the CCD image sensor. For example, when a CCD image sensor is used as a digital still camera, an image may be transferred by a method called interlace. There are 3: 1, 4: 1, etc. interlace systems, and the number of channels mounted on the vertical driver varies depending on this system. The required number of ternary vertical driver blocks 51 and binary vertical driver blocks 52 differs depending on the number of channels.

  FIG. 6 shows an example of a timing diagram according to the configuration of the conventional example. The signal voltage from the timing generator input to the control circuit is set to an input voltage high level (for example, 3.3 V) and an input voltage low level (for example, 0 V). In one example, switching between a middle level voltage (for example, 0 V) and a low level voltage (for example, −6 V) is shown. The switching of the output voltage with respect to the switching of the input voltage depends on the on-resistance of the transistor and the capacitance of the CCD image sensor. The waveform delay is caused by the influence of. (For example, refer to Patent Document 1) In FIG. 6, symbol tf indicates a fall time, and symbol tf indicates a rise time.

In recent years, as the number of pixels of a CCD image sensor has increased, a technique for transferring charges stored in the CCD image sensor at high speed is required. In order to transfer charges accumulated in the CCD image sensor at high speed, it is necessary to transfer charges in the vertical register to the horizontal register at high speed. In order to satisfy this requirement, it is required to increase the rise time tr and fall time tf of the charge transfer voltage (middle level voltage and low level voltage) of the vertical driver.
JP-A-7-23299

  However, in the above conventional configuration, the output transistor is used as a general switching element, and the rise time tr and rise of the charge transfer voltage (middle level voltage and low level voltage) due to the influence of the load of the CCD image sensor. When speeding up the fall time tf is required, it is necessary to increase the size of the output transistor and reduce the on-resistance of the output transistor. For this reason, it is necessary to increase the element size of the output transistor, which has the disadvantage of increasing the area.

  It is an object of the present invention to drive a vertical register of a CCD image pickup device that can increase the rise time and fall time of a charge transfer voltage by reducing the on-resistance of an output transistor while preventing an increase in device size. Is to provide a device.

  In order to solve the above-described problems, the vertical register driving device for a CCD image pickup device according to the present invention determines the level of the gate voltage applied to the gate of the output transistor when the output transistor is made conductive to the gate of the output transistor. By providing a gate voltage shift circuit that reduces the on-resistance of the output transistor by shifting (converting) the level of the output transistor, the on-resistance of the output transistor is reduced while preventing the device size from increasing, thereby transferring charge. The rise time and fall time of the operating voltage can be increased. The configuration of the gate voltage shift circuit changes depending on the conductivity type of the output transistor, and a booster circuit is used for an N-channel output transistor, and a step-down circuit is used for a P-channel output transistor. Thus, by providing a gate voltage shift circuit composed of a booster circuit or a step-down circuit at the gate of the output transistor, the gate voltage of the transistor is converted to improve the current capability of the output transistor, while preventing an increase in element size. The on-resistance of the output transistor is reduced, thereby realizing a faster rise time and fall time of the charge transfer voltage.

  In addition, the vertical register driving device of the CCD image pickup device of the present invention includes a substrate potential switching circuit that switches the substrate potential of the output transistor, thereby reducing the on-resistance of the output transistor while preventing an increase in the element size. Thus, the rise time and fall time of the charge transfer voltage can be increased. In other words, in order to reduce the influence of the substrate bias effect at the location where the substrate potential is at a low level voltage, a circuit for switching the substrate potential at an appropriate time is provided in the intermediate potential output stage. In the output transistor to which the substrate potential switching circuit is connected, the substrate potential can be switched only when the output transistor operates to reduce the influence of the substrate bias effect, and the rise of the output voltage in the vertical register driving device of the CCD image sensor Time and fall time can be increased.

  This will be specifically described below.

  The first CCD image sensor vertical register driving apparatus of the present invention has a signal input terminal for inputting a binary signal, and a voltage for driving the vertical register of the CCD image sensor based on the level of the binary signal inputted from the signal input terminal. A control circuit for converting to and outputting the output, an output transistor to which a gate voltage is supplied from the control circuit, a drive voltage output terminal connected to the output transistor, and an output provided between the control circuit and the gate of the output transistor And a gate voltage shift circuit that reduces the on-resistance of the output transistor by shifting the level of the gate voltage applied to the gate of the output transistor from the level of the output voltage of the control circuit when the transistor is turned on.

  In the above configuration, the following configuration is preferable. The control circuit converts the level of the binary signal input from the signal input terminal into two potentials, a high level potential and a low level potential for driving the vertical register of the CCD image sensor, and outputs the first and second potentials. Output terminal.

  The output transistor includes a first N-channel transistor having a drain connected to a middle level potential point having a middle level potential between the high level potential and the low level potential, and a gate voltage supplied from a first output terminal of the control circuit. And a second N-channel transistor having a source connected to a low-level potential point having a low-level potential and a gate voltage supplied from a second output terminal of the control circuit.

  The drive voltage output terminal is connected to the source of the first N-channel transistor and the drain of the second N-channel transistor.

  The gate voltage shift circuit is provided between the first output terminal of the control circuit and the gate of the first N-channel transistor, and is connected to the gate of the first N-channel transistor when the first N-channel transistor is turned on. A first booster circuit for raising the applied gate voltage; and a second booster circuit provided between the second output terminal of the control circuit and the gate of the second N-channel transistor to conduct the second N-channel transistor. And a second booster circuit for raising the gate voltage applied to the gates of the two N-channel transistors.

  In the above configuration, the control circuit converts the level of the binary signal input from the signal input terminal into two potentials, a high level potential and a low level potential for driving the vertical register of the CCD image sensor. A first P-channel transistor having a third output terminal for outputting, a source connected to a high-level potential point having a high-level potential, and a gate voltage being supplied from the third output terminal of the control circuit; The drain of the first P-channel transistor is preferably connected to the drive voltage output terminal.

  Further, in the above configuration, the gate of the first P-channel transistor is provided between the third output terminal of the control circuit and the gate of the first P-channel transistor to make the first P-channel transistor conductive. It is preferable to provide a step-down circuit that lowers the gate voltage applied to the.

  Moreover, in the said structure, it is preferable to have the following structures. The control circuit includes a first inverted output terminal that outputs a signal whose output level is inverted from the first output terminal, and a second inverted output terminal that outputs a signal whose output level is inverted from the second output terminal. Have

  The first booster circuit includes a first capacitor, a first clamp circuit including a first diode, a second P-channel transistor having a gate connected to each other and a drain connected to each other, and a third N-channel transistor. A first inverter circuit composed of a channel transistor, one end of the first capacitor connected to the first output terminal of the control circuit, and the cathode of the first diode connected to the other end of the first capacitor. The anode of the first diode is connected to the high level potential point, the cathode of the first diode is connected to the source of the second P channel transistor, and the source of the third N channel transistor is connected to the low level potential point. And the common terminal of the second P-channel transistor and the third N-channel transistor is connected to the first inverting output terminal of the control circuit. Over: it is connected, the common drain of the second P-channel transistor and the third N-channel transistor is first boosted voltage output terminal.

  The second booster circuit includes a second capacitor, a second clamp circuit including a second diode, a third P-channel transistor having a gate connected to each other and a drain connected to each other, and a fourth N-channel transistor. A second inverter circuit comprising a channel transistor, one end of the second capacitor being connected to the second output terminal of the control circuit, and the cathode of the second diode being connected to the other end of the second capacitor. The anode of the second diode is connected to the high-level potential point, the cathode of the second diode is connected to the source of the third P-channel transistor, and the source of the fourth N-channel transistor is connected to the low-level potential point. The third P-channel transistor and the fourth N-channel transistor are connected to the second inverting output terminal of the control circuit. Over: it is connected, the common drain of the third P-channel transistor and a fourth N-channel transistor is a second boosted voltage output terminal.

  Moreover, in the said structure, it is preferable to have the following structures. The control circuit has a third inverted output terminal for outputting a signal whose output level is inverted from that of the third output terminal.

  The step-down circuit includes a third capacitor, a third clamp circuit composed of a third diode, and a fourth P-channel transistor and a fifth N-channel transistor that have gates connected in common and drains connected in common. A third inverter circuit, one end of the third capacitor connected to the third output terminal of the control circuit, the anode of the third diode connected to the other end of the third capacitor, The anode of the third diode is connected to the low-level potential point, the anode of the third diode is connected to the source of the fifth N-channel transistor, and the source of the fourth P-channel transistor is connected to the high-level potential point. Common third gate of fourth P-channel transistor and fifth N-channel transistor at third inverted output terminal of circuit Is connected, the common drain of the fourth P-channel transistor and the fifth N-channel transistor is the third step-down voltage output terminal.

  In the configuration of the present invention, a substrate potential switching circuit that switches the substrate potential of the output transistor in conjunction with the change in the output potential of the drive voltage output terminal may be provided between the control circuit and the substrate of the output transistor. Good.

  Specifically, the control circuit converts the level of the binary signal input from the signal input terminal into two potentials, a high level potential and a low level potential for driving the vertical register of the CCD image sensor, and outputs the two potentials. A fourth output terminal; and a substrate potential of the first N-channel transistor between the fourth output terminal of the control circuit and the substrate of the first N-channel transistor, and an output potential of the drive voltage output terminal There may be provided a substrate potential switching circuit for switching in conjunction with the change of the above.

  In the above configuration, in the substrate potential switching circuit, one power input terminal is connected to the middle level potential point, the other power input terminal is connected to the low level potential point, and the input terminal is the fourth output of the control circuit. Preferably, the inverter circuit is connected to the terminal and the output terminal is connected to the substrate of the first N-channel transistor.

  According to the second CCD image sensor vertical register driving apparatus of the present invention, a signal input terminal for inputting a binary signal and a level of the binary signal input from the signal input terminal are set to voltages for driving the vertical register of the CCD image sensor. A control circuit that converts and outputs, an output transistor to which a gate voltage is supplied from the control circuit, a drive voltage output terminal connected to the output transistor, and a substrate of the output transistor between the control circuit and the substrate of the output transistor A substrate potential switching circuit that switches the potential in conjunction with a change in the output potential of the drive voltage output terminal is provided.

  In the said structure, it is preferable to have the following structures. The control circuit converts the level of the binary signal input from the signal input terminal into two potentials, a high level potential and a low level potential for driving the vertical register of the CCD image sensor, and outputs the first and second potentials. And a third output terminal.

  The output transistor includes a first N-channel transistor having a drain connected to a middle level potential point having a middle level potential between the high level potential and the low level potential, and a gate voltage supplied from a first output terminal of the control circuit. And a second N-channel transistor having a source connected to a low-level potential point having a low-level potential and a gate voltage supplied from a second output terminal of the control circuit.

  The drive voltage output terminal is connected to the source of the first N-channel transistor and the drain of the second N-channel transistor.

  The substrate potential switching circuit is provided between the third output terminal of the control circuit and the substrate of the first N-channel transistor, and the substrate potential of the first N-channel transistor is set to the output potential of the drive voltage output terminal. Switch in conjunction with change.

  In the above configuration, the substrate potential switching circuit has one power supply input terminal connected to the middle level potential point, the other power supply input terminal connected to the low level potential point, and the input terminal serving as the third output terminal of the control circuit. And an inverter circuit having an output terminal connected to the substrate of the first N-channel transistor.

In the above configuration, the control circuit converts the level of the binary signal input from the signal input terminal into two potentials, a high level potential and a low level potential for driving the vertical register of the CCD image sensor, and outputs the two potentials. A fourth output terminal;
The semiconductor device further includes a first P-channel transistor having a source connected to a high-level potential point having a high-level potential and supplied with a gate voltage from a fourth output terminal of the control circuit, the drain of the first P-channel transistor being a drive voltage It is preferable to be connected to the output terminal.

  The third CCD image pickup device vertical register driving apparatus of the present invention includes a first CCD image pickup device vertical register drive having a binary output voltage and a second first CCD image pickup device having a ternary output voltage. Each of the vertical register driving devices is provided.

  A vertical register driving device for a first CCD image pickup device uses a first signal input terminal for inputting a binary signal, and a level of the binary signal inputted from the first signal input terminal for a vertical register of the CCD image pickup device. A first control circuit having first and second output terminals that convert and output two potentials, a high level potential and a low level potential for driving, and a middle level between the high level potential and the low level potential A first N-channel transistor having a drain connected to a middle level potential point having a potential and a gate voltage supplied from a first output terminal of the first control circuit; and a source at a low level potential point having a low level potential. A second N-channel transistor connected to and supplied with a gate voltage from a second output terminal of the first control circuit; and a source of the first N-channel transistor A first drive voltage output terminal connected to the drain of the second N-channel transistor, a first output terminal of the first control circuit, and a gate of the first N-channel transistor are provided. A first booster circuit for raising a gate voltage applied to the gate of the first N-channel transistor when the one N-channel transistor is turned on; a second output terminal of the first control circuit; and a second N-channel And a second booster circuit that is provided between the gate of the transistor and raises the gate voltage applied to the gate of the second N-channel transistor when the second N-channel transistor is made conductive.

  The vertical register driving device of the second CCD image pickup device has a second signal input terminal for inputting a binary signal, and the level of the binary signal inputted from the second signal input terminal to the vertical register of the CCD image pickup device. A second control circuit having first, second, and third output terminals that convert and output two potentials of a high level potential and a low level potential for driving, and an intermediate between the high level potential and the low level potential A third N-channel transistor whose drain is connected to a middle level potential point having a middle level potential and whose gate voltage is supplied from the first output terminal of the second control circuit; and a low level potential point having a low level potential A fourth N-channel transistor to which a source is connected and a gate voltage is supplied from the second output terminal of the second control circuit, and a high level potential having a high level potential. A P-channel transistor having a source connected to the potential point and supplied with a gate voltage from the third output terminal of the second control circuit; a source of the third N-channel transistor; a drain of the fourth N-channel transistor; and a P-channel A third N-channel transistor provided between the second drive voltage output terminal connected to the drain of the transistor, the first output terminal of the second control circuit, and the gate of the third N-channel transistor Between the third booster circuit for raising the gate voltage applied to the gate of the third N-channel transistor when conducting the second N-channel transistor, the second output terminal of the second control circuit, and the gate of the fourth N-channel transistor A gate current applied to the gate of the fourth N-channel transistor when the fourth N-channel transistor is provided between And a gate which is provided between the third output terminal of the second control circuit and the gate of the P-channel transistor and is added to the gate of the P-channel transistor when the P-channel transistor is made conductive And a step-down circuit that lowers the voltage.

  According to the vertical register driving device for a CCD image pickup device according to the present invention, the transistor size can be prevented from being enlarged and the charge transfer voltage can be switched at high speed.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
Hereinafter, a vertical driver (semiconductor integrated circuit device) according to a first embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 shows a vertical driver according to Embodiment 1 of the present invention. In this vertical driver, a binary signal voltage (for example, 3.3 V, 0 V) from the timing generator is applied from the input terminal 11 in the same manner as in the conventional configuration, and the voltage of the output driver is controlled by performing voltage conversion. A control circuit 1 that generates a voltage; a P-channel output transistor 2 that outputs a high-level voltage (for example, 12 V) to a CCD image sensor 5 connected to the output terminal 12; And an N-channel output transistor 4 that outputs a low-level voltage (for example, −6 V) to the CCD image pickup device 5.

  In addition to the above-described configuration, this vertical driver includes a step-down circuit 6 before the P-channel output transistor 2, that is, between the gate of the P-channel output transistor 2 and the control circuit 1. Further, boosting circuits 7 and 8 are provided before the N-channel output transistors 3 and 4, that is, between the gates of the N-channel output transistors 3 and 4 and the control circuit 1. The vertical driver further includes a substrate potential switching circuit 9 that switches the substrate potential of the intermediate potential output stage at appropriate times. The substrate potential switching circuit 9 is inserted in the substrate of a transistor that outputs a middle level voltage. Reference numeral 13 denotes a ternary vertical driver block, which includes a control circuit 1, a P-channel output transistor 2, and N-channel output transistors 3 and 4. Reference numeral 16 denotes a binary vertical driver block, which is composed of a control circuit and two N-channel output transistors. That is, the P-channel output transistor is omitted from the circuit of FIG. 1, and the internal circuit of the control circuit related thereto is omitted.

  2A shows a specific configuration of the booster circuits 7 and 8 in the vertical driver of FIG. 1, and FIG. 2B similarly shows a specific configuration of the step-down circuit 6. Since the booster circuits 7 and 8 have the same configuration, the booster circuit 7 will be described as a representative.

  The booster circuit 7 includes a capacitor 41, a clamp circuit 22 composed of a diode-connected P channel transistor 21, and an inverter 25 composed of a P channel transistor 23 and an N channel transistor 24. In the clamp circuit 22, a power supply 26 of a high level voltage (12 V) is connected to the anode side of the diode (the drain of the P-channel transistor 21). In addition, the cathode side (source and gate of the P-channel transistor 21) of the diode that is the output terminal is connected to the source of the P-channel transistor 23 of the inverter 25 and the clamp circuit 22 is connected to the source of the N-channel transistor 24 of the inverter 25. A power supply 27 having a level voltage (−6V) is connected.

  The step-down circuit 6 includes a capacitor 42, a clamp circuit 32 composed of a diode-connected P-channel transistor 31, and an inverter 35 composed of a P-channel transistor 33 and an N-channel transistor 34. In the clamp circuit 32, a power source 36 of a low level voltage (−6V) is connected to the cathode side of the diode (source and gate of the P-channel transistor 31). In the clamp circuit 32, the anode side (drain of the P-channel transistor 31) of the diode that is the output end is connected to the source of the N-channel transistor 34 of the inverter 35. A power source 37 having a high level voltage (12 V) is connected to the source of the P-channel transistor 33 of the inverter 35.

  A high level voltage (12 V) or a low level voltage (−6 V) is applied to the first control terminals 28 and 38, and a signal opposite to the first control terminals 28 and 38 is applied to the second control terminals 29 and 39. Is done.

  As described above, by using the booster circuits 7 and 8 for the N-channel transistors 3 and 4, the gate voltage when the N-channel transistors 3 and 4 are made conductive can be increased. Further, by using the step-down circuit 6 for the P-channel transistor 2, the gate voltage when the P-channel transistor is made conductive can be lowered. Therefore, the on-resistance of N channel MOS transistors 3 and 4 and P channel transistor 2 can be reduced. The reason will be described below.

  The on-resistance of a general MOS transistor can be expressed by the following equation.

Ron = {1 / (W / L)} μ _n C _OX (V _G -V _t ) (1)
Here, the symbol W / L indicates the ratio of the channel length L and the channel width W of the transistor, the symbol μ _N indicates the mobility, the symbol Cox indicates the oxide film capacitance, the symbol V _G indicates the gate voltage, V _T indicates a threshold voltage.

Since the mobility mu _N and the oxide film capacitance Cox is a constant determined by the diffusion process, in order to reduce the on-resistance of the MOS transistor, by increasing the channel width W, raising the gate voltage, and further the threshold voltage This can be realized by reducing the size. However, increasing the size of the channel width W causes an increase in the chip area, so in the first embodiment of the present invention, the gate voltage is converted to reduce the on-resistance.

  As an example, FIG. 3A shows the waveform characteristics of the first control terminal 28, the second control terminal 29, and the output terminal 30 of the booster circuit 7 when the high level voltage is 12V and the low level voltage is −6V. As an example, FIG. 3B shows the waveform characteristics of the first control terminal 38, the second control terminal 39, and the output terminal 40 of the step-down circuit 8 when the high level voltage is 12V and the low level voltage is −6V. . 12A and 12B show an equivalent circuit diagram of the capacitor 41 and the clamp circuit 22 in the booster circuit 7, and waveforms of voltages Vina and Vouta appearing at one end and the other end of the capacitor 41. FIG. 13A and 13B show equivalent circuit diagrams of the capacitor 42 and the clamp circuit 32 in the step-down circuit 6 and waveforms of voltages Vinb and Voutb appearing at one end and the other end of the capacitor 42.

  In the booster circuit 7, when a voltage of −6 V is input to the first control terminal 28 by the action of the capacitor 41 and the clamp circuit 22, a voltage of 12 V appears at the output terminal of the clamp circuit 22, and the first control terminal When a voltage of 12 V is input to 28, a voltage of 30 V appears at the output terminal of the clamp circuit 22. That is, when the voltage of the first control terminal 28 changes between −6V and 12V, the voltage at the output terminal of the clamp circuit 22 changes between 12V and 30V. This voltage is applied to the inverter 25.

  When a voltage of −6 V is applied to the first control terminal 28, a voltage of 12 V is applied to the second control terminal 29, so that the N-channel transistor 24 of the inverter 25 becomes conductive and the output terminal 30 A level voltage (-6V) is output. Further, when a voltage of 12V is applied to the first control terminal 28, a voltage of -6V is applied to the second control terminal 29, so that the P-channel transistor 23 of the inverter 25 becomes conductive and the output terminal 30 Outputs a voltage of 30 V, which is the output voltage of the clamp circuit 22.

  In the step-down circuit 6, when a voltage of 12 V is input to the first control terminal 38 by the action of the capacitor 42 and the clamp circuit 32, a voltage of −6 V appears at the output terminal of the clamp circuit 32, and the first control terminal When a voltage of −6 V is input to 38, a voltage of −24 V appears at the output terminal of the clamp circuit 32. That is, when the voltage of the first control terminal 38 changes between 12V and -6V, the voltage at the output terminal of the clamp circuit 32 changes between -6V and -24V. This voltage is applied to the inverter 35.

  When a voltage of 12V is applied to the first control terminal 38, a voltage of -6V is applied to the second control terminal 39, so that the P-channel transistor 33 of the inverter 35 becomes conductive and the output terminal 40 is high. A level voltage (12V) is output. Further, when a voltage of −6 V is applied to the first control terminal 38, a voltage of 12 V is applied to the second control terminal 39, so that the N-channel transistor 34 of the inverter 35 becomes conductive and the output terminal 40 Outputs a voltage of −24 V, which is the output voltage of the clamp circuit 32.

  The step-up circuit 7 and the step-down circuit 6 can change the gate voltage of each transistor. Voltage conversion is performed only when each transistor is turned on. The booster circuit 7 and the step-down circuit 6 are effective when the number of power supplies is limited, and the power supply range has the upper limit of the specification voltage of the process used.

  The substrate potential switching circuit 9 is another means for reducing the on-resistance of the MOS transistor due to the effect of the substrate effect. The threshold voltage of a MOS transistor considering the effect of the substrate bias effect is generally given by the following equation.

V _t = V _t0 + γ {√ (2φ _f + V _SB ) −√2φ _f } (2)
Here, γ and φ _f are constants determined by the diffusion process, V _SB indicates a source-substrate voltage, and V _t0 indicates a threshold voltage when V _SB is zero.

  It is generally known that the threshold voltage of a MOS transistor increases when a negative voltage is applied to the substrate voltage. Since the ON resistance of the MOS transistor increases as the threshold voltage increases, the substrate potential switching circuit 9 is inserted to reduce the influence of the substrate bias effect during the operation of the MOS transistor. More specifically, when the output terminal 12 is at a low level voltage, the substrate potential switching circuit 9 outputs a low level voltage and sets the substrate potential to a low level potential. Next, when the output terminal 12 is set to the middle level potential, the substrate potential switching circuit 9 outputs the middle level voltage and switches the substrate potential to the middle level potential. This eliminates the difference between the substrate potential and the potential of the output terminal 12 at all times, thereby reducing the influence of the substrate bias effect.

  The timing of the substrate potential switching circuit 9 is also controlled from the control circuit 1 in the same manner as the booster circuits 7 and 8 and the step-down circuit 6. In addition, since the substrate potential switching circuit 9 forms a PN junction during the switching operation, it also has a function of improving the current driving capability. This point will be described with reference to FIG. By changing the output of the substrate potential switching circuit 9 to the middle level voltage and setting the booster circuit 7 to the high level voltage from the state where the output terminal 12 is at the low level voltage, the substrate of the output transistor 3 and the source of the output transistor 3 are connected. A parasitic diode (PN junction) formed therebetween is turned on, and a current flows. Due to this influence, the current of the parasitic diode is added to the current flowing when the output transistor 3 itself is turned on, and the voltage of the output terminal 12 is quickly switched.

  FIG. 4 is a timing chart for explaining an example of the operation of FIG. The input voltage high level or the input voltage low level is applied to the input terminal of the control circuit 1 as in FIG. The characteristic indicated by the broken line indicates the rising and falling characteristics of the output voltage in the conventional configuration. As an example, an operation of falling from the middle level voltage to the low level voltage and then rising to the middle level voltage will be described.

  When the output voltage is in the middle level voltage state, the N-channel output transistor 3 is in the on state. At this time, the booster circuit 7 is operated from the control circuit 1, and the substrate potential switching circuit 9 also converts the substrate potential to a middle level voltage.

  When the output voltage falls from the middle level voltage to the low level voltage, the N-channel output transistor 3 is turned from the on state to the off state, and the N-channel output transistor 4 is turned on. At the time of switching, the booster circuit 7 in the middle level voltage output stage changes from the boost operation to a voltage for turning off the N-channel output transistor, and the booster circuit 8 in the low level voltage output stage receives the signal from the control circuit 1 and performs the boost operation. I do. The substrate potential switching circuit 9 converts the substrate potential from a middle level voltage to a low level voltage at the same time as the booster circuit 7 switches to a signal for turning off the N-channel output transistor 3.

  When the output voltage rises from the low level voltage to the middle level voltage, the boost circuit 8 in the low level voltage output stage switches to a voltage that turns off the N-channel output transistor 4, and the boost circuit 7 in the middle level voltage output stage boosts the voltage. Start operation. At the same time, the substrate potential switching circuit 9 switches the substrate potential to the middle level voltage.

  Therefore, when the booster circuits 7, 8, the step-down circuit 6, and the substrate potential switching circuit 9 are applied to the semiconductor integrated device that drives the vertical register of the CCD image pickup device 5, charges in the vertical register can be transferred at high speed. it can. Therefore, it is possible to increase the rise time and fall time of the charge transfer voltage by reducing the on-resistance of the output transistor while preventing enlargement of the element size.

In the above-described embodiment, the booster circuits 7, 8, the step-down circuit 6, and the substrate potential switching circuit 9 are provided. However, the booster circuits 7, 8, and the step-down circuit 6 are provided, and the substrate potential switching circuit 9 is omitted. Also good. Further, the substrate potential switching circuit 9 may be provided, and the booster circuits 7 and 8 and the step-down circuit 6 may be omitted.
The configuration of the CCD image pickup device as a vertical register drive system includes a vertical register drive device for a first CCD image pickup device having a binary output voltage and a vertical register for a second first CCD image pickup device having a ternary output voltage. It is the same as the prior art in that at least one driving device is provided. However, the configuration of the vertical register driving device for the first and second CCD image sensors is different from the prior art as described above.

  As described above, the vertical register driving device for a CCD image pickup device according to the present invention is effective for a method for controlling the high-speed switching while suppressing the enlargement of the output transistor.

It is a circuit diagram which shows the structure of the vertical driver of Embodiment 1 of this invention. FIG. 3 is a circuit diagram illustrating a configuration of a booster circuit in the vertical driver according to the first embodiment of the present invention. It is a circuit diagram which shows the structure of the pressure | voltage fall circuit in the vertical driver of Embodiment 1 of this invention. It is a characteristic view of the booster circuit in the vertical driver of Embodiment 1 of the present invention. FIG. 6 is a characteristic diagram of a step-down circuit in the vertical driver according to the first embodiment of the present invention. It is a timing diagram in the vertical driver of Embodiment 1 of the present invention. It is a circuit diagram which shows a prior art example. It is a timing diagram of a prior art example. 1 is a block diagram showing a general semiconductor integrated device around a CCD image sensor driving circuit. (A) is a block diagram of the control circuit, (b) is a waveform diagram showing the input and output waveforms of the control circuit. (A) is a block diagram showing a ternary vertical driver block, and (b) is a block diagram showing a binary vertical driver block. It is a schematic diagram which shows the structure of the vertical register | resistor drive system of a CCD image pick-up element. It is a schematic diagram which shows operation | movement of a substrate potential switching circuit. (A) shows an equivalent circuit diagram of a capacitor and a clamp circuit in the booster circuit, and (b) shows a waveform of a voltage appearing at one end and the other end of the capacitor. (A) shows an equivalent circuit diagram of a capacitor and a clamp circuit in the step-down circuit, and (b) shows a waveform of a voltage appearing at one end and the other end of the capacitor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Control circuit 2 P channel output transistor 3 N channel output transistor 4 N channel output transistor 5 CCD image pick-up element 6 Voltage step-down circuit 7, 8 Voltage step-up circuit 9 Substrate potential switching circuit

Claims (14)

A signal input terminal for inputting a binary signal;
A control circuit for converting the level of the binary signal input from the signal input terminal into a voltage for driving the vertical register of the CCD image sensor and outputting the voltage;
An output transistor to which a gate voltage is supplied from the control circuit;
A drive voltage output terminal connected to the output transistor;
By shifting the level of the gate voltage that is provided between the control circuit and the gate of the output transistor and applied to the gate of the output transistor when the output transistor is made conductive from the level of the output voltage of the control circuit, A vertical register driving device for a CCD image pickup device, comprising: a gate voltage shift circuit for reducing an on-resistance of the output transistor. The control circuit converts the level of the binary signal input from the signal input terminal into two potentials, a high level potential and a low level potential for driving the vertical register of the CCD image sensor, and outputs the first and second potentials. A second output terminal;
The output transistor has a drain connected to a middle level potential point having a middle level potential between the high level potential and the low level potential, and a gate voltage is supplied from a first output terminal of the control circuit. An N-channel transistor;
A source connected to a low level potential point having the low level potential, and a second N-channel transistor to which a gate voltage is supplied from a second output terminal of the control circuit;
The drive voltage output terminal is connected to a source of the first N-channel transistor and a drain of the second N-channel transistor;
The gate voltage shift circuit is provided between the first output terminal of the control circuit and the gate of the first N-channel transistor to conduct the first N-channel transistor. A first booster circuit for raising a gate voltage applied to the gate of the channel transistor;
Provided between the second output terminal of the control circuit and the gate of the second N-channel transistor, and added to the gate of the second N-channel transistor when the second N-channel transistor is made conductive. 2. A vertical register driving device for a CCD image pickup device according to claim 1, further comprising a second booster circuit for raising the gate voltage. The control circuit converts the level of the binary signal input from the signal input terminal into two potentials, a high level potential and a low level potential for driving the vertical register of the CCD image sensor, and outputs the third potential. An output terminal;
A first P-channel transistor having a source connected to a high-level potential point having the high-level potential and a gate voltage supplied from a third output terminal of the control circuit;
3. The vertical register driving device for a CCD image pickup device according to claim 2, wherein a drain of the first P-channel transistor is connected to the driving voltage output terminal.   A gate provided between the third output terminal of the control circuit and the gate of the first P-channel transistor and applied to the gate of the first P-channel transistor when the first P-channel transistor is turned on 4. A vertical register driving device for a CCD image pickup device according to claim 3, further comprising a step-down circuit for lowering the voltage. The control circuit outputs a signal whose output level is inverted from the first output terminal, and a second inversion that outputs a signal whose output level is inverted between the first output terminal and the second output terminal. An output terminal,
The first booster circuit includes: a first capacitor; a first clamp circuit including a first diode; a second P-channel transistor having gates connected in common and drains connected in common; A first inverter circuit composed of an N-channel transistor, one end of the first capacitor being connected to a first output terminal of the control circuit, and the first diode being connected to the other end of the first capacitor. The cathode of the first diode is connected to a high-level potential point, the cathode of the first diode is connected to the source of the second P-channel transistor, and the third N-channel transistor Is connected to a low-level potential point, and the second P-channel transistor is connected to the first inverting output terminal of the control circuit. And the common gate of the third N-channel transistor is connected, the common drain of the second P-channel transistor and said third N-channel transistor serves as the first boosted voltage output terminal,
The second booster circuit includes a second capacitor, a second clamp circuit including a second diode, a third P-channel transistor having a gate connected to each other and a drain connected to each other, and a fourth P-channel transistor. A second inverter circuit composed of an N-channel transistor, one end of the second capacitor being connected to a second output terminal of the control circuit, and the second diode being connected to the other end of the second capacitor. The cathode of the second diode is connected to a high-level potential point, the cathode of the second diode is connected to the source of the third P-channel transistor, and the fourth N-channel transistor Is connected to the low-level potential point, and the third P-channel transistor is connected to the second inverting output terminal of the control circuit. And a common gate of the fourth N-channel transistor is connected, and a common drain of the third P-channel transistor and the fourth N-channel transistor is a second boosted voltage output terminal. Vertical register drive device for CCD image sensor. The control circuit has a third inverted output terminal for outputting a signal whose output level is inverted from that of the third output terminal,
The step-down circuit includes a third capacitor, a third clamp circuit composed of a third diode, a fourth P-channel transistor and a fifth N-channel transistor having gates connected in common and drains connected in common A third inverter circuit, one end of the third capacitor is connected to a third output terminal of the control circuit, and an anode of the third diode is connected to the other end of the third capacitor. Connected, the anode of the third diode is connected to a low level potential point, the anode of the third diode is connected to the source of the fifth N-channel transistor, and the source of the fourth P-channel transistor is The fourth P-channel transistor and the third inverted output terminal of the control circuit are connected to a high-level potential point. 6. The CCD imaging device according to claim 5, wherein a common gate of a fifth N-channel transistor is connected, and a common drain of the fourth P-channel transistor and the fifth N-channel transistor is a third step-down voltage output terminal. Device vertical register drive.   2. The CCD according to claim 1, further comprising a substrate potential switching circuit for switching the substrate potential of the output transistor in conjunction with a change in the output potential of the drive voltage output terminal between the control circuit and the substrate of the output transistor. Vertical register driving device for image sensor. The control circuit converts the level of the binary signal input from the signal input terminal into two potentials, a high level potential and a low level potential for driving the vertical register of the CCD image sensor, and outputs the second potential. An output terminal;
Between the fourth output terminal of the control circuit and the substrate of the first N-channel transistor, the substrate potential of the first N-channel transistor is interlocked with the change in the output potential of the drive voltage output terminal. 5. A vertical register driving device for a CCD image pickup device according to claim 4, further comprising a substrate potential switching circuit for switching.   The substrate potential switching circuit has one power supply input terminal connected to the middle level potential point, the other power supply input terminal connected to the low level potential point, and an input terminal connected to the fourth output terminal of the control circuit. 9. A vertical register driving device for a CCD image pickup device according to claim 8, wherein an output terminal is constituted by an inverter circuit connected to a substrate of the first N-channel transistor. A signal input terminal for inputting a binary signal;
A control circuit for converting the level of the binary signal input from the signal input terminal into a voltage for driving the vertical register of the CCD image sensor and outputting the voltage;
An output transistor to which a gate voltage is supplied from the control circuit;
A drive voltage output terminal connected to the output transistor;
A vertical register of a CCD imaging device comprising a substrate potential switching circuit for switching the substrate potential of the output transistor in conjunction with a change in the output potential of the drive voltage output terminal between the control circuit and the substrate of the output transistor Drive device. The control circuit converts the level of the binary signal input from the signal input terminal into two potentials, a high level potential and a low level potential for driving the vertical register of the CCD image sensor, and outputs the first potential, Having second and third output terminals;
The output transistor has a drain connected to a middle level potential point having a middle level potential between the high level potential and the low level potential, and a gate voltage is supplied from a first output terminal of the control circuit. An N-channel transistor;
A source connected to a low level potential point having the low level potential, and a second N-channel transistor to which a gate voltage is supplied from a second output terminal of the control circuit;
The drive voltage output terminal is connected to a source of the first N-channel transistor and a drain of the second N-channel transistor;
The substrate potential switching circuit is provided between a third output terminal of the control circuit and the substrate of the first N-channel transistor, and outputs the substrate potential of the first N-channel transistor to the drive voltage output 11. The vertical register driving device for a CCD image pickup device according to claim 10, wherein the switching is performed in conjunction with a change in the output potential of the terminal.   The substrate potential switching circuit has one power supply input terminal connected to a middle level potential point, the other power supply input terminal connected to a low level potential point, and an input terminal connected to a third output terminal of the control circuit. 12. A vertical register driving device for a CCD image pickup device according to claim 11, wherein the output end is constituted by an inverter circuit connected to a substrate of the first N-channel transistor. The control circuit converts the level of the binary signal input from the signal input terminal into two potentials, a high level potential and a low level potential for driving the vertical register of the CCD image sensor, and outputs the second potential. An output terminal;
A first P-channel transistor having a source connected to a high-level potential point having the high-level potential and a gate voltage supplied from a fourth output terminal of the control circuit;
13. The vertical register driving device for a CCD image pickup device according to claim 12, wherein a drain of the first P-channel transistor is connected to the driving voltage output terminal. CCD imaging device including at least one vertical register driving device for a first CCD image pickup device having a binary output voltage and a vertical register driving device for a second first CCD image pickup device having a ternary output voltage A vertical register drive system for the element,
The vertical register driving device of the first CCD image sensor is:
A first signal input terminal for inputting a binary signal;
First and second signals that are converted from the level of the binary signal input from the first signal input terminal into two potentials, a high level potential and a low level potential for driving the vertical register of the CCD image sensor, and output. A first control circuit having a plurality of output terminals;
A first N channel in which a drain is connected to a middle level potential point having a middle level potential between the high level potential and the low level potential, and a gate voltage is supplied from a first output terminal of the first control circuit. A transistor,
A second N-channel transistor having a source connected to a low-level potential point having the low-level potential and a gate voltage supplied from a second output terminal of the first control circuit;
A first drive voltage output terminal connected to a source of the first N-channel transistor and a drain of the second N-channel transistor;
The gate of the first N-channel transistor, which is provided between the first output terminal of the first control circuit and the gate of the first N-channel transistor to make the first N-channel transistor conductive. A first booster circuit for raising the gate voltage applied to
The gate of the second N-channel transistor, which is provided between the second output terminal of the first control circuit and the gate of the second N-channel transistor to make the second N-channel transistor conductive. A second booster circuit for raising the gate voltage applied to
The vertical register driving device of the second CCD image sensor is:
A second signal input terminal for inputting a binary signal;
First and second signals that are converted from the level of the binary signal input from the second signal input terminal into two potentials, a high level potential and a low level potential for driving the vertical register of the CCD image sensor, are output. And a second control circuit having a third output terminal;
A third N channel in which a drain is connected to a middle level potential point having a middle level potential between the high level potential and the low level potential, and a gate voltage is supplied from a first output terminal of the second control circuit A transistor,
A fourth N-channel transistor having a source connected to a low-level potential point having the low-level potential and a gate voltage supplied from a second output terminal of the second control circuit;
A P-channel transistor having a source connected to a high-level potential point having the high-level potential and a gate voltage supplied from a third output terminal of the second control circuit;
A second drive voltage output terminal connected to the source of the third N-channel transistor, the drain of the fourth N-channel transistor, and the drain of the P-channel transistor;
The gate of the third N-channel transistor, which is provided between the first output terminal of the second control circuit and the gate of the third N-channel transistor and makes the third N-channel transistor conductive. A third booster circuit for raising the gate voltage applied to
The gate of the fourth N-channel transistor, which is provided between the second output terminal of the second control circuit and the gate of the fourth N-channel transistor to make the fourth N-channel transistor conductive. A fourth booster circuit for raising the gate voltage applied to
A step-down circuit that is provided between the third output terminal of the second control circuit and the gate of the P-channel transistor, and lowers the gate voltage applied to the gate of the P-channel transistor when the P-channel transistor is made conductive. A vertical register driving system for a CCD image pickup device.

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