JP2007304225A - Image display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To control an image display device such that abnormal display does not occur on a screen at the time of vertical inversion operation in the image display device having a vertical inversion function and provided successively with scanning scanners of a plurality of systems. <P>SOLUTION: A scanner part is divided into: a first scanner 3 for supplying a first control signal for video signal sampling in a first scanning line VSCAN1; a second scanner 4 for supplying a second control signal for light emitting element lighting in a second scanning line VSCAN2; and a third scanner 5 for supplying a third control signal for correction in a third scanning line VSCAN3. Inversion operation vertically inverting and displaying images is enabled by successively switching a scanning direction on the line of a pixel array part 1, and when performing the inversion operation during displaying the images in the pixel array part 1, the first scanner 3, the second scanner 4 and the third scanner 5 are reset within one field before and after the inversion operation to prevent malfunction. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an active matrix image display device. Specifically, the present invention relates to an image display apparatus using a light emitting element such as an organic EL element for each pixel. More particularly, the present invention relates to a control technique for a plurality of scanners included in an image display device having a screen upside down function.

In recent years, organic EL displays using organic EL light-emitting elements for pixels have been actively developed as active matrix image display devices. In an organic EL display, a drive transistor such as a thin film transistor (TFT) is incorporated in order to drive an organic EL light emitting element included in each pixel. Furthermore, an additional transistor is formed to correct the variation in TFT characteristics of the drive transistor. Such an image display device is described in, for example, Patent Document 1 below.
JP2004-347993

  In general, active matrix image display devices such as an organic EL display and a liquid crystal display (LCD) generally have a screen upside down function and a left side upside down function for the purpose of enhancing the function of the panel. A general method for realizing the upside down function is a method of inverting the rolling direction of the shift register constituting the V scanner that performs line sequential scanning of the screen.

  Here, in the case of an LCD, there is usually only one V scanner that controls data writing by line sequential scanning. Therefore, even when upside down is performed, as long as the inversion timing and data are synchronized, no major problem in image display occurs.

  Further, even in an organic EL display, since there is only one V scanner when the simplest pixel circuit is used, there is no problem if data is synchronized with upside down like the LCD.

  However, in an active matrix organic EL display in which a TFT is formed for each pixel to drive a light emitting element, a pixel circuit having a variation correction function is used as described above in order to cancel variations in TFT characteristics for each pixel. Is common. In this case, since each pixel circuit is driven line-sequentially, it is necessary to use a plurality of V scanners instead of a single one.

  Here, the plurality of V scanners have a phase relationship with each other. Therefore, when the screen is turned upside down with the transfer data remaining in the shift register that constitutes the V scanner, the timing of the video signal sampling operation, the drive transistor correction operation, the light emitting element driving, etc. Inappropriate, problems such as flashing of the screen may occur, which is a problem to be solved.

  In view of the above-described problems of the prior art, the present invention controls an image display apparatus having a vertical inversion function and a plurality of line sequential scanning scanners so that abnormal display does not occur on the screen during the vertical inversion operation. With the goal. In order to achieve this purpose, the following measures were taken. That is, the image display device according to the present invention includes a pixel array section and a peripheral circuit section that drives the pixel array section. The pixel array section includes a row-shaped scanning line, a column-shaped signal line, each scanning line, and each signal. The peripheral circuit section supplies a control signal to each scanning line in order to perform line sequential scanning of the pixel array section over one field. A scanner unit, and a driver for supplying an image signal to each signal line in accordance with line sequential scanning and displaying an image on the pixel array unit. Each pixel includes at least a sampling transistor, a drive transistor, a switching transistor, , A correction transistor, and a light emitting element, and the sampling transistor conducts in response to the first control signal supplied from the first scanning line and is supplied with the video signal supplied from the signal line. The drive transistor supplies an output current corresponding to the sampled video signal to the light emitting element, and the light emitting element has a luminance corresponding to the video signal by the output current supplied from the drive transistor. The switching transistor is arranged in a current path through which the output current flows, and is turned on according to the time width of the second control signal supplied from the second scanning line, and the output current is supplied to the light emitting element. The light emitting element is caused to emit light for a light emission period corresponding to the time width, and the correction transistor operates in a predetermined correction period according to a third control signal supplied from a third scanning line, and the sampling transistor A correction operation of the drive transistor is performed in cooperation with the transistor or the switching transistor, and the scanner unit includes at least the first scanning line. A first scanner that supplies a first control signal; a second scanner that supplies a second control signal to the second scanning line; and a third scanner that supplies a third control signal to the third scanning line. The scanner unit can perform a reversing operation in which the image of the pixel array unit is switched in line-sequential scanning to display the image upside down. When performing the reversing operation while displaying the image on the pixel array unit, Within one field before and after the operation, at least one of the first scanner, the second scanner, and the third scanner is reset.

  Preferably, the correction transistor performs a correction operation for canceling a variation in threshold voltage of the drive transistor in a correction period preceding the light emission period, and the scanner unit performs a first operation within one field before and after the inversion operation. All the one scanner, the second scanner, and the third scanner are reset, and at that time, within the 10 horizontal period immediately before the third scanner applies the third control signal to the first third scanning line of the pixel array section. Reset to. The light emitting element is an organic electroluminescence element.

  An image display apparatus according to the present invention includes a pixel array section and a peripheral circuit section that drives the pixel array section. The pixel array section includes a row-shaped scanning line, a column-shaped signal line, each scanning line, and each signal. The peripheral circuit section supplies a control signal to each scanning line in order to perform line sequential scanning of the pixel array section over one field. A scanner unit, and a driver for supplying an image signal to each signal line in accordance with line sequential scanning and displaying an image on the pixel array unit. Each pixel includes at least a sampling transistor, a drive transistor, a switching transistor, , A correction transistor, and a light emitting element, and the sampling transistor conducts in response to the first control signal supplied from the first scanning line and is supplied from the signal line. The drive transistor supplies an output current corresponding to the sampled video signal to the light emitting element, and the light emitting element has a luminance corresponding to the video signal by the output current supplied from the drive transistor. The switching transistor is arranged in a current path through which the output current flows, and is turned on according to the time width of the second control signal supplied from the second scanning line, and supplies the output current to the light emitting element. Then, the light emitting element is caused to emit light for a light emission period corresponding to the time width, and the correction transistor operates in a predetermined correction period according to a third control signal supplied from a third scanning line, and the sampling transistor Alternatively, the drive transistor performs a correction operation in cooperation with the switching transistor, and the scanner unit at least applies to the first scan line. A first scanner that supplies one control signal, a second scanner that supplies a second control signal to the second scanning line, and a third scanner that supplies a third control signal to the third scanning line. The scanner unit can perform a reversing operation of switching the line-sequential scanning direction of the pixel array unit to display the image upside down. When performing the reversing operation while displaying an image on the pixel array unit, the scanner unit (2) The output of the scanner is turned off, all the light emitting elements included in each pixel are set in a non-light emitting state, and the pixel array portion is displayed in black.

  Preferably, the scanner unit turns off the output of the second scanner and displays the pixel array unit in black within one field immediately after the inversion operation. The second scanner is generated while maintaining the generation of the second control signal by the shift register as it is and the shift register that sequentially generates the second control signal in accordance with the line sequential scanning. The second control signal is masked to forcibly turn off the output of the second scanner. The light emitting element is an organic electroluminescence element.

  According to the first aspect of the present invention, when a reversal operation is performed while an image is displayed on the pixel array unit, each scanner is configured by resetting a plurality of scanners within one field before and after the reversal operation. The internal state of the shift register is initialized. Thereby, even when the reversal operation is started, each scanner can sequentially perform normal line-sequential scanning while maintaining a predetermined phase relationship. Accordingly, it is possible to provide an image display device in which screen flushing or the like does not occur even when upside down display is performed.

  According to the second aspect of the present invention, when the reversal operation is performed while an image is displayed on the pixel array section, the output of the scanner that controls the light emission period of the light emitting elements among a plurality of scanners is turned off. Thereby, all the light emitting elements included in each pixel are brought into a non-light emitting state, and the screen of the pixel array portion is displayed in black. As a result, even if the phase relationship is temporarily lost due to the reversing operation of the shift register of each scanner and there is a possibility of abnormal display, there is no possibility that flashing or the like is actually visually recognized by displaying the screen in black.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of an image display apparatus according to the present invention. As shown in the figure, the present image display device basically includes a pixel array section 1 and a peripheral circuit section for driving the pixel array section 1. The pixel array unit 1 includes a row-shaped scanning line VSCAN, a column-shaped signal line DATA, and pixels 2 arranged in a column shape at a portion where each scanning line VSCAN and each signal line DATA intersect. The row number and column number of each pixel 2 are shown in parentheses. For example, the pixel located in the first row and the first column is represented by (1, 1). The row number of the scanning line VSCAN is also shown with parentheses. For example, the first scanning line (first line) is represented by VSCAN (1). In addition, the column number of the signal line DATA is also shown in parentheses. For example, the signal line in the first column is represented by DATA (1). In this specification, a control signal supplied to the scanning line VSCAN may be expressed by using the same symbol VSCAN. Similarly, the same code DATA may be used to represent a video signal supplied to the signal line DATA.

  The peripheral circuit section includes a scanner section that sequentially supplies a control signal VSCAN to each scanning line VSCAN in order to perform line sequential scanning of the pixel array section 1 over one field, and a video signal DATA for each signal line in accordance with the line sequential scanning. And an H driver 6 that supplies data to the DATA and displays an image on the pixel array unit 1.

  Each pixel 2 includes at least a sampling transistor, a drive transistor, a switching transistor, a correction transistor, and a light emitting element such as an organic EL device. The sampling transistor conducts in response to the first control signal VSCAN1 supplied from the first scan line VSCAN1, and samples the video signal DATA supplied from the signal line DATA. The drive transistor supplies an output current corresponding to the sampled video signal DATA to the light emitting element. The light emitting element emits light with luminance according to the video signal DATA by the output current supplied from the drive transistor. The switching transistor is arranged in a current path through which the output current flows, and is turned on according to the time width of the second control signal VSCAN2 supplied from the second scanning line VSCAN2, and the output current is supplied to the light emitting element to increase the time width. The light emitting element is caused to emit light for the corresponding light emission period. The correction transistor operates in a predetermined correction period according to the third control signal VSCAN3 supplied from the third scan line VSCAN3, and performs a correction operation of the drive transistor in cooperation with the sampling transistor or the switching transistor.

  The scanner unit includes at least a first scanner (V scanner 1) 3 that supplies a first control signal to the first scanning line VSCAN1, and a second scanner (V scanner 2) that supplies a second control signal to the second scanning line VSCAN2. 4 and a third scanner (V scanner 3) for supplying a third control signal to the third scanning line VSCAN3. The scanner unit can perform a reversing operation for switching the line sequential scanning direction of the pixel array unit 1 so as to display the image upside down. As a feature of the present invention, when an inversion operation is performed while an image is displayed on the pixel array unit 1, at least one of the first scanner 3, the second scanner 4, and the third scanner 5 is within one field before and after the inversion operation. Reset one.

  Preferably, the correction transistor included in each pixel 1 performs a correction operation to cancel the variation in the threshold voltage of the drive transistor in the correction period preceding the light emission period. In this case, the scanner unit resets all of the first scanner 3, the second scanner 4, and the third scanner 5 within one field before and after the reversing operation. At this time, the third scanner 5 resets the first third scanning line VSCAN3 (1) of the pixel array unit 1 within 10 horizontal periods immediately before applying the third control signal.

  In the second aspect of the present invention, when the reversing operation is performed while displaying an image on the pixel array unit 1, the output of the second scanner 4 is turned off, and all the light emitting elements included in each pixel 2 are in a non-light emitting state. The pixel array unit 1 is displayed in black. Preferably, the scanner unit turns off the output of the second scanner 4 and displays the pixel array unit 1 in black within one field immediately after the inversion operation. In a specific configuration, the second scanner 4 directly generates the second control signal VSCAN2 by the shift register that generates the second control signal VSCAN2 in accordance with the line sequential scanning, and performs the inversion operation. While maintaining, the generated second control signal VSCAN2 is masked to forcibly turn off the output of the second scanner 4.

  FIG. 2 is a circuit diagram showing a basic configuration example of the pixel 2 included in the image display apparatus shown in FIG. As illustrated, the pixel 2 includes at least a sampling transistor Tr1, a drive transistor Trd, a switching transistor Tr2, a correction transistor Tr3, and a light emitting element OLED. The drive transistor Trd is of a P channel type, for example, and has a drain connected to the power supply line VDD1 and a source connected to the anode of the two-terminal light emitting element OLED via the switching transistor Tr2. The switching transistor Tr2 is, for example, an N-channel type, and is inserted between the drive transistor Trd and the light emitting element OLED. The gate of the switching transistor Tr2 is connected to the second scanning line VSCAN2 (i). Note that the insertion position of the switching transistor Tr2 is not limited to the example shown in the figure, and may be interposed in the current path of the output current flowing through the light emitting element OLED. The cathode of the light emitting element OLED is connected to the ground potential Vss1. As is apparent from the illustrated example, the output current flows from the power supply line VDD1 through the light emitting element OLED via the drive transistor Trd and the switching transistor Tr2, and flows into the ground line VSS1.

  On the other hand, the sampling transistor Tr1 is an N-channel type, for example, and is connected from the signal line DATA to the gate of the drive transistor Trd via the additional circuit 7. The gate of the sampling transistor Tr1 is connected to the first scanning line VSCAN1 (i). The correction transistor Tr3 is included in the additional circuit 7, and its gate is connected to the third scanning line VSCAN3 (i).

  In such a configuration, the sampling transistor Tr1 conducts in response to the first control signal supplied from the first scanning line VSCAN1 (i) and samples the video signal supplied from the signal line DATA. Actually, the sampled video signal is held in the additional circuit 7. The drive transistor Trd supplies an output current corresponding to the sampled video signal to the light emitting element OLED. The light emitting element OLED is made of, for example, an organic EL device, and emits light with luminance according to the video signal by the output current supplied from the drive transistor Trd. The switching transistor Tr2 is arranged in a current path through which an output current flows, and is turned on according to the time width of the second control signal supplied from the second scanning line VSCAN2 (i), and supplies the output current to the light emitting element OLED. Thus, the light emitting element OLED emits light for the light emission time corresponding to the time width. The correction transistor Tr3 is included in the additional circuit 7, and operates in a predetermined correction period according to the third control signal supplied from the third scanning line VSCAN3 (i), and the sampling transistor Tr1, the switching transistor Tr2, etc. In cooperation, the drive transistor Trd is corrected.

  FIG. 3 is a circuit diagram showing a specific configuration example of the additional circuit 7 included in the pixel shown in FIG. As shown in the figure, the additional circuit 7 includes a pixel capacitor Cs, a correction transistor Tr3, and another correction transistor Tr4. The pixel capacitor Cs is inserted between the gate and source of the drive transistor Trd. The correction transistor Tr3 is connected between the source of the drive transistor Trd and a predetermined initialization potential Vini. As described above, the gate of the correcting transistor Tr3 is connected to the third scanning line VSCAN3 (i). Another correction transistor Tr4 is connected between the gate of the drive transistor Trd and a predetermined reference potential Vofs. The gate of the correction transistor Tr4 is connected to the fourth scanning line VSCAN4 (i). As is clear from this example, the number of scanning lines corresponding to the number of correction transistors increases, and the number of V scanners driving the corresponding scanning lines increases accordingly. In the figure, the equivalent capacity of the light emitting element OLED is represented as Coled.

  A timing chart for explaining the operation of the pixel circuit is shown in the lower part of FIG. This timing chart represents the driving state of the pixels 2 in the i-th row together with the waveforms of the first to fourth control signals VSCAN1 (i) to VSCAN4 (i) supplied to the gates of the transistors. This driving state is divided into a correction period for the drive transistor Trd, a video signal writing period, a light emitting period of the light emitting element OLED, and a light extinction period. In the first correction period, first, VSCAN3 (i) becomes high level, the correction transistor Tr3 is turned on, and the source of the drive transistor Trd is initialized to the initial potential Vini. Also, the control signal VSCAN4 (i) becomes high level and the other correction transistor Tr4 is turned on. As a result, the gate of the drive transistor Trd is set to the reference potential Vofs. In this state, after the correcting transistor Tr3 is turned off, the control signal VSCAN2 (i) becomes high level and the switching transistor Tr2 is turned on. As a result, the output current starts to flow from VDD1 through the drive transistor Trd. At this time, since the anode potential of the light emitting element OLED is in a reverse bias state by the initialization potential Vini, the output current does not flow to the light emitting element OLED. This output current charges the pixel capacitor Cs without charging the equivalent capacitor Coled of the light emitting element OLED. The drive transistor Trd is cut off when the potential written to the pixel capacitor Cs has just reached the threshold voltage Vth of the drive transistor Trd. By this operation, a voltage necessary for canceling the threshold voltage of the drive transistor Trd is held in the pixel capacitor Cs.

  Thereafter, in the writing period, the control signal VSCAN1 (i) becomes high level and the sampling transistor Tr1 is turned on. As a result, the video signal is sampled from the signal line DATA and written to the pixel capacitor Cs. Thereafter, in the light emission period, the control signal VSCAN2 (i) becomes high level again, and the switching transistor Tr2 is turned on. Accordingly, the output current flows from the power supply line VDD1 through the drive transistor Trd to the light emitting element OLED and enters the light emitting state. The output current at this time has a level corresponding to the video signal sampled in the pixel capacitor Cs. Thereafter, when the control signal VSCAN2 (i) becomes low level, the light emitting element OLED enters the extinguishing period. Thus, the control signal VSCAN2 (i) controls the light emission period of the light emitting element OLED. By controlling the light emission period, the luminance level of the screen can be adjusted.

  FIG. 4 is a schematic diagram illustrating a driving state of a pixel array including the pixels illustrated in FIG. The illustrated example is a case where line sequential scanning is performed in order from the top to the bottom of the pixel array. For each line (pixel row) of the pixel array, an image is displayed by performing a correction operation, a writing operation, a light emitting operation, and an extinguishing operation sequentially from the top. Since the line-sequential scanning shifts backward on the time axis for each line, the lines that delimit the correction period, the writing period, the light emitting period, and the extinguishing period are inclined from the upper left to the lower right.

  FIG. 5 is a schematic timing chart showing line sequential scanning of the V scanner. The upper row represents the rolling motion from the top to the bottom, and the bottom row represents the rolling motion from the bottom to the top. In the rolling operation from top to bottom, the V scanner outputs a control signal in order from the top toward the i + 4th line from the i-th line. Specifically, the V scanner is composed of a shift register, operates in response to a clock signal input from the outside, and similarly starts from an externally input start pulse and moves in sequence every one horizontal period (1H). The control signals are output as i row, i + 1 row, i + 2 row, i + 3 row, i + 4 row, and so on.

  In the upside-down roll, the V-scanner shift register rolls the start pulse from the bottom up, and the control signals are in the order of i + 4 line, i + 3 line, i + 2 line, i + 1 line, i line. Output. As a result, the image is inverted and displayed on the screen.

  This upside down function is common to all V scanners 1, 2, 3, and 4. Normally, these V scanners 1 to 4 operate with a common clock signal in order to maintain a constant phase relationship with each other. The difference is that the waveform and input timing of the start pulse differ according to the function assigned to each V scanner.

  FIG. 6 is a circuit diagram showing a configuration example of a V scanner having an upside down function. As described above, the V scanner has a multistage connection of shift registers (SR), and sequentially shifts the start pulse in accordance with the clock signal and outputs the control signal VSCAN (i) for each stage.

  FIG. 6 shows a rolling operation from top to bottom. Each stage of the shift register is provided with a rolling input terminal IN and a rolling output terminal OUT. By switching the connection between the rolling input terminal IN and the rolling output terminal OUT of each stage with a switch, it is possible to switch the rolling from the top to the bottom and the rolling from the bottom to the top. For this purpose, a switch for switching is attached to each stage of the shift register. These switches are on / off controlled by an upside down signal supplied from the outside. When the up / down inversion signal is at the high level Hi, each switch is connected so that the start pulse rolls from top to bottom. For example, the start pulse input to the i-th stage SR is output from the output terminal OUT in synchronization with the clock signal, and is transferred to the input terminal IN of the next line i + 1. The start pulse output from the output terminal OUT again in synchronization with the clock signal is further supplied to the SR input terminal IN of the next line i + 2. In this way, the control signals VSCAN (i), (i + 1), (i + 2),... Are output while the start pulse sequentially rolls from the upper stage side to the lower stage side of the shift register.

  FIG. 7 also shows the rolling operation of the shift register, in which the start pulse rolls from bottom to top. At this time, the upside down signal becomes low level (Lo), and the rolling path of the star and the pulse is switched. In the rolling from the bottom to the top, the start pulse is input not to the uppermost stage of the shift register but to the lowermost stage, and rolls upward from here. For example, the signal input to the SR of the i + 4 line is output with a delay of one clock and supplied to the SR input terminal of the next line i + 3. Here, the signal is output with a delay of one horizontal period, and is further moved to the SR of the previous line i + 2.

  FIG. 8 is a schematic diagram for explaining the operation of the scanner unit of the image display apparatus shown in FIG. In this example, the rolling direction of each V scanner is switched while an image is displayed on the pixel array section. That is, when the upside down signal input to the scanner unit is switched from the high level to the low level, the rolling direction of the V scanner is switched from the forward rolling from the top to the bottom to the reverse running direction from the bottom to the top. . During this time, the V scanner 1, V scanner 2, V scanner 3 and the like constituting the scanner unit are always in an operating state (active) in accordance with the clock signal and performing a rolling operation. During the rolling operation of each V scanner, the rolling path is switched by the upside down signal, thereby switching the forward rolling and the backward rolling.

  However, at the time of reversing to switch the rolling direction, if no measures are taken, the phase relationship of the control signals sequentially output from the V scanner 1, V scanner 2 and V scanner 3 may become inconsistent, and screen abnormalities such as flushing may occur. There is.

  FIG. 9 is a timing chart showing measures taken against the screen abnormality that occurs during the above-described reversing operation. In order to facilitate understanding, the same notation as in FIG. 8 is adopted. As can be seen from the figure, when an inversion operation is performed by changing the level of an upside down signal while an image is displayed on the pixel array section, the V scanner 1, V scanner 2 and V scanner are within one field before and after the inversion operation. At least one of 3 is reset. In this embodiment, all V scanners 1, 2, 3 are reset. For this purpose, a reset signal is input to each of the V scanners 1, 2, and 3 at the same timing. By this reset signal, each of the V scanners 1, 2, and 3 in the active state is reset once, and then the rolling operation is started again from the head. By resetting in this way, the logical state of each stage of the shift register constituting the V scanner is reset so that phase mismatch between the V scanners 1, 2, and 3 does not occur due to the inversion operation. Yes. After all of the V scanners 1, 2, and 3 are initialized by reset, a display operation according to a predetermined sequence can be performed by starting a rolling operation again.

  FIG. 10 is a schematic diagram showing the most preferable timing when resetting is performed. If the reset timing is inappropriate, it may still cause a screen abnormality. As described above, the drive timing of each pixel incorporating the threshold voltage correction function is generally “correction period”, “data writing period”, and “light emission period” for each line. Therefore, it is appropriate to reset before the correction period. In addition, resetting too early can cause image quality degradation, so resetting during the 10 horizontal periods immediately before the correction period minimizes image quality degradation due to screen reset while preventing abnormalities such as screen flashing during inversion. It is possible to suppress it.

  FIG. 11 is a circuit diagram showing a configuration example of a V scanner incorporated in the image display apparatus according to the present invention. This V scanner has an upside down function and a reset function. Each stage of the shift register constituting the V scanner includes a reset terminal in addition to an output terminal for the pixel, a rolling pulse input terminal and a rolling output terminal. A V scanner reset signal is externally supplied to a reset terminal (reset) at each stage of the shift register. This V scanner reset signal is input in synchronization with the switching of the upside down signal, and the shift register is reset once.

  FIG. 12 is a schematic timing chart showing another embodiment of the image display apparatus according to the present invention. In order to facilitate understanding, the same notation as the previous timing chart shown in FIG. 9 is adopted. The difference is that the previous embodiment shown in FIG. 9 resets each V scanner at the time of inversion, whereas this embodiment forcibly turns off the output of the V scanner 2 at the time of inversion. The screen display can be stopped by forcibly turning off the output of the V scanner 2 that controls light emission and non-light emission of the light emitting element included in each pixel. This prevents screen abnormalities such as flashes from being visually recognized. Note that when the V scanner 2 is forcibly turned off, the screen is displayed in black, and if this is over a long period of time, it may be mistaken for a screen abnormality. On the other hand, when the V scanner operates for one field period after being inverted, all the transfer data of the shift register constituting the V scanner is normally refreshed with the inverted data. Therefore, the forced OFF period of the V scanner 2 may be within one field after inversion. As a result, it is possible to prevent screen abnormality at the time of inversion while minimizing image quality deterioration due to screen non-display (black display).

  FIG. 13 is a schematic circuit diagram showing a configuration example of the V scanner 2 that realizes the embodiment shown in FIG. As shown in the figure, the V scanner 2 includes a shift register SR, and includes an output terminal for pixels, a rolling input terminal IN, and a rolling output terminal OUT. A switch for switching the rolling path is attached to the rolling input terminal IN and the rolling output terminal OUT of each stage. This switch is switched by an upside down signal. An AND gate element is attached to each stage of the shift register SR, and the opening and closing of the gate is controlled by a forced OFF signal of the V scanner 2. In this way, the V scanner 2 performs the inversion operation with the shift register SR that sequentially generates the second control signals VSCAN2 (i), VSCAN2 (i + 1), VSCAN2 (i + 2). While maintaining the generation of the second control signal VSCAN2 by the shift register SR, the output of the V skinner 2 is forcibly turned off by masking the generated second control signal VSCAN2. As described above, all the internal data of the shift register is refreshed to the inverted data in one field period after the V scanner is inverted. Therefore, the forced OFF period of the V scanner 2 may be within one field after inversion. Therefore, even when the V scanner 2 is forcibly turned off, the shift register SR of the V scanner 2 needs to be operated as usual. Therefore, as shown in FIG. 13, the circuit configuration of the V scanner 2 is forcibly turned off by masking the output of each stage of the shift register SR while performing the rolling operation as usual in the shift register SR.

1 is a block diagram showing an overall configuration of an image display device according to the present invention. FIG. 2 is a circuit diagram illustrating a general configuration example of a pixel incorporated in the image display device illustrated in FIG. 1. FIG. 6 is a circuit diagram and a timing chart showing a specific configuration example of a pixel. It is a schematic diagram with which operation | movement description of an image display apparatus is provided. 3 is a schematic timing chart showing the reversal operation of the image display device. It is a circuit diagram which shows the structure of the scanner which has an inversion function. It is a circuit diagram of the scanner which similarly has an inversion function. It is a timing chart which shows the upside down operation | movement of an image display apparatus. It is a timing chart which shows 1st Embodiment of the image display apparatus concerning this invention. It is a schematic diagram which similarly shows 1st Embodiment. It is a circuit block diagram of the V scanner similarly used for 1st Embodiment. It is a timing chart which shows 2nd Embodiment of the image display apparatus concerning this invention. It is a circuit diagram which shows the structural example of the V scanner used for 2nd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Pixel array part, 2 ... Pixel, 3 ... 1st scanner (V scanner 1), 4 ... 2nd scanner (V scanner 2), 5 ... 3rd scanner (V scanner) 3), 6 ... H driver

Claims (7)

It consists of a pixel array part and a peripheral circuit part that drives it,
The pixel array unit includes a row-shaped scanning line, a column-shaped signal line, and pixels arranged in a matrix at a portion where each scanning line and each signal line intersect,
The peripheral circuit section supplies a control signal to each scanning line in order to perform line sequential scanning of the pixel array section over one field, and supplies a video signal to each signal line in accordance with the line sequential scanning. And a driver for displaying an image on the pixel array unit,
Each pixel includes at least a sampling transistor, a drive transistor, a switching transistor, a correction transistor, and a light emitting element.
The sampling transistor conducts in response to a first control signal supplied from a first scanning line and samples a video signal supplied from the signal line,
The drive transistor supplies an output current corresponding to the sampled video signal to the light emitting element,
The light emitting element emits light with a luminance corresponding to the video signal by an output current supplied from the drive transistor,
The switching transistor is arranged in a current path through which the output current flows, and is turned on according to a time width of a second control signal supplied from the second scanning line, and supplies the output current to the light emitting element. The light emitting element emits light only during the light emission period according to the time width,
The correction transistor operates in a predetermined correction period according to a third control signal supplied from the third scanning line, and performs a correction operation of the drive transistor in cooperation with the sampling transistor or the switching transistor.
The scanner unit includes at least a first scanner that supplies a first control signal to the first scan line, a second scanner that supplies a second control signal to the second scan line, and a second scanner that supplies a second control signal to the second scan line. Divided into a third scanner that supplies three control signals,
The scanner unit can perform a reversing operation in which the line sequential scanning direction of the pixel array unit is switched to display an image upside down. When performing a reversing operation while displaying an image on the pixel array unit, An image display apparatus comprising: resetting at least one of the first scanner, the second scanner, and the third scanner within one field before and after. The correction transistor performs a correction operation for canceling variations in the threshold voltage of the drive transistor in a correction period preceding the light emission period;
The scanner unit resets all of the first scanner, the second scanner, and the third scanner within one field before and after the reversal operation,
2. The image display according to claim 1, wherein the third scanner performs a reset within 10 horizontal periods immediately before applying the third control signal to the first third scanning line of the pixel array unit. apparatus.   The image display apparatus according to claim 1, wherein the light emitting element is an organic electroluminescence element. It consists of a pixel array part and a peripheral circuit part that drives it,
The pixel array unit includes a row-shaped scanning line, a column-shaped signal line, and pixels arranged in a matrix at a portion where each scanning line and each signal line intersect,
The peripheral circuit section supplies a control signal to each scanning line in order to perform line sequential scanning of the pixel array section over one field, and supplies a video signal to each signal line in accordance with the line sequential scanning. And a driver for displaying an image on the pixel array unit,
Each pixel includes at least a sampling transistor, a drive transistor, a switching transistor, a correction transistor, and a light emitting element.
The sampling transistor conducts in response to a first control signal supplied from a first scanning line and samples a video signal supplied from the signal line,
The drive transistor supplies an output current corresponding to the sampled video signal to the light emitting element,
The light emitting element emits light with a luminance corresponding to the video signal by an output current supplied from the drive transistor,
The switching transistor is arranged in a current path through which the output current flows, and is turned on according to a time width of a second control signal supplied from the second scanning line, and supplies the output current to the light emitting element. The light emitting element emits light only during the light emission period according to the time width,
The correction transistor operates in a predetermined correction period according to a third control signal supplied from the third scanning line, and performs a correction operation of the drive transistor in cooperation with the sampling transistor or the switching transistor.
The scanner unit includes at least a first scanner that supplies a first control signal to the first scan line, a second scanner that supplies a second control signal to the second scan line, and a second scanner that supplies a second control signal to the second scan line. Divided into a third scanner that supplies three control signals,
The scanner unit can perform a reversing operation of switching the line sequential scanning direction of the pixel array unit to display an image upside down. When performing the reversing operation while displaying an image on the pixel array unit, An image display device characterized in that the output of the scanner is turned off, all the light emitting elements included in each pixel are in a non-light emitting state, and the pixel array portion is displayed in black.   The image display device according to claim 4, wherein the scanner unit turns off the output of the second scanner and displays the pixel array unit in black within one field immediately after the inversion operation.   The second scanner sequentially generates the second control signal in accordance with the line sequential scanning, and when performing the inversion operation, the second scanner generates the second control signal while maintaining the generation of the second control signal as it is. 5. The image display apparatus according to claim 4, wherein the output of the second scanner is forcibly turned off by masking the two control signals. The image display apparatus according to claim 4, wherein the light emitting element is an organic electroluminescence element.

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