JP2007226308A - Interface circuit and storage controller therewith - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an interface circuit capable of taking in data effectively for a certain period of time by eliminating delay time until a strobe signal output from a delay circuit reaches a flip-flop and changes in the delay time. <P>SOLUTION: The interface circuit includes a plurality of data delay circuit parts for outputting corresponding data input from the outside, each with a delay of a first predetermined delay time; a strobe signal delay circuit part for outputting strobe signals with a delay of a second predetermined delay time; and a plurality of latch circuit parts for taking in the output data of the corresponding data delay circuit parts in synchronism with the output signals of the strobe signal delay circuit part. The latch circuit parts are each arranged so that data transmission time from each corresponding data delay circuit part to each latch circuit part equals the signal transmission time from the strobe signal delay circuit part to each latch circuit part. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an interface circuit that captures data output from a storage device in synchronization with a strobe signal output together with the data, and a storage control device including the interface circuit.

  As a data interface method between devices, based on a method of transmitting and receiving data in synchronization with the clock using a single clock whose phase is controlled between devices, and a strobe signal output from the transmitting device by the receiving device There is a method to capture the data inside. Examples of the latter data interface include ultra DMA in a hard disk, DDR (double data rate) -SDRAM, and DDR2-SDRAM. Among these interfaces, even in the case of Ultra DMA, even if it is Ultra DMA 100, the frequency of the strobe signal is 50 MHz at the maximum. Therefore, it is difficult to receive data in an ASIC (Application Specific Integrated Circuit) design with a hard disk interface. Absent. However, in the case of DDR-SDRAM, data must be received in synchronization with a high-speed strobe signal such as 400 MHz or 266 MHz, and the timing specification of the strobe signal and data is strict. If this mechanism is not used, it is difficult to receive data. Furthermore, in the case of a DDR2-SDRAM, since data must be received in synchronization with a strobe signal of 400 MHz or higher, it becomes more difficult to receive data.

  As a technique for solving the above problem, for example, a technique using a DLL (Delay Locked Loop) as described in Non-Patent Document 1 is known. FIG. 11 shows a configuration example of the interface circuit 101 of the data receiving device using this method. As shown in FIG. 11, in the DLL circuit 102, the delay circuit 103 delays the clock signal CK0 input from the outside of the DLL circuit 102 by a time equal to the period of the clock signal CK0, and thereby a phase comparator. To 104. The phase comparator 104 compares the phase of the clock signal CK0 with the phase of the clock signal that has passed through the delay circuit 103, and outputs the comparison result. The delay control circuit 105 calculates the delay setting value Av corresponding to the delay time equal to the cycle of the clock signal CK0 from the comparison result, and outputs the delay setting value Av to the delay circuit 103 and the delay setting value calculation circuit 106, respectively. The delay setting value calculation circuit 106 calculates a delay setting value Bv for delaying the strobe signal DQS00 from the delay setting value Av calculated by the delay control circuit 105 and the gear ratio setting value GV0 given from the outside. Output to the delay circuit 107. The delay circuit 107 delays the input strobe signal DQS00 based on the delay setting value Bv output from the delay setting value calculation circuit 106, and outputs the delayed strobe signal DQS01 as a corrected strobe signal DQS01. The correction strobe signal DQS01 is input to the plurality of flip-flops FF00 to FF03 via the buffers 108 to 110, respectively.

  Here, if the gear ratio set value GV0 is 45%, for example, the delay set value calculation circuit 106 sets the delay value corresponding to 45% of the delay time of the cycle of the clock signal CK0 as the delay set value Bv, and the delay circuit 107. Set to. The delay circuit 107 delays the input strobe signal DQS00 by the delay value and outputs the delayed signal. The above description is based on the premise that the delay circuits 103 and 107 are delay circuits having the same configuration. These delay circuits 103 and 107 are provided with a delay value even if the gear ratio set value GV0 is 0%. The minimum delay circuits Md00 to Md03 have the same delay value as the delay values of the delay circuits 103 and 107 when the gear ratio set value GV0 is 0%.

  Hereinafter, the operation of the interface circuit 101 will be described. In the following, in order to clarify the delay caused by the delay circuit 107, the delay by the buffer from each data input terminal T00 to T03 to each minimum delay circuit Md00 to Md03, and from the strobe signal input terminal ST0 to the delay circuit 107 is explained. Buffer delay is not taken into account. FIG. 12 is a timing chart for explaining the reception timing of each data DQ00 to DQ03 when the gear ratio set value GV0 is 25% in the interface circuit 101 of FIG. As shown in FIG. 12, the delay circuit 107 delays the strobe signal DQS00 by a delay time td corresponding to 25% of the cycle tckw of the clock signal CK0 and outputs the delayed signal.

  Next, the overall operation of the interface circuit 101 shown in FIG. 11 will be described with reference to FIG. FIG. 13A shows an ideal operation timing of the interface circuit 101. As shown in FIG. 13A, each data DQ00 to DQ03 is input from the corresponding terminals T00 to T03 until it reaches the flip-flops FF00 to FF03 via the minimum delay circuits Md00 to Md03. Delay by time TDD. The strobe signal DQS00 is delayed by the time TD1 by the delay circuit 107. Here, the delay circuit 107 includes a plurality of partial delay elements that respectively delay the input signal by a predetermined unit time, and the delay time of the strobe signal DQS00 is determined by the number of partial delay elements through which the strobe signal DQS00 has passed. With such a configuration, the jitter J1 exists in the strobe signal DQS01 obtained by delaying the strobe signal DQS00.

In the ASIC design, the delay time TDD needs to be constant between the plurality of data DQ00 to DQ03. Therefore, in the conventional interface circuit 101, as shown in FIG. 11, the flip-flops FF00 to FF03 are arranged in the vicinity of the corresponding minimum delay circuits Md00 to Md03 so that there is no difference in the delay time TDD. It was. In addition, clock tree synthesis is performed between the delay circuit 107 and each of the flip-flops FF00 to FF03 so that the skew of the strobe signal DQS01 is reduced.
“DDR SDRAM Functionality and Controller Read Data Capture”, Micro Design Line, vol. 8, Issue. 3,3Q99

  However, the conventional interface circuit 101 has a problem in that the distance from the delay circuit 107 to each of the flip-flops FF00 to FF03 becomes longer and the strobe signal DQS01 is delayed. In addition, the delay time of the signal from the delay circuit 107 to each of the flip-flops FF00 to FF03 has a problem that it largely fluctuates due to temperature and voltage fluctuations. FIG. 13B shows the actual operation timing of the interface circuit 101. In FIG. 13B, the delay time of the strobe signal DQS01 from the delay circuit 107 to each of the flip-flops FF00 to FF03 is represented by “Tc”, and the variation amount of the delay time is represented by “J2”. . The strobe signal DQS02 indicates the strobe signal immediately before being input to the clock terminals of the flip-flops FF00 to FF03.

  Here, when FIGS. 13A and 13B are compared, at the ideal operation timing shown in FIG. 13A, the margin is “M1A” and “M1B” with respect to the effective data window TDW. In contrast, in the actual operation timing shown in FIG. 13B, the margins are “M2A” and “M2B”. That is, the actual interface circuit 101 has a problem that the margin balance with respect to the data window TDW is deteriorated and the margin on one side becomes extremely small. As described above, when the balance of the margin is deteriorated, there is a problem that a period during which each data DQ00 to DQ03 can be effectively taken in synchronization with the strobe signal DQS02 is reduced.

  The present invention solves the above-described problems, and can effectively capture data for a certain period by eliminating the delay time until the strobe signal output from the delay circuit reaches the flip-prop and its fluctuation amount. An object of the present invention is to provide an interface circuit and a storage control device including such an interface circuit.

  The interface circuit according to the present invention is an interface circuit that takes in a plurality of data input from the outside in synchronization with a strobe signal input together with each data. The interface circuit includes a plurality of data delay circuit units that output the respective corresponding data delayed by a predetermined first delay time, and delay the strobe signal by a predetermined second delay time. A strobe signal delay circuit unit for outputting, and a plurality of latch circuit units for capturing the output data of the corresponding data delay circuit units in synchronization with the output signal of the strobe signal delay circuit unit. Each latch circuit unit has a data transmission time from the corresponding data delay circuit unit to the latch circuit unit, and a signal transmission time from the strobe signal delay circuit unit to the latch circuit unit. They are arranged to be equal to each other. Hereinafter, this interface circuit is referred to as a “first interface circuit”.

  Preferably, in the first interface circuit, the strobe signal delay circuit unit receives either the input strobe signal or the reference clock signal in accordance with a first control signal input from the outside. A selection circuit unit that selects and outputs the output signal, a first delay circuit unit that outputs the output signal of the selection circuit unit with a delay by the first delay time, and the reference circuit unit that outputs the reference signal When the clock signal is output, a DLL circuit unit is provided that outputs the reference clock signal with a delay so that the phase of the reference clock signal coincides with the output signal of the first delay circuit unit. When the reference clock signal is output from the selection circuit unit, the DLL circuit unit has a difference between a delay time of the reference clock signal and a delay time by the first delay circuit unit as the reference clock signal. The delay time of the reference clock signal is controlled so as to be equal to the signal cycle, and when the strobe signal is output from the selection circuit unit, the strobe signal is set to the delay time of the reference clock signal. Output after delaying by equal time. Hereinafter, this interface circuit is referred to as a “second interface circuit”.

Preferably, in the first interface circuit, the strobe signal delay circuit unit receives either the input strobe signal or the reference clock signal in accordance with a first control signal input from the outside. A selection circuit unit that selects and outputs the output signal, a first delay circuit unit that outputs the output signal of the selection circuit unit with a delay by the first delay time, and the reference circuit unit that outputs the reference signal When the clock signal is output, a DLL circuit unit is provided that outputs the reference clock signal with a delay so that the phase of the reference clock signal coincides with the output signal of the first delay circuit unit. When the reference clock signal is output from the selection circuit unit, the DLL circuit unit has a difference between a delay time of the reference clock signal and a delay time by the first delay circuit unit as the reference clock signal. The delay time of the reference clock signal is controlled so as to be equal to the period of the signal. When the strobe signal is output from the selection circuit unit, the strobe signal is set to the delay time of the reference clock signal. The output is delayed by a time equal to a predetermined fraction. Hereinafter, this interface circuit is referred to as a “third interface circuit”.

Preferably, in the first interface circuit, the strobe signal delay circuit unit receives either the input strobe signal or the reference clock signal in accordance with a first control signal input from the outside. A selection circuit unit that selects and outputs the output signal, a first delay circuit unit that outputs the output signal of the selection circuit unit with a delay by the first delay time, and the reference circuit unit that outputs the reference signal When the clock signal is output, a DLL circuit unit is provided that outputs the reference clock signal with a delay so that the phase of the reference clock signal coincides with the output signal of the first delay circuit unit. When the reference clock signal is output from the selection circuit unit, the DLL circuit unit has a difference between a delay time of the reference clock signal and a delay time by the first delay circuit unit as the reference clock signal. The delay time of the reference clock signal is controlled so as to be equal to the period of the signal, and when the strobe signal is output from the selection circuit unit, the strobe signal is set to the delay time of the reference clock signal. The output is delayed by a time increased or decreased at a predetermined rate. Hereinafter, this interface circuit is referred to as a “fourth interface circuit”.

  Preferably, in the second interface circuit, the DLL circuit unit delays the output signal of the selection circuit unit by a set delay time and outputs the second delay circuit unit, and the selection When the reference clock signal is output from the circuit unit, the phase difference detection circuit unit that detects and outputs the phase difference between the output signals of the first and second delay circuit units, and the selection circuit unit When the reference clock signal is output, the second delay circuit unit includes a delay control circuit unit that controls a delay time so that the phase difference is eliminated. Hereinafter, this interface circuit is referred to as a “fifth interface circuit”.

  Preferably, in the third interface circuit, the DLL circuit unit delays the output signal of the selection circuit unit by a set delay time and outputs the second delay circuit unit, and the selection When the reference clock signal is output from the circuit unit, the phase difference detection circuit unit that detects and outputs the phase difference between the output signals of the first and second delay circuit units, and the selection circuit unit When the reference clock signal is output, the delay time is controlled so as to eliminate the phase difference with respect to the second delay circuit unit, and the strobe signal is output from the selection circuit unit. A delay control circuit unit that sets a delay time of the second delay circuit unit to a predetermined fraction of the delay time. Hereinafter, this interface circuit is referred to as a “sixth interface circuit”.

  Preferably, in the fourth interface circuit, the DLL circuit unit delays an output signal of the selection circuit unit by a set delay time and outputs the second delay circuit unit, and the selection When the reference clock signal is output from the circuit unit, the phase difference detection circuit unit that detects and outputs the phase difference between the output signals of the first and second delay circuit units, and the selection circuit unit When the reference clock signal is output, the delay time is controlled so as to eliminate the phase difference with respect to the second delay circuit unit, and the strobe signal is output from the selection circuit unit. And a delay control circuit unit that sets the delay time of the second delay circuit unit to a time obtained by increasing or decreasing the delay time at a predetermined rate. Hereinafter, this interface circuit is referred to as a “seventh interface circuit”.

  Preferably, in the seventh interface circuit, the delay control circuit unit changes the ratio according to a second control signal input from the outside.

  Preferably, in the first interface circuit, the strobe signal is composed of a pair of signals forming a differential signal, and the strobe signal delay circuit unit outputs one signal corresponding to the differential signal. Each of the latch circuit units includes two latch circuits that respectively capture output data of the corresponding data delay circuit units. Each of the latch circuits takes in the output data of the corresponding data delay circuit unit in synchronization with the output signal of the corresponding signal delay circuit unit.

  The storage control device according to the present invention includes an interface circuit that takes in a plurality of data output from the storage device based on a strobe signal output together with each data. The interface circuit delays the corresponding strobe signal by a predetermined second delay time and a plurality of data delay circuit sections that output the corresponding data by delaying the data by a predetermined first delay time, respectively. Output strobe signal delay circuit units, and a plurality of latch circuit units that capture the output data of the corresponding data delay circuit units in synchronization with the output signals of the strobe signal delay circuit units. Each latch circuit unit has a data transmission time from the corresponding data delay circuit unit to the latch circuit unit, and a signal transmission time from the strobe signal delay circuit unit to the latch circuit unit. They are arranged to be equal to each other.

  According to the interface circuit of the present invention, each latch circuit unit transmits the data transmission time from each corresponding data delay circuit unit to each latch circuit unit, and signal transmission from the strobe signal delay circuit unit to each latch circuit unit. Since the time is arranged to be equal to each other, there is no delay time of the strobe signal output from the strobe signal delay circuit unit for each data output from each corresponding data delay circuit unit. be able to. That is, when each latch circuit unit fetches data, the delay time for the strobe signal data is held at the time set by the strobe signal delay circuit unit, so that the delay time is appropriately set by the strobe signal delay circuit unit. By setting to, data can be fetched effectively for a certain period in the latch circuit portion.

Embodiments of the present invention will be described below with reference to the accompanying drawings.
(Embodiment 1)
First, the interface circuit according to the first embodiment of the present invention will be described. In the following description, the case where the data input to the interface circuit is 8 bits and the strobe signal is a pair of differential signals will be described as an example. FIG. 1 shows a configuration example of an interface circuit according to the first embodiment. As shown in FIG. 1, the interface circuit 1 according to the first embodiment includes eight data input terminals T0 to T7 equal to the number of input data DQ0 to DQ7, eight data delay circuits Md0 to Md7, , Eight latch circuit units DT0 to DT7, a pair of differential signals DQS0 and DQSB0 forming a strobe signal, strobe signal input terminals ST1 and ST2, a strobe signal delay circuit unit SSD, and a plurality of buffers Bf00, Bf01, Bf1 to Bf4, and Bf70 to Bf72. In FIG. 1, only the configuration related to the data DQ0 and DQ7 is shown for simplicity of illustration, and the configuration related to the data DQ1 to DQ6 is omitted. The strobe signal delay circuit unit SSD is composed of two signal delay circuit units SD1 and SD2 to which differential signals DQS0 and DQSB0 are input via a buffer Bf1 and the like, respectively. Each latch circuit portion DT0 to DT7 includes two flip-flops. Here, the latch circuit units DT0 to DT7 have the same configuration, so that the latch circuit unit DT0 will be described as an example. The latch circuit unit DT0 includes two flip-flops FF01 and FF02. The data delay circuits Md0 to Md7 each constitute a data delay circuit section, and each flip-flop FF01, FF02, FF11, FF12, FF21, FF22, FF31, FF32, FF41, FF42, FF51, FF52, FF61, FF62, FF71. , FF72 form a latch circuit.

  The data DQ0 to DQ7 input to the corresponding data input terminals T0 to T7 are input to the data delay circuits Md0 to Md7 via the corresponding buffers Bf00 to Bf70, respectively. The data delay circuits Md0 to Md7 delay the respective corresponding data DQ0 to DQ7 input for a predetermined time and output them. Here, since the configuration of each of the data delay circuits Md0 to Md7 is the same, an explanation will be given of an arbitrary data delay circuit Mdk (k = 0 to 7). The data delay circuit Mdk receives the input data DQk as a predetermined value. Delayed in time and output to the data terminals D of the flip-flops FFk1 and FFk2, respectively. In the interface circuit 1 shown in FIG. 1, the data input terminals T0 to T7, the buffers Bf00 to Bf70, and the data delay circuits Md0 to Md7 have the same arrangement relationship for all the data DQ0 to DQ7. Therefore, the delay times generated from when the data DQ0 to DQ7 are input to the corresponding data input terminals T0 to T7 until they reach the data delay circuits Md0 to Md7 are all the same.

  The differential signals DQS0 and DQSB0 input to the strobe signal input terminals ST1 and ST2 are input to the strobe signal delay circuit unit SSD via the buffer Bf1, respectively. At this time, the signal DQS0 is input to the buffer Bf1, and the signal DQSB0 is inverted and input. The output signal DQS1 of the buffer Bf1 is input to the signal delay circuit unit SD1, and is inverted by the inverter Iv and input to the delay circuit unit SD2 as the signal DQSB1. The signal delay circuit section SD1 delays the input signal DQS1 and outputs it to the clock terminals of the flip-flops FF01, FF11, FF21, FF31, FF41, FF51, FF61, and FF71, respectively. The signal delay circuit unit SD2 delays the input signal DQSB1 and outputs the delayed signal to the clock terminals of the flip-flops FF02, FF12, FF22, FF32, FF42, FF52, FF62, and FF72. Arbitrary flip-flops FFk1 and FFk2 output data DQk output from data delay circuit Mdk based on strobe signals DQS2 and DQSB2 output from corresponding signal delay circuit sections SD1 and SD2, respectively. The configuration and operation of each signal delay circuit unit SD1, SD2 will be described in detail later.

  The flip-flop FFk1 is arranged so that the data transmission time from the data delay circuit Mdk to the flip-flop FFk1 is equal to the signal transmission time from the signal delay circuit unit SD1 to the flip-flop FFk1. The flip-flop FFk2 is arranged so that the data transmission time from the data delay circuit Mdk to the flip-flop FFk2 is equal to the signal transmission time from the signal delay circuit unit SD2 to the flip-flop FFk2. Further, when the data transmission time and the signal transmission time are long, the wiring path from the data delay circuit Mdk to each flip-flop FFk1, FFk2, and from each signal delay circuit unit SD1, SD2 to each corresponding flip-flop FFk1, FFk2. The same buffer may be arranged in each of the wiring paths. For example, in FIG. 1, a buffer Bf72 is arranged in the wiring path from the data delay circuit Md7 to each of the flip-flops FF71 and FF72, and the wiring path from each of the signal delay circuit units SD1 and SD2 to each of the flip-flops FF71 and FF72. Corresponding buffers Bf3 and Bf4 are respectively arranged. These buffers Bf3, Bf4, and Bf72 are all the same. Buffers such as buffers Bf3, Bf4, and Bf72 arranged in the wiring path may be appropriately arranged as necessary. The wiring path from the data delay element Mdk to each of the flip-flops FFk1 and FFk2, and the strobe signal delay A buffer may or may not be arranged in the wiring path from the circuit unit SSD to each of the flip-flops FFk1 and FFk2.

  Next, the signal delay circuit units SD1 and SD2 constituting the strobe signal delay circuit unit SSD will be described. Since the signal delay circuit units SD1 and SD2 have the same configuration, the configuration of the signal delay circuit unit SD1 will be described below as an example. FIG. 2 shows a configuration example of the signal delay circuit unit SD1. As shown in FIG. 2, the signal delay circuit unit SD1 includes a multiplexer (hereinafter referred to as “MUX”) 11, a first delay circuit 12, a second delay circuit 13, a phase comparator 14, a delay control circuit 15, and Five buffers 16 to 20 are provided. The MUX 11 forms a selection circuit unit. The second delay circuit 13, the phase comparator 14, and the delay control circuit 15 form a DLL circuit unit.

  A reference clock RCK and a strobe signal DQS1 are input to the MUX 11, and a correction mode signal CMS is input as a switching signal. The MUX 11 selects either the reference clock RCK or the strobe signal DQS 1 based on the correction mode signal CMS, and outputs the selected clock to the first delay circuit 12 and the second delay circuit 13. Specifically, the MUX 11 selects the reference clock RCK in the correction mode in which the correction mode signal CMS is active, and selects the strobe signal DQS1 in the normal mode in which the correction mode signal CMS is inactive.

  The first delay circuit 12 delays the reference clock RCK or the strobe signal DQS1 input from the MUX 11 by a predetermined delay time, and outputs the delayed signal to the phase comparator 14 via the buffer 16 and the buffer 17. Here, the delay time by the first delay circuit 12 is the same as the delay time by the data delay circuits Md0 to Md7 shown in FIG. On the other hand, the second delay circuit 13 delays the reference clock RCK or the strobe signal DQS1 input from the MUX 11 by a set delay time, and outputs it to the phase comparator 14 via the buffer 18 and the buffer 19. The data is output to the latch circuit units DT0 to DT7 via the buffer 18 and the buffer 20, respectively.

  The output signal of the first delay circuit 12 via the buffers 16 and 17 and the output signal of the second delay circuit 13 via the buffers 18 and 19 are input to the phase comparator 14. The phase comparator 14 compares the phases of these input signals to detect a phase difference, and outputs the detection result to the delay control circuit 15. The delay control circuit 15 controls the delay time of the second delay circuit 13 based on the phase difference detected by the phase comparator 14 so that the phase difference is eliminated. For example, the delay control circuit 15 outputs the phase difference signal Sg indicating the phase difference to the second delay circuit 13.

  FIG. 3 is a circuit diagram showing a configuration example of the second delay circuit 13. As illustrated in FIG. 3, the second delay circuit 13 includes a plurality of delay elements M <b> 0 to Mp (p is a positive integer) and a selection circuit 22. The selection circuit 22 selects output signals from one or more delay elements M0 to Mp according to the phase difference signal Sg.

  Further, the phase comparator 14 compares the output signal of the first delay circuit 12 and the output signal of the second delay circuit 13 to determine which signal is advanced, and the delay control circuit 15 The second delay circuit 13 may be controlled according to the determination result. That is, when the phase comparator 14 determines that the phase of the output signal of the first delay circuit 12 is more advanced than that of the output signal of the second delay circuit 13, the delay control circuit 15 causes the second delay circuit 13 to In contrast, the number of delay elements M0 to Mp through which the signal input to the second delay circuit 13 passes is controlled to increase by one, and the output signal of the second delay circuit 13 is output by the phase comparator 14. When it is determined that the phase is ahead of the output signal of the first delay circuit 12, the number of delay elements M0 to Mp through which the input signal passes is decreased by one with respect to the second delay circuit 13. You may control as follows.

  Next, the operation of the signal delay circuit unit SD1 shown in FIG. 2 will be described. Note that, in order to clarify the operations of the first delay circuit 12 and the DLL circuit unit, it is assumed that the buffers 16 to 20 do not exist. FIG. 4 is a timing chart for explaining the operation of the signal delay circuit unit SD1 when the reference clock RCK is selected by the MUX 11. FIG. 4 shows a reference clock Rck1 immediately after being output from the MUX 11, a reference clock Rck2 immediately before being input to the phase comparator 14 via the first delay circuit 12, and an input to the phase comparator 14 via the second delay circuit 13. Each waveform of the reference clock Rck3 immediately before the start is shown. Here, the reference clocks Rck3a, Rck3b, and Rck3c are all the reference clock Rck3 immediately before being input to the phase comparator 14 via the second delay circuit 13, but are set for the second delay circuit 13. The delay time is different. The timing difference between the two reference clocks Rck1 and Rck2 indicates the delay time tDmin by the first delay circuit 12.

  The delay time by the second delay circuit 13 is set to the minimum unit time or a time close to the minimum unit time in the initial state. The reference clock Rck3a shows the waveform of the reference clock Rck3 in such an initial state. When the initial setting of the delay time for the second delay circuit 13 is the minimum unit time, that is, when the same delay time is set in the second delay circuit 13 and the first delay circuit 12, two reference clocks Rck2, Rck3a This timing difference is caused by the reference clock RCK passing through the selection circuit 22 shown in FIG. At this time, the delay control circuit 15 controls the second delay circuit 42 in the initial state to increase the delay time. In this case, the reference clock Rck3 immediately before being input to the phase comparator 14 changes from the reference clock Rck3a to the reference clock Rck3b.

  When the reference clock Rck3 is delayed from the reference clock Rck3c, the delay control circuit 15 controls the second delay circuit 13 so as to reduce the delay time. Thereafter, the delay control circuit 15 controls the delay time by the second delay circuit 13 so that the edges of the signals input to the phase comparator 14 coincide. In such a case, the time tDlock shown in FIG. 4 matches the cycle of the reference clock RCK.

Also, as shown in FIG. 2, the output end point of the MUX 11, the output end point of the first delay circuit 12, one input end point of the phase comparator 14, the output end point of the second delay circuit 13, and the phase comparison When the other input end points of the device 14 are points A to E, the following equation is established.
(Delay time from point A to point B (minimum unit delay time)) + (delay time from point B to point C) + one cycle of reference clock RCK) = (delay time from point A to point D) + (point D ~ Delay time by point E)
Here, by arranging the first delay circuit 12, the second delay circuit 13, the phase comparator 14, the buffer and the like at appropriate locations, (delay time from point B to point C) = (point D to point) E delay time) is realized.

  Further, the delay time due to the wiring path from the I / O pad constituting each data input terminal T0 to T7 of FIG. 1 to the corresponding data delay circuit Md0 to Md7, and the I / O pad constituting the strobe signal input terminal ST1. The elements on the respective wiring paths are arranged so that the delay times due to the wiring paths from to the signal delay circuit unit SD1 are equal. According to the interface circuit 1 according to the first embodiment, the delay time caused by the wiring path from the data delay circuit Mdk to each of the flip-flops FFk1, FFk2, and the wiring from the signal delay circuit unit SD1 to each of the flip-flops FFk1, FFk2. Since the delay time caused by the path is equal, the difference between the delay time of the data DQk input to the data input terminal Tk and the delay time of the strobe signal DQS0 input to the strobe signal input terminal ST1 is the difference of the reference clock RCK. Equal to one period. That is, when the signal is input to the flip-flop FFk1, the strobe signal is delayed by one cycle of the reference clock RCK with respect to the data.

  On the other hand, when the correction mode signal CMS becomes inactive, the signal delay circuit unit SD1 enters the normal mode, and the strobe signal DQS1 is selected by the MUX11. The second delay circuit 13 delays the input strobe signal DQS1 by a delay time set using the reference clock RCK in the correction mode, and outputs the delayed signal to the clock terminal of the flip-flop FFk1 via the buffers 18 and 20. .

  As can be seen from the above description, the corresponding strobe signals DQS2, DQSB2 respectively input to the clock terminals of the flip-flops FFk1, FFk2 with respect to the data DQk input to the data terminals of the flip-flops FFk1, FFk2, respectively. Are delayed by one cycle of the reference clock RCK. By periodically performing the delay time setting process (hereinafter referred to as “correction process”) using the reference clock RCK described above, an ideal strobe delay can be maintained.

  The interface circuit 1 described above can be used as an interface of a storage control device that controls data input / output of the storage device. FIG. 5 shows an example of the configuration of the interface of the storage control device 32 that controls the input / output of data to / from the storage device 31. FIG. 5 shows a DDR2-SDRAM and a memory control LSI as examples of the storage device 31 and the storage control device 32, respectively. As shown in FIG. 5, data DQ0 to DQ7 and strobe signals DQS and DQSB are input from the storage device 31 to the storage control device 32, respectively. In the interface circuit shown in FIG. 5, for the sake of simplicity, only the configuration related to the data DQ0 and DQ7 is shown, and the configuration related to the data DQ1 to DQ6 is omitted.

  The storage control device 32 is controlled by the control circuit unit 33. The control circuit unit 33 outputs a correction mode signal CMS and other control signals such as a gear ratio setting signal GV (described later) to the storage control device 32. The storage device 31 and the storage control device 32 operate based on the bus clock BCK generated by the bus clock generation circuit 34. The bus clock generation circuit 34 is controlled by the control circuit unit 33.

  Further, the storage control device 32 includes a reference clock generation circuit 35. The reference clock generation circuit 35 generates a reference clock RCK based on the input bus clock BCK and outputs it to the signal delay circuit units SD1 and SD2.

  FIG. 6 is a timing chart for explaining the operation of the interface circuit used in the storage control device 32 shown in FIG. FIG. 6 shows waveforms of the reference clock RCK, bus clock BCK, data DQ0 to DQ7, strobe signal DQS0, and strobe signals DQS2 and DQSB2 obtained by delaying the strobe signal DQS0. Here, the frequency of the reference clock RCK is four times the frequency of the bus clock BCK. Further, the data setup operation and hold operation are performed over a period of one cycle of the reference clock RCK between the edges of the bus clock.

  The timing chart of FIG. 6 shows the data transfer timing of the double data rate method. In the double data rate method, data is input / output to / from the storage device 31 both when the strobe signal rises and when it falls. To explain using the data DQ0 to DQ7, for example, the data DQ0 is output from the storage device 31 at the first rising edge of the strobe signal, and the data DQ1 is output at the first falling edge.

  However, when data is actually captured in the storage control device 32, it is not always effective at the rising edge of the strobe signal or during the H (High) level period due to the difference in delay time between the data D0 to D7 and the AC characteristics of the memory. Data is not input and the period during which valid data can be captured is limited. In the example shown in FIG. 6, the strobe signal DQS0 must be delayed by the 90-degree phase of the bus clock BCK in order to capture valid data.

  Therefore, in the interface circuit 1 according to the first embodiment, the strobe signal is delayed using the reference clock RCK having one period corresponding to the 90-degree phase of the bus clock BCK. As described above, the strobe signals input to the clock terminals of the flip-flops FFk1 and FFk2 are delayed by one cycle of the reference clock RCK from the data input to the data terminals of the same flip-flops FFk1 and FFk2. Therefore, if the reference clock RCK is a quadruple clock of the bus clock BCK, the strobe signal DQS0 can be delayed by a phase of 90 degrees of the bus clock BCK, and as a result, valid data can be captured. In FIG. 6, the timing difference between the strobe signal before correction and the strobe signal after correction is represented by time tcyc + tDmin. This time tcyc + tDmin is the sum of the delay time tDmin by the data delay circuit Mdk and one cycle tcyc of the reference clock RCK. Here, to the delay time of the strobe signal DQS0, the delay time tDmin by the delay data delay circuit Mdk is added to the time corresponding to the phase of 90 degrees of the bus clock BCK, but the delay time tDmin is 1 of the reference clock RCK. This is smaller than the period tcyc, and does not cause a problem in that the interface circuit 1 can fetch data effectively.

  Note that the switching timing of the operation mode of the interface circuit is arbitrarily controlled by the control circuit unit 33. Usually, after the reset of the storage device 31 is released, the correction mode is set, and thereafter, the mode is switched to the normal mode. Then, after entering the normal mode, data is read from and written to the storage device 31. In addition, for example, the operation mode may be periodically switched in synchronization with the refresh cycle of the storage device 31, and the correction process using the reference clock RCK may be periodically performed.

  According to the interface circuit 1 according to the first embodiment, each of the latch circuit units DT0 to DT7 has a data transmission time from each corresponding data delay circuit Md0 to Md7 to each of the latch circuit units DT0 to DT7, and a strobe signal delay. Since the signal transmission times from the circuit unit SSD to the latch circuit units DT0 to DT7 are equal to each other, the data DQ0 to DQ7 output from the corresponding data delay circuits Md0 to Md7, respectively. Thus, the strobe signals DQS2 and DQSB2 output from the strobe signal delay circuit unit SSD can be made to have no delay. That is, when the data DQ0 to DQ7 are fetched by the latch circuit units DT0 to DT7, the delay time for the data DQ0 to DQ7 of the strobe signals DQS2 and DQSB2 is the time set by the strobe signal delay circuit unit SSD, that is, the reference It is held for one cycle of the clock RCK. Therefore, in the interface circuit 1 according to the first embodiment, by appropriately selecting the cycle of the reference clock RCK, the delay time for the data of the strobe signals DQS2 and DQSB2 is set to a desired time when the data DQ0 to DQ7 are fetched. Therefore, the data DQ0 to DQ7 can be taken in effectively.

  In the configuration example shown in FIG. 2, the reference clock RCK is directly input to the MUX 11. However, the reference clock RCK is provided with a pulse generator that generates a pulse of one cycle based on the reference clock RCK. You may input into MUX11. FIG. 7 shows a configuration example of the signal delay circuit unit SD1 including a pulse generator. Since the configuration shown in FIG. 7 is the same as the configuration shown in FIG. 2 except that the pulse generator 36 is added, the description thereof is omitted.

(Embodiment 2)
Next, an interface circuit according to the second embodiment of the present invention will be described. The interface circuit according to the second embodiment is different from the interface circuit 1 according to the first embodiment in that each signal delay circuit section SD1, SD2 is given a delay time by the second delay circuit 13 at that time according to the operation mode. A delay time setting circuit for resetting the delay time to 1 / N (N is a positive integer) is added. The delay time setting circuit resets the delay time set for the second delay circuit 13 to 1 / N of the delay time in the normal mode, that is, when the strobe signals DQS1 and DQSB1 are selected by the MUX 11. Since other components are the same as those of the interface circuit according to the first embodiment, description thereof is omitted.

  FIG. 8 shows a configuration example of the signal delay circuit unit SD1 in the interface circuit according to the second embodiment. As shown in FIG. 8, the signal delay circuit part SD1 of the interface circuit according to the second embodiment has a delay time for reducing the delay time by the second delay circuit 13 to 1 / N according to the input correction mode signal CMS. A setting circuit 41 is provided. When the correction mode signal CMS becomes inactive, the delay time setting circuit 41 sets the second delay so that the delay time set for the second delay circuit 13 is reset to 1 / N of the delay time. A control signal is output to the selection circuit 22 of the circuit 13. The delay time setting circuit 41 and the delay control circuit 15 constitute a delay control circuit unit.

  On the other hand, when the correction mode signal CMS becomes active, the delay time setting circuit 41 outputs the control signal Sg output from the delay control circuit 15 to the second delay circuit 13 as it is. That is, the operation of the interface circuit in the correction mode is the same as that described in the first embodiment.

  Further, the interface circuit according to the second embodiment can be applied to the storage control device in the same manner as the interface circuit 1 according to the first embodiment. For example, when it is desired to delay the strobe signals DQS0 and DQSB0 by the phase of 90 degrees of the bus clock BCK in order to capture valid data, the frequency of the reference clock RCK input to each signal delay circuit unit SD1 and SD2 is set. The frequency is the same as that of the bus clock BCK. Then, in the correction mode, the delay time by the second delay circuit 13 is such that the signal input to the clock terminal of the flip-flop FFk1 is delayed by one cycle of the bus clock BCK with respect to the data input to the data terminal. Is set. Next, when the delay time by the second delay circuit 13 is set to 1/4 of the delay time set in the correction mode in the normal mode, the signal input to the clock terminal of the flip-flop FFk1 is input to the data terminal. The data is delayed by 1/4 cycle of the bus clock BCK. As a result, the strobe signal DQS0 can be delayed by the phase of 90 degrees of the bus clock BCK, and valid data can be captured.

  Note that this is the case where N = 4, but even if the frequency of the reference clock RCK is doubled the frequency of the bus clock and N = 2, the strobe signals DQS0 and DQSB0 are equivalent to the phase of 90 degrees of the bus clock BCK. It can be delayed and, as a result, valid data can be captured.

(Embodiment 3)
Next, an interface circuit according to a third embodiment of the present invention will be described. The interface circuit according to the third embodiment is different from the interface circuit 1 according to the first embodiment in that gear logic and MUX are added. The gear logic adjusts the delay time set in the second delay circuit 13 in accordance with a gear ratio setting signal GV indicating a gear ratio setting value input from the outside.

  FIG. 9 shows a configuration example of the signal delay circuit unit SD1 in the interface circuit according to the third embodiment. As shown in FIG. 9, the signal delay circuit unit SD <b> 1 of the interface circuit according to the third embodiment includes a gear logic 51 and a MUX 52. The gear logic 51 increases or decreases the delay time indicated by the control signal output from the delay control circuit 15 at a predetermined ratio corresponding to the gear ratio setting value, and outputs the result to the MUX 52. The gear logic 51, the MUX 52, and the delay control circuit 15 constitute a delay control circuit unit.

  The MUX 52 receives the output signal of the gear logic 51 and the output signal of the delay control circuit 15, and the correction mode signal CMS as a switching signal. The MUX 52 selects one of the output signals of the gear logic 51 and the delay control circuit 15 based on the correction mode signal CMS, and outputs the selected signal to the first delay circuit 12 and the second delay circuit 13. Specifically, the MUX 52 selects the output signal of the delay control circuit 15 in the correction mode in which the correction mode signal CMS is active, and outputs the output signal of the gear logic 51 in the normal mode in which the correction mode signal CMS is inactive. select.

  According to the signal delay circuit portion SD1 of the interface circuit according to the third embodiment, the set delay time can be adjusted in the normal mode even after the delay time by the second delay circuit 13 is set in the correction mode. . Thereby, even when there is a wiring delay difference between the data transmission path and the strobe signal transmission path in the storage control device 31, the delay time by the second delay circuit 13 can be adjusted so as to eliminate this difference. . The gear ratio set value may be determined in advance or may be changed by the control circuit unit 33.

  Further, the above-described configuration for adjusting the delay time of the second delay circuit 13 in accordance with the gear ratio set value can also be applied to the signal delay circuit unit SD1 shown in FIG. FIG. 10 shows a configuration in which a gear logic 51 and a MUX 52 are added to the signal delay circuit unit SD1 shown in FIG. The delay time setting circuit 41, the gear logic 51, the MUX 52, and the delay control circuit 15 constitute a delay control circuit unit. The gear logic 51 increases or decreases the delay time set for the second delay circuit 13 by the delay time setting circuit 41 at a predetermined rate corresponding to the gear ratio setting value. The MUX 52 receives the output signal of the gear logic 51 and the output signal of the delay control circuit 15, and the correction mode signal CMS as a switching signal. The MUX 52 selects the output signal of the delay time control circuit 15 in the correction mode in which the correction mode signal CMS is active, and selects the output signal of the gear logic 51 in the normal mode in which the correction mode signal CMS is inactive. Also in this case, similarly to the configuration shown in FIG. 9, even if there is a wiring delay difference between the data transmission path and the strobe signal transmission path in the storage control device 31, the second so as to eliminate this difference. The delay time by the delay circuit 13 can be adjusted.

It is the figure which showed the structural example of the interface circuit by Embodiment 1 of this invention. FIG. 2 is a diagram illustrating a configuration example of a signal delay circuit unit illustrated in FIG. 1. FIG. 3 is a circuit diagram illustrating a configuration example of a second delay circuit illustrated in FIG. 2. It is a timing chart for demonstrating operation | movement of the signal delay circuit part at the time of correction | amendment mode. 2 shows a configuration example of an interface unit of a storage control device. 6 is a timing chart for explaining the operation of an interface circuit used in the storage control device shown in FIG. The example of a structure of the signal delay circuit part provided with the pulse generator is shown. 5 shows a configuration example of a signal delay circuit unit in an interface circuit according to a second embodiment of the present invention. 7 shows a configuration example of a signal delay circuit unit in an interface circuit according to a third embodiment of the present invention. 10 shows another configuration example of the signal delay circuit unit in the interface circuit according to the third embodiment of the present invention. It is the figure which showed the structural example of the conventional interface circuit. 12 is a timing chart for explaining the reception timing of each data in the interface circuit of FIG. It is the figure which showed the operation timing of the interface circuit.

Explanation of symbols

1 interface circuit DQ0 to DQ7 data DQS0 to DQS2, DQSB0 to DQSB2 strobe signal Md0 to Md7 data delay circuit SSD strobe signal delay circuit section SD1, SD2 signal delay circuit section DT0, DT7 data capture circuit section FF01, FF02, FF71, FF72 flip-flop The

Claims (10)

In an interface circuit that captures a plurality of data input from the outside in synchronization with a strobe signal input together with the data,
A plurality of data delay circuit units that output the corresponding data with a predetermined first delay time, respectively;
A strobe signal delay circuit unit that outputs the strobe signal by delaying the strobe signal by a predetermined second delay time;
A plurality of latch circuit units that capture the output data of each corresponding data delay circuit unit in synchronization with the output signal of the strobe signal delay circuit unit,
In each of the latch circuit units, the data transmission time from the corresponding data delay circuit unit to the latch circuit unit is equal to the signal transmission time from the strobe signal delay circuit unit to the latch circuit unit. An interface circuit characterized by being arranged as follows. The strobe signal delay circuit unit is
A selection circuit unit that selects and outputs either the input strobe signal or the reference clock signal according to a first control signal input from the outside;
A first delay circuit unit that outputs the output signal of the selection circuit unit with a delay by the first delay time;
When the reference clock signal is output from the selection circuit unit, a DLL circuit unit that outputs the reference clock signal with a delay so that the phase of the reference clock signal matches the output signal of the first delay circuit unit,
When the reference clock signal is output from the selection circuit unit, the DLL circuit unit determines that the difference between the delay time of the reference clock signal and the delay time of the first delay circuit unit is the period of the reference clock signal. The delay time of the reference clock signal is controlled so as to be equal, and when the strobe signal is output from the selection circuit unit, the strobe signal is output after being delayed by a time equal to the delay time of the reference clock signal. The interface circuit according to claim 1. The strobe signal delay circuit unit is
A selection circuit unit that selects and outputs either the input strobe signal or the reference clock signal according to a first control signal input from the outside;
A first delay circuit unit that outputs the output signal of the selection circuit unit with a delay by the first delay time;
When the reference clock signal is output from the selection circuit unit, a DLL circuit unit that outputs the reference clock signal with a delay so that the phase of the reference clock signal matches the output signal of the first delay circuit unit,
When the reference clock signal is output from the selection circuit unit, the DLL circuit unit determines that the difference between the delay time of the reference clock signal and the delay time of the first delay circuit unit is the period of the reference clock signal. The delay time of the reference clock signal is controlled to be equal, and when the strobe signal is output from the selection circuit unit, the strobe signal is equal to a predetermined fraction of the delay time of the reference clock signal. 2. The interface circuit according to claim 1, wherein the output is delayed by time. The strobe signal delay circuit unit is
A selection circuit unit that selects and outputs either the input strobe signal or the reference clock signal according to a first control signal input from the outside;
A first delay circuit unit that outputs the output signal of the selection circuit unit with a delay by the first delay time;
When the reference clock signal is output from the selection circuit unit, a DLL circuit unit that outputs the reference clock signal with a delay so that the phase of the reference clock signal matches the output signal of the first delay circuit unit,
When the reference clock signal is output from the selection circuit unit, the DLL circuit unit determines that the difference between the delay time of the reference clock signal and the delay time of the first delay circuit unit is the period of the reference clock signal. The delay time of the reference clock signal is controlled so as to be equal, and when the strobe signal is output from the selection circuit unit, the delay time of the reference clock signal is increased or decreased at a predetermined rate. The interface circuit according to claim 1, wherein the output is delayed by a predetermined time. The DLL circuit unit includes:
A second delay circuit unit that outputs the output signal of the selection circuit unit with a delay of a set delay time; and
When the reference clock signal is output from the selection circuit unit, a phase difference detection circuit unit that detects and outputs a phase difference between output signals of the first and second delay circuit units;
When the reference clock signal is output from the selection circuit unit, a delay control circuit unit that controls a delay time so as to eliminate the phase difference with respect to the second delay circuit unit is provided. The interface circuit according to claim 2. The DLL circuit unit includes:
A second delay circuit unit that outputs the output signal of the selection circuit unit with a delay of a set delay time; and
When the reference clock signal is output from the selection circuit unit, a phase difference detection circuit unit that detects and outputs a phase difference between output signals of the first and second delay circuit units;
When the reference clock signal is output from the selection circuit unit, the delay time is controlled so that the phase difference is eliminated for the second delay circuit unit, and the strobe signal is output from the selection circuit unit. The interface circuit according to claim 3, further comprising a delay control circuit unit that sets a delay time of the second delay circuit unit to a predetermined fraction of the delay time. The DLL circuit unit includes:
A second delay circuit unit that outputs the output signal of the selection circuit unit with a delay of a set delay time; and
When the reference clock signal is output from the selection circuit unit, a phase difference detection circuit unit that detects and outputs a phase difference between output signals of the first and second delay circuit units;
When the reference clock signal is output from the selection circuit unit, the delay time is controlled so that the phase difference is eliminated for the second delay circuit unit, and the strobe signal is output from the selection circuit unit. The delay control circuit unit configured to set a delay time of the second delay circuit unit to a time obtained by increasing or decreasing the delay time at a predetermined rate. Interface circuit.   8. The interface circuit according to claim 7, wherein the delay control circuit unit changes the ratio in accordance with a second control signal input from the outside. The strobe signal is composed of a pair of signals forming a differential signal,
The strobe signal delay circuit unit includes two signal delay circuit units that delay and output one of the corresponding signals of the differential signal,
Each of the latch circuit units includes two latch circuits that respectively capture the output data of the corresponding data delay circuit units,
2. The interface circuit according to claim 1, wherein each of the latch circuits takes in output data of each of the corresponding data delay circuit units in synchronization with an output signal of each of the corresponding signal delay circuit units. In a storage control device including an interface circuit that captures a plurality of data output from a storage device based on a strobe signal output together with each data,
The interface circuit is
A plurality of data delay circuit units that output the corresponding data with a predetermined first delay time, respectively;
A strobe signal delay circuit unit that outputs the strobe signal by delaying the strobe signal by a predetermined second delay time;
A plurality of latch circuit units that capture the output data of each corresponding data delay circuit unit in synchronization with the output signal of the strobe signal delay circuit unit,
In each of the latch circuit units, the data transmission time from the corresponding data delay circuit unit to the latch circuit unit is equal to the signal transmission time from the strobe signal delay circuit unit to the latch circuit unit. The storage control device is arranged as described above.

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