JP2007215030A - Solid-state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging device with which image information is read at a high speed. <P>SOLUTION: The solid-state imaging device 10 has a plurality of pixels Ca, arranged into a matrix form and selects one pixel Ca determined by line address signals X0, X1 and column address signals Y0, Y1. Then, the solid-state imaging device 10 outputs image information of the a single selected pixel Ca, namely, photoelectric conversion signal according to an amount of incident light generated by photoelectric conversion, as the output signal Do. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device.

  Conventionally, MOS type solid-state imaging devices are used to acquire various image data. In this type of solid-state imaging device, a plurality of pixels are arranged in, for example, a matrix, rows (lines) are sequentially scanned by a vertical scanning circuit, image signals are read from pixels in each column, and image signals for one line are scanned by a horizontal scanning circuit. Is read out for each pixel. Each pixel is a linear conversion type image sensor, which stores image information photoelectrically converted by a photodiode in a predetermined charge accumulation time, so-called integration time, as a charge in a capacitor, and outputs an image signal corresponding to the amount of accumulated charge. Output. As described above, since the integration operation for accumulating the charge in the capacitor is performed, if the charge is accumulated in the capacitor, the amount of charge accumulated in the capacitor in the next accumulation period does not correspond to the incident light amount. For this reason, it is necessary to perform a reset operation for applying a reference potential level to the capacitor.

  However, since the reset operation is erasing stored charge, an integration time is required to store the next image information after reset. The reset operation, the integration operation, and the information reading operation must be repeated. For this reason, even if it is attempted to continuously read out information of dynamically changing images, the integration time and the reset operation are the limiting conditions, and high-speed reading cannot be performed.

  An object of the present invention is to read image information at high speed.

  A solid-state imaging device according to the present invention includes: an imaging unit in which pixels that detect a current flowing through a light receiving element and convert it into an electrical signal are connected to intersections of a plurality of row signal lines and column data lines and arranged in a matrix; A decoder connected to the row signal line and the column data line and selecting a row signal line and a column data line based on an address signal, and an input from a pixel connected to the selected row signal line via the column data line An amplifying circuit for amplifying the photoelectric conversion signal, a first drive signal for controlling a current corresponding to the amount of incident light to flow through the light receiving element, and a second for resetting a sense node to which the light receiving element is connected. A voltage control circuit that generates a drive signal, switches the first drive signal and the second drive signal in response to the control signal, and supplies the drive signal to the pixel.

  In the present invention, the current flowing through the light receiving element in the pixel is detected and converted into an electric signal under an electrical equilibrium state, that is, the operating principle is exclusively based on the static state. There is no need to reset every time necessary image information is read. For this reason, it is possible to continuously read image information from the pixels selected by the address signals by changing the address signals while supplying the first drive signal, and the reading interval is shortened. That is, an effective high reading speed can be obtained and image information can be read at high speed. Further, by resetting the pixel with the control signal, it is possible to prevent the afterimage generated in the pixel from affecting the image information to be read next.

  In a preferred embodiment of the present invention, a readout detection circuit for detecting readout with respect to the pixel, and the number of readouts is counted based on a detection result of the readout detection circuit, and the control is performed by comparing the count value with a set value. And a reset control circuit for outputting a signal. With this configuration, by resetting the pixels intermittently, it is not necessary to control from the outside, and it is possible to prevent the afterimage from affecting the image information to be read next.

  In one aspect of the present invention, the pixel is connected to a light receiving element, and operates in a subthreshold region by the first drive signal, and a sense node between the light receiving element and the load transistor. A logarithmic conversion type pixel including an amplification transistor that is connected and outputs a photoelectric conversion signal corresponding to the potential of the sense node, and a readout transistor that contacts and separates the amplification transistor and the column data line. Since the logarithmic conversion type pixel has a wider dynamic range than the linear conversion type pixel, there is no blackout in a dark part and overexposure in a bright part, so that a clear image can be obtained.

  As described above, according to the present invention, a solid-state imaging device capable of reading image information at high speed can be provided.

DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, an embodiment of the invention will be described with reference to the drawings.
FIG. 1 is a schematic block circuit diagram of a solid-state imaging device.
The solid-state imaging device 10 includes an imaging unit 11, an X decoder 12 and a Y decoder 13 as address decoders, a column amplifier 14 as an amplifier circuit, an output circuit 15, and a voltage control circuit 16.

  The imaging unit 11 includes a plurality of pixels Ca arranged in a matrix. In order to simplify the description, in the present embodiment, the imaging unit 11 including the pixels Ca arranged in a matrix of 4 rows and 4 columns will be described. Each pixel Ca is a pixel that detects a current flowing through the light receiving element and converts it into an electrical signal. The pixels Ca in each row are connected to row signal lines R0 to R3, respectively, and the pixels Ca in each column are connected to column data lines C0 to C3, respectively.

  The X decoder 12 is connected to four row signal lines R <b> 0 to R <b> 3 corresponding to the number of rows of the imaging unit 11, and receives 2-bit row address signals X <b> 0 and X <b> 1 corresponding to the number of rows of the imaging unit 11. The X decoder 12 decodes the row address signals X0 and X1 and selects one of the row signal lines R0 to R3. Then, the X decoder 12 controls the potential of one selected row signal line to a voltage level for reading image information from the pixel Ca. Therefore, in the present embodiment, a voltage for reading image information is supplied as a read signal to the four pixels Ca connected to the row signal line via the selected row signal line. Each pixel Ca outputs image information to the column data lines C0 to C3 in response to the readout signal supplied via the row signal lines R0 to R3.

  Photoelectric conversion signals as image information read from the four pixels Ca are input to the column amplifier 14 via column data lines C0 to C3 to which the pixels Ca are connected. The column amplifier 14 is connected to a Y decoder 13, and 2-bit column address signals Y 0 and Y 1 corresponding to the number of columns of the imaging unit 11 are input to the Y decoder 13. The Y decoder 13 outputs a signal obtained by decoding the address signals Y0 and Y1 to the column amplifier 14.

  The column amplifier 14 includes an amplification unit, a multiplexer circuit unit, and an analog-digital (A / D) conversion unit, and the amplification unit is provided corresponding to each column data line C0 to C3. The photoelectric conversion signals input via the column data lines C0 to C3 are respectively amplified by the amplifiers and transmitted to one A / D converter via the multiplexer circuit unit. The A / D conversion unit samples the output signal of the corresponding amplification unit based on a predetermined clock signal, and converts the sampled analog quantity (for example, voltage) into a digital signal. That is, the column amplifier 14 generates four digital signals corresponding to the photoelectric conversion signals read from the four pixels Ca connected to the row signal lines R0 to R3. The column amplifier 14 selects one digital signal corresponding to the logic levels of the address signals Y0 and Y1 from the four digital signals based on the output signal of the Y decoder 13, and outputs the digital signal to the output circuit 15. To do. The output circuit 15 outputs an output signal Do obtained by converting the output signal of the column amplifier 14.

  That is, the solid-state imaging device 10 includes a plurality of pixels Ca arranged in a matrix, and selects one pixel Ca determined by the row address signals X0 and X1 and the column address signals Y0 and Y1. Then, the solid-state imaging device 10 outputs, as an output signal Do, image information of one selected pixel Ca, that is, a photoelectric conversion signal corresponding to the amount of incident light generated by photoelectric conversion. Therefore, the image information of the pixel Ca at an arbitrary position can be read by the row address signals X0 and X1 and the column address signals Y0 and Y1.

  The pixels Ca in each column constituting the imaging unit 11 are connected to voltage supply lines L0 to L3, respectively. That is, each of the voltage supply lines L0 to L3 is connected with four pixels Ca, similarly to the row signal lines R0 to R3. Each voltage supply line L <b> 0 to L <b> 3 is connected to the voltage control circuit 16.

  The voltage control circuit 16 controls the voltage of the drive signal supplied to each pixel Ca via the voltage supply lines L0 to L3 in response to the control signal Sc input from the outside. For example, the voltage control circuit 16 supplies a drive signal of a first voltage (hereinafter referred to as a first drive signal) to each pixel Ca based on an L level control signal Sc, and generates a first voltage based on an H level control signal Sc. A drive signal having a voltage of 2 (hereinafter referred to as a second drive signal) is supplied to each pixel Ca. The first drive signal is a signal whose voltage is set to perform a photoelectric conversion operation in each pixel Ca. The second drive signal is a signal whose voltage is set to perform a reset operation in each pixel Ca. In response to the first drive signal, each pixel Ca photoelectrically converts incident light to generate image information. Each pixel Ca erases the image information held immediately before the input of the second drive signal in response to the second drive signal. Therefore, when using this solid-state imaging device 10, by supplying the control signal Sc, it is possible to obtain an image after resetting each pixel Ca as necessary and once erasing the image information.

  The level of the control signal Sc to which the voltage control circuit 16 responds may be changed as appropriate. The control signal Sc may be composed of a plurality of bits or a plurality of signals, and the voltage of the drive signal is controlled based on a combination of logic levels of the plurality of bits or the plurality of signals.

Next, the configuration of the pixel Ca will be described. Since each pixel Ca has the same configuration, the pixel Ca connected to the row signal line R0 and the column data line C0 will be described.
As shown in FIG. 2, the pixel Ca of the present embodiment is a logarithmic conversion type image element. Since the logarithmic conversion type image element has a wider dynamic range than the linear conversion type pixel, there is no blackout in a dark part or whiteout in a bright part, and therefore a clear image can be obtained.

  The pixel Ca includes a photodiode PD as a light receiving element and three transistors T1, T2, and T3. The first to third transistors T1 to T3 are one-conductive channel type transistors (N-channel type MOS transistors in the present embodiment), and a back gate is connected to the ground GND (not shown).

  The drain (first terminal) of the first transistor T1 as the load transistor is supplied with the high potential power supply Vdd, the gate (control terminal) is connected to the voltage supply line L0, and the source (second terminal) is the cathode of the photodiode PD. It is connected to the. The anode of the photodiode PD is connected to a low potential power source (ground GND in this embodiment). The photodiode PD passes a current Ip corresponding to the amount of incident light.

  A sense node N1, which is a connection point between the first transistor T1 and the photodiode PD, is connected to the gate of the second transistor T2 as an amplification transistor. The high potential power supply Vdd is supplied to the drain of the second transistor T2, and the source is connected to the first terminal (for example, drain) of the third transistor T3 as the pixel selection transistor.

  The gate of the third transistor T3 is connected to the row signal line R0, and the second terminal (source) is connected to the column data line C0. The third transistor T3 is turned on / off according to the read signal supplied through the row signal line R0, and connects and disconnects the second transistor T2 and the column data line C0. Therefore, when the third transistor T3 is turned on, the second transistor T2 and the column data line C0 are connected. A constant current source (not shown) is connected to the column data line C0, and the constant current source and the second transistor T2 form a source follower circuit. The potential of the sense node N1 is converted into a photoelectric conversion signal via the second transistor T2. Is output to the column data line C0.

  The voltage control circuit 16 shown in FIG. 1 supplies the first drive signal and the second drive signal to the pixel Ca configured as described above. The first drive signal is a signal set with a voltage so that the pixel Ca performs a photoelectric conversion operation, and the second drive signal is a signal set with a voltage so that the pixel Ca performs a reset operation.

  The voltage control circuit 16 is a first drive signal whose voltage is set so that the first transistor T1 is in a weakly inverted state, that is, a so-called subthreshold region operation, for example, a first drive signal of the high potential power supply Vdd that is the same as the drain potential. Supply.

  When light strikes the pixel Ca, a photocurrent Ip flows through the photodiode PD according to the amount of light. Since the first transistor T1 is in a weak inversion state due to the first drive signal, the same amount of subthreshold current flows as the photocurrent Ip, and the potential of the sense node N1 corresponds to the photocurrent Ip. Stable to potential. A state where the potential of the sense node N1 is stable is referred to as an electrically stable state (or an electrically balanced state). Since the subthreshold current flowing through the first transistor T1 is equal to the photocurrent Ip flowing through the photodiode PD, the potential of the sense node N1 is a potential obtained by logarithmically converting the photocurrent Ip. Then, by turning on the third transistor T3 by the readout signal, a photoelectric conversion signal having a potential corresponding to the potential of the sense node N1, that is, the incident light amount is obtained.

  The voltage control circuit 16 is a second drive signal in which the voltage is set so that the first transistor T1 operates in a strong inversion state, that is, an on state, for example, a voltage higher than the threshold voltage of the transistor T1 above the drain potential. A second drive signal is supplied. Then, the potential of the sense node N1 becomes the same voltage as the high potential power supply Vdd, and the output potential is initialized. This initialization can prevent the light incident on the photodiode PD in the past from affecting the next photoelectric conversion signal, that is, the influence of the afterimage.

Next, a case where the amount of incident light changes in a state where the first drive signal is supplied to the pixel Ca will be described.
Similarly to the above, when light strikes the pixel Ca, a photocurrent Ip flows through the photodiode PD in accordance with the first light amount. Since the first transistor T1 is in a weak inversion state by the first drive signal, the potential of the sense node N1 is in an equilibrium state that is stable at a potential corresponding to the photocurrent Ip.

  When the amount of incident light on the pixel Ca changes to the second amount of light, a photocurrent Ip2 flows through the photodiode PD according to the amount of incident light. The potential of the sense node N1 is a so-called transient state that varies to a potential corresponding to the photocurrent Ip2 based on the second light quantity. As the time elapses, the potential of the sense node N1 is stabilized at a potential corresponding to the photocurrent Ip2, that is, an electrically stable state is obtained.

  Here, the time in the transient state varies depending on the stray capacitance existing in the sense node N1. The pixel Ca of this embodiment does not include a capacitor for positively accumulating charges. However, in reality, a minute stray capacitance exists between the wirings. If this stray capacitance is in an ideal state that is so small that it can be regarded as almost zero, the transient time can be regarded as zero. That is, the extra charge accumulated in the stray capacitance is extracted or the stray capacitance is accumulated in order to compensate for the insufficient charge, and the substantial transient time can be regarded as zero. Therefore, since the time in the transient state is zero, that is, the waiting time until the sense node N1 is stabilized after the amount of incident light changes is zero, it is not necessary to provide a waiting time, and substantially high-speed reading can be performed.

  When the stray capacitance is not so small as to be almost zero, the sense node N1 has a potential affected by the first light amount, that is, an afterimage occurs in the transient state. That is, the photoelectric conversion signal read out at this time includes a signal based on the second incident light amount and an afterimage signal based on the first incident light amount. However, the afterimage signal decreases as the potential of the sense node N1 approaches the equilibrium state, and becomes 0 (zero) in the equilibrium state. Then, by turning on the third transistor T3 by the read signal, a photoelectric conversion signal having a potential corresponding to the second light amount is obtained.

  That is, in the present embodiment, it is possible to obtain a photoelectric conversion signal having a potential corresponding to the changed amount of light without performing a reset operation. Therefore, when the amount of light is constant, the potential of the sense node N1 is in an equilibrium state, so that the potential of the sense node N1 can be read immediately, that is, reading can be performed at high speed.

  When the amount of light changes, it takes time corresponding to the amount of change in incident light from when the amount of light changes according to the amount of change in the amount of light until it reaches an equilibrium state. By performing reading at a time interval equal to or longer than this time, a photoelectric conversion signal having no afterimage can be obtained. Even in this case, since the reset operation is not necessary, the time until reading is shortened compared with the case of performing the reset operation, and the reading can be performed at high speed.

  Further, when the incident light quantity changes gradually, the potential of the sense node N1 changes according to the change in the light quantity. Therefore, if the change in the amount of incident light is about the time required to shift from the transient state to the equilibrium state or less, it can be said that the potential of the sense node N1 changes in an almost equilibrium state. On the other hand, when the reset operation is performed as in the conventional example, the potential of the sense node N1 is reset to the reference potential, so that the time corresponding to the amount of change in incident light in order to change from the reference potential to the potential according to the amount of light. It takes more time. In other words, the conventional example requires a period for the reset operation and a period until the equilibrium state is reached, and the reading interval is long. However, in the present embodiment, since the potential of the sense node N1 changes in an almost balanced state, the reading interval is shorter than in the conventional example, and reading can be performed almost continuously.

  The time required for the transition from the change in the amount of light to the transition to the equilibrium state, that is, the time for which the afterimage signal remains, is the direction of change (decrease or increase) even if the absolute value of the change in the amount of incident light is the same. ) Depends on. When the amount of incident light decreases, the photocurrent Ip decreases, so it takes time to extract the charge accumulated in the stray capacitance. The remaining time is long. Conversely, when the amount of incident light increases, the photocurrent Ip increases, so the time for accumulating charges in the stray capacitance is short and the time for which the afterimage signal remains is short.

  Thus, the afterimage disappearance time varies depending on the amount of incident light, that is, subject illuminance. For this reason, in a processing circuit that performs image processing such as edge enhancement and color correction on the output signal Do of the solid-state imaging device 10 described above, the amount of change between two photoelectric conversion signals read out continuously, that is, two The processing may be selectively performed based on the absolute value of the difference between the photoelectric conversion signals and the sign of the difference. For example, when the amount of incident light has greatly increased, that is, when the value of the photoelectric conversion signal has increased, it is determined that there is no afterimage, and image processing is executed. On the other hand, when the amount of incident light is greatly reduced, that is, when the value of the photoelectric conversion signal becomes small and the absolute value of the value is larger than the reference value set by the reading interval, it is determined that there is an afterimage and the process is suspended. At the same time, a control signal Sc is output to reset the pixel Ca. As a result, it is possible to prevent image processing on a photoelectric conversion signal including an afterimage and to prevent the influence of the afterimage.

As described above, according to the present embodiment, the following effects can be obtained.
The solid-state imaging device 10 includes a plurality of pixels Ca arranged in a matrix, and selects one pixel Ca determined by the row address signals X0 and X1 and the column address signals Y0 and Y1. Then, the solid-state imaging device 10 outputs, as an output signal Do, image information of one selected pixel Ca, that is, a photoelectric conversion signal corresponding to the amount of incident light generated by photoelectric conversion. Therefore, the image information of the pixel Ca at an arbitrary position can be read by the row address signals X0 and X1 and the column address signals Y0 and Y1.

  The voltage control circuit 16 supplies the first drive signal to each pixel Ca via the voltage supply lines L0 to L3 in response to the control signal Sc, and causes each pixel Ca to function as a logarithmic conversion type pixel. Further, the voltage control circuit 16 supplies a second drive signal for performing a reset operation to each pixel Ca in response to the control signal Sc. Each pixel Ca erases the image information held immediately before the input of the second drive signal in response to the second drive signal. Therefore, by resetting the pixel Ca by the control signal, it is possible to prevent the afterimage generated in the pixel Ca from affecting the image information to be read next.

  The pixel Ca is a logarithmic conversion type pixel that is a logarithmic conversion type pixel including a photodiode PD and a first transistor T1 connected to the photodiode PD and operating in a subthreshold region. In addition, since the dynamic range is wide, there is no blackout in a dark part and whiteout in a bright part, so that a clear image can be obtained.

In addition, you may implement each said embodiment in the following aspects.
-You may change suitably the structure of the solid-state imaging device 10 in the said embodiment.
For example, as shown in FIG. 3, a solid-state imaging device is configured. The solid-state imaging device 20 includes a serial-parallel conversion circuit (serial-parallel conversion circuit: SP conversion circuit) 21. The SP conversion circuit 21 receives the serially converted address signal Si and converts the row address signals X0 and X1 and the column address signals Y0 and Y1 generated by parallel conversion of the address signal Si to the X decoder 12 and the Y decoder 13. Output. In this way, by configuring the solid-state imaging device 20, it is not necessary to provide dedicated pins for inputting the row address signals X0 and X1 and the column address signals Y0 and Y1, and thus the package size of the solid-state imaging device 20 is reduced. Can do.

  Moreover, as shown in FIG. 4, a solid-state imaging device is comprised. The solid-state imaging device 30 includes an address generation circuit 31. The address generation circuit 31 uses row address signals X0 and X1 and column addresses for designating all the pixels Ca included in the readout area based on the top data Sp and the final data Ep that designate diagonal pixels in the readout area. Signals Y0 and Y1 are sequentially generated. With this configuration, since the photoelectric conversion signals are sequentially and sequentially output from all the pixels Ca included in the reading area, partial image information can be easily read from the imaging unit 11. Instead of the top data Sp and the last data Ep, a reference position (for example, the position of the pixel Ca having the smallest address) and the size of the area (number of pixels) may be input.

  Moreover, as shown in FIG. 5, a solid-state imaging device is comprised. The solid-state imaging device 40 includes a plurality (two in FIG. 5) of column amplifiers 41 and 42 and an output circuit 43. Both column amplifiers 41 and 42 have a pipeline configuration, and output digital signals generated by sampling photoelectric conversion signals. Then, both column amplifiers 41 and 42 are operated alternately. That is, when a digital signal is output from one column amplifier, the photoelectric conversion signal read by the other column amplifier is sampled. The output circuit 43 outputs a digital signal alternately output from both the column amplifiers 41 and 42 as an output signal Do.

  When a readout signal is supplied via the row signal lines R0 to R3, photoelectric conversion signals are simultaneously output from the plurality of pixels Ca connected to the row signal lines R0 to R3. Therefore, in order to read out image information of the pixel Ca connected to one row signal line, it is necessary to specify a row address and a column address, and then an image of another pixel Ca connected to the same row signal line. In order to read out information, only the column address needs to be specified. For this reason, a difference occurs in the time from the address designation to the output of the output signal. Therefore, even if an address is specified at a constant interval, the output interval of the output signal may be different. This phenomenon occurs when the row signal line to be selected is changed, that is, the row address signal is changed. For this reason, a plurality of image information read by designating one row address is sampled by one column amplifier, and output signals are sequentially output. While outputting this output signal, the image information read from the plurality of pixels Ca connected to the row signal line is input to another column amplifier by designating another row address. The output circuit 43 starts reading from another column amplifier when reading from one column amplifier is completed. In this way, by alternately performing ramp ring and signal reading for the first column amplifier 41 and the second column amplifier 42, the output signal Do is output at a constant interval even if the row address is changed. Can do.

  The pixel Ca in each of the above embodiments performs a so-called static operation in which the potential of the sense node N1 set by the photocurrent Ip is read. Incidentally, the conventional pixel performs a dynamic operation for accumulating / discharging the capacitor. For this reason, the configuration may be changed as long as it is a pixel exclusively for static operation, that is, a pixel that detects the photocurrent Ip flowing through the photodiode PD and converts it into an electrical signal. For example, as shown in FIG. A pixel including the resistor R1 may be used. This pixel reads a voltage change of the sense node N1 caused by the photocurrent Ip flowing through the resistor R1 as a photoelectric conversion signal. Note that the pixel shown in FIG. 6 may include a transistor for resetting the sense node N1.

  In the above embodiment, the pixel Ca is reset by the input control signal Sc, but the solid-state imaging device itself may determine and reset the pixel Ca. One specific example is shown in FIG. The solid-state imaging device 50 includes a readout detection circuit 51 and a reset control circuit 52. The readout detection circuit 51 is connected to the row signal lines R0 to R3, detects readout of image information based on voltage changes of the row signal lines R0 to R3, and outputs a detection signal. The reset control circuit 52 counts the number of readings based on the detection signal of the reading detection circuit 51, and outputs a control signal Sc to the voltage control circuit 16 when the count value matches a set value (for example, 30 times). With this configuration, it is possible to intermittently reset the read operation, and it is possible to periodically remove the influence of afterimages. Note that the read detection circuit may detect reading based on a change in the level of the column data line, changes in the address signals (row address signals X0 and X1 and column address signals Y0 and Y1), and the like.

  In each of the above embodiments, an N-channel type MOS transistor is used as a one-conductive channel type transistor, but a P-channel type MOS transistor may be used. Alternatively, a CMOS structure using an N-channel MOS transistor and a P-channel MOS transistor may be used.

  In the above embodiment, all the pixels Ca are reset at once, but may be reset separately. For example, the voltage control circuit 16 receives selection information of the row signal lines R0 to R3 selected based on the row address signals X0 and X1, and based on the selection information, the pixel Ca from which the image information has been read out By supplying the second drive signal to the connected row signal line, the pixel Ca in the row where the reading operation is performed is reset. According to this configuration, when image information is read from the pixel Ca connected to one row signal line, the pixel Ca in the row where the reading has been completed can be reset, that is, reading and reset are performed simultaneously. Therefore, unlike the conventional example, it is not necessary to wait until the reset is completed, and it is possible to continuously read out the image information, and the reading time of a plurality of pieces of image information is shortened, that is, the effective reading speed is reduced. Can be improved.

  In each of the above embodiments, the pixels Ca in each row are connected to the same voltage supply lines L0 to L3. However, the voltage supply lines may be separately connected to the individual pixels Ca. Further, a plurality of rows of pixels Ca may be connected to one voltage supply line.

  In each of the above embodiments, the voltage of the signal supplied to the gate of the first transistor T1 is controlled so as to function as a load transistor for logarithmic conversion and a transistor for resetting. And a transistor for resetting the sense node N1 may be configured separately.

The technical ideas that can be grasped from the above embodiments are described below.
An address generation circuit is provided, which receives area information for setting a readout area and sequentially generates address signals for selecting all pixels included in the readout area based on the area information. Item 4. The solid-state imaging device according to any one of Items 1 to 3.

  The solid-state imaging device according to any one of claims 1 to 3, further comprising a serial-parallel conversion circuit that converts the serial signal into parallel to generate the address signal.

1 is a block circuit diagram of a solid-state imaging device according to an embodiment. The circuit diagram of a pixel. The block circuit diagram of another solid-state imaging device. The block circuit diagram of another solid-state imaging device. The block circuit diagram of another solid-state imaging device. The circuit diagram of another pixel. The block circuit diagram of another solid-state imaging device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Imaging part, 16 ... Voltage control circuit, 52 ... Reset control circuit, C0-C3 ... Column data line, Ca ... Pixel, Ip ... Photo current, N1 ... Sense node, R0-R3 ... Row signal line, Sc ... Control Signal, X0, X1... Row address signal, Y0, Y1... Column address signal, T1.

Claims (3)

An image pickup unit in which pixels that detect a current flowing through a light receiving element and convert it into an electrical signal are connected to intersections of a plurality of row signal lines and column data lines and arranged in a matrix,
A decoder connected to the row signal line and the column data line and selecting a row signal line and a column data line based on an address signal;
An amplifying circuit for amplifying a photoelectric conversion signal input from a pixel connected to the selected row signal line via a column data line;
Responsive to the control signal, a first drive signal for controlling the light receiving element to flow a current corresponding to the amount of incident light and a second drive signal for resetting the sense node to which the light receiving element is connected are generated. A voltage control circuit that switches between the first drive signal and the second drive signal and supplies the first drive signal to the pixel;
A solid-state imaging device comprising: A readout detection circuit for detecting readout from the pixels;
A reset control circuit that counts the number of reads based on the detection result of the read detection circuit, compares the count value with a set value, and outputs the control signal;
The solid-state imaging device according to claim 1, further comprising:   The pixel is connected to a light receiving element and connected to a load transistor operating in a subthreshold region by the first drive signal, and a sense node between the light receiving element and the load transistor, and the potential of the sense node is 3. The logarithmic conversion type pixel comprising: an amplifying transistor that outputs a corresponding photoelectric conversion signal; and a reading transistor that contacts and separates the amplifying transistor and the column data line. Solid-state imaging device.

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