JP2007214285A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a semiconductor device in which the deterioration of performance resulting from a power supply voltage drop (IR drop) in the semiconductor device can be suppressed easily. <P>SOLUTION: When a semiconductor device 100 comprising a semiconductor substrate 10, a circuit element 20 formed on the semiconductor substrate, and a multilayer wiring portion 50 having a large number of wiring formed across a plurality of layers and constituting an integrated circuit together with the circuit element is manufactured on the semiconductor substrate, thermoelectric generating portions 60A-60C are formed in the multilayer wiring portion and individual thermoelectric generating portions are connected with predetermined wiring in the multilayer wiring portion. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a semiconductor substrate, a circuit element formed on the semiconductor substrate, and a multilayer wiring portion in which a large number of wirings constituting an integrated circuit together with the circuit element are formed over a plurality of layers.

  In today's electronic equipment, various semiconductor devices including integrated circuits are used. Each semiconductor device has a semiconductor substrate, a circuit element formed on the semiconductor substrate, and a multilayer wiring portion in which a large number of wirings constituting an integrated circuit together with the circuit element are formed over a plurality of layers. The multilayer wiring portion is formed on the semiconductor substrate. In recent years, the performance of electronic devices has been rapidly improved, and accordingly, the power consumption of individual semiconductor devices is increasing.

  On the other hand, portable electronic devices are also rapidly spreading, and in order to increase the continuous use time of high-performance portable electronic devices, the improvement of secondary batteries and the development of small fuel cells are also being promoted. It has been. Further, development of a thermoelectric power generation element as a new power source is also in progress. For example, Patent Document 1 describes a module including a semiconductor element and a thermoelectric power generation element externally attached to the semiconductor element.

Japanese Patent Laid-Open No. 2004-158531

  In order to obtain a high-performance semiconductor device, not only the performance of individual circuit elements constituting the semiconductor device is improved, but also signal delay due to a drop in power supply voltage (IR drop) in the semiconductor device. It is necessary to suppress a decrease in performance due to the occurrence of the above.

  The present invention has been made in view of the above, and an object of the present invention is to obtain a semiconductor device that can easily suppress a decrease in performance due to an IR drop.

  A semiconductor device of the present invention that achieves the above object includes a semiconductor substrate, a circuit element formed on the semiconductor substrate, and a multilayer wiring portion in which a plurality of wirings constituting an integrated circuit together with the circuit elements are formed over a plurality of layers. And a thermoelectric power generation part provided in the multilayer wiring part and connected to a predetermined wiring in the multilayer wiring part.

  In the semiconductor device according to the present invention, a thermoelectric power generation unit is provided in the multilayer wiring unit, and the thermoelectric power generation unit and a predetermined wiring in the multilayer wiring unit are connected to each other. The voltage drop at the element can be suppressed by feeding from the thermoelectric generator. As a result, it becomes easy to suppress a decrease in performance due to the IR drop.

  Embodiments of a semiconductor device according to the present invention will be described below in detail with reference to the drawings. The present invention is not limited to the embodiments described below.

Embodiment 1 FIG.
FIG. 1 is a plan view schematically showing an example of the semiconductor device of the present invention. The semiconductor device 100 shown in FIG. 1 includes a semiconductor substrate, a circuit element formed on the semiconductor substrate, a multilayer wiring portion in which a plurality of wirings constituting an integrated circuit together with the circuit elements are formed over a plurality of layers, and a multilayer wiring portion. A thermoelectric power generation unit and the like that are provided and connected to predetermined wirings in the multilayer wiring unit are provided. And three thermoelectric power generation unit 60A~60C in FIG. 1, a power supply voltage supply line W _VDD, a ground line W _GND, wiring 44a, and 44b, a protective layer 70 covering the multilayer wiring portion, and a plurality of pads P thermoelectric power generation unit 60A of the indicated and, three thermoelectric power generation unit 60A~60C is disposed in a central portion of the plane of the multilayer wiring portion is connected to the power voltage supply line W _VDD by a wire 44a It is connected to a ground line W _GND by a wire 44b with. The other thermoelectric generators 60B and 60C are each connected directly to a predetermined wiring in the multilayer wiring part or via a contact plug.

The multilayer wiring portion is smaller than the semiconductor substrate, and the edge of the semiconductor substrate spreads around the multilayer wiring portion in plan view. The wirings 44a and 44b are formed on the uppermost interlayer insulating film in the multilayer wiring part and covered with the protective layer 70. The power supply voltage supply line _WVDD and the ground line _WGND are _connected to the uppermost interlayer in the multilayer wiring part. The insulating layer is formed over a predetermined pad P and is covered with a protective layer 70. Each pad P is formed on the edge of the uppermost interlayer insulating film in the multilayer wiring portion and connected to a predetermined wiring or contact plug in the multilayer wiring portion. In FIG. 1, the thermoelectric power generation units 60 </ b> A to 60 </ b> C, the power supply voltage supply line W _VDD , the ground line W _GND , the wiring 44 a, and the wiring 44 b are drawn with solid lines for convenience.

  FIG. 2 is a schematic view of a section taken along line II-II shown in FIG. As shown in the figure, in the semiconductor device 100, a circuit element 20 is formed on the semiconductor substrate 10, and a multilayer wiring part 50 is formed on the semiconductor substrate 10 so as to cover the circuit element 20. A protective layer 70 is formed so as to cover the surface. Each thermoelectric power generation unit 60A-60C shown in FIG. 1 is provided in the multilayer wiring unit 50 as described above. However, only the thermoelectric generator 60A appears in FIG.

The semiconductor substrate 10 may be a substrate made of an elemental semiconductor such as silicon, or may be a substrate made of a compound semiconductor such as gallium arsenide. Furthermore, an SOI (Silicon on Insulator) substrate may be used. A predetermined element region (well) corresponding to the type of circuit element to be formed on the semiconductor substrate 10 and an element isolation region having a predetermined shape are formed at predetermined positions of the semiconductor substrate 10. In the semiconductor substrate 10 shown in the figure, an N-type well 3 and a P-type well (not shown in FIG. 2) are formed at predetermined positions of the P ⁻ -type silicon substrate 1, and each element region is partitioned in plan view. Thus, the element isolation region (element isolation film) 7 is formed.

  Which element is formed as the circuit element is appropriately selected according to the function required for the semiconductor device 100. The circuit element 20 shown in FIG. 2 is a field effect transistor (hereinafter referred to as “field effect transistor 20”). The field effect transistor 20 includes a source region 12 and a drain region 14 formed in the N-type well 3, a gate electrode 18 disposed on the semiconductor substrate 10 via a gate insulating film 16, and a line width direction in the gate electrode 18. Side wall spacers SW, SW provided on the both side surfaces of each. When a predetermined voltage is applied to the gate electrode 18, a channel is formed between the source region 12 and the drain region 14.

The multilayer wiring section 50 includes a first interlayer insulating film 30 positioned at the bottom, a second interlayer insulating film 35 positioned at the center, and a third interlayer insulating film 40 positioned at the top. In each of the insulating films 30, 35, and 40, a contact plug and a large number of wirings that form an integrated circuit together with the above-described circuit elements by electrically connecting the contact plugs in a predetermined pattern are formed. In FIG. 2, of the contact plugs and wirings formed in the interlayer insulating films 30, 35, and 40, the first layer contact plug 32 a connected to the source region 12 and the first plug connected to the drain region 14. Layer contact plug 32b, four first layer wirings 34a to 34d, one second layer contact plug 37, two second layer wirings 39a and 39b, one third layer contact plug 42, three Third layer wiring (third layer wiring 44c, power supply voltage supply line W _VDD , and ground line W _GND ) appears. A protective layer 70 is formed on the multilayer wiring portion 50 by a desired inorganic material or organic material, and each wiring and each contact plug formed in the multilayer wiring portion 50 are protected from oxidation, corrosion, and the like.

The thermoelectric generator 60A is formed on the second interlayer insulating film 35, and the thermoelectric generator 60A has a structure in which _two thermoelectric generators 60A ₁ and 60A ₂ that generate power using the Seebeck effect are connected in series. have. The individual thermoelectric power generation elements 60A ₁ and 60A ₂ have the same structure, and each includes a plurality of lower electrodes, a plurality of N-type semiconductor layers, a plurality of P-type semiconductor layers, and a plurality of upper electrodes. Have. In FIG. 2, two lower electrodes 52, 52, one N-type semiconductor layer 54, one P-type semiconductor layer 55, and two upper electrodes 57, 57 appear. Here, a thermoelectric power generation element that generates power using the Seebeck effect will be specifically described with reference to FIG.

FIG. 3 is a side view schematically illustrating an example of a thermoelectric power generation element that generates electric power using the Seebeck effect. The thermoelectric power generation element TE shown in the figure is an element having a structure in which _three power generation units U _{1 to} U ₃ are connected in series, and each power generation unit U _{1 to} U ₃ includes one N-type semiconductor layer Sn, One P-type semiconductor layer Sp, one lower electrode Be connecting the N-type semiconductor layer Sn and the P-type semiconductor layer Sp, an upper electrode connected to the N-type semiconductor layer Sn, and the P-type semiconductor layer Sp And a connected upper electrode.

Adjacent power generation units are connected by one upper electrode so that the P-type semiconductor layer in one power generation unit and the N-type semiconductor layer in the other power generation unit face each other. In the illustrated example, an N-type semiconductor layer Sn are connected by the upper electrode Ue ₂ the P-type semiconductor layer Sp and power generation unit U ₂ in the power generation unit U _1, the generator and the P-type semiconductor layer Sp in the power generation unit U ₂ units U ₃ is connected to the N-type semiconductor layer Sn by the upper electrode Ue ₃ . The upper electrode Ue ₁ is connected to the N-type semiconductor layer Sn in the power generation unit U _1, and the upper electrode Ue ₄ is connected to the P-type semiconductor layer Sp in the power generation unit U ₃ .

In the thermoelectric power generation element TE having such a structure, when a temperature difference occurs between each lower electrode Be and each upper electrode Ue _{1 to} Ue ₄ , the individual semiconductor layers Sn and Sp go from the high temperature side to the low temperature side. The carrier moves. In the N-type semiconductor layer Sn, free electrons move from the high temperature side to the low temperature side, and in the P type semiconductor layer Sp, holes move from the high temperature side to the low temperature side. Therefore, when the upper electrode Ue ₁ and the upper electrode Ue ₄ are connected to an external load to form one circuit, the upper electrode Ue ₁ becomes the negative electrode and the upper electrode Ue ₄ becomes the positive electrode, and the thermoelectric generator TE generates power. .

As a material of each of the N-type semiconductor layer Sn and the P-type semiconductor layer Sp, a semiconductor that can obtain a relatively large thermoelectromotive force even in an environment where the temperature difference between the lower electrode Be and the upper electrodes Ue _{1 to} Ue ₄ is small. For example, it is preferable to use a bismuth-tellurium-based semiconductor. Specific examples of bismuth and tellurium-based N-type semiconductors include Bi ₂ (Se, Te) ₃ , and specific examples of bismuth and tellurium-based P-type semiconductors include (Bi, Sb) ₂ Te _{3 and the} like. It is done.

Figure 2 each of the thermoelectric power generating device 60A _1, 60A ₂ shown is a thermoelectric power generation element having a structure similar to the thermoelectric power generation element TE as described above, N of a predetermined number corresponding to the N-type semiconductor layer Sn shown in FIG. 3 2 and a predetermined number of P-type semiconductor layers 55 (see FIG. 2) corresponding to the P-type semiconductor layer Sp shown in FIG. The thermoelectric power generation section 60A including these thermoelectric power generation elements 60A ₁ and 60A ₂ has contact plugs (not shown in FIG. 2) and wirings 44a (see FIG. 1) formed in the third interlayer insulating film 40. ) via the while being connected to the power supply voltage supply line W _VDD, and a contact plug formed in the third interlayer insulating film 40 (not shown in Figure 2.) and the wiring 44b (see FIG. 1) To the ground line W _GND . For this reason, when the field effect transistor 20 generates heat by driving and the lower electrode 52 of each thermoelectric power generation element 60A ₁ , 60A ₂ becomes hotter than the upper electrode 57, these thermoelectric power generation elements 60A ₁ , 60A ₂ generate power. _Thus , power is supplied from the thermoelectric generator 60A to the power supply voltage supply line _WVDD .

  Although not shown in FIG. 2, each of the thermoelectric power generation units 60B and 60C shown in FIG. 1 also includes a thermoelectric power generation element using the Seebeck effect, and each is connected to a predetermined circuit element or wiring. . Similarly to the above-described thermoelectric power generation unit 60A, each thermoelectric power generation unit 60B, 60C also generates power when driving the semiconductor device 100 and supplies power to a predetermined circuit element or wiring.

Also in the semiconductor device 100 described above, IR drop occurs as in the conventional semiconductor device. However, for powering the thermoelectric power generation unit 60A~60C during driving of the semiconductor device 100 (see FIG. 1) is generating power to the power voltage supply line W _VDD like, each being formed on the semiconductor substrate 10 (see FIG. 2) The voltage drop at the circuit element can be suppressed. In particular, since it is connected most prominent places IR drop, i.e. the thermoelectric power generation unit 60A to the power voltage supply line W _VDD in the central portion of a plan view of the multilayer wiring section 50, the semiconductor substrate 10 (see FIG. 2) Thus, the voltage drop in each circuit element formed in the circuit can be efficiently suppressed. As a result, in this semiconductor device 100, it is easy to suppress a decrease in performance due to the IR drop. Further, since the design margin and the manufacturing margin of the integrated circuit are increased in the semiconductor device 100, it is easy to obtain a device having desired performance.

The semiconductor device 100 having such a technical effect can be manufactured in the same manner as a conventional semiconductor device except that the thermoelectric generators 60A to 60C (see FIG. 1) are formed in the multilayer wiring portion 50. The thermoelectric power generation elements constituting the individual thermoelectric power generation units 60A to 60C, for example, the thermoelectric power generation elements 60A ₁ and 60A ₂ (see FIG. 2) constituting the thermoelectric power generation part 60A are, for example, the first layer wiring 34a. To 34c are formed together with the first wiring layers 34a to 34c, and then the N-type semiconductor layer 54 and the P-type semiconductor layer 55 in each of the thermoelectric generators 60A ₁ and 60A ₂ are formed. Then, the second interlayer insulating film 35 is formed, and then the upper electrode 57 is formed together with the second wiring layers 39a, 39b when the second layer wirings 39a, 39b are formed. The thermoelectric power generation elements constituting the other thermoelectric power generation units 60B and 60 to 60C can be formed in the same manner.

Embodiment 2. FIG.
In the semiconductor device of the present invention, above the region where the amount of heat generated in the integrated circuit formed in the semiconductor device is large, for example, the region where the integration density of field effect transistors is high or the region where wiring having a high operating frequency is arranged. It is preferable to arrange the thermoelectric power generation unit above.

FIG. 4 is a plan view schematically showing an example of a semiconductor device in which a thermoelectric power generation unit is arranged above a region where a large amount of heat is generated in an integrated circuit. The semiconductor device 110 shown in the figure can be divided into four regions R _{1 to} R ₄ in a plan view according to the amount of heat generated in the integrated circuit. The heat generation amount in the region R ₂ is the smallest, and the heat generation amount in the region R ₄ is the largest. The amount of heat generated in the regions R ₁ and R ₃ is larger than the amount of heat generated in the region R ₂ and smaller than the amount of heat generated in the region R ₄ . The thermoelectric power generation unit 105 is disposed in the region R ₄ that generates the largest amount of heat among these regions R _{1 to} R ₄ . Also in this case, the thermoelectric power generation unit 105 is provided in the multilayer wiring unit 50 (see FIG. 2) and is connected to a predetermined wiring in the multilayer wiring unit 50.

In the integrated circuit, when the thermoelectric power generation unit 105 is arranged above the region R ₄ where the heat generation amount is large, the temperature difference between the lower electrode and the upper electrode of the thermoelectric power generation element is larger than when the thermoelectric generation unit 105 is arranged in the region where the heat generation amount is small. Therefore, the thermoelectromotive force in the thermoelectric power generation element increases, and the amount of power generation in the thermoelectric power generation unit 105 also increases. As a result, the drop in the power supply voltage due to the IR drop is compensated by the power supply from the thermoelectric generator 105, so that the voltage drop in each circuit element can be easily suppressed, and the semiconductor device 100 having desired performance can be easily obtained.

Further, in the integrated circuit, the region R _{4 where the} amount of heat generation is large is also a region where power consumption is large. In this region, the rate of decrease in the power supply voltage is high, and therefore, in each circuit element formed in the region R ₄ . By suppressing the voltage drop by power feeding from the thermoelectric generator 105, the operation margin of the integrated circuit can be easily increased.

Embodiment 3 FIG.
The semiconductor device described in the first embodiment has a structure in which the thermoelectric generator is covered with the third interlayer insulating film. In the semiconductor device of the present invention, the upper surface of the thermoelectric generator is formed from the multilayer wiring portion. Can be exposed.

  FIG. 5 is a cross-sectional view schematically showing an example of a semiconductor device in which the thermoelectric generator is arranged with the upper surface of the thermoelectric generator exposed from the multilayer wiring portion. A semiconductor device 150 shown in the figure includes a thermoelectric power generation unit 120 disposed above the field effect transistor 20 and a thermoelectric power generation unit 130 disposed above the first layer wirings 34c and 34e.

It said thermoelectric power generating unit 120 is _{for 1} two thermoelectric power generation element 120A, 120A ₂ are connected in series, the two thermoelectric power generating device 120A _1, 120A ₂ is between the third interlayer insulating each of the upper surface The second interlayer insulating film 35 is exposed from the second interlayer insulating film 35 to the third interlayer insulating film 40 and is connected to a predetermined wiring in the multilayer wiring portion 50. Each of the thermoelectric power generation elements 120A ₁ and 120A ₂ is an element that generates electric power using the Seebeck effect. Similar to the thermoelectric power generation element TE shown in FIG. 3, a plurality of lower electrodes, a plurality of N-type semiconductor layers, and a plurality of P A type semiconductor layer and a plurality of upper electrodes. In FIG. 5, lower electrodes 112 and 112, an N-type semiconductor layer 114, a P-type semiconductor layer 115, and upper electrodes 117 and 117 appear.

  On the other hand, the thermoelectric power generation unit 130 is disposed in the third interlayer insulating film 40 and connected to a predetermined wiring in the multilayer wiring unit 50 with its upper surface exposed from the third interlayer insulating layer 40. . The thermoelectric power generation unit 130 includes one thermoelectric power generation element 130A that generates power using the Seebeck effect. The thermoelectric power generation element 130A includes two lower electrodes 122 and 122, two N-type semiconductor layers 124 and 124, and 2 Two P-type semiconductor layers 125, 125 and three upper electrodes 127, 127, 127 are provided.

Note that openings OP ₁ and OP ₂ that expose the upper surfaces of the thermoelectric generators 120 and 130 are formed in the protective layer 70 formed on the multilayer wiring portion 50. Among the constituent elements shown in FIG. 5, those common to the constituent elements shown in FIG. 2 are denoted by the same reference numerals as those used in FIG. 2, and description thereof is omitted. Reference numeral “39c” in FIG. 5 indicates one second-layer wiring.

In the semiconductor device 150 shown in FIG. 5, since the upper surface of the thermoelectric power generation unit 120 is exposed, heat radiation from the thermoelectric power generation unit 120 occurs more easily than when the thermoelectric power generation unit 120 is covered with an interlayer insulating film. Therefore, the temperature difference between the lower electrodes 112 and 112 and the upper electrodes 117 and 117 in each thermoelectric power generation element 120A ₁ and 120A ₂ is increased, and the thermoelectromotive force in each thermoelectric power generation element 120A ₁ and 120A ₂ is also increased. . As a result, the amount of power generated by the thermoelectric power generation unit 120 also increases. For the same reason, in the thermoelectric power generation 130, the thermoelectromotive force is increased and the amount of power generation is increased.

Embodiment 4 FIG.
In the semiconductor device of the present invention, a heat insulating part can be provided on the side of the thermoelectric power generating part. When providing this heat insulation part, arrange the heat insulation part from the side of the circuit element or wiring that becomes the heat source of the thermoelectric power generation part to the side of the thermoelectric power generation part, and the heat generated in the circuit element or wiring that becomes the heat source. It is preferable to supply a large amount to the thermoelectric generator.

  FIG. 6 is a cross-sectional view schematically showing an example of a semiconductor device in which a heat insulating part is provided on the side of the thermoelectric power generating part. The semiconductor device 160 shown in the figure has the same structure as the semiconductor device 100 shown in FIG. 2 except that a heat insulating part 155 is provided from the side of the field effect transistor 20 to the side of the thermoelectric power generation part 60A. have. Among the constituent elements shown in FIG. 6, the same constituent elements as those shown in FIG. 2 are denoted by the same reference numerals as those used in FIG.

  The heat insulating unit 155 is configured to supply most of the heat generated in the field effect transistor 20 serving as the heat source of the thermoelectric power generation unit 60A to the thermoelectric power generation unit 60A. The interlayer insulating film 35 is formed from the first interlayer insulating film 30 to the second interlayer insulating film 35 with a desired inorganic material or organic material having higher heat insulation than any of the interlayer insulating films 35.

By providing the heat insulating portion 155, most of the heat generated in the field effect transistor 20 is supplied to the thermoelectric power generating portion 60A. Therefore, the thermoelectric power generating elements 60A ₁ , 60A are compared with the case where the heat insulating portion 155 is not provided. ₂ The temperature difference between the lower electrodes 52, 52 and the upper electrodes 57, 57 in each of the _two becomes larger, and the thermoelectromotive force in each of the thermoelectric generators 60A ₁ , 60A ₂ also becomes larger. As a result, the amount of power generated by the thermoelectric generator 60A also increases.

  Although the semiconductor device according to the present invention has been described with reference to four embodiments, the present invention is not limited to the above-described embodiments as described above. For example, the number of thermoelectric power generation units arranged in one semiconductor device and the number of thermoelectric power generation elements constituting each thermoelectric power generation unit can be appropriately selected, and the configuration of each thermoelectric power generation element can also be appropriately selected. In addition, the height of each thermoelectric power generation element can be made smaller than the film thickness of the interlayer insulating film constituting the multilayer wiring part, or can be set to the height over a plurality of interlayer insulating films constituting the multilayer wiring part. it can. When the upper surface of the thermoelectric power generation unit is exposed from the multilayer wiring unit, the upper surface of the thermoelectric power generation unit can be covered with a protective layer. The configuration of the semiconductor device other than the thermoelectric power generation unit can be appropriately changed according to the intended use of the semiconductor device, the function required for the semiconductor device, and the like. The semiconductor device of the present invention can be variously modified, modified, combined, and the like.

It is a top view which shows roughly an example of the semiconductor device of this invention. It is the schematic of the II-II line cross section shown in FIG. It is a side view which shows roughly an example of the thermoelectric power generation element which produces electric power using a Seebeck effect. It is a top view which shows roughly an example of the semiconductor device by which the thermoelectric power generation part was arrange | positioned above the area | region with much calorific value among integrated circuits. It is sectional drawing which shows roughly an example of the semiconductor device with which the thermoelectric power generation part has been arrange | positioned with the upper surface of this thermoelectric power generation part exposed from a multilayer wiring part. It is sectional drawing which shows roughly an example of the semiconductor device by which the heat insulation part was provided in the side of the thermoelectric power generation part.

Explanation of symbols

10 Semiconductor substrate 20 Circuit element (field effect transistor)
50 multilayer wiring section 52,112,122 lower electrode 54,114,124 N-type semiconductor layer 55,115,125 P-type semiconductor layer 57,117,127 upper electrode _{60A 1, 60A 2, 120A 1} ~120A 4, 130A thermoelectric Power generation element 60A, 60B, 60C, 105, 120, 130 Thermoelectric power generation unit 100, 110, 150, 160 Semiconductor device 155 Thermal insulation unit W _VDD Power supply voltage supply line W _GND Ground line

Claims (5)

  A semiconductor substrate; a circuit element formed on the semiconductor substrate; a multi-layer wiring part in which a plurality of wirings constituting an integrated circuit together with the circuit element are formed over a plurality of layers; A semiconductor device comprising: a predetermined wiring in a multilayer wiring portion; and a thermoelectric generator connected to each other.   The semiconductor device, wherein the thermoelectric power generation unit and the power supply voltage supply line in the multilayer wiring unit are connected to each other.   3. The semiconductor device according to claim 1, wherein the thermoelectric power generation unit is disposed above a region of the integrated circuit where a large amount of heat is generated.   The semiconductor device according to claim 1, wherein an upper surface of the thermoelectric power generation unit is exposed from the multilayer wiring unit.   The semiconductor device according to claim 1, further comprising a heat insulating portion provided on a side of the thermoelectric power generation unit.

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