JP2007208364A - Drive method of solid-state image pickup device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem wherein a method for improving the arrangement of wiring to reduce crosstalk due to parasitic capacity generated between the wires of a solid-state image pickup device is difficult due to an increase in a circuit scale, and a method for rounding waveform by providing an integrating circuit causes the circuit scale to increase and load capacity to increase. <P>SOLUTION: The level difference in each stage of stepped waveform is large when performing prescribed operation by the stepped waveform, where a control signal applied to the gate of a transistor for outputting signals in each pixel in the solid-state image pickup device changes in three steps of Low, Vg1, and High1. Therefore, crosstalk due to the parasitic capacity between wires becomes a problem, so that a control signal in stepped waveform in five steps as shown in (D) having a middle level in each stage of Low, Vg1, and High1 is generated for control. Since the level change of the generated control signal is small, crosstalk due to the parasitic capacity generated can be reduced between the wires, and an increase in load capacity can also be prevented since no integral circuits are used. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a driving method of a solid-state imaging device, and more particularly to a driving method of a solid-state imaging device that reduces crosstalk generated between control signal lines connected to pixels.

  In general, as an imaging device used in a video system such as a video camera and a digital camera, a solid-state imaging device in which a photodiode and a MOS field effect transistor (hereinafter referred to as a MOSFET) are combined is known (for example, patent document). 1). This solid-state imaging device includes an amplification type solid-state imaging device having an amplifier in a pixel such as a CMOS image sensor. Such a solid-state imaging device has a signal processing circuit such as a circuit for driving a pixel and a noise suppression circuit around a pixel covering region (pixel portion). When driving the pixels, it is possible to drive in units of rows or all pixels at once.

  FIG. 11 shows an example of such a solid-state imaging device, which is disclosed in Patent Document 1. In the figure, pixels Px are regularly arranged in a pixel covering region (pixel portion) 1. Here, for simplification, a total of four pixels Px, two in the vertical direction and two in the horizontal direction, are arranged in a matrix. Further, on the left side of the pixel spread area 1 in the figure, there is a circuit group for driving the pixel Px, which includes, for example, a vertical scanning circuit 2, an electronic shutter scanning circuit 3, and a multiplexer 4. These circuits can switch between driving the pixels Px in units of rows or all pixels at once.

  In the drawing of the pixel covering region 1, there is a current source 5 serving as a load of the pixel amplifier output in the upper part, and a voltage generated in the current source 5 becomes a signal of each pixel Px. The signal output of each pixel Px is subjected to signal processing for noise suppression by the noise suppression circuit 6 and is sequentially output from the output terminal 9 through the switches 7a and 7b which are sequentially switched by the horizontal scanning circuit 8.

  FIG. 12 shows a circuit diagram of one pixel Px. As shown in the figure, the pixel Px includes a photodiode PD1 that converts incident light into an electrical signal, a transfer transistor M1, a reset transistor M2, and a pixel amplifier transistor M3. The connection point between the sources of the transistors M1 and M2 and the gate of the transistor M3 forms a floating diffusion (FD) portion.

  Next, the reset operation and readout operation of the pixel Px will be described. At the time of resetting, when the power supply line VDDCEL of the pixel Px is set to H level and the current source 5 is subsequently turned on, a current is supplied to the pixel Px to enter the operation mode, and the pixel reset pulse connected to the multiplexer 4 in FIG. When the transistor M2 is turned on by the signal on the line ΦRST, the FD portion is set to the same H level as VDDCEL.

  Subsequently, when the transistor M2 is turned off by the signal of ΦRST and then the transistor M1 is turned on by the signal of the pixel transfer pulse line ΦTR connected to the multiplexer 4, the charge accumulated in the photodiode PD1 passes through M1. It is transferred to the FD unit and stored. As a result, the charge of the photodiode PD1 is cleared and a reset operation is performed. Thereafter, the transistor M1 is turned off by the signal of ΦTR, the PD1 is set in the charge accumulation state, and the reset operation is finished.

  When VDDCEL is set to L level and the transistor M2 is turned on by the signal of ΦRST, the FD portion is set to the same L level as VDDCEL, and then the transistor M2 is turned off by the signal of ΦRST, so that the FD portion is at the L level. And the pixel Px becomes non-operating. In this state, light incident on the PD 1 is photoelectrically converted and accumulated as charges in the PD 1.

  Next, when reading out the pixel Px, VDDCEL is set to H level, the transistor M2 is turned on by a signal of ΦRST, and the FD portion is set to the same H level as VDDCEL. Subsequently, after the transistor M2 is turned off by the signal of ΦRST, the transistor M1 is turned on by the signal of ΦTR, and the charge accumulated in the PD1 is transferred to the FD section through M1. Thereafter, the transistor M1 is turned off to complete the transfer. The electric charge in the FD portion is output as a voltage to the output line PIXOUT of the pixel through the transistor M3.

  Subsequently, VDDCEL is set to L level, the transistor M2 is turned on by the signal of ΦRST, the FD portion is set to the same L level as VDDCEL, the transistor M2 is turned off by the signal of ΦRST, and the FD portion is set to L level. , The signal readout from the pixel Px is completed.

JP 2005-64550 A

  However, in the solid-state imaging device, as shown in FIG. 11, each pixel Px is connected to the pixel reset pulse line ΦRST and the pixel transfer pulse line ΦTR wired in parallel, and the power supply line is the line ΦRST. Further, wiring such as readout signal lines crosses each other or is wired in parallel, which causes a problem between the wirings in the layout.

  The problem between the wirings in this layout will be described with reference to FIG. A problem in wiring layout is (A) crosstalk that occurs when wirings running in parallel are short and (B) wirings intersect. For example, as shown in FIG. 13A, when the distance between the wirings 11 and 12 laid out in parallel is short, a parasitic capacitance 13 is generated between them. As shown in FIG. 13B, when the first-layer wiring 14 and the second-layer wiring 15 intersect, a parasitic capacitance 16 is generated between the wirings 14 and 15.

  The parasitic capacitors 13 and 16 cause a differentiation circuit represented by an equivalent circuit as shown in FIG. Here, in FIG. 13C, C is the parasitic capacitance 13 or 16, and R indicates the wiring resistance. As a result, when the pulse signal shown in FIG. 13D1 is input to the wiring 11 (or 14), the differential pulse shown in FIG. 13D2 is generated in the wiring 12 (or 15). This is crosstalk.

  As measures against such crosstalk, it is conceivable to improve the layout of the wiring by the layout (expand the distance between the wirings that run in parallel. Eliminate the wiring that crosses, etc.), but the improvement by the layout becomes difficult as the circuit scale increases. It has become.

  Further, an integration circuit constituted by an RC circuit as shown in FIG. 14A is provided on the wiring, and the rise of the input signal (in this case, the potential) shown in FIG. 14B is shown in FIG. As shown, there is a method of preventing crosstalk between wirings by smoothing (see, for example, Japanese Patent Laid-Open No. 5-128410). However, when this method is used, the circuit scale due to the addition of the RC circuit increases, and the load capacity on the wiring increases (decrease in driving capability).

  In particular, an increase in the load capacity is ideally achieved when a signal having a waveform as shown in FIG. 15A is transmitted. As shown in FIG. Does not rise to the original High1 and causes the potential High1 ′ (High1> High1 ′). This phenomenon occurs remarkably in a wiring connected to a pixel far from the control circuit. That is, variations in reset occur in pixels in the same row. Further, it is considered that the same phenomenon occurs even at the potential of Vg1 shown in FIG. For this reason, adding an integration circuit for solving the problem of crosstalk becomes a major problem as the number of pixels increases, that is, the number of wirings increases.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a driving method of a solid-state imaging device that reduces crosstalk generated between wirings during pixel driving and prevents malfunction of signal processing.

  In order to achieve the above object, the present invention provides a photodiode that photoelectrically converts light to accumulate charges, a charge transfer transistor that transfers charges accumulated in the photodiode during an exposure period during a readout period, and a charge transfer transistor. A solid-state imaging device driving method in which a plurality of pixels each including a signal output transistor having an amplifying function for outputting transferred charges to a signal output line as a change in threshold value has a pixel laying area regularly arranged. The signal output transistor is controlled by a control signal having a staircase waveform that is transmitted through the first wiring and whose level changes in M steps (M is a natural number of 2 or more). The amount of charge input through a charge transfer transistor whose operation is controlled by a transfer control signal transmitted by wiring is used as a change in threshold value. When performing a predetermined operation, there are N stages (N is a natural number greater than M) having an intermediate level between each of the M stages and variably setting the switching time position to the intermediate level. A staircase waveform is generated as a control signal, and the signal output transistor is driven and controlled by the control signal.

  In the present invention, since the control signal of the signal output transistor transmitted through the first wiring has an N-stage staircase waveform that is larger than the minimum required M-stage, the size of each step of the staircase waveform (level change) Can be made smaller than the M-step staircase waveform, and the influence of the parasitic capacitance generated between the first wiring and another wiring such as the second wiring adjacent thereto can be reduced.

  Here, the signal output transistor includes a ring-shaped gate electrode on the substrate, a source region provided at a position of the substrate corresponding to the central opening of the ring-shaped gate electrode, a source region surrounding the source region, and a ring The charge transfer transistor is designed to transfer charges accumulated in the photodiode to the corresponding source vicinity region in the same pixel all at once. The transfer and signal output transistor operates by supplying an N-stage control signal to the ring-shaped gate electrode.

  In the present invention, in the solid-state imaging device having the global shutter function, between the first wiring connected to the signal output transistor having the ring-shaped gate electrode and the other wiring such as the second wiring adjacent thereto. The influence of the generated parasitic capacitance can be reduced.

  According to the present invention, the control signal of the signal output transistor transmitted through the first wiring has an N-step staircase waveform that is larger than the minimum required M-steps, whereby the size of each step of the staircase waveform is increased. (Level change) is made smaller than the M-step staircase waveform, and the crosstalk due to the parasitic capacitance generated between the first wiring and another wiring such as the second wiring adjacent thereto is represented by the M-step staircase waveform. Since it can be reduced more than when it is used, it is possible to prevent readout of noise that has been transferred due to malfunction due to crosstalk between wiring lines, and crosstalk can be reduced without using an integration circuit. An increase and a decrease in driving ability can also be prevented.

Next, an embodiment of the present invention will be described. 1A is a top view of an example of one pixel of a solid-state imaging device to which the driving method of the solid-state imaging device according to the present invention is applied, and FIG. 1B is a line XX ′ in FIG. FIG. As shown in FIGS. 1A and 1B, the CMOS sensor of the present embodiment grows a p ⁻ type epitaxial layer 42 on a p ⁺ type substrate 41, and an n well 43 on the surface of the epitaxial layer 42. There is. On the n-well 43, a gate electrode 45 having a ring shape as a first gate electrode is formed with a gate oxide film 44 interposed therebetween.

An n ⁺ -type source region 46 is formed on the surface of the n-well 43 corresponding to the center portion of the ring-shaped gate electrode 45, a source vicinity p-type region 47 is formed adjacent to the source region 46, and An n ⁺ -type drain region 48 is formed at a position spaced outside the source region 46 and the p-type region 47 near the source. In addition, there is a buried p ⁻ type region 49 in the n well 43 below the drain region 48. The buried p ⁻ type region 49 forms a buried photodiode 50 shown in FIG. 1A by a pn junction with the n well 43.

  Between the embedded photodiode 50 and the ring-shaped gate electrode 45, there is a transfer gate electrode 51 which is a second gate electrode. The drain region 48, the ring-shaped gate electrode 45, the source region 46, and the transfer gate electrode 51 include a drain electrode wiring 52, a ring-shaped gate electrode wiring 53, a source electrode wiring (output line) 54, and a transfer gate electrode, which are metal wirings, respectively. A wiring 55 is connected. Further, as shown in FIG. 1B, a light shielding film 56 is formed above each of the above components, and an opening 57 is formed at a position corresponding to the embedded photodiode 50 in the light shielding film 56. Has been. The light shielding film 56 is formed of a metal or an organic film. The light reaches the embedded photodiode 50 through the opening 57 and is photoelectrically converted.

  Next, the pixel structure of the CMOS sensor and the entire structure of the image sensor will be described with reference to FIG. In the figure, first, pixels are arranged in a pixel spread area 61 in m rows and n columns. In FIG. 2, one pixel 62 of s rows and t columns among these m rows and n columns is represented by an equivalent circuit. The pixel 62 includes a ring-shaped gate MOSFET 63, a photodiode 64, and a transfer gate MOSFET 65. The drain of the ring-shaped gate MOSFET 63 is the n-side terminal of the photodiode 64 and the drain electrode wiring 66 (corresponding to 52 in FIG. 1). , The source of the transfer gate MOSFET 65 is connected to the p-side terminal of the photodiode 64, and the drain is connected to the back gate of the ring-shaped gate MOSFET 63.

In FIG. 1B, the ring-shaped gate MOSFET 63 has a p-type region 47 near the source directly below the ring-shaped gate electrode 45 as a gate region, and an n ⁺ -type source region 46 and an n ⁺ -type drain region 48. An n-channel MOSFET. In addition, in FIG. 1B, the transfer gate MOSFET 65 has an n well 43 just below the transfer gate electrode 51 as a gate region, a p ⁻ type region 49 embedded with a photodiode 50 as a source region, and a p-type region 47 near the source. A p-channel MOSFET serving as a drain.

  In FIG. 2, in order to read a signal for one frame from each pixel of m rows and n columns, there is a circuit 67 for generating a frame start signal for giving a signal to start reading. The frame start signal may be given from outside the image sensor. This frame start signal is supplied to the vertical shift register 68. The vertical shift register 68 outputs a signal indicating which row of pixels is read out from each pixel of m rows and n columns.

  The pixels in each row are connected to a control circuit that controls the potentials of the ring-shaped gate electrode, transfer gate electrode, and drain electrode, and these control circuits are supplied with the output signal of the vertical register 68. For example, the ring-shaped gate electrode of each pixel in the s-th row is connected to the ring-shaped gate potential control circuit 70 via the ring-shaped gate electrode wiring 69 (corresponding to 53 in FIG. 1B), and the transfer of each pixel is performed. The gate electrode is connected to the transfer gate potential control circuit 72 via the transfer gate electrode wiring 71 (corresponding to 55 in FIG. 2), and the drain electrode of each pixel is connected to the drain electrode wiring 66 (52 in FIG. 1B). The drain potential control circuit 73 is connected. Each control circuit 70, 72, 73 is supplied with an output signal from the vertical shift register 68.

  Since the ring-shaped gate electrode is controlled for each row, wiring is performed in the horizontal direction. However, since the transfer gate electrode is controlled simultaneously for all pixels, the wiring direction is not limited and the vertical direction may be used. Here, it is expressed as wiring in the horizontal direction. The drain potential control circuit 73 controls all the pixels at the same time, but may be controlled for each row. Therefore, the drain potential control circuit 73 is represented by being connected to both the frame start signal and the vertical register 68.

  The source electrode of the ring-shaped gate MOSFET 63 of the pixel 62 is branched into two via a source electrode wiring 74 (corresponding to 54 in FIG. 1B), one of which controls the source electrode potential via the switch SW1. The other is connected to the circuit 75, and the other is connected to the signal readout circuit 76 via the switch SW2. When reading the signal, the switch SW1 is turned off and the switch SW2 is turned on. When the source potential is controlled, the switch SW1 is turned on and the switch SW2 is turned off. Since the signal is output in the vertical direction, the wiring direction of the source electrode is set to be vertical.

  The signal readout circuit 76 is configured as follows. The output of the pixel 62 is performed from the source of the ring-shaped gate MOSFET 63, and a load, for example, a current source 77 is connected to the output line 74. Therefore, it is a source follower circuit. One end of each of the capacitor C1 and the capacitor C2 is connected to the current source 77 via the switch sc1 and the switch sc2. One end of each of the capacitors C1 and C2 whose other ends are grounded is connected to the inverting input terminal and the non-inverting input terminal of the differential amplifier 78, and the potential difference between the capacitors C1 and C2 is output from the differential amplifier 78. It is like that.

  Such a signal readout circuit 76 is called a CDS circuit (correlated double sampling circuit), and various circuits other than the method described here have been proposed, and the circuit is not limited to this circuit. The signal output from the signal readout circuit 76 is output via the output switch swt. The output switches swt in the same column are subjected to switching control by a signal output from the horizontal shift register 79.

Next, a method for driving the CMOS sensor shown in FIG. 2 will be described with reference to the timing chart of FIG. First, in the period shown in FIG. 3A, light is incident on the embedded photodiode (50 in FIG. 1A, 64 in FIG. 2, etc.), and an electron / hole pair is generated due to the photoelectric conversion effect. Holes accumulate in the buried p ^- type region 49 of the diode. At this time, the potential of the transfer gate electrode 51 is the same as the drain potential Vdd, and the transfer gate MOSFET 65 is off. These accumulations are performed at the same time as the previous frame read operation is being performed.

  In the subsequent period shown in FIG. 3 (2), when the reading of the previous frame is completed, a new frame start signal is transmitted as shown in FIG. First, all the pixels are performed simultaneously from the photodiode (50 in FIG. 1A, 64 in FIG. 2 etc.) to the p-type region (47 in FIG. 1) near the source of the ring-shaped gate electrode (45 in FIG. 1). It is to transfer the hole. Therefore, as shown in FIG. 3B, the transfer gate control signal output from the transfer gate potential control circuit 72 falls from Vdd to Low2, the potential of the transfer gate electrode (41 in FIG. 1) becomes Low2, and the transfer gate MOSFET 65 Turns on.

  At this time, the potential of the ring-shaped gate electrode wiring 69 controlled by the ring-shaped gate potential control circuit 70 changes from Low to Low1 as shown in FIG. 3C, but Low2 is larger than Low1. Low1 may be the same as Low. Most simply, Low1 = Low = 0 (V) is set.

  On the other hand, the source potential of all the pixels including the source potential supplied from the source potential control circuit 75 to the source of the ring-shaped gate MOSFET 63 from the source electrode wiring 74 through the switch SW1 is as shown in FIG. The potential is set to S1. S1> Low1, which keeps the ring-shaped gate MOSFET 63 off and prevents current from flowing. As a result, charges (holes) accumulated in the photodiodes of all the pixels are transferred all at once under the ring-shaped gate electrodes of the corresponding pixels.

  In the region below the ring-shaped gate electrode 45 shown in FIG. 1B, the p-type region 47 near the source has the lowest potential, so the holes accumulated in the photodiode reach the p-type region 47 near the source. Accumulated in. As a result of the accumulation of holes, the potential of the p-type region 47 near the source rises.

Subsequently, in the period shown in FIG. 3 (3), the transfer gate electrode becomes Vdd again and the transfer gate MOSFET 65 is turned off as shown in FIG. 3 (B). As a result, in the photodiode (50 in FIG. 1A, 64 in FIG. 2, etc.), electron-hole pairs are generated again due to the photoelectric conversion effect, and holes start to be accumulated in the buried p ⁻ -type region 49 of the photodiode. This accumulation operation is continued until the next charge transfer.

  On the other hand, since the reading operation is sequentially performed in units of rows, the potential of the ring-shaped gate electrode is low as shown in FIG. 3C in the period (3) in which the first to (s−1) th rows are read. In this state, a standby state is entered with holes accumulated in the p-type region 47 near the source. The source potential can take various values depending on the value of the signal from the pixel while the signal is read from another row. The ring-shaped gate electrode potential can take various values for each row, but is set to Low in the s-th row, and the ring-shaped gate MOSFET 63 is in an off state.

  In the subsequent period shown in FIGS. 3 (4) to (6), pixel signal readout is performed. This signal readout operation will be described representatively for the pixel 62 in the s-th row and the t-th column. First, in a state where holes are accumulated in the p-type region 47 near the source, the vertical shift register 68 shown in FIG. In the period (4) in which the output signal is at a low level as shown in FIG. 5H, the ring-shaped gate electrode 45 is controlled by the control signal output from the ring-shaped gate potential control circuit 70 to the ring-shaped gate electrode wiring 69. Is increased from Low to Vg1, as shown in FIG.

Here, the potential Vg1 is between the potentials Low, Low1, and Vdd described above.
Low ≦ Low1 ≦ Vg1 ≦ Vdd (where Low <Vdd)
Is an electric potential that holds the inequality. In the period (4), the switch SW1 is turned off as shown in FIG. 3I, the switch SW2 is turned on as shown in FIG. 3J, and the switch sc1 is turned on as shown in FIG. The switch sc2 is turned off as shown in FIG. As a result, the source follower circuit connected to the source of the ring-shaped gate MOSFET 63 works, and the source potential of the ring-shaped gate MOSFET 63 is S2 (= Vg1-Vth1) in the period (4) as shown in FIG. Become. Here, Vth1 is a threshold voltage of the ring-shaped gate MOSFET 63 in a state in which there is a hole in the back gate (p-type region 47 near the source). The source potential S2 is stored in the capacitor C1 through the switch sc1 that is turned on.

  In the subsequent period shown in FIG. 3 (5), the potential of the ring-shaped gate electrode 45 is set as shown in FIG. 3 (K) by the control signal output from the ring-shaped gate potential control circuit 70 to the ring-shaped gate electrode wiring 69. At the same time as raising to High1, the switch SW1 is turned on and the switch SW2 is turned off as shown in FIGS. 1I and 1J, and the source potential output from the source potential control circuit 75 is shown in FIG. Raise to Highs as shown. Here, High1 and Highs> Low1.

  The values of the potentials High1 and Highs may be the same or different, but High1 and Highs ≦ Vdd are desirable for simplicity of design. In a simple setting, High1 = Highs = Vdd. Further, it is desirable to set the potential so that the ring-shaped gate MOSFET 63 is turned on and no current flows. As a result, the potential of the p-type region 47 near the source rises, and holes are discharged to the epitaxial layer 42 beyond the barrier of the n-well 43 (reset).

  In the subsequent period shown in FIG. 3 (6), the same signal readout state as in the period (4) is set again. However, unlike the period (4), as shown in FIGS. 3M and 3N, the switch sc1 is turned off and the switch sc2 is turned on. The ring-shaped gate electrode has the same Vg1 as that in the period (4) as shown in FIG. However, in this period (6), holes are discharged to the substrate in the immediately preceding period (5), and no holes are present in the p-type region 47 near the source, so the source potential of the ring-shaped gate MOSFET 63 is as shown in FIG. L), the period (6) is S0 (= Vg1-Vth0). Here, Vth0 is the threshold voltage of the ring-shaped gate MOSFET 63 in a state where there is no hole in the back gate (p-type region 47 near the source).

  The source potential S0 is stored in the capacitor C2 through the switch sc2 that is turned on. The differential amplifier 78 outputs the potential difference between the capacitors C1 and C2. That is, the differential amplifier 78 outputs (Vth0−Vth1). This output value (Vth0-Vth1) is a change in threshold value due to hole charge. Thereafter, among the pulses shown in FIG. 3F output from the horizontal shift register 79, the output switch swt shown in FIG. 2 is turned on based on the output pulse in the t-th column shown in FIG. During the ON period, as schematically shown by hatching in FIG. 3P, the threshold value change due to the Hall charge from the differential amplifier 78 is output to the outside of the sensor as the output signal Vout of the pixel 62.

  Subsequently, in the period indicated by (7) in FIG. 3, the potential of the ring-shaped gate electrode 45 is set to low again as shown in FIG. 3 (B), and all of the p-type region 47 near the source has no holes. It waits until the signal processing of the next row is completed (until the readout of the pixels of the s + 1 row to the nth row is completed). During these readout periods, the photodiode 64 is accumulating holes due to the photoelectric conversion effect. Thereafter, the process returns to the period (1) and repeats from the hole transfer. As a result, the output signal shown in FIG. 3G is read from each pixel.

  In the solid-state imaging device having the configuration shown in FIGS. 1A and 1B, the ring-shaped gate MOSFET 63 having the ring-shaped gate electrode 45 is an amplification MOSFET. As shown in FIG. It is a kind of CMOS sensor in the sense that it has an amplifying MOSFET. In this CMOS sensor, the charge (hole) accumulated in the photodiode is transferred to the p-type region 47 in the vicinity of the source under the ring-shaped gate electrode of the corresponding pixel at the same time. Is realized.

  Note that the potential supply of the source electrode wiring 74 at the time of resetting in the period (5) of FIG. That is, in the period (5), both the switches SW1 and SW2 are turned off, and the source electrode wiring 74 is floated. Here, when the potential of the ring-shaped gate electrode wiring 69 is High1, the ring-shaped gate MOSFET 63 is turned on, current is supplied from the drain to the source electrode, and the source electrode potential rises. As a result, the potential of the p-type region 47 in the vicinity of the source is raised, and holes are discharged to the p-type epitaxial layer 42 beyond the barrier of the n-well 43 (reset). The source electrode potential when the holes are completely discharged becomes High1-Vth0. This method can reduce the number of transistors that supply Highs in the source potential control circuit 75, and as a result, the chip area can be reduced.

Next, layout images of the ring-shaped gate potential control circuit 70 and the transfer gate potential control circuit 72 of the solid-state imaging device represented by the equivalent circuit shown in FIG. 2 with the structure shown in FIGS. Will be described with reference to FIG. 4, the same components as those in FIG. 2 are denoted by the same reference numerals, and the description thereof is omitted. In FIG. 4, assuming that pixels in m rows and n columns are arranged in the pixel covering region 61, a ring-shaped gate potential control circuit 70 is connected for each pixel in each row. That is, the first row ring-shaped gate potential control circuit 70-1 is connected to the pixels 33 _{11 to} 33 _1n in the first row via the first row ring-shaped gate electrode wiring 69-1, and each of the m-th row. An m-th ring-shaped gate potential control circuit 70-m is connected to each of the pixels 33 _{m1 to} 33 _mn via an m-th ring-shaped gate electrode wiring 69-m.

  Further, the transfer gate potential control circuit 72 is depicted in FIG. 2 such that there is a transfer gate potential control circuit in each row, but actually, as shown in FIG. It is commonly connected to all n pixels via a transfer gate electrode wiring 71. This is because the operation of the transfer gate electrode of the pixel is simultaneous for all the pixels at all timings, as can be seen from the timing chart of FIG. Therefore, as shown in FIG. 4, the transfer gate potential control circuit 72 is arranged at one place and outputs the same signal simultaneously. Further, the transfer gate potential control circuit 72 is connected to the frame start signal generation circuit 67.

  The output signal of the vertical shift register 68 is supplied to the ring-shaped gate potential control circuits 70-1 to 70-m of each row. This signal becomes a start signal to the ring-shaped gate potential control circuits 70-1 to 70-m. The power supply unit 30 has a configuration in which the three power supplies that generate the voltages Vdd, Low, and Vg1 described with reference to FIG. 3 are collectively arranged at one place, and m ring-shaped gate potential control circuits 70- A voltage is supplied through a power supply wiring group 31 in which wirings of each power supply (three power supply wirings in the figure) are collectively shown at 1 to 70-m. The power supply unit 30 supplies a voltage to the transfer gate potential control circuit 41 through a power supply wiring group 32 in which wirings of each power supply (two power supply wirings of Vdd and Low in the drawing) are collectively shown.

  FIG. 5 shows a block diagram of an embodiment of the ring-shaped gate potential control circuit 70 (70-1 to 70-m in FIG. 4). In the figure, the same components as in FIG. In FIG. 5, a ring-shaped gate potential control circuit 70 includes a signal switching control circuit 701 to which a signal from a vertical shift register 68 is supplied and an analog switch circuit 702 having a CMOS structure for switching the potential of a signal supplied to a pixel. .

  A switch switching signal 703 is input from the signal switching control circuit 701 to the analog switch circuit 702. The power supply unit 30 supplies a voltage to the analog switch circuit 702. The ring-shaped gate electrode control signal 704 output from the analog switch circuit 702 changes the signal potential by the switch switching signal 703. In FIG. 5, the ring-shaped gate potential control circuit 70 has been described as a configuration example. However, the transfer gate potential control circuit 72 and other control circuits (73, 75, etc. in FIG. 2) are similar to the signal switching control circuit as in FIG. It consists of an analog switch circuit.

  FIG. 6 shows a circuit diagram of an example of the analog switch circuit 702 in FIG. The analog switch circuit 702 includes analog switches 81, 82, and 83 having a CMOS circuit structure composed of an n-channel MOSFET and a p-channel MOSFET in which the sources and drains are connected to each other, and n of each analog switch 81, 82, and 83. It comprises inverters 84, 85, 86 that supply output signals to the gates of the channel MOSFETs.

  One of the connection points of each of the two MOSFETs of the analog switches 81, 82, and 83 is connected to each other, and the other is connected to the power supply voltage Low for the analog switch 81, the power supply voltage Vg 1 for the analog switch 82, and the power supply voltage Vdd ( High1) is connected. An arbitrary signal potential can be supplied to the pixel by controlling the gate potential of the MOSFETs constituting the analog switches 81, 82, and 83.

  Next, the operation of the analog switch circuit 702 will be described. For example, a potential low switching signal 87, a potential Vg1 switching signal 88, and a potential High1 (Vdd) switching signal 89 are supplied from the signal switching circuit 701 to the analog switch circuit 702, and the voltage source Low and voltage source High ( Vdd), assuming that the voltage source Vg1 is connected, in order to set the potential of the ring-shaped gate electrode to Low, the potential Low switching signal 87 is set to “L” and the voltage Low from the voltage source 30 is set to the signal potential. The analog switch 81 is turned on so as to be selected. At this time, the other switching signals 88 and 88 are set to “H”, and the analog switches 82 and 83 are turned off. As a result, the potential of the output signal supplied from the analog switch circuit 702 to the ring-shaped gate electrode in the corresponding row of the pixel portion is Low. Similarly, when the potential of the ring-shaped gate electrode is set to the voltage High 1 (Vdd), only the analog switch 83 is turned on, and only the analog switch 82 is turned on to set the potential of the voltage Vg 1.

  In FIG. 4, only the layout of the ring-shaped gate potential control circuits 70-1 to 70-m and the transfer gate potential control circuit 72 has been described for the sake of simplicity. As described above, the drain control potential circuit 73 and the source potential control circuit 75 are also laid out in this solid-state imaging device. Therefore, in addition to the transfer gate electrode wiring 71 and the ring-shaped gate electrode wiring 69 (69-1 to 69-m), the drain electrode wiring 66 and the source electrode wiring 74 are connected to the pixel covering area 61 shown in FIG. ing. As a result, there arises a problem between the wirings in the layout similar to the conventional technique described above.

  For this reason, for example, the potential of the signal output from the ring-shaped gate potential control circuit 70 to the ring-shaped gate electrode wiring 69 in accordance with the readout from the pixel in the column with s rows is as shown in FIG. As shown in A), when changing to Low, Vg1, and High1, the potential of the adjacent transfer gate electrode wiring 71 should ideally be maintained at High1 as shown in FIG. However, if the distance (interval) between the ring-shaped gate electrode wiring 69 and the transfer gate electrode wiring 71 in the s-th row in FIG. 2 is short depending on the layout state, the ring-shaped gate electrode wiring 69 and the transfer gate electrode wiring 71 The equivalent circuit of the differential circuit described with reference to FIG. 13 is generated between the transfer gate electrode wiring 71 and the s-th ring-shaped gate electrode wiring 71 on the transfer gate electrode wiring 71 along with the steep change in potential shown in FIG. Produces a differential pulse as shown in FIG.

  As a result, when a differential pulse that instantaneously drops from the potential High1 to the vicinity of Low is generated, the pixels in the s-1 and s + 1 rows adjacent to the sth row are the photodiodes described in (2) of FIG. There is a risk of performing the same operation as the charge transfer from. This is because the transfer gate electrode wiring 71 is connected to all the pixels, which causes the differential pulse to spread to the pixels in each row. As described above, the transfer of charges during accumulation during the reading operation of each pixel means that data (noise) other than the original data is read from each pixel. As a result, the differential pulse generated by a sharp change in potential causes deterioration of the pixel data.

  Therefore, in this embodiment, the signal switching control circuit 701 constituting the ring-shaped gate potential control circuit 70 (70-1 to 70-m) shown in FIG. 5 is configured as shown in FIG. FIG. 8 is a block diagram of a signal switching control circuit 701 that realizes an embodiment of a method for driving a solid-state imaging device according to the present invention. In FIG. 8, the central processing unit (CPU) 91 supplies a potential High1 (Vdd) switching signal on position information holding circuit 92, a potential Low switching signal on position information holding circuit 93, and a potential Vg1 switching signal on position information holding circuit 94, respectively. Predetermined ON position information is held. The switching signal ON position can be variably adjusted to an optimal position for reducing the above-described crosstalk by the CPU 91.

  The counter 95 counts up in synchronization with the signal output from the vertical shift register 68 shown in FIG. 2 and supplies the count value to the comparison circuit 96. The comparison circuit 96 individually compares the count value from the counter 95 and the output signals (reference values) of the switching signal ON position information holding circuits 92 to 94, and selects the selectors 97, 98, and 99 according to the comparison result. Control individually. The selectors 97, 98, and 99 generate a level “H” or “L” switching signal based on the select signal from the comparison circuit 96.

  Thus, for example, in the control period of the pixels in the corresponding row, as shown in FIG. 9B, the “L” potential Vg1 switching signal is output from the selector 99 at time t1, and from the selector 98 at time t1. As shown in FIG. 9A, an “L” potential Low switching signal is output, and from the selector 97, an “H” potential High 1 (Vdd) switching signal is output as shown in FIG. The Thereby, the analog switches 81 and 82 in FIG. 6 are simultaneously turned on from time t1.

  Subsequently, as shown in FIG. 9 (A) at time t2, only the potential Low switching signal output from the selector 98 is switched to “L”, and at time t3, as shown in FIG. 9 (C), the selector 97 Only the potential High1 (Vdd) switching signal output from is switched to “H”. Accordingly, from time t2 to immediately before time t3, the analog switch 81 in FIG. 6 is switched from on to off, and the analog switch 82 continues to be on, and from time t3, the analog switches 82 and 83 are simultaneously turned on. .

  At subsequent time t4, as shown in FIG. 9B, the potential Vg1 switching signal output from the selector 95 is switched to “H”, and then switched to “L” at time t5. At time t6, as shown in FIG. 9C, only the potential High1 (Vdd) switching signal output from the selector 97 is switched to “H”, and at time t7, as shown in FIG. Is switched to “L”, and the potential Vg1 switching signal shown in FIG. 5B is switched to “H” at time t8.

  Accordingly, only the analog switch 83 of FIG. 6 is turned on from time t4 to immediately before time t5, and the analog switches 82 and 83 are simultaneously turned on from time t5 to immediately before time t6, and from time t6 to time t7. Until just before, only the analog switch 82 is turned on, from time t7 to just before time t8, the analog switches 81 and 82 are turned on simultaneously, and after time t8, only the analog switch 81 is turned on.

  Here, since only the analog switch 81 is in the on state before the time t1 and after the time t8, as can be seen from FIG. 6, the ring-shaped gate potential control signal output from the ring-shaped gate potential control circuit 70 is as shown in FIG. As shown in (D), the potential is Low. Further, in each period immediately before time t2 to time t3 and immediately before time t6 to time 7, only the analog switch 82 is in an on state, so that the ring-shaped gate potential control signal is as shown in FIG. Furthermore, the potential is Vg1. Further, since only the analog switch 83 is in an on state in the period from time t4 to immediately before time t5, the ring-shaped gate potential control signal is at the potential High1 (Vdd) as shown in FIG. 9D. .

  On the other hand, in the periods T1 and T4 from time t1 to immediately before time t2 and from time t7 to immediately before time t8, the analog switches 81 and 82 are simultaneously turned on, and from time t3 to time t4. Since the analog switches 82 and 83 are simultaneously turned on in the periods T2 and T3 from immediately before and immediately before time t5 to time t6, the output potential of the ring-shaped gate potential control circuit 70 is in the periods T1 and T4. Is an intermediate potential between the potentials Low and Vg1, and is an intermediate potential between the potentials Vg1 and High1 (Vdd) in the periods T2 and T3.

  This will be described in more detail with reference to FIG. For example, if the analog switches 82 and 83 shown in FIG. 6 are turned on at the same time, the analog switch circuit 702 has a resistor 102 (resistance value R2) when the analog switch 83 is on as shown in FIG. ) And a resistor 101 (resistance value R1) when the analog switch 82 is in an on state are connected in series, represented by a series circuit in which the voltage High1 (Vdd) is applied to one end and the voltage Vg1 is applied to the other end. it can. In this series circuit, since High 1 (Vdd)> Vg 1, current I flows in the direction of the arrow in FIG. 10, and is applied to the ring-shaped gate electrode of the pixel in the corresponding row from the connection point of resistors 101 and 102. Potential V to be taken out.

  Here, when there is a potential difference of High1 (Vdd)> V> Vg1, the potential V is expressed by the following equation. Since High1 = Vdd, High1 (Vdd) will be described below as High1.

V = High1-R2 · I (1)
The current I is expressed by the following equation.

I = (High1-Vg1) / (R1 + R2) (2)
Therefore, the following equation is established from the equations (1) and (2).

V = High1-R2 · {(High1-Vg1) / (R1 + R2)}
= (High1 · R1 + Vg1 · R2) / (R1 + R2) (3)
Here, the resistance values R1 and R2 when the analog switches 82 and 83 are on are equal because the analog switches 82 and 83 are made under the same process conditions. Therefore, the expression (3) is expressed by the following expression.

V = (High1 + Vg1) / 2 (4)
Therefore, when the analog switches 82 and 83 are simultaneously turned on, the output potential Vg1 when only the analog switch 82 is turned on from the equation (4), and the output potential High1 when only the analog switch 83 is turned on. A potential that is ½ times the sum of these is output. As a result, according to the present embodiment, as shown in FIG. 9D, the ring-shaped gate potential control circuit 70 has the staircase shape shown in FIGS. 3K, 7A, and 7C. A step-shaped ring-shaped gate potential control signal having a smaller step than the ring-shaped gate potential control signal can be generated.

  The potential switching signals 87 to 89 output from the signal switching control circuit 701 are shown in FIGS. 3 (K), 7 (A), and (C) so that the analog switches 81 to 83 are not simultaneously turned on. A ring-shaped gate electrode control signal having a three-step staircase waveform is generated, and the ring-shaped gate MOSFET 63 can be operated in a predetermined manner by the ring-shaped gate electrode control signal. However, since the above-mentioned ring-shaped gate electrode control signal has a large step and changes sharply, as described above, adjacent wirings (ring-shaped gate electrode wiring and transfer gate electrode wiring 71 in the case of FIG. 4). ) Occurs.

  On the other hand, in this embodiment, by appropriately providing a period in which two analog switches in the on state among the analog switches 81 to 83 exist at the same time, a five-step staircase waveform as shown in FIG. Since the ring-shaped gate electrode control signal with a small potential change is generated, the same effect as the waveform is smoothed by using the integration circuit to prevent the abrupt change in potential described with reference to FIG. And the influence of crosstalk on other wirings can be reduced. As a result, it is possible to prevent readout of noise transferred by charge due to malfunction due to crosstalk between wirings. In this embodiment, since the reduction of crosstalk can be realized without using the integration circuit described in the conventional example, an increase in circuit scale can be prevented, and a reduction in driving capability can also be prevented.

  Note that the present invention is not limited to the above-described embodiment, and the ring-shaped gate potential control circuit 70 has been described in the above-described embodiment, but in the transfer gate potential control circuit 72, the source potential control circuit 75, and the like. However, crosstalk between the wirings can be reduced by adopting the same configuration as that of the embodiment. In the above embodiment, the crosstalk reduction of the solid-state imaging device of FIG. 1 represented by the equivalent circuit shown in FIG. 2 has been described. However, the crosstalk reduction of the conventional solid-state imaging device shown in FIG. Of course, it can be done in the same way.

FIG. 4 is a top view and a longitudinal sectional view of an example of one pixel of a solid-state imaging device to which the driving method of the solid-state imaging device of the present invention is applied. FIG. 2 is an equivalent circuit diagram of an example of the solid-state imaging device of FIG. 1. 3 is a timing chart for explaining the operation of FIG. 2. 3 is a layout image of a ring-shaped gate potential control circuit and a transfer gate potential control circuit of the solid-state imaging device of FIGS. 1 and 2. FIG. 5 is a block diagram of an example of a ring-shaped gate potential control circuit of FIGS. 2 and 4. FIG. 6 is a circuit diagram of an example of an analog switch circuit in FIG. 5. It is explanatory drawing of the problem between wiring in the layout which generate | occur | produces in the solid-state imaging device of FIG.1 and FIG.2. 1 is a block diagram of a signal switching control circuit that realizes an embodiment of a method for driving a solid-state imaging device of the present invention. 9 is a timing chart for explaining the operation of FIG. 8. 6 is an equivalent circuit diagram of FIG. 6 for explaining the potential of the output ring-shaped gate electrode control signal of FIG. 5 when two analog switches are simultaneously turned on in FIG. It is a block diagram of an example of the conventional solid-state imaging device. FIG. 12 is a circuit diagram of one pixel in FIG. 11. It is explanatory drawing of the problem between wiring in the layout which generate | occur | produces in a solid-state imaging device. It is a figure which shows the integration circuit using RC for solving the problem between the wiring in a layout conventionally, its input waveform, and an output waveform. It is a wave form chart for explanation of a problem which arises when capacity is loaded to ring-shaped gate electrode wiring.

Explanation of symbols

30 Power supply part 43 n well 45 ring-shaped gate electrode 46 n ⁺ type source region 47 source near p type region 48 n ⁺ type drain region 49 buried p ⁻ type region 50, 64 photodiode 51 transfer gate electrode 52, 66 drain electrode wiring 53, 69 Ring-shaped gate electrode wiring 54, 74 Source electrode wiring (output line)
55, 71 Transfer gate electrode wiring 61 Pixel covering area 62 Pixel 63 Ring-shaped gate MOSFET
65 Transfer gate MOSFET
70, 70-1 to 70-m Ring-shaped gate potential control circuit 72 Transfer gate potential control circuit 73 Drain potential control circuit 75 Source potential control circuit 81-83 Analog switch 91 Central processing unit (CPU)
92 electric potential High1 (Vdd) switching ON position information holding circuit 93 electric potential Low switching ON position information holding circuit 94 electric potential Vg1 switching ON position information holding circuit 96 comparison circuit 97 to 99 selector 701 signal switching control circuit 702 analog switch circuit

Claims (2)

A photodiode that photoelectrically converts light to accumulate charge, a charge transfer transistor that transfers charge accumulated in the photodiode during an exposure period during a readout period, and the charge transferred through the charge transfer transistor as a signal output line A method of driving a solid-state imaging device in which a pixel composed of a signal output transistor having an amplification function for outputting as a change in threshold value has a plurality of regularly arranged pixel covering regions,
The signal output transistor is controlled by a control signal having a staircase waveform that is transmitted through the first wiring and whose level changes stepwise in M steps (M is a natural number of 2 or more). When performing a predetermined operation for outputting the amount of charge input through the charge transfer transistor whose operation is controlled by a transfer control signal to be transmitted as a change in threshold value, there is an intermediate between each of the M stages. N step (N is a natural number greater than M) staircase waveform having a level step and variably setting a switching time position to the intermediate level is generated as the control signal, and the signal output is performed by the control signal. A driving method for a solid-state imaging device, wherein the driving transistor is controlled to be driven. The signal output transistor includes a ring-shaped gate electrode on a substrate, a source region provided at a position of the substrate corresponding to a central opening of the ring-shaped gate electrode, the source region surrounding the source region, and the ring Near the source provided in the substrate so as not to reach the outer periphery of the gate electrode, and the charge transfer transistor converts the charge accumulated in the photodiode into the corresponding source neighborhood in the same pixel. 2. The method of driving a solid-state imaging device according to claim 1, wherein all of the pixels are transferred simultaneously, and the signal output transistor operates by supplying the N-stage control signal to the ring-shaped gate electrode.

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