JP2007295377A - Signal strength detection circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that an output characteristic of a signal strength detection circuit is varied by fluctuation of power supply voltage. <P>SOLUTION: The signal strength detection circuit is driven by the power supply voltage Vdd, and comprises: saturation differential amplification circuits 60-1 to 60-n which sequentially amplify input voltage Vin, and are continuously connected at a plurality of steps; full-wave rectifiers 80-1 to 80-n which rectify signals amplified by the saturation differential amplification circuits 60-1 to 60-n at each step, respectively; a current mirror circuit 100 for finding a signal strength detection current IO of an a sum of output currents of the full-wave rectifiers 80-1 to 80-n at each step; and a power supply voltage fluctuation suppressing circuit 110 which depends on the power supply voltage Vdd to change the amount of the current. Further, the output current of the circuit 110 is added to the signal strength detection current IO, and thus, power supply voltage dependency is reduced in the signal strength detection voltage Vrssi. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a signal strength detection circuit that detects the strength of a carrier signal such as a reception signal or a transmission signal in a communication reception device such as a television, radio, CATV, or radio.

  Conventionally, as a technique related to this type of signal intensity detection circuit, for example, there is one described in the following documents.

JP 7-30353 A

FIG. 6 is a configuration diagram of a conventional signal strength detection circuit described in Patent Document 1 and the like.
The signal strength detection circuit has input terminals 1 and 2 for inputting an input voltage Vin, and a plurality (n) stages of saturated differential amplifier circuits 10-1 to 10-n are cascaded to the input terminals 1 and 2. The output terminals 21 and 22 that output the output voltage Vout are connected to the last stage saturated differential amplifier circuit 10-n. Half-wave rectifiers 30-1 to 30- (n + 1) are respectively connected to the input terminals of the saturated differential amplifier circuits 10-1 to 10-n at each stage, and the (n + 1) -stage half-wave rectifier 30-0 is connected thereto. A current mirror circuit 40 including P-channel MOS transistors (hereinafter referred to as “PMOS”) 41 and 42 is connected to output terminals of ˜30-n. The output terminal of the current mirror circuit 40 is grounded via an output terminal 43 that outputs the signal strength detection voltage Vrssi and a current / voltage conversion resistor 44.

  The half-wave rectifiers 30-1 to 30- (n + 1) at each stage include a constant voltage source 31 that applies a DC offset voltage Vos to one input terminal of each of the saturated differential amplifier circuits 10-1 to 10-n, and a power source A pair of PMOSs 32 and 33 for load to which the voltage Vdd is applied, a capacitor 34 for rectifying the differential output current, and a gate by the voltage of the other input terminal of each of the saturated differential amplifiers 10-1 to 10-n. A differential pair consisting of an N-channel MOS transistor (hereinafter referred to as “NMOS”) 35 to be controlled and an NMOS 36 gate-controlled by a voltage on the constant voltage source 31 side, and a constant current I to this differential pair. And a constant current source 37 for flowing.

  In the signal strength detection circuit having such a configuration, when an input voltage Vin such as an intermediate frequency signal is input from the input terminals 1 and 2, the input voltage Vin is supplied to the saturated differential amplifier circuits 10-1 to 10 in each stage. The differential output is sequentially amplified by −n, and the amplified output voltage Vout is output from the output terminals 21 and 22. The signals amplified by the saturated differential amplifier circuits 10-1 to 10-n at each stage are input to the half-wave rectifiers 30-1 to 30- (n + 1), respectively. The sum of the output currents of the half-wave rectifiers 30-1 to 30- (n + 1) at each stage is converted into a voltage by the resistor 44 via the current mirror circuit 40, and the signal strength detection voltage Vrssi is output from the output terminal 43. .

  Here, if the gains of the saturated differential amplifier circuits 10-1 to 10-n at each stage are all the same, the gain of the second stage is the square of the gain of the first stage, and the (n-1) stage is Since the output voltage increases exponentially to the nth power of the (n-1) th power and the nth power, and the weight of the nth power is added, the signal strength detection voltage Vrssi that is the sum is the dBm of the input signal power. It will increase linearly with increasing unit.

FIG. 7 is a block diagram showing an example of the saturated differential amplifier circuit in FIG.
The saturation differential amplifier circuit 10 is a circuit that is generally used in the prior art, and includes input terminals 11 and 12 for inputting two input voltages, load resistors 13 and 14 to which a power supply voltage Vdd is applied, Output terminals 15 and 16 connected to one end thereof, differential input NMOSs 17 and 18 gate-controlled by input voltages input from the input terminals 11 and 12, and a constant current to the NMOSs 17 and 18. It is comprised by NMOS19 for the constant current source to flow. In the saturated differential amplifier circuit 10 having such a configuration, two input voltages input to the input terminals 11 and 12 are differentially amplified by the NMOSs 17 and 18, and the amplified voltages are output from the output terminals 15 and 16. Is done.

  In the conventional signal strength detection circuit as shown in FIG. 6, when the saturation differential amplifier circuit 10 as shown in FIG. 7 that is generally used is used for each of the saturation differential amplifier circuits 10-1 to 10-n, The output voltage V1, V2,..., Vout of the saturation differential amplifier circuits 10-1, 10-2,. The saturation amplitude and gain fluctuate due to non-constant current characteristics due to the channel length modulation effect. In other words, in the case of an amplifier circuit in which the gain or saturation amplitude of the saturated differential amplifier circuit 10 is dependent on the power supply voltage, there has been a problem that the output characteristics of the signal strength detection circuit vary greatly depending on the power supply voltage Vdd.

  The signal strength detection circuit of the present invention is driven by a power supply voltage, and a plurality of cascaded saturation amplification circuits that sequentially amplify an input signal, and a plurality of signals that rectify signals amplified by the saturation amplification circuits of the respective stages. A stage rectifier, a circuit for obtaining a signal strength detection current that is a sum of output currents of the rectifiers of the respective stages, and a power supply voltage that adds a current whose amount of current changes depending on the power supply voltage to the signal strength detection current And a fluctuation suppression circuit.

  According to the present invention, the voltage fluctuation suppression circuit in which the amount of current changes depending on the power supply voltage is provided, and this output current is added to the signal strength detection current. As a result, the dependence of the signal strength detection output on the power supply voltage can be reduced.

  The signal strength detection circuit is driven by a power supply voltage, and rectifies signals amplified by a plurality of cascaded saturated differential amplifier circuits that sequentially amplify an input signal and signals amplified by the saturated differential amplifier circuits of the respective stages. A multi-stage full-wave rectifier, a current mirror circuit for obtaining a signal intensity detection current that is a sum of output currents of the full-wave rectifiers of each stage, and a current whose current amount varies depending on the power supply voltage. A power supply voltage fluctuation suppressing circuit for adding to the detected current.

(Configuration of Example 1)
FIG. 1 is a configuration diagram of a signal strength detection circuit showing Embodiment 1 of the present invention.

  This signal strength detection circuit has a pair of input terminals 51 and 52 for inputting an input signal (for example, input voltage) Vin, and a plurality of (n) stage saturation amplifier circuits (for example, for example) Saturation differential amplifier circuit) 60-1 to 60-n are cascade-connected. Rectifiers (for example, full-wave rectifiers) 80-1 to 80-n are connected to the output terminals of the saturated differential amplifier circuits 60-1 to 60-n at the respective stages.

  That is, one input terminal 51 is connected to the (+) input terminal of the first stage (first stage) saturated differential amplifier circuit 60-1, and the other input terminal 52 is connected to the saturated differential amplifier circuit 60-1. Connected to the (-) input terminal. The (+) output terminal of the saturated differential amplifier circuit 60-1 is connected to the (+) input terminal of the second stage saturated differential amplifier circuit 60-2 and one input of the full-wave rectifier 80-1. The (−) output terminal of the saturated differential amplifier circuit 60-1 is connected to the (−) input terminal of the second stage saturated differential amplifier circuit 60-2, and the full-wave rectifier 80- 1 is connected to the other input terminal. The (+) output terminal of the saturated differential amplifier circuit 60-2 is connected to the (+) input terminal of the third stage saturated differential amplifier circuit 60-3 and one input of the full-wave rectifier 80-2. Connected to the terminal. The (−) output terminal of the saturated differential amplifier circuit 60-2 is connected to the (−) input terminal of the third stage saturated differential amplifier circuit 60-3 and the other input of the full-wave rectifier 80-2. Connected to the terminal.

  The same connection is repeated, and the (+) output terminal of the saturation differential amplifier circuit 60-n at the final stage is connected to an output terminal 71 that outputs an output signal (for example, output voltage) Vout, and a full-wave rectifier 80. The (−) output terminal of the saturated differential amplifier circuit 60-n is connected to an output terminal 72 that outputs an output signal (for example, output voltage) Vout, and is connected to one input terminal of −n. It is connected to the other input terminal of the rectifier 80-n.

  The saturated differential amplifier circuits 60-1 to 60-n in each stage are configured by, for example, the saturated differential amplifier circuit 10 in FIG.

  All the output terminals of the full-wave rectifiers 80-1 to 80-n are connected to the drain terminal and gate terminal of the PMOS 101 and the gate terminal of the PMOS 102 in the current mirror circuit 100 including the PMOSs 101 and 102. A feature of the first embodiment is that a power supply voltage fluctuation suppressing circuit 110 is connected to the current mirror circuit 100. The power supply voltage fluctuation suppressing circuit 110 includes a current mirror circuit composed of PMOSs 111 and 112 and a resistor 113 connected in series with a node N on the drain terminal side of the PMOS 111.

  All the output terminals of the full-wave rectifiers 80-1 to 80-n are also connected to the drain terminal of the PMOS 112. The PMOS 112 has a source terminal connected to a power supply voltage terminal to which a power supply voltage Vdd is applied (hereinafter referred to as “Vdd terminal”), and a gate terminal connected to the gate terminal and drain terminal of the PMOS 111 and one terminal of the resistor 113. It is connected. The source terminal of the PMOS 111 is connected to the Vdd terminal, and the other terminal of the resistor 113 is grounded.

  The source terminal of the PMOS 101 constituting the current mirror circuit 100 is connected to the Vdd terminal. The PMOS 102 has a source terminal connected to the Vdd terminal, a drain terminal connected to the output terminal 103 for outputting the signal strength detection voltage Vrssi, and also connected to one terminal of the resistor 104 for current / voltage conversion. ing. The other terminal of the resistor 104 is grounded.

  The output currents of the full-wave rectifiers 80-1 to 80-n are IB1, IB2,..., IBn, respectively, and the sum of these output currents is IO. The current flowing between the drain and source of the PMOS 101 is I1, the current flowing between the drain and source of the PMOS 102 is I2, the current flowing between the drain and source of the PMOS 111 is I3, and the current flowing between the drain and source of the PMOS 112 is I4. To do.

FIG. 2 is a configuration diagram illustrating an example of each of the full-wave rectifiers 80-1 to 80-n in FIG.
The full-wave rectifier 80 includes a pair of input terminals 81 and 82, a load resistor PMOS 83, an output terminal 84, differential input NMOSs 85 and 86, a constant current source 87 for supplying a constant current I11, and a differential input NMOS 88. , 89 and a constant current source 90 for supplying a constant current I12.

  The gate terminal of the NMOS 85 is connected to the input terminal 81 and is also connected to the gate terminal of the NMOS 89. The gate terminal of the NMOS 86 is connected to the input terminal 82 and is also connected to the gate terminal of the NMOS 88. The source terminal of the NMOS transistor 85 is connected to the source terminal of the NMOS 86 and to the input terminal of the constant current source 87. The output terminal of the constant current source 87 is grounded. The source terminal of the NMOS 88 is connected to the source terminal of the NMOS 89 and to the input terminal of the constant current source 90. The output terminal of the constant current source 90 is grounded.

  The drain terminal of the NMOS 85 is connected to the drain terminal of the NMOS 88 and to the drain terminal and the gate terminal of the PMOS 83. The source terminal of the PMOS 83 is connected to the Vdd terminal. The drain terminal of the NMOS 86 is connected to the output terminal 84 and is also connected to the drain terminal of the NMOS 89.

  Note that NMOS 85 and 86 and NMOS 88 and 89 have different transistor sizes.

(Operation of Example 1)
The basic operation (A) of the signal intensity detection circuit in the first embodiment and the operation (B) when the power supply voltage Vdd varies will be described.

(A) Basic Operation of Signal Strength Detection Circuit FIG. 3 is a diagram showing voltage-current characteristics of the PMOS 111 and the resistor 113 in FIG.
As a basic operation as a signal strength detection circuit, operations other than the power supply voltage fluctuation suppression circuit are almost the same as those of the conventional circuit. In FIG. 1, when an input voltage Vin such as an intermediate frequency signal is input to the input terminals 51 and 52, the input voltage Vin is sequentially amplified by a plurality of stages of saturated differential amplifier circuits 60-1 to 60-n, The amplified output voltage Vout is output from the output terminals 71 and 72.

  The signals amplified by the saturated differential amplifier circuits 60-1 to 60-n at each stage are respectively input to the full-wave rectifiers 80-1 to 80-n and rectified. The output currents of the full-wave rectifiers 80-1 to 80-n at the respective stages are added together to become a total calculated force current IO. A current I3 flows through the PMOS 111 and the resistor 113 in the power supply voltage fluctuation suppressing circuit 110.

The current I3 flowing through the PMOS 111 has both the voltage-current characteristic of the equation (1) based on the PMOS characteristic and the voltage-current characteristic relationship of the expression (2) of the resistor 113 when the gate and source voltage of the PMOS 111 is Vg. Current value.
I = k (Vdd−Vg−Vt) ² (1)
Where k: constant of PMOS 111, Vt: threshold voltage of PMOS
I = Vg / R2 (2)
However, R2; the resistance value of the resistor 113, that is, as shown in FIG. 3, the intersection of the curve of the current I and the straight line of the current I is the point where the two formulas (1) and (2) are compatible. Is the voltage Vg, and the Y-axis value is the current I3 that flows. Further, since the PMOS 111 and the PMOS 112 have a current mirror configuration, a similar current flows through the PMOS 112. The current I1 flowing through the PMOS 101 is obtained by subtracting the current I4 of the PMOS 112 from the current IO.
I1 ＝ IO−I4
It becomes. Further, the current I1 is converted into a voltage by the resistor 104 via the current mirror circuit 100 including the PMOS 101 and the PMOS 102, and the signal strength detection voltage Vrssi is output from the output terminal 103.

  Here, when the output amplitudes of the fully saturated differential amplifier circuits 60-1 to 60-n are saturated, the peak values of the output currents IB1 to IBn of the full wave rectifiers 80-1 to 80-n are also saturated. Assuming that the output of signal strength detection (hereinafter referred to as “RSSI”) becomes 1 when the output saturation of one saturation differential amplifier circuit is simply detected, the relationship between input signal power and RSSI output is as follows: I understand that

  If the gains of the saturation differential amplifier circuits 60-1 to 60-n in FIG. 1 are all the same, the second stage gain is the square of the first stage gain, the third stage is the third power, and the fourth stage is The power increases exponentially to the fourth power. In the case of input signal power at which the nth stage, which is the final stage in FIG. 1, is just saturated, 1 is output as the RSSI output only after amplification with the nth power of the gain of the first stage. The input signal power whose magnitude is just saturated at the second stage from the last stage is saturated through the (n-1) stage saturation differential amplifier circuits 60-1 to 60- (n-1). In addition to the RSSI output, the RSSI output 1 is also output from the (n-1) stage, and the RSSI total output (signal strength detection voltage Vrssi) is output 2 together with the RSSI output 1 of the final stage. Is done. Similarly, it can be seen that at the large input signal power level at which the first stage saturated differential amplifier circuit 60-1 is just saturated, all the saturated differential amplifier circuits are saturated, and the total RSSI output is n.

  As described above, since the RSSI output of each stage is added with the weight of the nth power, the RSSI total output (signal strength detection voltage Vrssi), which is the sum of the RSSI outputs, is increased with respect to the increase in dBm unit of the input signal power. It will increase in a straight line.

(B) Operation when the power supply voltage Vdd fluctuates FIGS. 4A and 4B show the RSSI output characteristics of the signal strength detection circuit when the saturation amplitude of the saturation differential amplifier circuit of FIG. 1 depends on the power supply voltage. FIG. 6A is a characteristic diagram when no power supply voltage fluctuation suppression circuit is added, and FIG. 5B is a characteristic chart when a power supply voltage fluctuation suppression circuit is added. Further, FIGS. 5A and 5B are RSSI output characteristic diagrams of the signal strength detection circuit when the gain of the saturated differential amplifier circuit of FIG. 1 has a power supply voltage dependency, and FIG. The characteristic diagram when the power supply voltage fluctuation suppressing circuit is not added and FIG. 5B are characteristic charts when the power supply voltage fluctuation suppressing circuit is added.

  When the saturation amplitude increases as the power supply voltage Vdd applied to the saturation differential amplifier circuits 60-1 to 60-n increases, the combined calculation current IO of the full-wave rectifiers 80-1 to 80-n increases accordingly. Since the output current of the full-wave rectifier in the front stage including the first stage is very small, if the input signal power is small, the current increases around the final stage and nearby full-wave rectifier output currents IBn and IB (n-1) However, as the input signal power increases, the current increase affects the full-wave rectifier output currents IB (n-2), IB (n-3),. Effect.

  When the power supply voltage fluctuation suppressing circuit 110 is not provided as in the prior art, the output current I1 is I1 = IO, and further, a similar current flows through the resistor 104 due to the current mirror configuration of the PMOSs 101 and 102. FIG. ), And the slope of RSSI output increases. If the saturation amplitude decreases with a decrease in the power supply voltage Vdd, the opposite is true, and similarly, the slope becomes smaller as shown in FIG.

  Here, consider the case where the power supply voltage fluctuation suppressing circuit 110, which is a feature of the first embodiment, is added.

As described above, the current I3 flowing through the PMOS 111 is, as shown in FIG. 3, the voltage-current characteristic I = k (Vdd−Vg−Vt) ² of the expression (1) based on the PMOS characteristic and the expression (2) of the resistor 113. Current-current characteristic I = Vg / R2 is satisfied.

  When the power supply voltage Vdd increases, the voltage-current characteristic of the PMOS 111 shown in FIG. 3 shifts (moves) in the positive direction of the X axis, and the intersection with the characteristic of the resistor 113 moves to the upper right in FIG. It can be seen that the current I3 also increases. Conversely, when the power supply voltage Vdd decreases, the voltage-current characteristic of the PMOS 111 in FIG. 3 shifts in the negative direction of the X axis, and the intersection with the characteristic of the resistor 113 decreases to the lower left, so the flowing current I3 also decreases. I understand that Further, since the PMOS 111 and the PMOS 112 have a current mirror configuration, a current similar to the current I3 flows in the current I4, and the current I1 flowing in the PMOS 101 is an amount obtained by subtracting the current I4 from the total calculated force current IO (= IO−I4). )

  Therefore, when the power supply voltage fluctuation suppressing circuit 110 is added, the signal strength detection voltage Vrssi moves in the direction of correcting in the Y-axis direction with respect to the fluctuation of the power supply voltage Vdd as shown in FIG. It becomes the direction which suppresses the dispersion | variation in the voltage Vrssi.

  Further, when the gain of the saturation differential amplifier circuits 60-1 to 60-n increases with the power supply voltage Vdd, each stage output is saturated with a smaller input signal power. If the amount of gain change per stage when the power supply voltage Vdd fluctuates is Δg [dB], the first stage saturated output level is Δg, the second stage saturated output level is 2Δg, and the sixth stage is It becomes saturated with an input signal power which is smaller by 6Δg. Therefore, when the power supply voltage fluctuation suppressing circuit 110 is not provided, a graph is obtained as shown in FIG. 5A, and the RSSI output characteristic moves upward.

  Similarly, when the gains of the saturation differential amplifier circuits 60-1 to 60-n decrease with the power supply voltage Vdd, the RSSI output characteristics are lower than the desired characteristics as shown in FIG. It will move. However, when the power supply voltage fluctuation suppressing circuit 110 is added, as described above, the current I3 flowing through this circuit increases when the power supply voltage Vdd increases, and conversely when the power supply voltage Vdd decreases, the current I3 also decreases. To do.

  Therefore, when the power supply voltage fluctuation suppression circuit 110 is added, the current I1 = IO−I4 has a characteristic. Therefore, as shown in FIG. 5B, the signal intensity detection voltage Vrssi moves in the direction of correction in the Y-axis direction. Therefore, the variation in the signal strength detection voltage Vrssi is suppressed.

  In the power supply voltage fluctuation suppressing circuit 110, the change width of the current I4 with respect to the power supply voltage fluctuation can be adjusted by changing the size ratio of the PMOSs 111 and 112 or changing the resistance value of the resistor 113. .

  For example, when the size ratio of the PMOSs 111 and 112 is changed, if the size ratio of the PMOSs 111 and 112 is set to 2: 1, the flowing current ratio is also I3: I4 = 2: 1. Therefore, if the change width of the current I3 flowing through the PMOS 111 when the power supply voltage Vdd increases by ΔVdd is ΔI, the change width of the current I4 flowing through the PM0S 112 can be ΔI / 2. Similarly, when the size ratio of the PMOSs 111 and 112 is set to 3: 1, the change width of the current I4 flowing through the PMOS 112 when the power supply voltage Vdd increases by ΔVdd can be set to ΔI / 3. By changing the size ratio of the PMOSs 111 and 112 in this way, the change width of the current I4 with respect to the power supply voltage Vdd can be adjusted.

(Effect of Example 1)
According to the first embodiment, by adding the current I4 of the power supply voltage fluctuation suppression circuit 110 in which the amount of current flowing according to the power supply voltage value increases or decreases to the total calculated force current IO, the power supply voltage at the output voltage level of the signal strength detection circuit. Variability with respect to Vdd can be reduced.

(Modification)
The present invention is not limited to the first embodiment, and various usage forms and modifications are possible. For example, there are the following forms (i) and (ii) as usage forms and modifications.

  (I) Although FIG. 1 shows an example in which the current mirror circuit 100 is configured by the PMOSs 101 and 102 and the current mirror circuit is further configured by the PMOSs 111 and 112, the current mirror circuit is configured using other transistors such as NMOS. It may be configured. In addition to the general circuit configuration shown in FIG. 7, the saturation differential amplifier circuits 60-1 to 60-n have various circuit configurations such as replacing the resistors 13 and 14 in FIG. 7 with load MOS transistors. Are applicable.

  (Ii) Although FIG. 2 shows a circuit example of the full-wave rectifier 80 using the NMOSs 85, 86, 88, and 89 in the differential pair configuration, other transistor configurations such as a PMOS can also be applied.

It is a block diagram of the signal strength detection circuit which shows Example 1 of this invention. It is a block diagram which shows an example of each full wave rectifier 80-1 to 80-n in FIG. It is a figure which shows the voltage-current characteristic of PMOS111 and the resistance 113 in FIG. FIG. 2 is an RSSI output characteristic diagram of a signal strength detection circuit when the saturation amplitude of the saturation differential amplifier circuit of FIG. FIG. 2 is an RSSI output characteristic diagram of a signal strength detection circuit when the gain of the saturated differential amplifier circuit of FIG. 1 has power supply voltage dependence. It is a block diagram of the conventional signal strength detection circuit. It is a block diagram which shows an example of the saturation differential amplifier circuit in FIG.

Explanation of symbols

60-1 to 60-n saturation differential amplifier circuit 80-1 to 80-n full wave rectifier 100 current mirror circuit 110 power supply voltage fluctuation suppression circuit

Claims (3)

A plurality of cascaded saturation amplifier circuits that are driven by a power supply voltage and sequentially amplify an input signal;
A plurality of stages of rectifiers for rectifying the signals amplified by the saturation amplification circuits of the respective stages;
A circuit for obtaining a signal strength detection current that is a sum of output currents of the rectifiers of the respective stages;
A power supply voltage fluctuation suppressing circuit for adding a current whose amount of current changes depending on the power supply voltage to the signal intensity detection current;
A signal strength detection circuit comprising:   2. The signal strength detection circuit according to claim 1, wherein the saturation amplifier circuit is a saturation differential amplifier circuit, and the rectifier is a full-wave rectifier. The circuit for obtaining the signal strength detection current is:
A first current mirror circuit;
The power supply voltage fluctuation suppressing circuit is
A second current mirror circuit connected between a power supply voltage terminal to which the power supply voltage is applied and a predetermined node, and connected in parallel to the first current mirror circuit;
A resistor connected between the predetermined node and a ground terminal to which a ground voltage is applied;
The signal strength detection circuit according to claim 1, wherein the signal strength detection circuit is configured as follows.

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