JP2007281373A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

Two types of capacitors having a thin ferroelectric film and a thick ferroelectric film as dielectrics are formed in one semiconductor device with a small number of man-hours.
After a ferroelectric film 3 is formed on a lower electrode layer 2, a partial region of the ferroelectric film 3 is etched to be thinned. Thereafter, an upper electrode layer 5 is deposited on the ferroelectric film 3, and the upper electrode layer 3, the ferroelectric film 3 and the lower electrode layer 2 are sequentially patterned, and a thick ferroelectric film 3a is formed in the thinned region. A capacitor 10b having a thick ferroelectric film 3b is formed in an unetched region. Two types of capacitors 10a and 10b can be formed only by adding an etching step of the ferroelectric film 3 to the step of forming one normal type capacitor.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device including two or more types of ferroelectric capacitors having ferroelectric films having different thicknesses as dielectrics, and a method for manufacturing the same, and particularly to easily manufacturing ferroelectric films having different thicknesses. The present invention relates to a semiconductor device that can be manufactured and a manufacturing method thereof.

  Ferroelectric memory (FeRAM) has non-volatility to retain information even when the power is turned off, and has low writing and reading power. For this reason, use for a semiconductor device incorporated in a portable device is being promoted, for example, where power saving is required.

  In such a ferroelectric memory, a ferroelectric capacitor in which a ferroelectric film is sandwiched between electrodes is used as a memory element. However, ferroelectric capacitors are not only used as memory elements, but many applications have been proposed by utilizing the feature that a large capacity can be realized with a small area. For example, it is conceivable to use a ferroelectric capacitor as a smoothing capacitor for power supply wiring of a logic circuit for driving a memory element.

Conventionally, capacitors of different applications have been manufactured by separate manufacturing processes. This is because capacitors having different applications require different characteristics and are difficult to manufacture by the same process. For example, a capacitor used for a memory element of a ferroelectric memory is required to have a low voltage operation, a large Qsw, an excellent retention characteristic and a good imprint characteristic, and a thin ferroelectric film is used as a capacitor dielectric satisfying these. in use. On the other hand, since a high dielectric breakdown voltage is given priority in the smoothing capacitor, SiO ₂ films and SiN films having a high dielectric breakdown voltage are often used as cupacitor dielectrics. Hereinafter, a conventional semiconductor device having two types of capacitors will be described.

FIG. 3 is a cross-sectional view of a conventional semiconductor device, and shows a semiconductor device having two types of capacitors, a capacitor having a two-layer film made of SiO ₂ / SiN and a ferroelectric capacitor.

Referring to FIG. 3, in the manufacture of a conventional semiconductor device including two types of capacitors, first, a lower electrode 2b and SiO ₂ / SiN are formed on an insulating film 1 formed on a semiconductor substrate (not shown). The dielectric film 3b and the upper electrode 5b are sequentially stacked. Next, the MIM capacitor 31b is formed by patterning the lower electrode 2b, the dielectric film 3b, and the upper electrode 5b in order from the top.

  Next, a lower layer portion of the interlayer insulating film 8 is deposited, and a lower electrode 2a, a ferroelectric film 3a, and an upper electrode 5a are sequentially deposited thereon. Next, the lower electrode 2a, the ferroelectric film 3a, and the upper electrode 5a are patterned in order from the top to form a ferroelectric capacitor 31a constituting a memory element.

  Next, after depositing the upper layer portion of the interlayer insulating film 8, vias 6 are formed through the interlayer insulating film 8 and connected to the lower electrodes 2a, 2b and the upper electrodes 5a, 5b. Thereafter, a wiring 7 connected to the via 6 is formed on the interlayer insulating film 8, and a semiconductor device is manufactured. (For example, refer to Patent Document 1).

  As described above, in the case where two types of capacitors incorporated in the same semiconductor device use different dielectrics such as a ferroelectric capacitor and an MIM capacitor, they are naturally manufactured in separate manufacturing steps. In such a manufacturing method, even when the two types of capacitors are both ferroelectric capacitors, for example, a capacitor having a thin ferroelectric for a memory element and a capacitor having a thick ferroelectric with a high withstand voltage are used. It can also be applied when coexisting. That is, in the above manufacturing method, when the ferroelectric films constituting the dielectric of the ferroelectric capacitor have different film thicknesses, it can be easily dealt with by depositing different ferroelectric films. It is.

  However, in the above-described conventional method, it is necessary to repeat the capacitor manufacturing process by the number of different ferroelectric film thicknesses of each ferroelectric capacitor, which increases the manufacturing process and increases the manufacturing cost. .

  On the other hand, there is known a method of manufacturing a ferroelectric capacitor having a capacitor film having a thin film portion and a thick portion and having two well voltages.

  FIG. 4 is a cross-sectional view of a capacitor of a conventional semiconductor device. FIG. 4A shows a ferroelectric capacitor using a ferroelectric film having two regions having different thicknesses as a capacitor dielectric, and FIG. This represents a ferroelectric capacitor in which a partial region has a two-layered ferroelectric film as a capacitor dielectric.

  Referring to FIG. 4A, in the first conventional method for manufacturing a ferroelectric capacitor having such two well voltages, first, on a partial region of the insulating film 1 in which the via 6A is formed, The barrier layer 11 is formed. Next, the ferroelectric film 3 is formed on the entire surface of the insulating film 1 by spin coating. This ferroelectric 3 is formed thin on the barrier layer 11 and thick on the outer insulating film 1. As a result, a thin ferroelectric film and a thick ferroelectric film are formed adjacent to each other. Next, an upper electrode 5 is formed on the ferroelectric film 3, and a ferroelectric capacitor is manufactured using the ferroelectric film 3 composed of a thin part and a thick part as a capacitor dielectric. (For example, see Patent Document 2).

  However, in the method of forming the thin portion and the thick portion on the ferroelectric film 3 by forming the barrier layer 11 on the insulating film 1 and providing the step, the ferroelectric film is thin on the step and thick on the step. Therefore, the manufacturing method of the ferroelectric film 3 is limited to, for example, the spin coating method, and the characteristic control of the ferroelectric film is restricted.

  Further, referring to FIG. 4B, in the second conventional method for manufacturing a ferroelectric capacitor having two tunnel voltages, a lower ferroelectric film 3A is formed on the lower electrode 2a, An upper ferroelectric film 3B is formed on a partial region of the ferroelectric film 3A. Thereafter, upper electrodes 5a and 5b are formed on the ferroelectric films 3A and 3B, and wirings for connecting the upper electrodes 5a and 5b are formed to manufacture a ferroelectric capacitor. (For example, see Patent Document 3).

This method of manufacturing a capacitor requires a complicated manufacturing process for laminating the ferroelectric films 3A and 3B, and increases the manufacturing cost.
Japanese Patent Laid-Open No. 2003-60054 JP 2001-244425 A JP-A-7-122661

  With the miniaturization of elements, the use of capacitors with the same thickness of ferroelectric as a dielectric as memory elements and smoothing capacitors, as in conventional semiconductor devices, satisfies the different characteristics required for these capacitors. Has become difficult. For this reason, it is necessary to form two or more types of capacitors having different ferroelectric thicknesses in the same semiconductor device.

  However, as described above, a conventional semiconductor device in which a capacitor using a thin ferroelectric film as a dielectric and a capacitor using a thick ferroelectric film as a dielectric are manufactured in separate steps in one semiconductor device. However, this manufacturing method requires a number of capacitor manufacturing processes, which increases the number of manufacturing processes and increases the manufacturing cost.

  In addition, when a conventional capacitor manufacturing method in which a step is provided on a lower electrode of a capacitor and a ferroelectric film is formed by spin coating is applied to the manufacture of a semiconductor device including such a capacitor, the manufacturing method of the ferroelectric film is There is a problem of being restricted. Furthermore, even if a conventional capacitor manufacturing method in which ferroelectric films are stacked to form a dielectric film is applied, the manufacturing process becomes complicated and the manufacturing cost increases.

  The present invention relates to a semiconductor device having a capacitor having a thin ferroelectric film as a dielectric and a capacitor having a thick ferroelectric film as a dielectric in a single semiconductor device, and a method for manufacturing the same. It is an object of the present invention to provide a semiconductor device that can be manufactured at a manufacturing cost and a manufacturing method thereof.

  In order to solve the above problems, a semiconductor device according to the present invention includes a first capacitor having a first ferroelectric film as a dielectric on an insulating film, and a first ferroelectric film in a different region on the insulating film. In a semiconductor device having a second capacitor using a second ferroelectric film having a thinner film thickness as a dielectric, the second ferroelectric film is a first ferroelectric film thinned by etching. It consists of a partial region.

  That is, in the capacitor of this semiconductor device, after the lower electrode layer and the first ferroelectric film are formed on the insulating film, the first ferroelectric film is etched and thinned to form the second ferroelectric film. It is manufactured by forming a body film and forming an upper electrode layer.

  Therefore, the semiconductor device of the present invention can be manufactured by simply adding a ferroelectric film etching process to the conventional manufacturing process of one type of ferroelectric capacitor. For this reason, compared with the conventional semiconductor device which manufactures two types (two types from which the film thickness of a ferroelectric substance differs) is a separate process, or its manufacturing method, there are few manufacturing processes and manufacturing cost is reduced.

  The lower electrode layer, the first and second ferroelectric layers, and the upper electrode layer are then patterned to form a first capacitor and a second capacitor. Alternatively, the lower electrode layer may be patterned from the beginning to form the lower electrode, and the first ferroelectric film may be formed thereon. In this case, it is sufficient to pattern the upper electrode or the upper electrode and the first ferroelectric film.

  According to the present invention, a semiconductor device including a capacitor having a thin ferroelectric film as a dielectric and a capacitor having a thick ferroelectric film as a dielectric can be simply added to the etching process of the ferroelectric film. It can be manufactured and the manufacturing cost is reduced.

  A first embodiment of the present invention includes a memory ferroelectric capacitor used as a ferroelectric memory element in a memory cell, and a smoothing ferroelectric capacitor used as a smoothing capacitor for a power supply wiring of a peripheral circuit. The present invention relates to a semiconductor device.

  FIG. 1 is a cross-sectional view of a manufacturing process of a semiconductor device according to a first embodiment of the present invention, showing a cross-sectional structure of a portion including a capacitor of the semiconductor device.

  With reference to FIG. 1A, in the manufacture of the semiconductor device of the first embodiment, first, the lower electrode layer 2 is formed on the upper surface of the insulating film 1 formed on the semiconductor substrate outside the drawing. The lower electrode layer 2 is later patterned to become the lower electrodes of two types of capacitors, and is made of, for example, Pt.

Next, a ferroelectric film 3 (corresponding to a second ferroelectric film) is formed on the lower electrode layer 2. This ferroelectric film 3 satisfies the FeRAM capacitor characteristics, and is, for example, a PZT material such as PZT (lead zirconate titanate), La-doped PZT (PLZT), or SrBi ₂ Ta ₂ O ₉ (STB: Y1). ), SrBi ₂ (TaNb) ₂ O ₉ (SBTN: YZ), etc., can be used.

  These ferroelectric films 3 can be formed by, for example, a sol-gel method, a sputtering method, or an MOCVD method. More specifically, firstly, a precursor of a ferroelectric film made of an amorphous phase is formed by using these methods, and then the precursor is crystallized by heat treatment to be converted into a ferroelectric having a perovskite structure. Thus, the ferroelectric film 3 is formed.

  Next, the formation region of the smoothing ferroelectric capacitor 10b (see FIG. 1E) is covered on the ferroelectric film 3, and the formation region of the memory ferroelectric capacitor 10a (see FIG. 1E) is formed. A resist mask 4 having an opening 4a that exposes is formed.

  Next, referring to FIG. 1B, the ferroelectric film 3 exposed on the bottom surface of the opening 4a is etched and thinned using reactive ion etching using the resist mask 4 as a mask. As a result, the ferroelectric film 3a (corresponding to the second ferroelectric film) on the memory ferroelectric capacitor 10a forming region is thinned, and the ferroelectric film on the smoothing ferroelectric capacitor 10b forming region is thinned. The film thickness 3b is left as it is without being reduced.

  The etching of the ferroelectric film 3 only needs to be performed using a mask, and other dry etching such as ion milling can be used, or wet etching can also be used.

  Next, referring to FIG. 1C, the upper electrode layer 5 is formed on the entire surface of the ferroelectric film 3. For this upper electrode layer 5, Pt is usually used. This is because when Pt is used as the upper electrodes 5a and 5b of the ferroelectric capacitors 10a and 10b, excellent capacitor characteristics such as a small leakage current and a large hysteresis curve are given. However, it is known that a ferroelectric capacitor for a memory has poor fatigue characteristics or is greatly deteriorated in the manufacturing process of a semiconductor device and has low reliability.

An oxide conductive material such as IrO ₂ or SRO (SrRuO ₃ ) can also be used as a material for the upper electrodes 5a and 5b to compensate for these drawbacks. By using these oxide conductive materials as the material for the upper electrode layer 5, the ferroelectric capacitors 10a and 10b having excellent fatigue characteristics and reliability are manufactured. As for the IrO ₂ upper electrode, Takamatsu announced ISIF 2000, 12th International Symposium on Integrated Ferroelectronics No. In S017C, the SRO upper electrode is disclosed in spring 99 (46) corresponding 29p-K-13 and in autumn 99 (60) corresponding 2p-A-6.

  The upper electrode layer 5 can be formed by sputtering. It can also be formed by other methods such as CVD.

  Next, referring to FIG. 1 (d), the upper electrode layer 5, the ferroelectric layer 3 and the lower electrode layer 2 are etched and patterned in this order, and the memory ferroelectric capacitor 10a and the smoothing ferroelectric material are then patterned. Capacitor 10b is formed.

  Specifically, first, an unillustrated etching mask for defining the upper electrodes 5a and 5b is formed on the upper electrode layer 5, and the upper electrode layer 5 is patterned by dry etching using the mask to obtain the upper electrode 5a. 5b. Next, an unillustrated etching mask for defining the dielectrics (dielectric films 3a and 3b) of the capacitors 10a and 10b is formed on the upper electrodes 5a and 5b and the ferroelectric film 3 exposed outside the upper electrodes 5a and 5b. The ferroelectric film 3 is patterned by dry etching using a mask to form dielectric films 3a and 3b. Next, similarly, the lower electrodes 2a and 2b of the capacitors 10a and 10b are defined on the upper electrodes 5a and 5b, the exposed ferroelectric films 3a and 3b, and the lower electrode layer 2 exposed outside the upper electrodes 5a and 5b. Then, the lower electrode layer 2 is patterned by dry etching using the mask to form the lower electrodes 2a and 2b.

  As a result, the ferroelectric capacitors 10a and 10b using the ferroelectric films 3a and 3b having different thicknesses as capacitor dielectrics were formed on the same semiconductor substrate.

Next, referring to FIG. 1E, an SiO ₂ interlayer insulating film 8 is formed on the entire surface of the insulating film 1. Next, via holes are formed in the interlayer insulating film 8 to expose the upper electrodes 5a and 5b and the lower electrodes 2a and 2b, and the vias 6 are formed by filling the via holes with a conductive material. Thereafter, a wiring 7 connected to the via 6 is formed on the interlayer insulating film 8. Further, the semiconductor device is manufactured through a normal semiconductor device manufacturing process.

  According to the first embodiment, the ferroelectric films 3a and 3b having different thicknesses are formed by a normal manufacturing process of a semiconductor device including one type of ferroelectric capacitor except for the etching process of the ferroelectric film 3. A semiconductor device including two types of ferroelectric capacitors 10a and 10b as dielectrics can be manufactured. Accordingly, a semiconductor device including two types of ferroelectric capacitors 10a and 10b can be manufactured with only a slight increase in cost caused by the addition of this etching process.

  FIG. 2 is a manufacturing process cross-sectional view of a semiconductor device according to a second embodiment of the present invention. The second embodiment is different from the first embodiment in that the ferroelectric film 3 is formed on the patterned lower electrodes 2a and 2b.

  Referring to FIG. 2, in the second embodiment, after the lower electrode layer 2 made of, for example, Pt is formed on the insulating film 1, the lower electrode layer 2 is patterned to form the lower electrodes 2a and 2b. Next, a ferroelectric film 3 covering the lower electrodes 2a and 2b is formed on the insulating film 1 by the same method as in the first embodiment. Next, a resist mask 4 similar to that of the first embodiment is formed on the ferroelectric film 3.

  Next, as in FIG. 1B, a part of the ferroelectric film 3 is etched and thinned. Next, the upper electrode layer 5 is formed on the ferroelectric film 3 as in FIG. 1C, and then the upper electrode layer 5 is patterned as in FIG. 1D to form the upper electrodes 5a and 5b. Further, the ferroelectric film 3 is patterned to form ferroelectric films 3a and 3b. Patterning of the ferroelectric film 3 is performed if necessary, and it is not always necessary to form the ferroelectric films 3a and 3b separated for each of the capacitors 10a and 10b. Next, a semiconductor device is manufactured by the same process as in the first embodiment.

  According to the present embodiment, since the lower electrode layer 2 is not patterned after the ferroelectric film 3 is patterned, deterioration due to the patterning of the lower electrode layer 2 of the ferroelectric films 3a and 3b can be avoided. .

  By applying the present invention to a semiconductor device incorporating FeRAM and a logic circuit, the semiconductor device can be manufactured with fewer steps and lower costs.

Sectional drawing of the manufacturing process of the semiconductor device by 1st Embodiment of this invention Sectional drawing of the manufacturing process of the semiconductor device by 2nd Embodiment of this invention Sectional view of a conventional semiconductor device Cross-sectional view of a conventional semiconductor device capacitor

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 1A insulating film 2 Lower electrode layer 2a Lower electrode 3, 3a, 3b Ferroelectric film 4 Resist mask 5 Upper electrode layer 5a Upper electrode 6, 6A Via 7 Wiring 8 Interlayer insulating film 10a, 10b Capacitor 11 Barrier layer

Claims (5)

A first capacitor in which a first lower electrode, a first ferroelectric film and a first upper electrode are sequentially stacked on the insulating film; a second lower electrode in the different region on the insulating film; In a semiconductor device including a second ferroelectric film having a thickness smaller than that of the first ferroelectric film and a second capacitor in which a second upper electrode is sequentially stacked,
The semiconductor device according to claim 1, wherein the second ferroelectric film is formed of a partial region of the first ferroelectric film thinned by etching.   2. The semiconductor device according to claim 1, wherein one of the first and second capacitors constitutes a smoothing capacitor for power supply wiring, and the other constitutes a ferroelectric memory cell. Forming a lower electrode layer on the insulating film;
Forming the first ferroelectric film on the lower electrode layer;
Etching and thinning the first ferroelectric film formed on the second capacitor formation region to form the second ferroelectric film;
And a step of forming an upper electrode layer on the first and second ferroelectric films.   4. The method of forming a first capacitor and a second capacitor by sequentially patterning the upper electrode layer, the first and second ferroelectric layers, and the lower electrode layer, respectively. The manufacturing method of the semiconductor device of description.   4. The method of manufacturing a semiconductor device according to claim 3, wherein instead of forming the lower electrode layer, first and second lower electrodes separated from each other are formed.

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