JP2007266577A - Nitride semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve, for example, high brightness and efficiency of a light emitting device, and to achieve normally-off characteristics of a field effect transistor, by suppressing spontaneous polarization which occurs on a nitride semiconductor. <P>SOLUTION: A nitride semiconductor device includes a semiconductor laminate 110 made of a nitride semiconductor comprising a first main surface and a second main surface that faces it, and containing a channel layer 104. On the first main surface, a plurality of rough parts each having a plane orientation of ä0001} are formed, and the second main surface has a plane orientation of ä1-101}. The channel layer 104 is formed along ä1-101} in plane orientation. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a nitride semiconductor device and a manufacturing method thereof, and more particularly to a nitride semiconductor device applicable to a field effect transistor or a semiconductor light emitting element and a manufacturing method thereof.

  Gallium nitride (GaN) -based semiconductors (nitride semiconductors) have a larger band gap than compound semiconductors such as gallium arsenide (GaAs) or semiconductors made of silicon (Si), and in the visible or ultraviolet region of blue or green. Research and development are actively pursued toward the realization of light-emitting elements capable of emitting light. Until now, it has been commercialized as a light-emitting diode element for various displays or a semiconductor laser element for a next-generation high-density optical disk.

GaN-based semiconductors are characterized by high breakdown voltage and high saturation drift speed, and are attracting attention for use in electronic devices such as high-output power devices and high-speed operation transistors. A GaN-based semiconductor is generally formed on a so-called heterogeneous substrate made of a material different from a nitride semiconductor such as sapphire (single crystal Al ₂ O ₃ ) or silicon carbide (SiC). Initially, it was difficult to improve the crystallinity of nitride semiconductors grown on different substrates, but a technique using a low-temperature buffer layer was developed in metal organic chemical vapor deposition (MOCVD). As a result, it has become possible to obtain relatively good nitride semiconductor crystals using different substrates.

  By the way, in the heteroepitaxial growth technology that makes it possible to commercialize optical devices such as blue light-emitting diode elements, the plane orientations of the main surfaces of the nitride semiconductor are all (0001) planes, so-called c-planes, and spontaneous polarization or piezopolarization occurs. It occurs in a direction perpendicular to the main surface. These polarizations generate a polarization electric field in a well layer in which electrons and holes are confined in a quantum well structure generally used as an active layer in a light emitting device. As a result, since electrons and holes are spatially separated, a so-called quantum Stark effect in which the light emission efficiency is reduced is observed (for example, see Non-Patent Document 1).

On the other hand, in an electronic device, since a nitride semiconductor layer is generally formed on the (0001) plane, a polarization electric field is generated perpendicularly to the (0001) plane by the spontaneous polarization or the piezoelectric electrode described above. Furthermore, fixed charges are generated at the interface and surface of the nitride semiconductor layer due to the polarization, and in order to neutralize this, for example, at the heterointerface between aluminum gallium nitride (AlGaN) and gallium nitride (GaN), an undoped state Even so, for example, a sheet carrier concentration of 1 × 10 ¹³ cm ⁻² or more occurs.

So far, it has been reported that a heterojunction field effect transistor having a large drain current utilizing this high sheet carrier concentration can be realized (see, for example, Non-Patent Document 2). Here, a large value of electron mobility exceeding 1000 cm ² / Vs at room temperature has been reported, and expectations are high as a future electronic device replacing the conventional GaAs compound semiconductor or Si semiconductor.
SFChichibu et al., "SPECTROSCOPIC STUDIES IN InGaN QUANTUM WELLS", MRS Internet J. Nitride Semicond. Res. 4S1, G2.7 (1999) M.Hikita et al., IEDM Tech. Digest 2004 p.803

  However, as described above, both the conventional GaN-based light-emitting device and the GaN-based field effect transistor are formed on the (0001) plane of the nitride semiconductor layer, and the spontaneous polarization and the piezo-polarization are on the (0001) plane. However, it occurs in a direction perpendicular to the direction. For this reason, in the light emitting device, it is difficult to improve the light emission efficiency from the quantum well due to the quantum Stark effect described above, and there is a problem that there is a limit to further increase in luminance and efficiency.

  In addition, in a field effect transistor, when a normally-off characteristic that is strongly demanded for a power device is to be realized, a high sheet carrier concentration is generated due to the polarization electric field described above, which makes it difficult to realize a normally-off characteristic. is there.

  In view of the above-described conventional problems, the present invention can suppress spontaneous polarization generated in a nitride semiconductor, for example, to realize high luminance and high efficiency in a light emitting device, and to realize normally-off characteristics in a field effect transistor. The purpose is to be able to.

  In order to achieve the above object, the present invention has a configuration in which an active layer in a nitride semiconductor device is formed along the {1-101} plane of the plane orientation.

  Specifically, a nitride semiconductor device according to the present invention includes a semiconductor stacked body that includes a first main surface and a nitride semiconductor having a second main surface facing the first main surface, and includes an active layer. A plurality of first concavo-convex portions each having a {0001} plane are formed on one main surface, the second main surface is a {1-101} plane, and the active layer is {1 It is formed along the −101} plane.

  According to the nitride semiconductor device of the present invention, since the active layer is formed along the {1-101} plane, polarization such as spontaneous polarization and piezoelectric polarization occurs in a direction perpendicular to the main surface of the active layer. There is nothing. Therefore, as a result of suppressing the influence of polarization, in the case of a field effect transistor, since the sheet carrier concentration can be reduced over a wide range, a normally-off type operation can be realized. In the case of a light emitting device, since the quantum Stark effect is suppressed, high sensitivity and high efficiency can be realized.

  For example, {0001} of the plane orientation represents one set of planes equivalent to the (0001) plane, and for example, a negative sign “−” in {1-101} represents an inversion of one exponent following the negative sign. It is shown for convenience.

  The nitride semiconductor device of the present invention further includes a substrate made of silicon having a plurality of second concavo-convex portions whose plane orientations are {111} planes, and the first concavo-convex portion of the semiconductor stacked body It is preferable that the body is formed by growing on the second uneven portion of the substrate.

  Thus, the {0001} plane of the nitride semiconductor grows on the {111} plane of the substrate made of silicon, and then the plane orientation of the growth plane is {1- 101} plane, the nitride semiconductor device of the present invention can be realized. Further, by using silicon that is easily available as a substrate for growing a nitride semiconductor, the cost can be reduced.

In this case, the semiconductor device further includes a buffer layer formed between the substrate and the semiconductor stacked body and having a general formula of Al _x Ga _1-x N (where x is 0 <x ≦ 1). Is preferred.

  In this way, since the stress generated between the substrate and the semiconductor stacked body is relieved, the thickness of the semiconductor stacked body including the active layer can be formed thicker. Can be improved.

  In the nitride semiconductor device of the present invention, it is preferable that the substrate has a {100} plane in the plane orientation of the main surface, and the plurality of second uneven portions are formed on the {100} plane of the substrate.

  If it does in this way, the 2nd uneven | corrugated | grooved part which the surface orientation of a wall surface makes {111} plane can be formed easily and reliably by anisotropic etching with respect to the main surface of {100} plane.

  In this case, the main surface of the substrate is preferably an off-substrate tilted from the {100} plane.

  In this way, the flatness of the second main surface (upper surface) of the semiconductor stacked body can be improved.

  In the case where the substrate is provided, the plurality of second concavo-convex portions are preferably formed in a stripe shape.

  In the case where the substrate is provided, it is preferable that each of the plurality of second concavo-convex portions is formed in an inverted quadrangular pyramid shape and arranged in a matrix shape.

  In this way, the second concavo-convex portion can be uniformly formed over the entire main surface of the substrate in both the stripe shape and the matrix shape.

  In the nitride semiconductor device of the present invention, the {1-101} plane in the semiconductor stacked body is preferably flat.

  Thus, when applied to a field effect transistor, since the mobility of carriers is large, a field effect transistor that can operate at high speed and has low on-resistance can be realized.

  The nitride semiconductor device of the present invention further includes a gate electrode formed on the {1-101} plane of the semiconductor stacked body, and a source electrode and a drain electrode formed on both sides of the gate electrode, respectively, and the active layer is A channel layer is preferred.

  Thus, a field effect transistor can be obtained as the nitride semiconductor device.

  In this case, the channel layer is preferably constituted by a heterojunction of a first layer made of gallium nitride and a second layer made of aluminum gallium nitride.

  In this case, since a two-dimensional electron gas layer generated by a heterojunction can be used as the channel layer, the carrier mobility is increased, so that a field effect transistor capable of high-speed operation and low on-resistance can be realized. Can do.

  In the nitride semiconductor device of the present invention, the semiconductor stacked body is formed on the first main surface side with respect to the active layer and on the second main surface side with respect to the active layer. It is preferable to have a p-type semiconductor layer.

  Thus, a light emitting device can be obtained as the nitride semiconductor device.

  The nitride semiconductor device of the present invention preferably further includes a holding substrate that is bonded to the second main surface of the semiconductor stacked body and holds the semiconductor stacked body.

  In this case, since the material excellent in heat dissipation can be used for the holding substrate, high output operation is possible.

  In this case, it is preferable that the holding substrate and the semiconductor laminated body are bonded together by an alloy layer containing gold and tin.

  If it does in this way, since gold | metal | money and tin will eutectic, lamination | stacking of a semiconductor laminated body and a holding substrate will become easy.

  In this case, the holding substrate is preferably made of silicon.

  In this way, it is possible to realize a device with low cost and excellent workability.

  When the semiconductor stacked body has an n-type semiconductor layer and a p-type semiconductor layer, the active layer is preferably a light emitting layer.

In this case, the first main surface of the semiconductor multilayer body is exposed, and the general formula is Al _x Ga _1-x N (where x is 0 <x ≦ 1) on the exposed surface of the semiconductor multilayer body. It is preferable that a first semiconductor layer is formed.

  In this case, the first semiconductor layer functions as a buffer layer when the semiconductor stacked body is grown.

  Further, in this case, a second semiconductor layer made of n-type gallium nitride is formed inside the first semiconductor layer in the semiconductor stacked body, and the first semiconductor layer is selected as the second semiconductor layer. It is preferable that an ohmic electrode is formed on the exposed portion of the second semiconductor layer.

  In this case, since the ohmic electrode is in contact with the n-type second semiconductor layer having a low sheet resistance, the current injected from the ohmic electrode is sufficiently spread in the lateral direction of the second semiconductor layer. A light emitting device capable of outputting uniform light emission in the plane of the layer can be realized.

  In the method for manufacturing a nitride semiconductor device according to the present invention, anisotropic etching is selectively performed on a main surface of a substrate whose main surface has a {100} plane orientation, and each plane orientation is {111}. } A step (a) of forming a plurality of concave and convex portions that are surfaces, and a semiconductor laminate including an active layer made of a nitride semiconductor by epitaxial growth on a substrate on which the plurality of concave and convex portions are formed. The method includes a step (b) of forming an upper surface to be flattened, and a step (c) of forming at least one first electrode on the semiconductor stacked body.

  According to the method for manufacturing a nitride semiconductor device of the present invention, a plurality of concavo-convex portions whose surface orientation is {111} plane is formed on the main surface of the substrate whose surface orientation is {100} plane, A semiconductor stacked body made of a nitride semiconductor and including an active layer is formed on a substrate having a plurality of uneven portions so that the upper surface of the semiconductor stacked body is flattened. As a result, since the active layer included in the semiconductor stacked body is formed along the {1-101} plane, polarization such as spontaneous polarization and piezoelectric polarization is in a direction perpendicular to the main surface of the active layer. It does not occur. Therefore, as a result of suppressing the influence of polarization, in the case of a field effect transistor, since the sheet carrier concentration can be reduced over a wide range, a normally-off type operation can be realized. In the case of a light emitting device, since the quantum Stark effect is suppressed, high sensitivity and high efficiency can be realized. Moreover, since the lateral growth of the semiconductor stacked body is promoted, the crystal defect density can be reduced. For this reason, in the case of a field effect transistor, it is possible to realize a device having high carrier mobility and capable of high-speed operation, and the semiconductor stacked body can be made thicker, so that a high breakdown voltage can be realized.

In the manufacturing method of the nitride semiconductor device of the present invention, when forming the semiconductor stacked body in the step (b), the general formula is Al _x Ga _1-x N (provided that It is preferable to form a buffer layer where x is 0 <x ≦ 1.

  In the method for manufacturing a nitride semiconductor device according to the present invention, in the step (b), the active layer is formed of a second layer made of gallium nitride and an aluminum gallium nitride layer on the second layer when forming the semiconductor stacked body. Forming a heterojunction composed of a third layer, and in step (c), as the first electrode, a gate electrode is formed on the third layer, and a source electrode and a drain electrode are formed on both sides of the gate electrode. It is preferable that the process of forming each is included.

  Thus, a heterojunction field effect transistor can be obtained as a nitride semiconductor device.

  In the method for manufacturing a nitride semiconductor device according to the present invention, in the step (b), the n-type semiconductor layer, the active layer, and the p-type semiconductor layer are sequentially formed from the substrate side when forming the semiconductor stacked body. Is preferred.

  Thus, a light emitting device can be obtained as the nitride semiconductor device.

  In the method for manufacturing a nitride semiconductor device of the present invention, after the step (c), the step (d) of bonding a holding substrate holding the semiconductor stacked body so as to be in contact with the first electrode on the semiconductor stacked body. And a step (e) of separating the substrate from the semiconductor stacked body after the step (d), and a step of forming a second electrode on the exposed surface of the semiconductor stacked body (f) after the step (e). ).

  In this case, when applied to a light emitting device, a plurality of uneven portions formed in the semiconductor laminate are formed on the opposite side of the holding substrate, that is, on the output side of the emitted light. Since the emitted light reflected inside the body is reduced, the light extraction efficiency is improved.

  In the method for manufacturing a nitride semiconductor device of the present invention, the substrate is preferably made of silicon.

  In this way, it is possible to reliably form a plurality of concave and convex portions whose surface orientation is the {111} plane on the main surface of the substrate whose surface orientation is the {100} plane.

  According to the nitride semiconductor device and the manufacturing method thereof according to the present invention, since the influence of the polarization electric field peculiar to the nitride semiconductor can be suppressed, for example, in the light emitting device, the quantum Stark effect is suppressed and high efficiency can be realized. In the field effect transistor, since the sheet carrier concentration can be reduced over a wide range, a normally-off operation can be realized.

(First embodiment)
A first embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 shows a nitride semiconductor device according to the first embodiment of the present invention, and shows a cross-sectional configuration of a heterojunction field effect transistor.

  As shown in FIG. 1, a plurality of grooves each having a V-shaped cross section, for example, are formed in stripes on an upper portion of a substrate 101 made of silicon (Si) whose principal surface has a {100} plane orientation. Concave and convex portions are formed on the entire surface. Here, the wall surface of each groove is the {111} plane of the plane orientation of the silicon crystal.

On the uneven portion of the substrate 101, a buffer layer 102 made of aluminum nitride (AlN) having a thickness of about 40 nm, an Al _0.5 Ga _0.5 N layer having a thickness of 5 nm, and a GaN having a thickness of 20 nm. A superlattice layer 103 having a thickness of 0.5 μm, in which 25 layers are stacked, a channel layer 104 made of undoped GaN having a thickness of 3 μm, and an n-type Al _0.26 Ga ₀ having a thickness of 25 nm. _The carrier supply layer 105 made of _.74 N is sequentially formed by epitaxial growth. Here, the plane orientation of the joint surface between the channel layer 104 and the carrier supply layer 105 constituting the semiconductor stacked body 110 is a {1-101} plane, and the heterojunction plane forms a contact with the carrier supply layer 105 in the channel layer 104. A two-dimensional electron gas (2DEG) layer generated in the vicinity of the interface becomes a substantial channel layer. Here, the thickness of the channel layer 104 refers to the thickness from the top surface of the convex portion of the substrate 101. The superlattice layer 103 is provided to prevent cracks generated in the semiconductor stacked body 110.

  In the semiconductor stacked body 110, an element isolation region 106 that is selectively oxidized, for example, so as to reach the channel layer 104 from the surface is formed, and on the element forming region inside the element isolation region 106 in the semiconductor stacked body 110. Is formed with a Schottky gate electrode 107 made of an alloy of palladium (Pd) and silicon (Si), and the regions on both sides of the gate electrode 107 are spaced apart from each other with titanium (Ti) and the top thereof. An ohmic source electrode 108 and a drain electrode 109 made of a laminated film with aluminum (Al) are formed.

Thus, according to the first embodiment, the semiconductor stacked body 110 made of a nitride semiconductor has a crystal that is in the polarization direction on the {1-101} plane that is the plane orientation of the upper surface (crystal growth surface). The <0001> direction of the band axis is located obliquely with respect to the {1-101} plane. For this reason, the intensity of the polarization electric field at the heterojunction surface between the channel layer 104 and the carrier supply layer 105 is smaller than that in the case of forming on the conventional {0001} plane (= c plane). As a result, when the heterojunction is formed using the channel layer 104 as an undoped layer as in the present embodiment, the sheet carrier concentration at the heterojunction surface is also compared with the case where the conventional {0001} surface is a heterojunction surface. For example, it becomes a value of 1 × 10 ¹² cm ⁻² units. Accordingly, by adjusting the doping concentration for the carrier supply layer 105 made of n-type Al _0.26 Ga _0.74 N, the drain current and threshold voltage of the field effect transistor can be controlled over a wide range. A field effect transistor can be realized.

  In addition, since the semiconductor stacked body 110 is promoted in the lateral direction when formed by crystal growth on the concavo-convex portion formed on the upper portion of the substrate 101, the crystal defect density in the semiconductor stacked body 110 can be reduced. The carrier mobility in the channel layer 104 becomes higher. Therefore, for example, a GaN field effect transistor having a large mutual conductance and a low on-resistance can be realized.

  Further, by forming the semiconductor stacked body 110 on the concavo-convex portion of the substrate 101, the semiconductor is formed by a difference in thermal expansion coefficient or a lattice constant between Si constituting the substrate 101 and GaN constituting the semiconductor stacked body 110. Cracks generated in the laminate 110 can be suppressed. Thereby, for example, the channel layer 104 can be formed relatively thick to about 3 μm, so that a transistor with a higher breakdown voltage can be realized.

  In the first embodiment, the shape of the concavo-convex portion formed on the upper portion of the substrate 101 is not limited to the configuration in which grooves having a V-shaped cross section are formed in a stripe shape. For example, the substrate 101 may be formed by arranging concave portions having an inverted quadrangular pyramid shape (inverted pyramid shape) over the entire surface of the substrate 101 in a matrix. Further, the concavo-convex portion does not necessarily have a periodic shape.

  In order to further improve the flatness of the {1-101} plane of the semiconductor stacked body 110, it is necessary to use a so-called off-substrate in which the plane orientation of the main surface of the substrate 101 itself is inclined by, for example, about 7 ° from the {100} plane. desirable. The tilt direction at this time is preferably the <1-10> direction of the crystal zone axis.

  In the first embodiment, in order to perform uniform electron transport in the channel region between the source and drain, for example, the width of the recess (V-shaped groove) is several μm that is the distance between the source electrode 108 and the drain electrode 109. Alternatively, it is desirable to make it larger or to form an ultrafine periodic structure of 0.5 μm or less.

  Note that in the case where the recesses are formed in a stripe shape, the direction in which the recesses on the stripe extend is preferably parallel or perpendicular to the direction in which the gate electrode 107 extends.

  As described above, according to the first embodiment, since the sheet carrier concentration in the heterojunction formed in the semiconductor stacked body 110 can be reduced over a wide range, a so-called normally-off type electric field having a threshold voltage value of 0 V or more. An effect transistor can be realized.

  Hereinafter, a method of manufacturing the field effect transistor configured as described above will be described with reference to FIGS. 2 (a) to 2 (d).

First, as shown in FIG. 2A, an alkaline solution such as potassium hydroxide (KOH) is used for the main surface of the substrate 101 made of Si having a main surface with a {100} plane orientation. By performing anisotropic wet etching, a plurality of concavo-convex portions having a V-shaped cross section with the surface orientation of each exposed surface being a {111} plane are formed on the substrate 101. Although not shown here, a plurality of concave and convex portions are formed by wet etching using a stripe or lattice mask film made of, for example, silicon oxide (SiO ₂ ). The interval and depth of the recesses can be controlled by wet etching conditions. Note that the mask film is not necessarily removed and may be left on the substrate 101.

  FIG. 3 shows an example of a scanning electron microscope (SEM) photograph of a plurality of concave and convex portions formed by arranging inverted quadrangular pyramidal concave portions in a matrix.

Next, as shown in FIG. 2B, ammonia (NH ₃ ) as a nitrogen source and TMG (trimethylgallium: Ga source) as a Ga source are formed on the substrate 101 on which the concavo-convex portions are formed, for example, by MOCVD. The buffer layer 102, the superlattice layer 103, and the channel layer 104 are epitaxially grown sequentially using (CH ₃ ) ₃ Ga) and TMA (trimethylaluminum: (CH ₃ ) ₃ Al) as an Al source.

  FIG. 4 shows an example of a cross-sectional SEM photograph of a channel layer (GaN layer) 104 epitaxially grown on a concave portion having a V-shaped cross section formed on the substrate 101. 4 that the channel layer 104 is selectively grown in the <0001> direction perpendicular to the {111} plane of Si exposed in the recess, that is, with a {0001} plane. Furthermore, when the growth of the channel layer 104 is continued, the channel layer 104 is planarized with the {1-101} plane of GaN as the crystal growth plane. Note that, when the depth of the recess as shown in FIG. 4 is deep, a thicker crystal growth is required. That is, the channel layer 104 is grown to a thickness of 1 μm with respect to the recess having a depth of 10 μm, and further growth of 3 μm or more is required to flatten the channel layer 104. However, as described above, the dimension of 3 μm is the thickness from the upper end surface of the recess. Further, since the channel layer 104 grows laterally from each {111} plane of Si exposed from the recess, crystal defects generated in a direction perpendicular to the main surface (= {100} plane) of the substrate 101 are suppressed. The As a result, the density of crystal defects is reduced. That is, dislocations, which are crystal defects generated from both wall surfaces of the recesses, are bonded to each other above the adjacent recesses, thereby reducing the density of crystal defects.

Subsequently, monosilane (SiH ₄ ) containing NH _{3 as} a nitrogen source, TMG as a Ga source, TMA as an Al source, and Si as an n-type dopant source is supplied onto the planarized channel layer 104. Then, a carrier supply layer 105 made of n-type Al _0.26 Ga _0.74 N having a thickness of 25 nm and having a Si concentration of 5 × 10 ¹⁸ cm ⁻³ is grown. Thereby, the semiconductor stacked body 110 including the channel layer 104 and the carrier supply layer 105 is formed. At this time, an AlN layer having a thickness of about 1 nm may be inserted between the channel layer 104 and the carrier supply layer 105. This is preferable because the carrier mobility is further improved.

  Next, as illustrated in FIG. 2C, the element isolation region 106 is formed by selectively oxidizing a part of the semiconductor stacked body 110 on the semiconductor stacked body 110.

  Next, as shown in FIG. 2D, the source electrode 108 made of a laminated film of Ti and Al is formed in the inner region of the element isolation region 106 in the semiconductor multilayer body 110 by an electron beam vapor deposition method and a lift-off method, respectively. The drain electrode 109 is selectively formed. Subsequently, a gate electrode 107 made of PdSi is selectively formed in a region between the source electrode 108 and the drain electrode 109 by electron beam evaporation and a lift-off method. Note that the order of forming the source electrode 108, the drain electrode 109, and the gate electrode 107 is not particularly limited. The lift-off method is a lithography method in which, for example, a resist pattern having an opening for opening an electrode formation region is formed on the semiconductor stacked body 110, and then a predetermined electrode material is applied to the resist pattern including the opening. It refers to a method of disposing an electrode in an electrode formation region by removing a resist pattern after being deposited thereon.

  Thus, according to the manufacturing method according to the first embodiment, the GaN-based field effect transistor shown in FIG. 1 can be obtained. That is, by setting the plane orientation of the growth surface of the channel layer 104 included in the semiconductor stacked body 110 made of a nitride semiconductor to the {1-101} plane, the spontaneous polarization and piezoelectric electrode peculiar to the group III-V nitride semiconductor are obtained. It can be made difficult to be influenced by the polarization electric field. Accordingly, since the sheet carrier concentration at the heterojunction surface between the channel layer 104 and the carrier supply layer 105 can be reduced over a wide range, a normally-off transistor having a threshold voltage value of 0 V or more can be realized.

  Furthermore, since the semiconductor stacked body 110 is epitaxially grown on the concavo-convex portion provided on the upper portion of the substrate 101, the crystal defect density is reduced by lateral growth, so that the mutual conductance can be increased and the on-resistance can be decreased. In addition, since the semiconductor stacked body 110 can be easily thickened by crystal growth on the uneven portion of the substrate 101, a high breakdown voltage transistor can be realized.

  In addition, since a silicon substrate that is easily available can be used as the substrate 101 for growing the semiconductor stacked body 110, the cost can be reduced.

  Note that the substrate 101 is not limited to silicon, and a cubic material capable of growing a nitride semiconductor, for example, gallium arsenide (GaAs), cubic silicon carbide (3C—SiC), indium phosphide (InP), or germanium (Ge). Etc. can be used.

(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

  FIG. 5 is a nitride semiconductor device according to the second embodiment of the present invention, and shows a cross-sectional configuration of a light-emitting diode element.

  As shown in FIG. 5, the GaN-based light emitting diode device according to the second embodiment includes a holding substrate 301 made of, for example, conductive silicon (Si) and a semiconductor stacked body 210 made of a nitride semiconductor, which are p-side electrodes. 207 and fixed by a solder layer 302 containing gold (Au) and tin (Sn). Note that the holding substrate is not limited to silicon, and a material that can obtain higher heat dissipation, such as copper tungsten (CuW), can be used.

The semiconductor stacked body 210 is formed on the removed growth substrate (not shown) in the same manner as in the first embodiment, and has a thickness of about 40 nm on the semiconductor stacked body 210. A superlattice layer 202 having a thickness of 0.5 μm in which a buffer layer 201 made of AlN, an Al _0.5 Ga _0.5 N layer having a thickness of 5 nm, and a GaN layer having a thickness of 20 nm are stacked for 25 periods. And are formed.

As will be described later, the semiconductor stacked body 210 is formed by epitaxial growth from the upper side to the lower side, an n-type contact layer 203 made of n-type GaN having a thickness of 1 μm, a multiple quantum well (MQW) active layer 204, a thickness Is formed of a p-type cladding layer 205 made of p-type AlGaN having a thickness of 20 nm and a p-type contact layer 206 made of p ⁺ -type GaN having a thickness of 200 nm. The MQW active layer 204 is formed by stacking, for example, a well layer made of InGaN having a thickness of 3 nm and a GaN layer having a thickness of 5 nm for six periods, and generates blue light emission having a wavelength of 470 nm, for example.

  The p-side electrode 207 in ohmic contact with the p-type contact layer 206 in the semiconductor stacked body 210 is composed of a stacked film of, for example, platinum (Pt) and titanium (Ti) thereon.

  The solder layer 302 has a three-layer structure in which an Au layer is provided between an upper layer and a lower layer of an alloy layer of Au and Sn so as to sandwich the alloy layer.

  In addition, the n-type contact layer 203 having a concavo-convex portion on the top has an exposed region having a flat bottom formed by selectively removing the buffer layer 201 and the superlattice layer 202 on the n-type contact layer 203. An ohmic n-side electrode 208 made of a laminated film of Ti and Al is formed.

  According to the second embodiment, the plane orientation of the crystal growth surface of the MQW active layer 204 included in the semiconductor stacked body 210 is the {1-101} plane as in the first embodiment. As described above, when the MQW active layer 204 is formed on the {1-101} plane, the influence of the polarization electric field is suppressed. Therefore, the electrons and holes in the well layer are spatially caused by the internal electric field in the quantum well layer. Reduction in light emission efficiency caused by the separation, so-called quantum Stark effect, is suppressed. Thereby, the light emission efficiency of the light emitting diode device according to the present embodiment is greatly improved as compared with the case where the conventional active layer is formed on the {0001} plane of the plane orientation.

  Further, when the MQW active layer 204 is formed on the {1-101} plane, the emission wavelength shifts to the short wavelength side due to an increase in injection current, which occurs in the case of the conventional active layer formed on the {0001} plane. Will not occur significantly.

  Further, in the light emitting diode device according to the second embodiment, unlike the conventional GaN-based light emitting diode device, the n-type layer such as the n-type contact layer 202 is opposite to the MQW active layer 204 from the holding substrate 301. That is, it is arranged on the output side of the emitted light. Nitride semiconductors generally have a smaller sheet resistance in the n-type layer than in the p-type layer, so that even if the n-side electrode 208 has a diameter of, for example, 100 μm or less, the injected current is n The mold contact layer 203 also extends sufficiently in the lateral direction. As a result, the emitted light can be emitted uniformly.

  For the p-side electrode 207 that is in ohmic contact with the p-type contact layer 206, for example, by selecting a metal having a higher reflectance with respect to blue light emission light, the surface side of the light emission light (the opposite side of the holding substrate 301) The extraction efficiency can be improved, that is, the light emission efficiency can be improved. In the second embodiment, platinum (Pt) is used as an ohmic electrode, but is not limited to platinum. For example, a metal having higher reflectivity such as silver (Ag) or rhodium (Rh) may be used. Furthermore, a material having a large work function is desirable for the p-side electrode 207 so that the contact resistance with the p-type contact layer 206 can be reduced, and an appropriate metal material may be selected depending on the relationship between the operating voltage and the luminance.

  In the light-emitting diode device according to the second embodiment, the exposed buffer layer 201, the superlattice layer 202 under the buffer layer 201, and the p-type contact layer 203 are formed in an uneven shape. This uneven portion can prevent the emitted light from being reflected inside the semiconductor stacked body 210 and reducing the light extraction efficiency. As a result, the light extraction efficiency is improved, and a light-emitting diode element with higher luminance and higher efficiency can be realized.

  Further, since the n-side electrode 208 and the p-side electrode 207 are provided at positions facing each other with the semiconductor stacked body 210 interposed therebetween, the chip area can be reduced.

  In the second embodiment, the case where blue emission light having a wavelength of, for example, 470 nm is generated from the MQW active layer 204 has been described. However, as long as the MQW active layer 204 is a nitride semiconductor, an arbitrary composition and thickness are possible. The emission wavelength may be any wavelength from the ultraviolet region to the visible region. Moreover, the structure which can apply | coat fluorescent substance on the upper surface of a light emitting diode element, and can output white light emission may be sufficient.

  Hereinafter, a method for manufacturing the light-emitting diode element configured as described above will be described with reference to FIGS. 6 (a) to 6 (c) and FIGS. 7 (a) to 7 (c).

  First, as shown in FIG. 6A, anisotropy using an alkaline solution such as KOH is used for the main surface of the growth substrate 211 made of Si having a main surface with a {100} plane orientation. By performing the etching, a plurality of exposed surface orientations on the growth substrate 211 are {111} planes, and a stripe pattern having a V-shaped cross section or an inverted quadrangular concave portion is arranged in a matrix. An uneven portion is formed.

Next, as shown in FIG. 6B, on the growth substrate 211 on which the concavo-convex portion is formed, for example, by MOCVD, SiH ₄ containing NH ₃ , TMG, TMA, and an n-type dopant source is used as a raw material. The buffer layer 201, the superlattice layer 202, and the n-type contact layer 203 are epitaxially grown sequentially. Subsequently, the n-type contact layer 203 is grown until it is planarized so that the upper surface of the n-type contact layer 203 becomes a {1-101} plane, and then planarized using NH ₃ , TMG, and TMIn (trimethylindium) as raw materials. An MQW active layer 204 is formed on the contact layer 203. Here, as the composition of the MQW active layer 204, for example, the well layer is made of In _0.35 Ga _0.65 N and the barrier layer is made of GaN, whereby blue light emission having a wavelength of 470 nm is obtained. Here, the MQW active layer 204 is formed on the n-type contact layer 203, but an n-type cladding layer made of n-type AlGaN may be provided between the n-type contact layer 203 and the MQW active layer 204. .

Subsequently, on the MQW active layer 204, a p-type cladding layer 205 and NH ₃ , TMG, TMA and cyclopentadienyl magnesium (Cp ₂ Mg) containing magnesium (Mg) as a p-type dopant source are used. A p-type contact layer 206 is formed sequentially.

  Next, as shown in FIG. 6C, ohmic p-side electrode 207 is formed by sequentially stacking Pt and Ti on the entire surface of p-type contact layer 206 by electron beam evaporation. Subsequently, a solder base layer 302a made of Au is formed on the p-side electrode 207 by electron beam evaporation.

  Subsequently, a holding substrate 301 made of conductive Si is prepared. A solder layer 302 made of Au, AuSn, and Au is formed on the main surface of the prepared holding substrate 301 by electron beam evaporation. The plane orientation of the main surface of the holding substrate 301 is not particularly limited, but here, the holding substrate 301 having a {100} plane is used.

  Subsequently, the solder base layer 302a formed on the semiconductor stacked body 210 in the growth substrate 211 and the solder layer 302 formed on the main surface of the holding substrate 301 are opposed to each other to hold the semiconductor stacked body 210 and the holding layer. The substrate 301 is bonded to each other. Thereby, the state shown in FIG. At this time, Au and AuSn are eutecticized by heating and pressurizing the growth substrate 211 and the holding substrate 301.

Next, as shown in FIG. 7B, the growth substrate 211 is selectively removed using, for example, a mixed solution of hydrofluoric acid (HF) and nitric acid (HNO ₃ ). At this time, the holding substrate 301 is masked with wax or the like.

  Next, as shown in FIG. 7C, for example, an inductive coupled plasma (ICP) is applied to the buffer layer 201 exposed by removing the growth substrate 211 and the superlattice layer 202 therebelow. The n-type contact layer 203 is exposed by selectively performing dry etching. Subsequently, an ohmic n-side electrode 208 made of a laminated film of Ti and Al is formed on the exposed region of the n-type contact layer 203 by an electron beam evaporation method and a lift-off method.

  Thus, according to the manufacturing method according to the second embodiment, the GaN-based light emitting diode element shown in FIG. 5 can be obtained. That is, by setting the plane orientation of the crystal growth surface of the MQW active layer 204 included in the semiconductor stacked body 210 made of a nitride semiconductor to the {1-101} plane, the spontaneous polarization and the III-V group nitride semiconductor are characterized. It can be made difficult to be affected by the polarization electric field generated by the piezoelectric electrode. Thereby, since the quantum Stark effect generated in the MQW active layer 204 is suppressed, high-efficiency light emission can be realized.

  Further, by providing uneven portions on the main surface of the growth substrate 211, lateral growth occurs in the initial stage of growth of the semiconductor stacked body 210, so that the crystal defect density is reduced, so that more efficient light emission can be achieved. realizable.

  Further, by removing the growth substrate 211, the n-type contact layer 203 having the concavo-convex part becomes the output side of the luminescent light, and therefore the luminescent light is hardly totally reflected by the concavo-convex part. In addition, since the p-side electrode 207 facing the n-type contact layer 203 is formed of a metal having high reflectance of emitted light, such as Pt, Ag, or Rh, the light extraction efficiency is improved and high luminance is achieved. And high efficiency can be realized.

  In addition, since a silicon substrate that is easily available can be used as the growth substrate 211, the cost can be reduced.

  Note that the growth substrate 211 is not limited to silicon, and a cubic material capable of growing a nitride semiconductor, for example, gallium arsenide (GaAs), cubic silicon carbide (3C—SiC), indium phosphide (InP), or germanium ( Ge) or the like can be used.

  Further, in the second embodiment, the growth substrate 211 is removed from the semiconductor stacked body 210 and the holding substrate 301 is bonded, so that emitted light is output from the n-type semiconductor layer side. It is not necessary to remove the substrate 211 for use. For example, the p-side electrode may be formed on the formed p-type contact layer 206 after manufacturing the structure shown in FIG. However, in this case, the growth substrate 211 needs to have conductivity.

  The nitride semiconductor device and the manufacturing method thereof according to the present invention can suppress the influence of a polarization electric field peculiar to a nitride semiconductor, and are particularly useful as a field effect transistor or a semiconductor light emitting element.

1 is a cross-sectional view illustrating a field effect transistor that is a nitride semiconductor device according to a first embodiment of the present invention. (A)-(d) is the structure sectional drawing of the order of a process which shows the manufacturing method of the field effect transistor which concerns on the 1st Embodiment of this invention. It is a SEM image of the substrate surface used for the field effect transistor concerning the 1st example of the present invention. It is a cross-sectional SEM image of the GaN layer grown on the board | substrate in the field effect transistor which concerns on the 2nd Example of this invention. It is a structure sectional view showing a light emitting diode element which is a nitride semiconductor device concerning a 2nd embodiment of the present invention. (A)-(c) is a structure sectional drawing of the order of a process which shows the manufacturing method of the light emitting diode element which concerns on the 2nd Embodiment of this invention. (A)-(c) is a structure sectional drawing of the order of a process which shows the manufacturing method of the light emitting diode element which concerns on the 2nd Embodiment of this invention.

Explanation of symbols

101 Substrate 102 Buffer layer 103 Superlattice layer 104 Channel layer (active layer)
105 Carrier supply layer 106 Element isolation region 107 Gate electrode 108 Source electrode 109 Drain electrode 110 Semiconductor stacked body 201 Buffer layer 202 Superlattice layer 203 n-type contact layer 204 Multiple quantum well (MQW) active layer 205 p-type cladding layer 206 p-type Contact layer 207 P-side electrode 208 N-side electrode 210 Semiconductor laminate 211 Growth substrate 301 Holding substrate 302 Solder layer 302a Solder underlayer

Claims (23)

A nitride semiconductor comprising a first major surface and a second major surface facing the first major surface, comprising a semiconductor laminate including an active layer,
A plurality of first concavo-convex portions each having a {0001} plane is formed on the first main surface, and the second main surface is a {1-101} plane.
The nitride semiconductor device, wherein the active layer is formed along the {1-101} plane. A substrate made of silicon having a plurality of second concavo-convex portions each having a plane orientation of {111} plane,
2. The nitriding according to claim 1, wherein the first uneven portion of the semiconductor stacked body is formed by growing the semiconductor stacked body on the second uneven portion of the substrate. Semiconductor light emitting device. A buffer layer formed between the substrate and the semiconductor stacked body and having a general formula of Al _x Ga _1-x N (where x is 0 <x ≦ 1) is further provided. The nitride semiconductor device according to claim 2.   4. The substrate according to claim 2, wherein the substrate has a {100} plane in a plane orientation of the main surface, and the plurality of second uneven portions are formed on the {100} plane. 5. Nitride semiconductor device.   5. The nitride semiconductor device according to claim 4, wherein a main surface of the substrate is an off-substrate inclined from a {100} plane.   The nitride semiconductor device according to claim 2, wherein the plurality of second concavo-convex portions are formed in a stripe shape.   6. The nitride semiconductor device according to claim 2, wherein each of the plurality of second concavo-convex portions is formed in an inverted quadrangular pyramid shape and arranged in a matrix shape. .   The nitride semiconductor device according to claim 1, wherein a {1-101} plane in the semiconductor stacked body is flat. A gate electrode formed on the {1-101} surface of the semiconductor laminate, and a source electrode and a drain electrode formed on both sides of the gate electrode, respectively.
The nitride semiconductor device according to claim 1, wherein the active layer is a channel layer.   The nitride semiconductor device according to claim 9, wherein the channel layer is configured by a heterojunction of a first layer made of gallium nitride and a second layer made of aluminum gallium nitride.   The semiconductor laminate includes an n-type semiconductor layer formed on the first main surface side with respect to the active layer, and a p-type semiconductor layer formed on the second main surface side with respect to the active layer. The nitride semiconductor device according to claim 1, wherein the nitride semiconductor device is provided.   The nitride semiconductor device according to claim 1, further comprising a holding substrate that is bonded to the second main surface of the semiconductor stacked body and holds the semiconductor stacked body.   The nitride semiconductor device according to claim 12, wherein the holding substrate and the semiconductor stacked body are bonded together by an alloy layer containing gold and tin.   The nitride semiconductor device according to claim 12, wherein the holding substrate is made of silicon.   The nitride semiconductor device according to claim 11, wherein the active layer is a light emitting layer. The first main surface of the semiconductor stacked body is exposed, and the general formula is Al _x Ga _1-x N (where x is 0 <x ≦ 1) on the exposed surface of the semiconductor stacked body. 16. The nitride semiconductor device according to claim 11, wherein a first semiconductor layer is formed. A second semiconductor layer made of n-type gallium nitride is formed inside the first semiconductor layer in the semiconductor stack,
The second semiconductor layer is exposed by selectively removing the first semiconductor layer;
The nitride semiconductor device according to claim 16, wherein an ohmic electrode is formed on the exposed portion of the second semiconductor layer. A step of selectively performing anisotropic etching on the main surface of the substrate whose surface orientation is the {100} plane to form a plurality of concave and convex portions whose surface orientation is the {111} plane ( a) and
A step (b) of forming, on the substrate on which the plurality of concavo-convex portions are formed, a semiconductor stacked body made of a nitride semiconductor and including an active layer by epitaxial growth so that the upper surface of the semiconductor stacked body is flattened;
And (c) forming at least one first electrode on the semiconductor laminate. A method for manufacturing a nitride semiconductor device, comprising: In the step (b), when forming the semiconductor stacked body, the general formula is Al _x Ga _1-x N (where x is 0 <x ≦ 1) on the concavo-convex portion as the first layer. 19. The method for manufacturing a nitride semiconductor device according to claim 18, wherein a buffer layer is formed. In the step (b), the active layer is a heterojunction formed of a second layer made of gallium nitride and a third layer made of aluminum gallium nitride on the second layer when forming the semiconductor stacked body. Formed by configuring
The step (c) includes forming, as the first electrode, a gate electrode on the third layer, and a source electrode and a drain electrode on both sides of the gate electrode, respectively. Item 20. The method for manufacturing a nitride semiconductor device according to Item 18 or 19.   The n-type semiconductor layer, the active layer, and the p-type semiconductor layer are sequentially formed from the substrate side when forming the semiconductor stacked body in the step (b). Of manufacturing a nitride semiconductor device. After the step (c), a step (d) of attaching a holding substrate for holding the semiconductor stacked body so as to be in contact with the first electrode on the semiconductor stacked body;
(E) separating the substrate from the semiconductor stack after the step (d);
The nitride semiconductor device according to claim 21, further comprising a step (f) of forming a second electrode on the exposed surface of the semiconductor stacked body after the step (e). Manufacturing method.   The method for manufacturing a nitride semiconductor device according to claim 18, wherein the substrate is made of silicon.