JP2007259112A - High-frequency switching circuit and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high-performance high-frequency switching circuit capable of reasonably increasing input power while suppressing harmonic distortion and insertion loss of a FET. <P>SOLUTION: A basic switching part (switching circuit) constituted of FETs connected in many stages is provided between an input/output terminal and a ground terminal or between input and output terminals, and gate width of an FET on the side of the input/output terminal to which signal power is impressed when the basic switching part is in an off state among a plurality of FETs included in one basic switching part is set larger than gate width of the remaining FET at a farther place from the input/terminal. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a high-frequency switch circuit, and realizes a switch circuit having high input power characteristics.

  In recent years, with the improvement in performance of mobile communication devices, there is a strong demand for miniaturization and high performance of high-frequency semiconductor devices used in terminals. In particular, high-frequency switch circuits that perform antenna switching are required to simultaneously achieve low insertion loss, low distortion, and high input power. In view of this, there has been proposed a method of constructing a high-frequency switch circuit using field effect transistors (hereinafter referred to as FETs) connected in multiple stages.

  FIG. 8 is a diagram showing a conventional high-frequency switch circuit described in Patent Document 1. In FIG. The high-frequency switch circuit shown in FIG. 8 includes input / output terminals 10, 20, and 30 (to which an antenna, a receiver, and a transmitter are connected), a receiving shunt FET1, a receiving transfer FET2, a transmitting transfer FET3, A credit shunt FET4 and first and second control terminals VC1 and VC2 are provided.

  First, at the time of signal reception, a high voltage is applied to the first control terminal VC1, and a low voltage is applied to the second control terminal VC2. As a result, the FETs 2 and 4 are turned on and the FETs 1 and 3 are turned off, so that the receiver and the antenna are short-circuited. Therefore, the reception signal input from the antenna is output from the receiver.

  At the time of signal transmission, a low voltage is applied to the first control terminal VC1, and a high voltage is applied to the second control terminal VC2. As a result, the FETs 2 and 4 are turned off and the FETs 1 and 3 are turned on, so that the transmitter and the antenna are short-circuited. Therefore, the transmission signal input from the transmitter is output from the antenna.

  In recent years, a multi-gate field effect transistor in which a plurality of gate electrodes are disposed between a source electrode and a drain electrode has been used in order to obtain a smaller, low-loss high-frequency switch (for example, Patent Document 2). reference). The multi-gate field effect transistor is a single three-terminal FET as a whole, but substantially (equivalent circuit-like) has a structure in which a plurality of field effect transistors are connected in multiple stages.

When FETs connected in multiple stages are used as components of the high-frequency switch, the signal voltage input from the antenna at the time of signal transmission is divided by each FET. Therefore, even when a large signal is input, the FET is easily maintained in an off state, and as a result, excellent distortion characteristics and a high input saturation voltage can be obtained as compared with the case of a single stage FET. Conventionally, FETs having the same conditions such as threshold value, gate length, gate width and the like are used as multi-stage FETs.
JP-A-8-70245 JP 2005-340739 A

  In a high-frequency switch circuit, increasing the number of FET stages improves the distortion characteristics and increases the input power, but conversely causes problems such as an increase in insertion loss and an increase in chip area. That is, both are in a trade-off relationship, and it is difficult to achieve both high-power input and suppression of increase in the number of FET stages to suppress degradation of harmonic distortion and insertion loss.

  The present invention has been made based on such considerations, and an object of the present invention is to make it possible to increase input power without deteriorating harmonic distortion and insertion loss.

  The present invention includes a plurality of input / output terminals for inputting and outputting a high-frequency signal, a basic switch unit provided between one of the input / output terminals and a ground terminal, or between the two input / output terminals, And a control terminal to which a control voltage for controlling on / off of the basic switch unit is input. The basic switch unit includes a plurality of gate electrodes each including a multi-stage field effect transistor. A switch circuit having a structure having a gate width of a field effect transistor having a gate electrode close to one of the plurality of input / output terminals as a constituent element. The gate width of the field effect transistor having any one of the gate electrodes located farther from the input / output terminal as a constituent element is larger. .

  When signal power is applied to the input / output terminals when the switch circuit constituting the basic switch unit is off, the signal power is applied to the stray capacitance of the multi-stage connected FET constituting the off switch circuit ( The voltage applied between the gate and source of each FET is gradually increased toward the input / output terminal side because the voltage is divided by the capacitance between the source and drain, the capacitance between the source and gate, and the capacitance between the drain and gate. A phenomenon that becomes larger occurs. Therefore, by designing the transistor size to intentionally non-uniformize the size of the multi-stage connection FET and set the gate width corresponding to the actual gate-source voltage, the desired number of FETs can be achieved. It is possible to realize an efficient switch circuit that can withstand this input power. Since the number of FET stages can be minimized, input power can be increased while maintaining harmonic distortion and insertion loss at conventional levels. A multi-stage FET can be realized by preparing a plurality of individual FETs and connecting them in series, or using a multi-gate FET. In addition, a switch circuit composed of multi-stage FETs is connected between input and output terminals as a transfer switch (a switch constituting a signal path for flowing a high-frequency signal input from one terminal to the other terminal). Alternatively, it may be used as a shunt switch (a switch for releasing signal power leaking into an off-state switch circuit to the ground potential) connected between the input / output terminal and the ground terminal.

  In one aspect of the high frequency switch circuit of the present invention, the basic switch unit provided between one of the input / output terminals and a ground terminal includes a plurality of field effect transistors connected in series, and one terminal A plurality of resistive elements connected to the gate electrode of any one of the field effect transistors and having the other terminal connected to the control terminal. Of the plurality of field effect transistors, the gate width of the field effect transistor closest to the input / output terminal is larger than the gate width of any remaining field effect transistor located farther from the input / output terminal. It is characterized by that.

  Construct "first switch circuit configured by connecting multiple individual FETs in series" used as "shunt switch", and the gate width of the FET on the input / output terminal side is farther It is larger than the gate width of the FET at the position, so that the input power can be divided by the FET having the smallest number of stages.

In another aspect of the high-frequency switch circuit of the present invention, the first switch circuit includes n (n is an integer of 2 or more) series-connected field effect transistors, and the input / output terminal side Where Wg (i) is the gate width of the i-th field effect transistor (i is an integer not smaller than 1 and not larger than n) counted from the following equation (1).
Wg (1)> Wg (2) ≧ ... ≧ Wg (n−1) ≧ Wg (n) (1)

  Rather than uniformly defining the gate width of a multi-stage FET, a flexible transistor size design concept of appropriately setting the gate width corresponding to the actual gate-source voltage is introduced.

  In another aspect of the high-frequency switch circuit of the present invention, the basic switch unit provided between the input / output terminals includes a plurality of field effect transistors connected in series and the field effect transistor having one terminal A second switch circuit including a plurality of resistance elements connected to the control terminal and having the other terminal connected to the control terminal. The second switch circuit includes: When the input / output terminal on the side to which signal power is applied in the off state is the active terminal when off, among the plurality of field effect transistors constituting the second switch circuit, the most active terminal when off The gate width of the near field effect transistor is larger than the gate width of any remaining field effect transistor farther away from the active terminal when it is off. The features.

  Constructs a "second switch circuit configured by connecting multiple individual FETs in series" used as a "transfer switch" and the switch circuit is turned off among the input / output terminals In this case, the terminal to which signal power is applied is defined as the “active terminal when off”, and the gate width of the FET on the active terminal side when off is set larger than the gate width of the FET at a farther position. Thus, the input power can be divided by the FET with the smallest number of stages.

Further, in the high-frequency switch circuit of the present invention, the second switch circuit is composed of n (n is an integer of 2 or more) field effect transistors connected in series, and counted from the active terminal side when off. When the gate width of the i-th field effect transistor (i is an integer not smaller than 1 and not larger than n) is Wg (i), the following equation (2) is established.
Wg (1)> Wg (2) ≧ ... ≧ Wg (n−1) ≧ Wg (n) (2)

  Rather than uniformly defining the gate width of a multi-stage FET, a flexible transistor size design concept of appropriately setting the gate width corresponding to the actual gate-source voltage is introduced.

  In another aspect of the high-frequency switch circuit of the present invention, the basic switch portion provided between one of the input / output terminals and a ground terminal has a plurality of gate electrodes arranged between a source electrode and a drain electrode. A multi-gate field effect transistor having a provided structure, and a plurality of resistance elements having one terminal connected to one of the gates of the multi-gate field effect transistor and the other terminal connected to the control terminal. A gate width of a field effect transistor having a gate electrode closest to the input / output terminal as a constituent element among the multi-gate field effect transistors configured by the third switch circuit and constituting the third switch circuit is The gate of a field-effect transistor comprising any remaining gate electrode farther away from the active terminal when off Greater than.

  The “third switch circuit composed of multi-gate FETs” used as a “shunt switch” is constructed, and the gate width of the FET on the input / output terminal side is larger than the gate width of the FET at a farther position. Thus, the input power can be divided by the FET having the smallest number of stages.

In another aspect of the high-frequency switch circuit of the present invention, the third switch circuit is configured by a multi-gate field effect transistor having n (n is an integer of 2 or more) gate electrodes, and the input / output terminal When the gate width of the i-th field effect transistor counted from the side (i is an integer not smaller than 1 and not larger than n) is Wg (i), the following equation (3) is established.
Wg (1)> Wg (2) ≧ ... ≧ Wg (n−1) ≧ Wg (n) (3)

  Rather than uniformly defining the gate width of a multi-stage FET, a flexible transistor size design concept of appropriately setting the gate width corresponding to the actual gate-source voltage is introduced.

  In another aspect of the high frequency switch circuit of the present invention, the basic switch portion provided between the input / output terminals has a structure in which a plurality of gate electrodes are disposed between a source electrode and a drain electrode. A fourth switch circuit comprising: a field effect transistor; and a plurality of resistance elements having one terminal connected to one of the gates of the multi-gate field effect transistor and the other terminal connected to the control terminal When the input / output terminal on the side to which signal power is applied when the fourth switch circuit is in the OFF state among the input / output terminals is an active terminal in the OFF state, the gate electrode of the multi-gate field effect transistor Among them, the gate width of the field effect transistor having the gate electrode closest to the off-time active terminal as a component is from the off-time active terminal, It is larger than the gate width of a field effect transistor as a component one of the gate electrodes of the remaining in the position far Ri.

  A "fourth switch circuit configured using a multi-gate FET" used as a "transfer switch" is constructed, and signal power is reduced when the switch circuit is in an OFF state among a plurality of input / output terminals. The applied terminal is defined as “active terminal when off”, and the gate width of the FET on the active terminal side when off is larger than the gate width of the FET at a farther position. The input power can be divided by the FET.

In another aspect of the high-frequency switch circuit of the present invention, the fourth switch circuit is configured by a multi-gate field effect transistor having n (n is an integer of 2 or more) gate electrodes, and the off-state active terminal side When the gate width of the i-th field effect transistor (i is an integer from 1 to n) counted from is Wg (i), the following equation (4) is established.
Wg (1)> Wg (2) ≧ ... ≧ Wg (n−1) ≧ Wg (n) (4)

  Rather than uniformly defining the gate width of a multi-stage FET, a flexible transistor size design concept of appropriately setting the gate width corresponding to the actual gate-source voltage is introduced.

  The high-frequency switch circuit of the present invention is configured to arbitrarily switch the flow of a high-frequency signal between a plurality of input / output terminals by arbitrarily combining the first, second, third, and fourth switch circuits. The

  By combining a switch circuit (transfer switch or shunt switch) constituting the basic switch unit of the present invention, a high-frequency switch that can arbitrarily switch the flow of a high-frequency signal between a plurality of input / output terminals can be efficiently and freely used. Can be built.

  The single pole double throw switch of the present invention includes first to third input / output terminals, first and second ground terminals, first and second control terminals, and the first input / output terminals. A first transfer switch connected between the second input / output terminal and the third input / output terminal; and a second transfer switch connected between the second input / output terminal and the third input / output terminal. A first shunt switch connected between the first input / output terminal and the first ground terminal; and a second shunt switch connected between the second input / output terminal and the second ground terminal. A second shunt switch, and simultaneously turning on / off the first transfer switch and the second shunt switch by a first control signal input from the first control terminal; In addition, the second transfer switch And the first shunt switch is simultaneously turned on / off by a second control signal input from the second control terminal, whereby a high-frequency signal path between the first and third input / output terminals, Or a single pole double throw (SPDT) circuit that complementarily forms a high frequency signal path between the second and third input / output terminals to control the flow of the high frequency signal, The first switch circuit or the third switch circuit is used as the first and second transfer switches, and the second switch circuit is used as the first and second shunt switches. Alternatively, the fourth switch circuit is used.

  As a result, it is possible to realize a high-performance single-pole double-throw switch circuit (SPDT circuit) in which the number of FET stages is minimized and insertion loss and harmonic distortion are suppressed to a conventional level.

  The semiconductor device of the present invention is a switch composed of a plurality of input / output terminals for inputting and outputting a high-frequency signal and a multi-stage field effect transistor for turning on / off electrical connection between the input / output terminals. A high-frequency switch circuit including a circuit integrated on a semiconductor substrate, wherein the switch circuit has a configuration in which a plurality of individual field effect transistors are connected in multiple stages, or the semiconductor A switch circuit comprising: a multi-gate field effect transistor including a plurality of gate electrodes disposed between a source electrode and a drain electrode provided on a substrate at intervals; When the input / output terminal to which signal power is applied in the off state is an off-time active terminal, the switch circuit includes a plurality of multi-stage connected Among the field effect transistors, the gate width of the field effect transistor closest to the off-state active terminal is set larger than the gate width of any of the remaining field effect transistors located farther from the off-state active terminal. As a result, the uniformity of the size of each of the multistage connected field effect transistors is intentionally broken.

  Thereby, it is possible to obtain a semiconductor device in which an efficient high-frequency switch circuit is integrated with an occupation area and power consumption being minimized.

  The high-frequency switch design method of the present invention is a high-frequency switch circuit design method in which a transfer switch constituting a high-frequency switch circuit is configured using a multi-stage connection field effect transistor, the multi-stage connection field effect transistor. The gate-source capacitance of the field-effect transistor located near the input / output terminal to which signal power is applied when the transfer switch is in the OFF state is further distant from the gate-source capacitance. The field-effect transistor is set to be larger than the gate-source capacitance.

  Rather than uniformly defining the gate width of a multi-stage FET, a flexible transistor size design concept of appropriately setting the gate width corresponding to the actual gate-source voltage is introduced.

  According to the high-frequency switch circuit of the present invention and the semiconductor device using the same, by using different gate widths as the gate widths of the multi-stage connected field effect transistors (or multi-gate field effect transistors), The input power can be increased while maintaining the same performance as the switch circuit.

  Therefore, in the high frequency switch circuit, the input power can be increased without difficulty without deteriorating harmonic distortion and insertion loss.

  Next, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
With reference to FIGS. 1-3, the high frequency switch circuit based on the 1st Embodiment of this invention and a semiconductor device using the same are demonstrated.

  FIG. 1 is a circuit diagram of a high-frequency switch circuit according to the first embodiment of the present invention. In the present embodiment, among the field effect transistors constituting the high frequency switch circuit, the gate width of the field effect transistor connected to the input / output terminal side is made larger than the gate width of any remaining field effect transistor. Features.

  A high-frequency switch circuit 100 shown in FIG. 1 includes four basic switch units configured by FETs connected in multiple stages, and functions as a single pole double throw switch SPDT (Single Pole Double Throw) circuit. The high-frequency switch circuit includes FETs 101 to 108, 111 to 118, first to third input / output terminals 121 to 123, first and second control terminals 131 and 132, and ground terminals 141 and 142.

  Each of the resistance elements R1 to R18 has one terminal connected to the gate electrode of one of the FETs and the other terminal connected to one of the control terminals (131, 132). In FIG. 2 and subsequent figures, the reference numerals are not assigned to the respective resistors.

  The first to third input / output terminals 121 to 123 are terminals for inputting and outputting high-frequency signals. For example, a receiver is connected to the first input / output terminal 121, a transmitter is connected to the second input / output terminal 122, and a third input / output terminal 123 is connected to an antenna.

  In FIG. 1, FETs 101 to 104 connected in multiple stages constitute a first basic switch unit (first switch circuit). Similarly, the FETs 105 to 108 constitute a second basic switch section (second switch circuit), the FETs 111 to 114 constitute a third basic switch section (third switch circuit), and the FETs 115 to 118 represent the second basic switch section (second switch circuit). 4 basic switch sections (fourth switch circuit) are configured.

  The first basic switch section is provided between the first input / output terminal 121 and the third input / output terminal 123, and the second basic switch section is connected to the second input / output terminal 122 and the third input / output terminal 123. The third basic switch unit is provided between the first input / output terminal 111 and the ground terminal 141, and the fourth basic switch unit is provided between the output terminal 123 and the second input / output terminal. 122 and the ground terminal 142.

  The first and second basic switch units inserted in series in the signal transmission path between the input and output terminals function as a transfer circuit (transfer switch circuit) that switches between passing and blocking the flow of the high-frequency signal. . On the other hand, the third and fourth basic switch units inserted in parallel in the signal transmission path between the input / output terminal and the ground function as a shunt circuit (shunt switch circuit) for allowing the leakage signal to escape to the ground. As described above, the high-frequency switch circuit 100 is configured by combining two transfer circuits and two shunt circuits.

  Hereinafter, the operation of the high-frequency switch circuit 100 configured as described above will be described.

  When a signal is transmitted from the first input / output terminal 121 to the third input / output terminal 123, a high voltage (for example, 3 V) is applied to the first control terminal 131, and the second control terminal 132 is applied to the second control terminal 132. A low voltage (for example, 0 V) is applied. As a result, the FETs 101 to 104 and 115 to 118 are turned on, and the FETs 105 to 108 and 111 to 114 are turned off, so that the first input / output terminal 121 and the third input / output terminal 123 are short-circuited. Therefore, a signal can be transmitted from the first input / output terminal 121 to the third input / output terminal 123.

  On the other hand, when a signal is transmitted from the second input / output terminal 122 to the third input / output terminal 123, a low voltage is applied to the first control terminal 131, and the second control terminal 132 is applied. A High voltage is applied. As a result, the FETs 101 to 104 and 115 to 118 are turned off, and the FETs 105 to 108 and 111 to 114 are turned on, so that the second input / output terminal 122 and the third input / output terminal 123 are short-circuited. Therefore, a signal can be transmitted from the second input / output terminal 122 to the third input / output terminal 123.

  FIG. 2 is a diagram illustrating the capacitance component of the FET in the off state in the high-frequency switch circuit 200.

  FIG. 2 shows the capacitance component of the transfer FET in the off state when a signal is transmitted from the first input / output terminal 221 to the third input / output terminal 223. When a signal is transmitted from the first input / output terminal 221 to the third input / output terminal 223, the FETs 201 to 204 and 215 to 218 are controlled to be in an on state, and the FETs 205 to 208 and 211 to 214 are controlled to be in an off state. At this time, the signal voltage input from the first input / output terminal 221 is divided by the stray capacitances (C11 to C14, C21 to C28) of the off-state FET. Therefore, the voltages at points B, C, and D shown in FIG. 2 are about 3/4 times, 2/4 times, and 1/4 times the voltage at point A, respectively. As described above, the terminal voltage decreases as the distance from the signal path increases. However, since the degree of influence on the signal path is reduced in proportion to the decrease in the voltage, the gate width of the FET can be reduced.

  Therefore, the closer the gate width of the FET constituting the transfer circuit is to the active terminal when it is off (the input / output terminal to which signal power is applied when the switch circuit is off) when the transfer circuit is off, Those having a large gate width are used. Specifically, considering that the signal power is applied to the third input / output terminal 223 side when the first basic switch unit is in an off state (that is, the FETs 201 to 204 are in an off state), the FETs 204 to For the gate width of 201, FETs having a gate width of 4000 μm, 3700 μm, 3400 μm, and 3250 μm are used in this order. In addition, when the second basic switch unit is in the off state (that is, the FETs 205 to 208 are in the off state), the gates of the FETs 205 to 208 are considered in consideration that signal power is applied to the third input / output terminal 223 side. For the width, FETs having a gate width of 4000 um, 3700 um, 3400 um, and 3250 um are used in order.

  FIG. 3A is a diagram showing the input power dependence of the insertion loss of the high-frequency switch circuit (reference numeral 200) in FIG. 2, and FIG. 3B is a harmonic of the high-frequency switch circuit (reference numeral 200). It is a figure which shows the input power dependence of distortion.

  In the high-frequency switch circuit 200 of FIG. 2, characteristics when the path from the first input / output terminal 221 to the third input / output terminal 223 is valid, and the third input / output terminal 222 to the third input / output terminal. The characteristics are the same when the path to the output terminal 223 is valid. Therefore, the results shown in FIGS. 3A and 3B may be regarded as the characteristics in any of these cases.

  In FIG. 3A, the vertical axis represents insertion loss, and the horizontal axis represents input power. As can be seen from FIG. 3A, the insertion loss at the low input level in the high-frequency switch circuit 200 is equivalent to that of the conventional high-frequency switch circuit, and the input level at which the insertion loss deteriorates in the high-frequency switch circuit 100 is the conventional level. It is about 0.5 dBm larger than the high-frequency switch circuit.

  In FIG. 3B, the vertical axis represents harmonic distortion, and the horizontal axis represents input power. As can be seen from FIG. 3B, the second harmonic distortion at the low input level in the high frequency switch circuit 200 is equivalent to the conventional high frequency switch circuit, and the degradation point of the second harmonic distortion in the high frequency switch circuit 100. Is approximately 1.0 dBm larger than the conventional high-frequency switch circuit.

  In the above description, the value of the gate width of the FET included in the high-frequency switch circuit 200 is shown as an example, but is not limited to the above value.

  In general, in the case of a transfer circuit composed of n (n is an integer of 2 or more) FETs in which the basic switch units are connected in series, the i-th (i is 1 or more and n) counting from the active terminal side when OFF. Wg (1) should be larger than any of Wg (2) to Wg (n), where Wg (i) is the gate width of the FET of the following integer). More preferably, the following equation (11) may be satisfied, and more preferably, the following equation (12) may be satisfied.

  Wg (1)> Wg (2) ≧ ... ≧ Wg (n−1) ≧ Wg (n) (11)

  Wg (1)> Wg (2)> ...> Wg (n-1)> Wg (n) ... (12)

  As described above, by using FETs having different values for the gate widths of the FETs connected in multiple stages, the input power can be increased while maintaining the same performance as that of the conventional high-frequency switch circuit.

  The same result can be obtained when the FET connected in multiple stages is a multi-gate FET or a high-frequency switch circuit in which a single gate FET and a multi-gate FET are mixed.

  Actually, for example, in an enhancement type MESFET device formed on a compound semiconductor substrate (such as a GaAs substrate), a plurality of MESFETs having meander-like or multi-finger gate electrodes are separated from each other on the semiconductor substrate. The gate width of each gate electrode is set to match the actual gate-source voltage.

  In this way, by introducing a flexible transistor size design concept that appropriately sets the gate width corresponding to the actual gate-source voltage, rather than uniformly defining the gate width of the multi-stage FET. A high-performance high-frequency switch circuit can be realized without difficulty.

(Second Embodiment)
With reference to FIGS. 4 and 5, a high-frequency switch circuit according to a second embodiment of the present invention and a semiconductor device using the same will be described.

  FIG. 4 is a circuit diagram of the high-frequency switch circuit according to the second embodiment of the present invention, and shows the capacitance component of the FET in the off state in the high-frequency switch circuit 400. FIG. 4 shows the capacitance component of the shunt FET in the off state when a signal is transmitted from the first input / output terminal 421 to the third input / output terminal 423.

  When signals are transmitted from the first input / output terminal 421 to the third input / output terminal 423, the FETs 401 to 404 and 415 to 418 are controlled to be in an on state, and the FETs 405 to 408 and 411 to 414 are controlled to be in an off state.

  At this time, the signal voltage input from the first input / output terminal 421 is divided by the stray capacitances (C31 to C34, C41 to C48) of the FET in the off state. Therefore, the voltages at points F, G, and H shown in FIG. 4 are 3/4 times, 2/4 times, and 1/4 times the voltage at point E, respectively. As described above, the terminal voltage decreases as the distance from the signal path increases. However, since the degree of influence on the signal path is reduced in proportion to the decrease in the voltage, the gate width of the FET can be reduced.

  Therefore, as the gate width of the FET constituting the shunt circuit, a gate having a larger gate width is used as it is closer to the off-time active terminal when the shunt circuit is in the off state. Specifically, considering that the signal power is applied to the third input / output terminal 423 side when the first basic switch unit is in the off state (that is, the FETs 401 to 404 are off), the FETs 404 to 404 are considered. For the gate width 401, FETs having gate widths of 400 μm, 300 μm, 240 μm, and 200 μm are used in this order. In addition, when the second basic switch unit is in the off state (that is, the FETs 405 to 408 are in the off state), the gates of the FETs 405 to 408 are taken into consideration that the signal power is applied to the third input / output terminal 423 side. For the width, FETs having gate widths of 400 μm, 300 μm, 240 μm, and 200 μm in order are used.

  5A is a diagram showing the input power dependence of the insertion loss of the high-frequency switch circuit (reference numeral 400) in FIG. 4, and FIG. 5B is the high-frequency switch circuit (reference numeral 400) in FIG. It is a figure which shows the input power dependence of the harmonic distortion of.

  Note that in the high-frequency switch circuit 400, characteristics when the path from the first input / output terminal 421 to the third input / output terminal 423 is effective, and the second input / output terminal 422 to the third input / output terminal 423 are used. The characteristics when the route to is valid are the same. Therefore, the results shown in FIGS. 5A and 5B may be regarded as the characteristics in any of these cases.

  In FIG. 5A, the vertical axis represents insertion loss and the horizontal axis represents input power. As can be seen from FIG. 5A, the insertion loss at the low input level in the high-frequency switch circuit 400 is equivalent to that of the conventional high-frequency switch circuit, and the degradation point of the second harmonic distortion in the high-frequency switch circuit 400 is the conventional. This is about 0.2 dBm larger than the high-frequency switch circuit.

  In FIG. 5B, the vertical axis represents harmonic distortion and the horizontal axis represents input power. As can be seen from FIG. 5B, the second harmonic distortion at the low input level in the high frequency switch circuit 400 is equivalent to the conventional high frequency switch circuit, and the degradation point of the second harmonic distortion in the high frequency switch circuit 400. Is approximately 0.5 dBm larger than the conventional high-frequency switch circuit.

  In the above description, the value of the gate width of the FET included in the high-frequency switch circuit 400 is shown as an example, but is not limited to the above value.

  In general, in the case of a transfer circuit composed of n (n is an integer of 2 or more) FETs in which the basic switch units are connected in series, the i-th (i is 1 or more and n) counting from the active terminal side when OFF. Wg (1) should be larger than any of Wg (2) to Wg (n), where Wg (i) is the gate width of the FET of the following integer). More preferably, the following equation (21) may be satisfied, and more preferably, the following equation (22) may be satisfied.

  Wg (1)> Wg (2) ≧ ... ≧ Wg (n−1) ≧ Wg (n) (21)

  Wg (1)> Wg (2)> ...> Wg (n-1)> Wg (n) ... (22)

  As described above, by using FETs having different values for the gate widths of the FETs connected in multiple stages, the input power can be increased while maintaining the same performance as that of the conventional high-frequency switch circuit.

  The same result can be obtained when the FET connected in multiple stages is a multi-gate FET or a high-frequency switch circuit in which a single gate FET and a multi-gate FET are mixed.

(Third embodiment)
A high frequency switch circuit according to a third embodiment of the present invention and a semiconductor device using the same will be described with reference to FIGS. The high-frequency switch circuit according to the present embodiment is a mixture of the high-frequency switch circuit according to the first embodiment and the second embodiment.

  FIG. 6 is a diagram illustrating the capacitance component of the FET in the off state in the high-frequency switch circuit 600. FIG. 6 shows the capacitance component of the FET in the off state when a signal is transmitted from the first input / output terminal 621 to the third input / output terminal 623. When a signal is transmitted from the first input / output terminal 621 to the third input / output terminal 623, the FETs 601 to 204 and 615 to 618 are controlled to be in an on state, and the FETs 605 to 608 and 611 to 614 are controlled to be in an off state. At this time, the signal voltage input from the first input / output terminal 621 is divided by the stray capacitances C11 to C14, C21 to C28, C31 to C34, and C41 to C48 of the off-state FET. For this reason, the voltages at points B, C, and D shown in FIG. 6 are 3/4 times, 2/4 times, and 1/4 times the voltage at point A, respectively, and B (F ), C (G), and D (H) are 3/4, 2/4, and 1/4 times the voltage at point A (E), respectively.

  As described above, the terminal voltage decreases as the distance from the signal path increases. However, since the degree of influence on the signal path is reduced in proportion to the decrease in the voltage, the gate width of the FET can be reduced.

  Therefore, as the gate width of the FET constituting the transfer circuit, a gate having a larger gate width is used as it is closer to the off-time active terminal when the transfer circuit is in the off state. Specifically, when the first basic switch unit is in the off state (that is, the FETs 601 to 604 are in the off state), considering that the signal power is applied to the third input / output terminal 623 side, FETs having a gate width of 4000 μm, 3700 μm, 3400 μm, and 3250 μm are sequentially used as the gate width of 601. In addition, when the second basic switch unit is in an off state (that is, the FETs 605 to 608 are in an off state), the gates of the FETs 605 to 608 are considered in consideration that signal power is applied to the third input / output terminal 623 side. For the width, FETs having a gate width of 4000 μm, 3700 μm, 3400 μm, and 3250 μm in order are used.

  As the gate width of the FET constituting the shunt circuit, a gate having a larger gate width is used as it is closer to the input / output terminal when in the off state. Specifically, in consideration of the fact that signal power is applied to the first input / output terminal 621 side when the third basic switch unit is in the off state (that is, the FETs 611 to 614 are in the off state). For the gate width 614, FETs having gate widths of 400 μm, 300 μm, 240 μm, and 200 μm are used in this order. In addition, when the fourth basic switch unit is in an off state (that is, the FETs 615 to 618 are in an off state), the gates of the FETs 615 to 618 are considered in consideration that signal power is applied to the second input / output terminal 622 side. For the width, FETs having gate widths of 400 μm, 300 μm, 240 μm, and 200 μm in order are used.

  7A is a diagram showing the input power dependence of the insertion loss of the high-frequency switch circuit (reference number 600) of FIG. 6, and FIG. 7B is the high-frequency switch circuit of FIG. 6 (reference number 600). It is a figure which shows the input power dependence of the harmonic distortion of. Note that in the high-frequency switch circuit 600, characteristics when the path from the first input / output terminal 621 to the third input / output terminal 623 is effective, and the second input / output terminal 622 to the third input / output terminal 623 are used. The characteristics when the route to is valid are the same. Therefore, the results shown in FIGS. 7A and 7B may be regarded as the characteristics in any of these cases.

  In FIG. 7A, the vertical axis represents insertion loss, and the horizontal axis represents input power. As can be seen from FIG. 7A, the insertion loss at the low input level in the high-frequency switch circuit 600 is equivalent to that of the conventional high-frequency switch circuit, and the degradation point of the second harmonic distortion in the high-frequency switch circuit 600 is the conventional. This is about 0.5 dBm larger than the high-frequency switch circuit.

  In FIG. 7B, the vertical axis represents harmonic distortion, and the horizontal axis represents input power. As can be seen from FIG. 7B, the second harmonic distortion at the low input level in the high frequency switch circuit 600 is equivalent to the conventional high frequency switch circuit, and the degradation point of the second harmonic distortion in the high frequency switch circuit 600. Is approximately 2.0 dBm larger than the conventional high-frequency switch circuit.

  In the above description, the value of the gate width of the FET included in the high-frequency switch circuit 600 is shown as an example, but is not limited to the above value.

  In general, in the case of a transfer circuit composed of n (n is an integer of 2 or more) FETs in which the basic switch units are connected in series, the i-th (i is 1 or more and n) counting from the active terminal side when OFF. Wg (1) should be larger than any of Wg (2) to Wg (n), where Wg (i) is the gate width of the FET of the following integer). More preferably, the following equation (31) may be satisfied, and more preferably, the following equation (32) may be satisfied.

  Wg (1)> Wg (2) ≧ ... ≧ Wg (n−1) ≧ Wg (n) (31)

  Wg (1)> Wg (2)> ...> Wg (n-1)> Wg (n) ... (32)

  As described above, by using FETs having different values for the gate widths of the FETs connected in multiple stages, the input power can be increased while maintaining the same performance as that of the conventional high-frequency switch circuit.

  The same result can be obtained when the FET connected in multiple stages is a multi-gate FET or a high-frequency switch circuit in which a single gate FET and a multi-gate FET are mixed.

  As described above, according to the high-frequency switch circuit of the present invention and the semiconductor device using the same, different gate widths are used as the gate widths of the multi-stage connected field effect transistors (or multi-gate field effect transistors). Thus, the input power can be increased while maintaining the same performance as the conventional high-frequency switch circuit.

  Therefore, in the high frequency switch circuit, the input power can be increased without difficulty without deteriorating harmonic distortion and insertion loss.

  The high-frequency switch circuit of the present invention has an effect that the input power can be increased while maintaining the same performance as the conventional high-frequency switch circuit. Therefore, the high-frequency switch circuit can be used for various high-frequency switch circuits such as an antenna switching circuit. it can.

Circuit diagram of high-frequency switch circuit according to the present invention 1 is a circuit diagram of a high-frequency switch circuit according to a first embodiment of the present invention. Characteristics diagram of the high-frequency switch circuit shown in FIG. 1 and the conventional high-frequency switch circuit Circuit diagram of high-frequency switch circuit according to second embodiment of the present invention FIG. 4 is a characteristic diagram of the high-frequency switch circuit and the conventional high-frequency switch circuit. Circuit diagram of high-frequency switch circuit according to second embodiment of the present invention Characteristics diagram of the high-frequency switch circuit shown in FIG. 6 and the conventional high-frequency switch circuit Circuit diagram of conventional high-frequency switch circuit

Explanation of symbols

100, 200, 400, 600 ... high frequency switch circuit 101-108, 111-118, 201-208, 211-218, 401-408, 411-418, 601-608, 611-618 ... FET
121, 221, 421, 621... First input / output terminal 122, 222, 422, 622... Second input / output terminal 123, 223, 423, 623 ... Third input / output terminal 131, 231, 431, 631. First control terminal 132, 232, 432, 632 ... Second control terminal 141, 142, 241, 242, 441, 442, 641, 642 ... Ground terminal

Claims (13)

A plurality of input / output terminals for inputting and outputting high-frequency signals;
A basic switch provided between one of the input / output terminals and the ground terminal, or between the two input / output terminals;
A control terminal to which a control voltage for controlling on / off of the basic switch unit is input, and
The basic switch unit is configured by a switch circuit having a structure including a plurality of gate electrodes configured to include a multi-stage field effect transistor, and the switch circuit includes a plurality of input / output terminals. The gate width of a field effect transistor having a gate electrode close to one input / output terminal as a component, and the gate width of a field effect transistor having any gate electrode farther from the input / output terminal as a component High-frequency switch circuit characterized by being larger than The high-frequency switch circuit according to claim 1,
The basic switch portion provided between one of the input / output terminals and a ground terminal,
A plurality of field effect transistors connected in series;
A plurality of resistance elements each having one terminal connected to the gate electrode of any one of the field effect transistors and the other terminal connected to the control terminal;
Among the plurality of field effect transistors constituting the first switch circuit, any one of the remaining electric fields in which the gate width of the field effect transistor closest to the input / output terminal is located farther from the input / output terminal A high-frequency switch circuit characterized by being larger than the gate width of an effect transistor. A high-frequency switch circuit according to claim 2,
The first switch circuit includes n (n is an integer of 2 or more) series-connected field effect transistors,
When the gate width of the i-th field effect transistor counted from the input / output terminal side (i is an integer of 1 to n) is Wg (i), the following equation (1) is satisfied. Switch circuit.
Wg (1)> Wg (2) ≧ ... ≧ Wg (n−1) ≧ Wg (n) (1) The high-frequency switch circuit according to claim 1,
The basic switch provided between the input / output terminals is:
A plurality of field effect transistors connected in series;
A plurality of resistance elements each having one terminal connected to the gate electrode of any one of the field effect transistors and the other terminal connected to the control terminal;
The second switch circuit constitutes the second switch circuit when the input / output terminal to which the signal power is applied when the second switch circuit is in the OFF state is used as the active terminal when OFF. Of the plurality of field effect transistors, the gate width of the field effect transistor closest to the off-state active terminal is larger than the gate width of any remaining field effect transistor located farther from the off-state active terminal. A high-frequency switch circuit characterized by that. A high-frequency switch circuit according to claim 4,
The second switch circuit includes n (n is an integer of 2 or more) field effect transistors connected in series,
When the gate width of the i-th field effect transistor counting from the active terminal side at the off time (i is an integer not less than 1 and not more than n) is Wg (i), the following equation (2) is satisfied. High frequency switch circuit.
Wg (1)> Wg (2) ≧ ... ≧ Wg (n−1) ≧ Wg (n) (2) The high-frequency switch circuit according to claim 1,
The basic switch portion provided between one of the input / output terminals and a ground terminal,
A multi-gate field effect transistor having a structure in which a plurality of gate electrodes are disposed between a source electrode and a drain electrode;
A plurality of resistance elements each having one terminal connected to one of the gates of the multi-gate field effect transistor and the other terminal connected to the control terminal;
Among the multi-gate field effect transistors constituting the third switch circuit, the field effect transistor having a gate electrode closest to the input / output terminal as a component has a gate width farther from the active terminal when it is off. A high-frequency switch circuit characterized by being larger than the gate width of a field effect transistor having any one of the remaining gate electrodes as a constituent element. The high-frequency switch circuit according to claim 6,
The third switch circuit includes a multi-gate field effect transistor having n (n is an integer of 2 or more) gate electrodes,
When the gate width of the i-th field effect transistor counted from the input / output terminal side (i is an integer of 1 to n) is Wg (i), the following equation (3) is satisfied. Switch circuit.
Wg (1)> Wg (2) ≧ ... ≧ Wg (n−1) ≧ Wg (n) (3) The high-frequency switch circuit according to claim 1,
The basic switch portion provided between the input / output terminals is
A multi-gate field effect transistor having a structure in which a plurality of gate electrodes are disposed between a source electrode and a drain electrode;
A plurality of resistance elements each having one terminal connected to one of the gates of the multi-gate field effect transistor and the other terminal connected to the control terminal.
Among the input / output terminals, when the input / output terminal to which signal power is applied when the fourth switch circuit is in the off state is an active terminal when off, of the gate electrodes of the multi-gate field effect transistor A field effect having a gate width of a field effect transistor having a gate electrode closest to the active terminal at the time of off as a constituent, and any remaining gate electrode at a position farther from the active terminal at the time of off. A high frequency switch circuit characterized by being larger than a gate width of a transistor. A high-frequency switch circuit according to claim 8,
The fourth switch circuit includes a multi-gate field effect transistor having n (n is an integer of 2 or more) gate electrodes,
When the gate width of the i-th field effect transistor counting from the active terminal side in the off state (i is an integer not less than 1 and not more than n) is Wg (i), the following equation (4) is satisfied. High frequency switch circuit.
Wg (1)> Wg (2) ≧ ... ≧ Wg (n−1) ≧ Wg (n) (4)   The first, second, third, and fourth switch circuits according to any one of claims 2 to 9 are arbitrarily combined, and a flow of a high-frequency signal is arbitrarily switched between a plurality of input / output terminals. A high-frequency switch circuit configured as described above. First to third input / output terminals (121, 122, 123);
First and second ground terminals (141, 142);
First and second control terminals (131, 132);
A first transfer switch (101 to 104) connected between the first input / output terminal (121) and the third input / output terminal (123);
A second transfer switch (105-108) connected between the second input / output terminal (122) and the third input / output terminal (123);
A first shunt switch (111 to 114) connected between the first input / output terminal (121) and the first ground terminal (141);
A second shunt switch (115-118) connected between the second input / output terminal (122) and the second ground terminal (142),
The first transfer switch (101 to 104) and the second shunt switch (115 to 118) are simultaneously turned on / off by a first control signal input from the first control terminal (131). In addition, the second transfer switch (105 to 108) and the first shunt switch (111 to 114) are simultaneously turned on by a second control signal input from the second control terminal (132). / High-frequency signal path between the first and third input / output terminals (121, 123) or high-frequency signal path between the second and third input / output terminals (122, 123) Is a single pole double throw (SPDT) circuit that controls the flow of high-frequency signals,
The first switch circuit according to claim 2 or claim 3 or the third switch circuit according to claim 6 or claim 7 is used as the first and second transfer switches,
Further, as the first and second shunt switches, the second switch circuit according to claim 4 or claim 5 or the fourth switch circuit according to claim 8 or claim 9 is used. Single pole double throw switch featuring A plurality of input / output terminals for inputting / outputting a high-frequency signal; and a switch circuit configured by a multi-stage field effect transistor for turning on / off electrical connection between the input / output terminals. A semiconductor device in which a high-frequency switch circuit is integrated on a semiconductor substrate,
The switch circuit has a configuration in which a plurality of individual field effect transistors are connected in multiple stages, or a plurality of gate electrodes are arranged between a source electrode and a drain electrode provided on the semiconductor substrate at intervals. Having any of the configurations including a multi-gate field effect transistor provided;
In addition, when an input / output terminal to which signal power is applied when the switch circuit is in an off state is an off-time active terminal, the switch circuit includes the plurality of field-effect transistors connected in multiple stages. The gate width of the field effect transistor closest to the active terminal is set to be larger than the gate width of any of the remaining field effect transistors located farther from the active terminal when the transistor is off. A semiconductor device, wherein the uniformity of the size of each field effect transistor is intentionally broken. A method for designing a high-frequency switch circuit in which a transfer switch constituting a high-frequency switch circuit is configured using a multi-stage field effect transistor,
The gate-source capacitance of the field-effect transistor in a position close to the input / output terminal to which signal power is applied when the transfer switch is in an OFF state is made non-uniform in the multi-stage field-effect transistor Is set to be larger than the gate-source capacitance of any one of the field-effect transistors located further away.

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