JP2007251226A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To secure high reliability even in a vertical packed multi-chip package in which a plurality of semiconductor chips are stacked. <P>SOLUTION: The semiconductor device 34 provided with a specified circuit pattern includes a lower layer semiconductor chip (a first semiconductor chip) 36, in which a digital circuit, for example, is formed, and an upper layer semiconductor chip (a second semiconductor chip) 37, in which an analogue circuit is formed, stacked through a heat transmitting conductive sheet (heat transmitting conductor) 38 with their circuit formed sides facing each other on a substrate 35, on which a lattice of ball-shaped bumps 35a, 35a, ... is formed, and sealed with molded resin 39. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device on which a plurality of semiconductor chips are mounted, and more particularly to a vertical mounting type semiconductor device.

In recent years, as a package system for semiconductor devices, a multi-chip package (MCP) system in which a plurality of IC chips are encapsulated in a single package to increase the chip mounting density is used to meet the demand for miniaturization. It has been.
Multi-chip packages are classified into a planar mounting type in which a plurality of chips are mounted in a planar shape on the same substrate and a vertical mounting type in a stack structure in which a plurality of chips are stacked in the vertical direction.
In the planar mounting type semiconductor device 101, as shown in FIG. 31, semiconductor chips 103 and 104 on which, for example, memory circuits are formed are arranged on the same plane on a substrate.
For vertically mounted semiconductor devices. For example, as shown in FIG. 32, there is known a semiconductor device 108 having a configuration in which semiconductor chips 106 and 107 are arranged and laminated on a substrate 105 so that circuit formation surfaces face upward.
Further, as shown in FIG. 33, a COC (chip on chip) type semiconductor device 112 in which semiconductor chips 110 and 111 are arranged so that circuit formation surfaces face each other on a substrate 109 has been put into practical use. .

Next, a method for manufacturing a semiconductor device employing a vertically mounted multichip package will be described.
For example, in the above-described method of manufacturing a COC type semiconductor device, first, as shown in FIG. 34A, an adhesive 113 is dropped or applied on a substrate 109, and a lower-layer side semiconductor chip 110 is formed on the substrate 109. Is placed. Next, as shown in FIG. 2B, the adhesive 113 is cured to form bumps 110 a on the semiconductor chip 110.
Next, as shown in FIG. 2C, the upper semiconductor chip 111 is positioned and placed on the semiconductor chip 110 so that the corresponding electrodes of the semiconductor chips 110 and 111 are in contact with each other, and heated and pressed. Then, the semiconductor chip 110 and the semiconductor chip 111 are joined. Thereafter, resin sealing is performed to obtain a semiconductor device 112 as shown in FIG.
When manufacturing a semiconductor device employing a vertically mounted multichip package, the thickness of the cured adhesive may vary, and the semiconductor chip on the lower layer may be inclined with respect to the substrate surface. is there.

However, in a semiconductor device that employs a vertical mounting type multi-chip package in order to achieve such miniaturization, particularly when a semiconductor chip with high power consumption is incorporated, the temperature of the semiconductor chip suddenly rises. In addition, there is a problem that heat is not sufficiently dissipated, causing malfunction or being destroyed.
For this reason, for example, as described in Japanese Patent Application Laid-Open No. 2000-294723, a heat dissipating metal plate is disposed above or between the semiconductor chips on the upper layer side. Technologies for dissipating the generated heat have been proposed.
JP 2000-294723 A

However, in the technique described in the above publication, in order to increase the functionality, for example, when a semiconductor chip in which an analog circuit is formed and a semiconductor chip in which a digital circuit is formed are mixedly mounted, the problem occurs in one semiconductor chip. There was a problem that noise adversely affects the other semiconductor chip.
In other words, although the technology described in the above publication has improved the heat dissipation characteristics, no countermeasures against noise are taken, so the analog circuit is particularly sensitive to noise, so it is easy for the analog circuit to induce noise and malfunction. There was a problem that reliability was lowered.
Therefore, there is a problem that it is difficult to reduce the size by adopting a vertical mounting type multichip package.

  The present invention has been made in view of the above-described circumstances. Even when a vertically mounted multi-chip package in which a plurality of semiconductor chips are stacked is adopted, heat dissipation is improved and adverse effects due to noise are eliminated. An object of the present invention is to provide a semiconductor device capable of ensuring high reliability.

  In order to solve the above problems, the invention according to claim 1 relates to a semiconductor device in which a plurality of semiconductor chips are stacked on a substrate, and the semiconductor chip is disposed between the substrate and the uppermost semiconductor chip. At least one heat transfer conductor having heat conductivity and conductivity for dissipating the heat generated in step 1 and shielding electromagnetic noise is inserted, and the heat transfer conductor is held at the ground potential of the substrate. The first and second semiconductor chips that are connected to the ground wiring and constitute the plurality of semiconductor chips and are adjacent to each other via the heat transfer conductor are in a state in which their circuit formation surfaces face each other. The heat transfer conductor is laminated and mounted on the substrate, and the heat transfer conductor is formed by laminating an insulating layer and a shield layer electrically and thermally connected to a ground wiring of the substrate, and the insulating layer and Within the shield layer It is characterized in that the connection wiring layer for electrically connecting the first semiconductor chip and the terminal of the second semiconductor chip is provided.

As described above, according to the configuration of the semiconductor device of the present invention, for example, the first semiconductor chip and the second semiconductor chip are arranged in the vertical direction. A heat transfer conductor held at a ground potential is interposed between the semiconductor chip and the second semiconductor chip, thereby transferring noise propagation between the first semiconductor chip and the second semiconductor chip. Can be shielded with a conductor.
In addition, heat generated in the first semiconductor chip and the second semiconductor chip is conducted to the heat transfer conductor through the contact location and is dissipated. For this reason, the heat dissipation characteristics can be improved and the operation can be stabilized. Therefore, reliability can be improved.

In addition, the first semiconductor chip and the second semiconductor chip are electrically connected to the substrate via the heat transfer conductor, thereby connecting the first semiconductor chip and the second semiconductor chip to the substrate, respectively. For example, the wire bonding process can be omitted.
In addition, by arranging the first semiconductor chip and the second semiconductor chip to be electrically connected to each other via the heat transfer conductor, the arrangement positions of the terminals of the first semiconductor chip and the second semiconductor chip. The degree of freedom in circuit design including the selection of can be increased.

  The first and second semiconductor chips adjacent to each other via the heat transfer conductor are stacked and mounted on the substrate with their circuit formation surfaces facing each other.

Embodiments of the present invention will be described below with reference to the drawings. The description will be made specifically using reference examples and examples.
First Reference Example FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first reference example of the present invention.
The semiconductor device 1 in this example is a semiconductor device in which two semiconductor chips are vertically mounted. As shown in FIG. 1, a predetermined circuit pattern is formed and a ball shape as an external connection electrode is formed. Are formed on a BGA (ball grid array) type substrate 2 in which bumps 2a, 2a,. The upper layer semiconductor chip (second semiconductor chip) 4 thus formed is laminated via a heat transfer conductive plate (heat transfer conductor) 5 made of a metal plate with the circuit formation surface facing upward. It is mounted and sealed with a mold resin 6.

The heat transfer conductive plate 5 is a plate-like member made of, for example, aluminum having a thickness of, for example, 20 [μm] to 150 [μm].
Here, the lower layer semiconductor chip 3, the upper layer semiconductor chip 4, and the heat transfer conductive plate 5 are electrically connected to the substrate 2 via bonding wires 7, 8, and 9, respectively. In particular, the heat transfer conductive plate 5 is connected to the ground wiring of the substrate 2 via the bonding wire 9 and is held at the ground potential.
In this example, the size of the heat transfer conductive plate 5 is set to be smaller than the size of the lower layer semiconductor chip 3 and larger than the size of the upper layer semiconductor chip 4. The substrate 2 and the lower semiconductor chip 3, the lower semiconductor chip 3 and the heat transfer conductive plate 5, and the heat transfer conductive plate 5 and the upper semiconductor chip 4 are each temporarily attached and sealed with an adhesive.

Next, the operation of the semiconductor device of this example will be described.
A heat transfer conductive plate 5 is interposed between the lower layer semiconductor chip 3 and the upper layer semiconductor chip 4, and this heat transfer conductive plate 5 is connected to the ground wiring of the substrate 2 through bonding wires 9. Is done.
As a result, the heat transfer conductive plate 5 is held at the ground potential, and noise propagation between the lower semiconductor chip 3 and the upper semiconductor chip 4 is blocked by the heat transfer conductive plate 5.
For example, noise emitted from the digital circuit of the lower layer semiconductor chip 3 and directed to the analog circuit of the upper layer semiconductor chip 4 is blocked by the heat transfer conductive plate 5. Therefore, this noise does not adversely affect the signal flowing through the analog circuit of the upper semiconductor chip 4.

Similarly, noise emitted from the analog circuit of the upper semiconductor chip 4 and directed to the digital circuit of the lower semiconductor chip 3 is blocked by the heat transfer conductive plate 5. Therefore, this noise does not adversely affect the signal flowing through the digital circuit of the lower layer semiconductor chip 3.
For this reason, for example, it is possible to avoid a malfunction that occurs due to noise on a signal that flows through the analog circuit of the upper semiconductor chip 4 and an inversion or delay of the signal that flows through the digital circuit of the lower semiconductor chip 3.
Further, the heat generated in the lower semiconductor chip 3 and the upper semiconductor chip 4 is conducted to the heat transfer conductive plate 5 through the contact points with the heat transfer conductive plate 5 and is dissipated. For this reason, the thermal resistance from the lower layer semiconductor chip 3 and the upper layer semiconductor chip 4 to the outer surface (package surface) of the mold resin 6 is reduced.

Thus, according to the configuration of this example, since the lower layer semiconductor chip 3 and the upper layer semiconductor chip 4 are arranged in the vertical direction, it is possible to achieve downsizing, and the lower layer semiconductor chip 3 and the upper layer semiconductor chip 4 can be reduced. Since the heat transfer conductive plate 5 held at the ground potential is interposed therebetween, the noise transfer between the lower layer semiconductor chip 3 and the upper layer semiconductor chip 4 can be blocked by the heat transfer conductive plate 5.
Therefore, in particular, it is possible to improve reliability by avoiding the occurrence of malfunction due to noise on the signal flowing through the analog circuit of the upper semiconductor chip 4 and causing inversion or delay of the signal flowing through the digital circuit of the lower semiconductor chip 3. Can do.
Moreover, since the metal plate-shaped member is used as the heat transfer conductive plate 5, the heat generated in the lower layer semiconductor chip 3 and the upper layer semiconductor chip 4 is conducted to the heat transfer conductive plate 5 through the contact points, Dissipated. For this reason, since the thermal resistance from the lower layer semiconductor chip 3 and the upper layer semiconductor chip 4 to the outer surface (package surface) of the mold resin 6 is reduced, the heat dissipation characteristics can be improved and the operation can be stabilized. Therefore, reliability can be improved.

Second Reference Example FIG. 2 is a cross-sectional view showing a configuration of a semiconductor device according to a second reference example of the present invention.
A significant difference between this example and the first reference example described above is that a heat transfer conductive plate is also interposed between the lower semiconductor chip and the substrate, as shown in FIG.
Since the configuration other than this is substantially the same as the configuration of the first reference example described above, the description thereof will be simplified.

  The semiconductor device 11 in this example is a semiconductor device in which two semiconductor chips are vertically mounted. As shown in FIG. 2, a predetermined circuit pattern is formed and a ball shape as an external connection electrode is formed. Of the bumps 12a, 12a,... Are arranged in a lattice shape, and the lower semiconductor chip (first circuit) on which the digital circuit is formed, for example, is disposed above the substrate 12 with the circuit formation surface facing upward. Semiconductor chip) 13 and upper semiconductor chip (second semiconductor chip) 14 on which an analog circuit is formed, substrate 12 and lower layer, for example. For example, an aluminum heat transfer conductive plate (heat transfer conductor) 15 interposed between the semiconductor chip 13 and the lower semiconductor chip 13 and the upper semiconductor chip 14 are inserted. And for example, aluminum heat transfer conductive plate (heat transmitting conductor) 16, which is provided with a mold resin 17 for sealing the lower semiconductor chip 13 and the upper semiconductor chip 14 and the like.

Here, the lower layer semiconductor chip 13, the upper layer semiconductor chip 14, and the heat transfer conductive plates 15 and 16 are electrically connected to the substrate 12 through bonding wires 18, 19, 21, and 22, respectively. In particular, the heat transfer conductive plates 15 and 16 are connected to the ground wiring of the substrate 12 via the bonding wires 21 and 22 and are held at the ground potential.
In this example, the lower layer semiconductor chip 13 and the heat transfer conductive plate 16 arranged on the upper layer side, the heat transfer conductive plate 15, the lower layer semiconductor chip 13 and the heat transfer conductive plate 16 arranged on the lower layer side as the upper layer semiconductor chip 14. The dimension is made to be smaller than that.

Next, the operation of the semiconductor device of this example will be described.
A heat transfer conductive plate 16 is inserted between the lower layer semiconductor chip 13 and the upper layer semiconductor chip 14, and this heat transfer conductive plate 16 is connected to the ground wiring of the substrate 12 through the bonding wires 22. Is done.
As a result, the heat transfer conductive plate 16 is held at the ground potential, and the noise transfer between the lower semiconductor chip 13 and the upper semiconductor chip 14 is blocked by the heat transfer conductive plate 16.
For example, noise emitted from the digital circuit of the lower layer semiconductor chip 13 and directed to the analog circuit of the upper layer semiconductor chip 14 is blocked by the heat transfer conductive plate 16. Therefore, this noise does not adversely affect the signal flowing through the analog circuit of the upper semiconductor chip 14.

Similarly, noise emitted from the analog circuit of the upper semiconductor chip 14 and directed to the digital circuit of the lower semiconductor chip 13 is blocked by the heat transfer conductive plate 16. Therefore, this noise does not adversely affect the signal flowing through the digital circuit of the lower layer semiconductor chip 13.
For this reason, for example, it is possible to avoid a malfunction that occurs due to noise on a signal that flows through the analog circuit of the upper semiconductor chip 14, or inversion or delay of a signal that flows through the digital circuit of the lower semiconductor chip 13.

Further, a heat transfer conductive plate 15 is interposed between the substrate 12 and the lower semiconductor chip 13, and the heat transfer conductive plate 15 is connected to the ground wiring of the substrate 12 through the bonding wire 21. Is done.
As a result, the heat transfer conductive plate 15 is held at the ground potential, and the noise transfer between the substrate 12 and the lower layer semiconductor chip 13 is blocked by the heat transfer conductive plate 15.
For example, when noise is carried on a signal flowing through the wiring of the substrate 12, the noise emitted from the wiring of the substrate 12 and directed to the digital circuit of the lower semiconductor chip 13 is blocked by the heat transfer conductive plate 15. Therefore, this noise does not adversely affect the signal flowing through the digital circuit of the lower layer semiconductor chip 13.

  Further, a part of the heat generated in the substrate 12 is conducted and dissipated to the heat transfer conductive plate 15 through the contact point with the heat transfer conductive plate 15, and the heat generated in the lower semiconductor chip 13 is transferred to the heat transfer conductive plate. Heat transferred to the heat transfer conductive plates 15 and 16 through the contact points with the heat transfer conductive plates 15 and 16, and the heat generated in the upper semiconductor chip 14 is transferred through the contact points with the heat transfer conductive plate 16. Conducted and dissipated. For this reason, the thermal resistance from the lower semiconductor chip 13 and the upper semiconductor chip 14 to the outer surface (package surface) of the mold resin 17 is reduced, and the heat dissipation of the substrate 12 is also promoted.

According to the configuration of this example, substantially the same effect as the first reference example described above can be obtained.
In addition, since the heat transfer conductive plate 15 is interposed between the substrate 12 and the lower layer semiconductor chip 13, the influence of noise can be further reduced and the reliability can be improved. The heat transfer conductive plate 15 also functions as a heat radiating plate and promotes heat radiating from the lower semiconductor chip 13 and the substrate 12, thereby further improving the heat radiating characteristics and contributing to the stabilization of the operation.

Third Reference Example FIG. 3 is a cross-sectional view showing a configuration of a semiconductor device according to a third reference example of the present invention, and FIG. 4 is a cross-sectional view taken along the line AA of FIG. FIG. 5 is a sectional view showing a configuration of a heat transfer conductive sheet constituting the semiconductor device. FIG.
This example is greatly different from the first reference example described above in that a heat transfer conductive sheet is disposed instead of the plate-shaped heat transfer conductive plate, as shown in FIGS.
Since the configuration other than this is substantially the same as the configuration of the first reference example described above, the description thereof will be simplified.

  The semiconductor device 24 in this example is a semiconductor device in which two semiconductor chips are vertically mounted. As shown in FIGS. 3 and 4, a predetermined circuit pattern is formed and an external connection electrode is used. Are formed in a lattice shape on the substrate 25, for example, a lower semiconductor chip (first semiconductor chip) 26 on which a digital circuit is formed, and an upper semiconductor on which an analog circuit is formed, for example. A chip (second semiconductor chip) 27 is stacked and mounted via a heat transfer conductive sheet (heat transfer conductor) 28 with the circuit formation surface facing upward, and sealed with a mold resin 29. It has been done.

As shown in FIG. 5, the heat transfer conductive sheet 28 is a flexible sheet-like member in which a shield layer 28a made of, for example, copper foil is laminated so as to be sandwiched between insulating layers 28b and 28c made of polyimide or the like. As shown in FIG. 4, a substantially rectangular shield part 28m interposed between the lower layer semiconductor chip 26 and the upper layer semiconductor chip 27 and a square part of the shield part 28m protrude from the ground wiring of the substrate 25. The connected lead portions 28n, 28n,...
Here, the lower layer semiconductor chip 26 and the upper layer semiconductor chip 27 are electrically connected to the substrate 25 via bonding wires 31 and 32.
The heat transfer conductive sheet 28 is held at the ground potential by being connected to the ground wiring of the substrate 25 through the lead portions 28n, 28n,.
In this example, the dimension of the shield part 28m of the heat transfer conductive sheet 28 is set smaller than the dimension of the lower layer semiconductor chip 26 and larger than the dimension of the upper layer semiconductor chip 27.

Next, the operation of the semiconductor device of this example will be described.
Between the lower layer semiconductor chip 26 and the upper layer semiconductor chip 27, a shield part 28m of the heat transfer conductive sheet 28 is inserted, and the shield part 28m is formed on the substrate via the lead parts 28n, 28n,. 25 ground wirings.
Thereby, the shield part 28m is held at the ground potential, and the propagation of noise between the lower layer semiconductor chip 26 and the upper layer semiconductor chip 27 is blocked by the shield part 28m.
For example, the noise emitted from the digital circuit of the lower semiconductor chip 26 and directed to the analog circuit of the upper semiconductor chip 27 is blocked from propagating by the shield part 28m. Therefore, this noise does not adversely affect the signal flowing through the analog circuit of the upper semiconductor chip 27.

Similarly, the noise emitted from the analog circuit of the upper semiconductor chip 27 and directed to the digital circuit of the lower semiconductor chip 26 is blocked from propagating by the shield portion 28m. Therefore, this noise does not adversely affect the signal flowing through the analog circuit of the lower layer semiconductor chip 26.
For this reason, for example, it is possible to avoid a malfunction that occurs due to noise on the signal flowing through the analog circuit of the upper semiconductor chip 27, or the inversion or delay of the signal flowing through the digital circuit of the lower semiconductor chip 26.
Of the lower semiconductor chip 26 and the upper semiconductor chip 27, heat generated particularly in the lower semiconductor chip 26 is conducted to the heat transfer conductive sheet 28 through the contact point with the heat transfer conductive sheet 28 and is dissipated. For this reason, in particular, the thermal resistance from the lower semiconductor chip 26 to the outer surface (package surface) of the mold resin 29 is reduced.

  According to the configuration of this example, substantially the same effect as the first reference example described above can be obtained.

FIG. 6 is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment of the present invention. FIG. 7 is a cross-sectional view taken along the line BB of FIG. FIG. 8 is a partially cutaway view of FIG. 8, and FIG. 8 shows the configuration of the heat transfer conductive sheet constituting the semiconductor device and the connection state between the lower layer semiconductor chip and the upper layer semiconductor chip via the heat transfer conductive sheet. It is sectional drawing shown.
This example is greatly different from the third reference example described above, as shown in FIGS. 6 and 7, the lower layer semiconductor chip and the upper layer semiconductor chip are arranged and connected with their circuit formation surfaces facing each other. Is a point.
Since the other configuration is substantially the same as the configuration of the third reference example described above, the description thereof will be simplified.

  The semiconductor device 34 in this example is a semiconductor device in which two semiconductor chips are vertically mounted. As shown in FIGS. 6 and 7, a predetermined circuit pattern is formed and an external connection electrode is used. Are formed on a substrate 35 on which a ball-shaped bump 35a, 35a,... Is formed in a grid, for example, a lower semiconductor chip (first semiconductor chip) 36 on which a digital circuit is formed, and an upper semiconductor on which an analog circuit is formed, for example. With the chip (second semiconductor chip) 37, the lower semiconductor chip 36 and the upper semiconductor chip 37, with their circuit forming surfaces facing each other, the heat transfer conductive sheet (heat transfer conductor) 38 is Are stacked and mounted, and sealed with a mold resin 39.

As shown in FIG. 8, the heat transfer conductive sheet 38 is connected to the lower wiring layer 38a to which the lower semiconductor chip 36 is connected, the insulating layer 38b, the shield layer 38c, the insulating layer 38d, and the upper semiconductor chip 37. The upper wiring layer 38e is a flexible sheet-like member formed by laminating in this order. As shown in FIG. 7, the substantially rectangular shape is interposed between the lower semiconductor chip 36 and the upper semiconductor chip 37. , And lead portions 38n, 38n,... Extending from the four end edges of the shield portion 38m and connected to the wiring of the substrate 35.
The lower layer semiconductor chip 36 and the upper layer semiconductor chip 37 are electrically connected to each other via the shield part 38m of the heat transfer conductive sheet 38, and further electrically connected to the substrate 35 via the lead part 38n.

That is, the bumps 36a and 36b of the lower layer semiconductor chip 36 are connected to corresponding portions of the lower wiring layer 38a, and the bumps 37a and 37b of the upper layer semiconductor chip 37 are connected to corresponding portions of the upper wiring layer 37a.
Here, for example, at a predetermined position where the corresponding bumps 36b and 37b are arranged at the same position along the direction perpendicular to the circuit formation surface of the lower layer semiconductor chip 36 and the upper layer semiconductor chip 37, the lower wiring layer 38a is formed. Corresponding portions, conductive portions formed in the insulating layer 38b immediately above, portions surrounded by the annular insulating region of the shield layer 38c directly above, conductive portions formed in the insulating layer 38d directly above, The corresponding portions of the upper wiring layer 38e are connected along the direction perpendicular to the circuit formation surface, whereby the lower semiconductor chip 36 and the upper semiconductor chip 37 are electrically connected to each other at this location. .
The heat transfer conductive sheet 38 is held at the ground potential by being connected to the ground wiring 35b of the substrate 35 through the lead portions 38n, 38n,.
In this example, the ground wiring 35 b is formed over the entire periphery of the peripheral portion of the upper surface of the substrate 35.
The dimension of the shield part 38 m of the heat transfer conductive sheet 38 is set smaller than the dimension of the lower layer semiconductor chip 36 and larger than the dimension of the upper layer semiconductor chip 37.

Next, the operation of the semiconductor device of this example will be described.
Between the lower layer semiconductor chip 36 and the upper layer semiconductor chip 37, a shield part 38m of a heat transfer conductive sheet 38 is inserted, and the shield part 38m is a substrate through lead parts 38n, 38n,. 35 ground wires 35b.
Thereby, the shield part 38m is held at the ground potential, and the propagation of noise between the lower layer semiconductor chip 36 and the upper layer semiconductor chip 37 is blocked by the shield part 38m.
Further, the heat generated in the lower layer semiconductor chip 36 and the upper layer semiconductor chip 37 is transmitted to the heat transfer conductive sheet 38 through the contact portion, and is conducted through the shield part 38m, the lead parts 38n, 38n,... And the ground wiring 35b. Dissipated. For this reason, the thermal resistance from the lower semiconductor chip 36 and the upper semiconductor chip 37 to the outer surface (package surface) of the mold resin 39 is reduced.

According to the configuration of this example, substantially the same effect as that of the third reference example described above can be obtained.
In addition, since the ground wiring 35b is formed over the entire periphery of the upper surface of the substrate 35, the heat generated in the lower layer semiconductor chip 36 and the upper layer semiconductor chip 37 is conducted through the ground wiring 35b to further increase. It is surely released.
Further, since the lower layer semiconductor chip 36 and the upper layer semiconductor chip 37 are electrically connected to each other via the shield portion 38m of the heat transfer conductive sheet 38, the degree of freedom in circuit design can be increased.
For example, the arrangement position of the electrodes can be selected relatively freely. That is, the corresponding bumps to be connected to the lower layer semiconductor chip 36 and the upper layer semiconductor chip 37 are not necessarily arranged at the same position along the direction perpendicular to the circuit formation surface.
Further, since the lower layer semiconductor chip 36 and the upper layer semiconductor chip 37 are electrically connected to the substrate 35 via the lead portions 38n, the steps of wire bonding the lower layer semiconductor chip 36, the upper layer semiconductor chip 37 and the substrate 35 respectively. Can be omitted.

FIG. 9 is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment of the present invention. FIG. 10 is a cross-sectional view taken along the line CC of FIG. FIG. 11 is a partially broken view of FIG. 11, and FIG. 11 shows the configuration of the heat transfer conductive sheet constituting the semiconductor device and the connection state between the lower layer semiconductor chip and the upper layer semiconductor chip via the heat transfer conductive sheet. It is sectional drawing shown.
This example differs greatly from the first embodiment described above, as shown in FIGS. 9 to 11, by changing the structure of the heat transfer conductive sheet and corresponding bumps to be connected to the lower and upper semiconductor chips. The point is that they are directly connected to each other, and the substrate and the lower layer semiconductor chip are connected by wire bonding.
Since the other configuration is substantially the same as the configuration of the first embodiment described above, the description thereof will be simplified.

  The semiconductor device 41 in this example is a semiconductor device in which two semiconductor chips are vertically mounted. As shown in FIGS. 9 and 10, a predetermined circuit pattern is formed and an external connection electrode is used. Are formed in a lattice shape on a substrate 42, for example, a lower semiconductor chip (first semiconductor chip) 43 in which a digital circuit is formed, and an upper semiconductor in which an analog circuit is formed, for example. In a state where the chip (second semiconductor chip) 44 and the lower layer semiconductor chip 43 and the upper layer semiconductor chip 44 have their circuit formation surfaces facing each other, the heat transfer conductive sheet (heat transfer conductor) 45 is And are laminated and sealed with a mold resin 46.

As shown in FIG. 11, the heat transfer conductive sheet 45 is a flexible sheet-like member in which the shield layer 45a is laminated so as to be sandwiched between the insulating layers 45b and 45c. As shown in FIG. A substantially rectangular shield part 45m interposed between the lower semiconductor chip 43 and the upper semiconductor chip 44, and extending so as to project from the square part of the shield part 45m, is connected to the ground wiring of the substrate 42. Lead portions 45n, 45n,...
Further, through holes 45 h for inserting the connected bumps 43 a, 44 a at locations where the corresponding bumps 43 a, 44 a to be connected to the lower semiconductor chip 43 and the upper semiconductor chip 44 of the heat transfer conductive sheet 45 are arranged. Is formed.

The lower-layer semiconductor chip 43 and the upper-layer semiconductor chip 44 are electrically connected to each other by connecting the corresponding bumps 43a, 44a to each other at a portion where the insertion hole 45h of the shield portion 45m of the heat transfer conductive sheet 45 is formed. Has been.
The lower semiconductor chip 43 is electrically connected to the substrate 42 via bonding wires 47.
Further, the heat transfer conductive sheet 45 is held at the ground potential by being connected to the ground wiring of the substrate 42 via the lead portions 45n, 45n,.
In this example, the dimension of the shield part 45m of the heat transfer conductive sheet 45 is set to be smaller than the dimension of the lower layer semiconductor chip 43 and larger than the dimension of the upper layer semiconductor chip 44.

Next, the operation of the semiconductor device of this example will be described.
Between the lower layer semiconductor chip 43 and the upper layer semiconductor chip 44, a shield part 45m of the heat transfer conductive sheet 45 is inserted, and the shield part 45m is a substrate through lead parts 45n, 45n,. 42 ground wiring.
Thereby, the shield part 45m is held at the ground potential, and the propagation of noise between the lower layer semiconductor chip 43 and the upper layer semiconductor chip 44 is blocked by the shield part 45m.
Further, the heat generated in the lower semiconductor chip 43 and the upper semiconductor chip 44 is conducted to the heat transfer conductive sheet 45 through the contact point with the heat transfer conductive sheet 45 and is dissipated. For this reason, the thermal resistance from the lower semiconductor chip 34 and the upper semiconductor chip 44 to the outer surface (package surface) of the mold resin 46 is reduced.

According to the configuration of this example, substantially the same effect as that of the first embodiment described above can be obtained.
In addition, since the configuration of the heat transfer conductive sheet can be simplified, it can be manufactured at low cost.

FIG. 12 is a cross-sectional view showing a configuration of a semiconductor device manufactured by a semiconductor device manufacturing method according to a third embodiment of the present invention, and FIG. 13 is a schematic configuration of a mount device used for manufacturing the semiconductor device. FIG. 14 is a bottom view showing the structure of the substrate of the semiconductor device, FIGS. 15 to 17 are process diagrams for explaining the method of manufacturing the semiconductor device, and FIG. FIG. 17 is a cross-sectional view taken along the line DD in FIG.
In this example, the method of manufacturing a semiconductor device includes two semiconductor chips mounted on a substrate in a state where their respective circuit formation surfaces face each other and are arranged in a vertical direction, as described in the second embodiment. It is suitable for use in a manufacturing method of a semiconductor device of a chip on chip) system.
As shown in FIG. 12, in the semiconductor device 51, a lower layer semiconductor chip (first semiconductor chip) 53 and an upper layer semiconductor chip (second semiconductor chip) 54 are formed on a circuit board 52 on respective circuit formation surfaces. Are stacked and mounted via a metal heat transfer conductive plate (heat transfer conductor) 55 and sealed with a mold resin 56.

Next, the mounting apparatus of this example used for bonding the upper semiconductor chip 54 to the lower semiconductor chip 53 mounted on the substrate 52 via an adhesive will be described.
As shown in FIG. 13, the mounting device 57 supports a substrate 52 on which a lower semiconductor chip 53 is mounted, and is capable of moving, for example, in directions orthogonal to each other, and an upper semiconductor chip 54. Is mounted by vacuum suction and transferred to above the lower semiconductor chip 53, and a mounting tool (component gripper) 59 for placing and connecting the upper semiconductor chip 54 on the lower semiconductor chip 53 is provided.
The mount stage 58 has a protrusion-like suction part (first suction part) 61 that is inserted into a through hole 52 a formed in the substrate 52. The suction part 61 is formed with a suction hole 61a. By operating a decompression device (not shown) such as an ejector vacuum pump, external air is sucked along a suction path communicating with the suction hole 61a. The lower semiconductor chip 53 is sucked and held by the tip surface 61 b of the sucking portion 61.

In addition, the mount stage 58 includes a heater (not shown) for heating and curing the thermosetting adhesive to bond the lower semiconductor chip 53 to the substrate 52, for example.
The mount tool 59 also has a suction part (second suction part) 62. The suction part 62 is formed with a suction hole 62a. By operating a decompression device (not shown), external air is sucked along a suction path communicating with the suction hole 62a, and the upper semiconductor chip 54 is attached to the suction part. It is sucked and gripped by the suction surface 62b of 62. Like the mount stage 58, the mount tool 59 also includes a heater.

In the manufacturing method of the semiconductor device of this example, first, as shown in FIG. 14, through holes 52a, 52a,. A substrate 52 which is a wiring substrate, for example, provided with external connection electrodes 52b, 52b,.
Then, as shown in FIG. 15A, after applying an adhesive 63 such as silver paste on the chip mounting surface of the substrate 52, the lower semiconductor chip 53 is lowered and mounted as shown in FIG. 15B. Put. Next, the adhesive 63 is heated and cured, and bumps 53 a are formed on the lower semiconductor chip 53.
In the step of mounting the lower semiconductor chip 53 on the substrate 52, a conventional mounting apparatus including a mount stage 64 and a mount stool 65 is used as shown in FIGS. 15 (a) and 15 (b). When the adhesive 63 is cured, the mount stage 64 is heated by a built-in heater.

Next, as shown in FIGS. 16A and 18, the substrate 52 on which the lower-layer semiconductor chip 53 is mounted so that the protruding suction portion 61 of the mount stage 58 is inserted into the through hole 52 a of the substrate 52. And the lower semiconductor chip 53 is adsorbed and supported by the front end surface 61b of the protruding adsorbing portion 61.
In this state, as shown in FIG. 5B, the heat transfer conductive plate 55 having insertion holes 55h for inserting the bumps 53a of the lower semiconductor chip 53 is adsorbed on the adsorption surface 62b of the mount tool 59, Lower layer semiconductor chip 53 and heat transfer conductive plate 55 are lowered while maintaining a parallel state, and heat transfer conductive plate 55 is placed on lower layer semiconductor chip 53.

Next, as shown in FIG. 17A, the upper semiconductor chip 54 is adsorbed on the adsorption surface 62b of the mount tool 59, and the lower semiconductor chip 53 and the heat transfer conductive plate 55 are parallel to the upper semiconductor chip 54. As shown in FIG. 6B, the upper semiconductor chip 54 is placed on and bonded to the heat transfer conductive plate 55 by bringing the corresponding electrodes into contact with each other in the aligned state. Thereafter, resin sealing is performed to obtain the semiconductor device 51.
In the semiconductor device 51 obtained in this way, the active elements and the like around the electrode are not damaged or damaged due to the biased pressing force applied to the circuit forming surface of the lower semiconductor chip 53.

According to the configuration of this example, the upper layer semiconductor chip 54 is pressed against the lower layer semiconductor chip 53 on which the heat transfer conductive plate 55 is placed while maintaining a parallel state to each other, so that each location where the bump 53a is formed In this case, even if the thickness of the adhesive 63 varies and the lower semiconductor chip 53 is inclined with respect to the substrate 52, for example, the circuit of the lower semiconductor chip 53 is damaged or damaged. It is possible to avoid the occurrence.
Further, when the heat transfer conductive plate 55 is placed on the lower semiconductor chip 53, the lower surface of the heat transfer conductive plate 55 and the wall surface of the insertion hole 55h are provided at each position where the bump 53a of the lower semiconductor chip 53 is formed. Even if it hits, since the biased pressure is not applied to a specific location, it is possible to avoid the occurrence of breakage or damage in the circuit of the lower layer semiconductor chip 53.
These effects can be obtained even if the thickness of the substrate varies. Therefore, the yield can be improved and high reliability can be ensured.
Further, while achieving miniaturization, the noise propagation between the lower semiconductor chip 53 and the upper semiconductor chip 54 is blocked to avoid malfunction, and the heat dissipation characteristics are improved to contribute to the stabilization of the operation. A semiconductor device with high reliability can be manufactured.

FIG. 19 is a cross-sectional view showing the structure of a semiconductor device manufactured by the method of manufacturing a semiconductor device according to the fourth embodiment of the present invention, and FIG. 20 is a process diagram for explaining the method of manufacturing the semiconductor device. It is.
The difference between this example and the third embodiment is that a heat transfer conductive plate is interposed between the lower layer semiconductor chip and the upper layer semiconductor chip, whereas, as shown in FIG. The step of placing the heat transfer conductive plate on the lower semiconductor chip is omitted before the upper semiconductor chip is bonded to the lower semiconductor chip.
Since the other configuration is substantially the same as the configuration of the third embodiment described above, the description thereof will be simplified.
As shown in FIG. 19, in the semiconductor device 66, a lower layer semiconductor chip (first semiconductor chip) 68 and an upper layer semiconductor chip (second semiconductor chip) 69 are provided on a substrate 67, respectively. Are stacked and mounted in a state where they are opposed to each other and arranged in the vertical direction, and sealed with a mold resin 71.

In the manufacturing method of the semiconductor device of this example, as shown in FIG. 20A, the lower layer semiconductor chip 68 is formed so that the protruding suction portion 61 of the mount stage 58 is inserted into the through hole 67a of the substrate 67. The mounted substrate 67 is placed, and the lower semiconductor chip 68 is sucked and supported by the tip end surface 61b of the protruding suction portion 61.
In this state, as shown in FIG. 5B, the upper semiconductor chip 69 is adsorbed on the adsorption surface 62b of the mount tool 59, and the lower semiconductor chip 68 and the upper semiconductor chip 69 are lowered while maintaining a parallel state. Then, the corresponding electrodes are brought into contact with each other in the aligned state, and the upper semiconductor chip 69 is placed on the lower semiconductor chip 68, and the upper semiconductor chip 69 is pressed against the lower semiconductor chip 68 from above and heated and pressed. Join.
Here, the mount stage 58 and the mount tool 59 are heated to a predetermined temperature by a built-in heater, and in this state, the upper semiconductor chip 69 and the lower semiconductor chip 68 are pressed against each other at the place where the bumps 68a are formed.
Thereafter, resin sealing is performed to obtain a semiconductor device 66 as shown in FIG.
In the semiconductor device 66 manufactured as described above, the circuit forming surface of the lower semiconductor chip 68 is not damaged.

According to the configuration of this example, the upper semiconductor chip 69 is pressed against the lower semiconductor chip 68 while maintaining a parallel state to each other. Even if the thickness of the adhesive varies, it is possible to avoid the occurrence of breakage or damage in the circuit of the lower semiconductor chip 68, for example.
This effect can be obtained even if the thickness of the substrate varies. Therefore, the yield can be improved and high reliability can be ensured.

The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and there are design changes and the like without departing from the gist of the present invention. Are also included in the present invention.
For example, in the above-described embodiment, the case where the lower semiconductor chip and the upper semiconductor chip are arranged in the vertical direction has been described. Of course, three or more semiconductor chips may be stacked and arranged in the vertical direction. good. Here, the heat transfer conductive plate or the heat transfer conductive layer may be interposed between all the semiconductor chips, or may be omitted as appropriate between the semiconductor chips on which digital circuits are formed.
In addition, the case where the upper-layer side semiconductor chip, the heat transfer conductive plate, etc. are set to be smaller than the lower layer side semiconductor chip, the heat transfer conductive plate, etc., is not limited to this. The size of the semiconductor chip or the like may be increased.

Further, the case where the digital circuit is associated with the lower layer semiconductor chip and the analog circuit is associated with the upper layer semiconductor chip has been described, but of course the opposite may be possible, both may be digital circuits, and both may be analog circuits.
Further, for example, in the first reference example, the bonding with the bonding wires 7, 8, 9 may be performed every time the lower semiconductor chip 3, the upper semiconductor chip 4 and the heat transfer conductive plate 5 are placed, or the lower semiconductor chip. 3. After the upper semiconductor chip 4 and the heat transfer conductive plate 5 are placed, the steps may be performed together.
Further, not only between the semiconductor chips but also the side surfaces may be covered with the heat transfer conductive plate or the heat transfer conductive sheet so as to surround the bonding wires. In this case, at least an injection port for resin injection is ensured.
Thereby, for example, noise propagation through the bonding wire can also be prevented.

In the first reference example, the case where a heat transfer conductive plate is interposed between the lower layer semiconductor chip and the upper layer semiconductor chip has been described. However, as shown in FIG. 21, a single semiconductor chip 72 is mounted. Also in the semiconductor device 73, the heat transfer conductive plate 75 is inserted between the semiconductor chip 72 and the substrate 74, and the heat transfer conductive plate 75 is connected to the ground wiring of the substrate 74 via the bonding wire 76. Also good.
Thereby, the propagation of noise between the substrate 74 and the semiconductor chip 72 is blocked by the heat transfer conductive plate 75, and the heat generated in the semiconductor chip 72 is also dissipated through the heat transfer conductive plate 75. 22 can be prevented, and the reliability can be remarkably improved as compared with the semiconductor device 79 in which the semiconductor chip 78 is mounted directly on the substrate 77 as shown in FIG.

Further, as shown in FIG. 23, for example, in a semiconductor device 82 in which two semiconductor chips 81a and 81b are arranged on the same plane, a heat transfer conductive plate 84 is provided between the substrate 83 and the semiconductor chips 81a and 81b. It may be inserted.
Further, in the third reference example, as the heat transfer conductive sheet 28, a case where a sheet-like member in which the shield layer 28a is laminated so as to be sandwiched between the insulating layers 28b and 28c is described, for example, as shown in FIG. As described above, the heat transfer conductive sheet 28A in which the shield layer 28a is simply formed on the insulating layer 28b may be used.
In addition, the heat transfer conductor is not limited to the heat transfer conductive plate or the heat transfer conductive sheet, but a heat transfer conductive layer formed by applying, for example, silver paste to a region where the terminals of the lower semiconductor chip are not formed is used. May be. After the formation of the heat transfer conductive layer, the upper semiconductor chip is placed.
Further, the material used for the heat transfer conductive plate and the heat transfer conductive layer is not limited to aluminum or copper, but may be, for example, chromium or silver.

Further, in the first embodiment, the corresponding bumps of the lower layer semiconductor chip and the upper layer semiconductor chip may be directly bonded to each other, or in the second embodiment, they are connected via the heat transfer conductive sheet. Anyway.
Also, for example, in the first reference example, when two semiconductor chips are both arranged with the circuit formation surface facing upward, in the first embodiment, the two semiconductor chips are connected to each other. Although the case where the two semiconductor chips are both arranged with the circuit formation surface facing downward has been described, the side where the two semiconductor chips are not formed with the circuit has been described. The heat transfer conductive plate may be inserted even when the surfaces are arranged in a state of facing each other.

For example, in the first embodiment, the case where the ground wiring is formed on the peripheral edge of the upper surface of the substrate 35 has been described. In addition, as shown in FIG. The metal layer (heat radiating portion) 85 may be formed so that the surface thereof is exposed and connected to the ground wiring. Thereby, heat dissipation can be more reliably performed.
Further, for example, in the third embodiment, the case where the lower semiconductor chip 53 is lowered and mounted after the adhesive 63 such as silver paste is applied on the chip mounting surface of the substrate 52 has been described. For example, a sheet-like conductive adhesive may be placed, and then the lower semiconductor chip 53 may be lowered and placed.
In the third embodiment, a heat transfer conductive sheet may be used instead of the heat transfer conductive plate 55.

In the third and fourth embodiments, the substrate 52 (in which a large number of circular through holes 52a (67a), 52a (67a),. 67) has been described, however, as shown in FIG. 26, a substrate 87 in which, for example, a groove-shaped opening 87a into which the suction portion 61 can be inserted is formed may be used. In addition, as shown in FIG. 27, a substrate 88 in which circular through holes 88a, 88a,... And groove-shaped openings 88b are formed in advance may be used.
Further, the substrate is not limited to the wiring substrate, and a lead frame in which a plurality of patterns are connected and an opening or a notch for inserting the suction portion 61 of the mount stage 58 is provided at a predetermined position may be used. good.

In the third and fourth embodiments, the case where the upper semiconductor chip is mounted while the lower semiconductor chip is inclined with respect to the substrate has been described. As shown in FIGS. After a columnar spacer 94 having a certain height is placed on the substrate 93 in the placement region 93a of the lower semiconductor chip 95, a predetermined amount of the adhesive 96 is dropped or applied to the placement region 93a. As shown in FIG. 27B, the lower semiconductor chip 95 may be lowered and mounted.
Further, as shown in FIG. 30, a frame-shaped dam portion 98 having a constant height is formed on the substrate 97, and a notch 99 is provided in this square portion, and a lower layer in the frame-shaped dam portion 98 is formed. A lower layer semiconductor chip may be mounted after a predetermined amount of adhesive is dropped or applied to the mounting area of the semiconductor chip.

  In the third and fourth embodiments, a method of manufacturing a COC-type semiconductor device in which two semiconductor chips are mounted on a substrate in a state where their respective circuit formation surfaces face each other and are arranged in a vertical direction. However, the present invention is not limited to this. In the case where two semiconductor chips are stacked and mounted on the substrate with their circuit formation surfaces facing upward, a through-chip is inserted into the upper semiconductor chip. A hole may be formed, and a bump connected to the circuit on the upper surface side through a through hole may be formed on the lower surface, and this may be applied when two semiconductor chips are connected to each other via the bump.

It is sectional drawing which shows the structure of the semiconductor device which is the 1st reference example of this invention. It is sectional drawing which shows the structure of the semiconductor device which is the 2nd reference example of this invention. It is sectional drawing which shows the structure of the semiconductor device which is the 3rd reference example of this invention. FIG. 4 is a cross-sectional view taken along line AA in FIG. 3, showing a part of the mold resin constituting the semiconductor device in a cutaway manner. It is sectional drawing which shows the structure of the heat-transfer conductive sheet which comprises the semiconductor device. 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention. FIG. 7 is a cross-sectional view taken along the line B-B in FIG. 6, showing a part of the mold resin constituting the semiconductor device in a cutaway manner. It is sectional drawing which shows the connection state of the structure of the heat-transfer conductive sheet which comprises the semiconductor device, and the lower-layer semiconductor chip and upper-layer semiconductor chip through the heat-transfer conductive sheet. It is sectional drawing which shows the structure of the semiconductor device which is 2nd Example of this invention. FIG. 10 is a cross-sectional view taken along the line C-C in FIG. 9 and is a view in which a part of the mold resin constituting the semiconductor device is broken away. It is sectional drawing which shows the connection state of the structure of the heat-transfer conductive sheet which comprises the semiconductor device, and the lower-layer semiconductor chip and upper-layer semiconductor chip through the heat-transfer conductive sheet. It is sectional drawing which shows the structure of the semiconductor device manufactured by the manufacturing method of the semiconductor device which is 3rd Example of this invention. It is explanatory drawing for demonstrating schematic structure of the mounting apparatus used in order to manufacture the same semiconductor device. It is a bottom view which shows the structure of the board | substrate of the same semiconductor device. FIG. 6 is a process diagram for describing the manufacturing method of the same semiconductor device. FIG. 6 is a process diagram for describing the manufacturing method of the same semiconductor device. FIG. 6 is a process diagram for describing the manufacturing method of the same semiconductor device. It is sectional drawing along the DD line of Fig.16 (a). It is sectional drawing which shows the structure of the semiconductor device manufactured by the manufacturing method of the semiconductor device which is 4th Example of this invention. FIG. 6 is a process diagram for describing the manufacturing method of the same semiconductor device. It is sectional drawing which shows the structure of the semiconductor device which is a modification of the 1st reference example of this invention. It is explanatory drawing for demonstrating a prior art. It is sectional drawing which shows the structure of the semiconductor device which is another modification of the 1st reference example of this invention. It is sectional drawing which shows the structure of the heat-transfer conductive sheet of the semiconductor device which is a modification of the 3rd reference example of this invention. It is sectional drawing which shows the structure of the semiconductor device which is a modification of 1st Example of this invention. It is a top view which shows the structure of the board | substrate used in the manufacturing method of the semiconductor device which is a modification of 3rd Example of this invention. It is a top view which shows the structure of the board | substrate used in the manufacturing method of the semiconductor device which is another modification of 3rd Example of this invention. It is process drawing for demonstrating the manufacturing method of the semiconductor device which is another modification of 3rd Example of this invention. FIG. 7 is an explanatory diagram for explaining the manufacturing method of the same semiconductor device. It is explanatory drawing for demonstrating the manufacturing method of the semiconductor device which is another modification of 3rd Example of this invention. It is explanatory drawing for demonstrating a prior art. It is explanatory drawing for demonstrating a prior art. It is explanatory drawing for demonstrating a prior art. It is explanatory drawing for demonstrating a prior art.

Explanation of symbols

1, 11, 24, 34, 41, 51, 66, 73, 79, 82 Semiconductor device 2, 12, 25, 35, 42, 52, 67, 74, 77, 83, 87, 88, 93, 97 Substrate 3 13, 26, 36, 43, 53, 68 Lower layer semiconductor chip (first semiconductor chip)
4, 14, 27, 37, 44, 54, 69 Upper layer semiconductor chip (second semiconductor chip)
5, 15, 16, 55 Heat transfer conductive plate (heat transfer conductor)
28, 38, 45 Heat transfer conductive sheet (heat transfer conductor)
58 Mount stage (component mounting table)
59 Mount tool (part gripping tool)
61 Suction part (first suction part)
62 Adsorption part (second adsorption part)

Claims (1)

A semiconductor device in which a plurality of semiconductor chips are stacked on a substrate,
Between the substrate and the uppermost semiconductor chip, at least one heat transfer conductor having heat conductivity and conductivity for dissipating heat generated in the semiconductor chip and shielding electromagnetic noise is interposed. The heat transfer conductor is connected to a ground wiring held at the ground potential of the substrate,
The first and second semiconductor chips that constitute the plurality of semiconductor chips and that are adjacent to each other via the heat transfer conductor are stacked with the circuit forming surfaces facing each other to form the substrate. Mounted on the
The heat transfer conductor is formed by laminating an insulating layer and a shield layer electrically and thermally connected to the ground wiring of the substrate,
A semiconductor device characterized in that a connection wiring layer for electrically connecting the first semiconductor chip and a terminal of the second semiconductor chip is provided in the insulating layer and the shield layer. .

Images