JP2007122337A - Arithmetic unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an arithmetic unit in which processing parts for executing an application program need not execute other processing than the application program, such as task management, and which can flexibly accommodate post-design changes in various processing contents. <P>SOLUTION: The arithmetic unit comprises a control means for reading in and executing a control means program to assign tasks forming an application program to each processing means according to the state of each processing means held in a state notification means, a plurality of processing means for executing the tasks assigned by the control means and outputting the states of task execution, and the state notification means for holding the states output by the processing means. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an arithmetic device including a plurality of processing units that execute a program.

  Various methods have been proposed and implemented in order to execute processing according to the purpose of data at high speed. For example, Non-Patent Document 1 describes a multiprocessor system equipped with a plurality of processors. FIG. 8 is a configuration diagram of the multiprocessor system described in Non-Patent Document 1, in which a plurality of processors and memories are connected via a bus. According to Non-Patent Document 1, a plurality of processors share a memory with one operating system, and the operating system performs a task (hereinafter referred to as an application program) according to a processing purpose as a thread (in Non-Patent Document 1, a thread). Or, it is divided into processes) and assigned to each processor.

  That is, each processor executes both the operating system and each task of the application program, and the entire execution time of the processor cannot be allocated to the execution of the application program, and the memory is shared. There is also a possibility that the operation of the operating system is affected by the execution of the application program.

  For this reason, Patent Document 1 describes a configuration that reduces overhead such as task management and scheduling in each processor. FIG. 9 is a configuration diagram of a multiprocessor system described in Patent Document 1. In addition to the configuration of FIG. 8, a state management unit is connected to a plurality of processors. According to Patent Document 1, the state management unit manages the availability of each processor and notifies each processor, and a processor in which a new task has occurred causes the other idle processor to execute the task, A new task is started immediately. According to Patent Document 1, the state management unit is realized by a combinational circuit.

JP 2004-86921 A “Introduction to Interface Microprocessor Architecture”, CQ Publishing Company, August 2004, p. 231-p. 233

  As described above, in the configuration in which the operating system performs task assignment processing to a plurality of processors, the execution time of the application program is reduced, and the operation of the application program can affect the operation of the operating system. There's a problem. For example, when the operating system is destroyed, the system is completely stopped.

  On the other hand, in the configuration described in Patent Document 1, the state management unit is a hardware block, and not all of the management functions of a plurality of processors can be realized, and a portion that cannot be realized by the hardware block needs to be executed by the processor. There is a decrease in the execution time of the application program. For example, in Patent Document 1, it is the processor itself that has generated a new task that causes a free processor to execute a new task. In addition, it is difficult to cope with a change in the processing content of the state management unit after the hardware block design.

  Accordingly, the present invention solves the above-described problems, and the processing unit that executes the application program does not need to execute processing other than the application program such as task management, and changes of various processing contents after the design. It is another object of the present invention to provide an arithmetic device that can flexibly cope with the above.

According to the arithmetic device of the present invention,
By reading and executing the program for the control means, the control means for allocating the tasks constituting the application program to each processing means based on the state of each processing means held by the status notification means, and the assignment to the control means A plurality of processing means for executing a given task and outputting a state related to the execution of the task, and a state notifying means for holding the state output by the processing means.

According to another embodiment of the arithmetic device of the present invention,
It is also preferable to have a first storage means used only by the control means and a second storage means used by the control means and the processing means.

According to another embodiment of the arithmetic device of the present invention,
The control unit allocates the area of the second storage unit and / or hardware resources for input / output to the requested processing unit based on the request from the processing unit, and the processing unit allocates the second resource allocated from the control unit. It is also preferable to access only the storage resource area and / or hardware resources for input / output.

Furthermore, according to another embodiment of the arithmetic unit of the present invention,
The control means and the first storage means are connected to the first bus, the plurality of processing means and the second storage means are connected to the second bus, and the first bus and the second bus are connected to each other. It is also preferable to have bus conversion means for connecting and preventing access from the processing means to the first storage means.

Furthermore, according to another embodiment of the arithmetic unit of the present invention,
The control means and the first storage means are connected to the first bus, the plurality of processing means are connected to the second bus, and the second storage means is connected to the first bus and the second bus It is also preferable.

  By realizing the operation of the control means by a program, it is possible to easily change the operation of the control means, and it is possible to easily cope with a change in processing contents. Further, even complicated control operations that are difficult with hardware blocks can be realized by a program. Further, the processing means does not need to perform processing other than execution of the application program such as task management, and the execution speed is improved.

  Further, the control unit manages the access to the storage unit and the hardware resource for input / output by the processing unit, so that it is possible to prevent problems caused by a plurality of processing units accessing the same resource. Further, by separating the first storage means used by the control means from the second storage means accessible by the processing means, it is possible to prevent the operation of the control means from being affected by the operation of the processing means. it can.

  The best mode for carrying out the present invention will be described in detail below with reference to the drawings.

  FIG. 1 is a block diagram of a first embodiment of a computing device according to the present invention. According to FIG. 1, the arithmetic device includes a control unit 1, a nonvolatile memory 2, a memory 3, a plurality of processing units 4, a shared memory 5, and a state notification unit 6. The control unit 1, the nonvolatile memory 2, the memory 3, each processing unit 4, and the shared memory 5 are connected to each other by a bus 8. Each processing unit 4 and the state notification unit 6 are connected by a line 71, and the state notification unit 6 and the control unit 1 are connected by a line 72.

  The control unit 1 is, for example, a processor that has a Reduced Instruction Set Computer (RISC) core and executes a program for the control unit stored in the nonvolatile memory 2, manages the tasks of the application program, and notifies the status Based on the state of each processing unit 4 held by the unit 6, the processing unit 4 that executes each task is determined, and load control of an application program for causing the determined processing unit 4 to execute the task via the bus 8 I do. It also manages shared memory and hardware resources for external input / output (not shown).

  The processing unit 4 is a processor that executes an application program. Here, as described above, the application program is a program for executing a desired purpose such as image data processing and communication data processing, and is executed by the control unit 1 and causes the processing unit 4 to execute the application program. Therefore, it is clearly distinguished from a control unit program which is a program for realizing various control processes for the purpose. The type of processor used in the processing unit 4 is an array in which a RISC core or a plurality of processor elements are arranged in a matrix and the processing contents in the processor elements and the connection configuration between the processor elements are changed according to the program to be executed. The type, such as the type, is arbitrary. For example, the processing unit 4 notifies the state notification unit 6 of the task execution state in the processing unit 4 such as a vacant state, a processing state, and a suspended state via a line 71. Note that a detailed identifier is assigned to each state as necessary, and the processing unit 4 notifies the state notification unit 6 of the detailed identifier together with the state. The detailed identifier will be described later.

  The non-volatile memory 2 is a non-volatile memory storing a control unit program, and the processing unit 4 does not access it. Non-volatile memories include ROM, EEPROM, flash memory, and the like. If a rewritable memory such as flash memory is used, the control program can be easily changed.

  The memory 3 is a readable / writable memory used as an area for storing various data when the control unit 1 executes the control unit program, and the processing unit 4 does not access it.

  The shared memory 5 is a readable / writable memory that stores an application program executed by the processing unit 4 and is also used as an area for storing various data when the application program is executed. The control unit 1 can also be used. It is.

  The state notification unit 6 holds the state of the processing unit 4 output to the line 71 by the processing unit 4 together with the detailed identifier. The control unit 1 can access the state notification unit 6 through the line 72, and recognizes the state and detailed identifier of the processing unit 4 by accessing the state notification unit 6. It is also possible to adopt a configuration in which the state notification unit 6 interrupts and notifies the control unit 1 when the state of the processing unit 4 changes. In addition, the status notification unit 6 is also connected to the bus 8, and the signal transmission / reception between the control unit 1 and the status notification unit 6 is performed by the bus 8, or only the interrupt notification to the processing unit 4 is performed on the line 72. 1 may be configured to check the status of the processing unit 4 to the status notification unit 6 through the bus 8 when an interrupt occurs.

  FIG. 4 is a diagram showing the relationship between application programs executed by the processing unit 4 and tasks. A part of the processing of the application program is called a task, and the application program is composed of a plurality of tasks. In FIG. 4, task A is executed first, and task B or task C is selectively executed according to the end result of task A. Task D is executed after completion of task B or C, and tasks E, F, and G are executed after completion of task D. Tasks E, F and G can be executed simultaneously or one by one. In any method, execution of the task H is started after all of the tasks E, F, and G are completed.

  As described above, only one task that constitutes the application program may be executed, or a plurality of tasks may be executed simultaneously, and the processing amount of each task is also different.

  How to set the task is a design matter by the compiler or the control means, but one or more basic blocks can be set as one task. A basic block is a unit of the control flow graph, and there is only one instruction to be executed first and one instruction to be executed last, and it branches to another basic block without going through the instruction to be executed last, Without stopping, it can be executed in a straight line from the instruction to be executed first to the instruction to be executed last, and the compiler normally recognizes it in the process.

  The control unit 1 recognizes the tasks constituting the application program and adds the recognized tasks to the task queue. As a method for adding a task to the task queue in the control unit 1, for example, a task table is provided in the application program, and the control unit 1 reads the task table included in the application program to pre-process all tasks constituting the application program. There is a way to add to the task queue. In this case, since all tasks can be recognized in advance, task scheduling described later can be performed effectively. Also, an entry task of an application program, that is, a task to be executed first is read, a task that may be executed next to the entry task is recognized, added to the task queue, and executed next when the task ends. There is also a method of repeatedly adding a task that may be executed next to the confirmed task to the task queue and deleting a task that is no longer necessary from the task queue when the task is confirmed. In this case, the application program has a structure capable of recognizing each task such as including information indicating the position of each task in the shared memory.

  In parallel with the addition of the task to the task queue, the control unit 1 performs task management and input / output management with the shared memory and the outside in order to cause the plurality of processing units 4 to execute the application program. Task management is classified into task assignment and task switching. Each of these controls is realized by a control unit program.

  Task assignment means control processing for grasping the processing amount of a task in the task queue, determining the processing unit 4 to execute the task, and causing the determined processing unit 4 to execute the task. At this time, in addition to assigning one task to one processing unit 4, if the task processing amount is large, it is also possible to divide one task and assign it to a plurality of processing units 4. For example, when a task is composed of a plurality of basic blocks, the control unit 1 can easily divide the task into a plurality of processing units 4 by including information indicating the basic block in the task. Can be executed. The control unit 1 notifies the task to be processed to the processing unit 4 determined by the bus 8 in order to cause the determined processing unit 4 to execute the assigned task.

  Next, task management processing in the control unit 1 will be described using the application program of FIG. 4 as an example. The control unit 1 first assigns and executes task A to an arbitrary processing unit 4. The control unit 1 can be executed by writing the task A to be executed in the processing unit 4, or can notify the processing unit 4 of the address of the shared memory 5 in which the portion corresponding to the task A of the application program is stored. However, it is also possible to make the processing unit 4 obtain a necessary application program from the shared memory 5.

  When the processing unit 4 executing the task A ends the execution of the task A, the processing unit 4 changes the state from the processing state to the empty state and outputs the detailed identifier # 1 or # 2 according to the processing result. . The control unit 1 recognizes the end of processing in the processing unit 4 executing the task A through the state notification unit 6 and the next task to be executed is the task B or the task C depending on the value of the detailed identifier. And the task to be executed is assigned to the processing unit 4 that is in an empty state and executed. Note that the task B or C, which is the next task after the task A, has already been added to the task queue by any of the above-described methods. When it exists, it is also possible to assign tasks B and C to the processing unit 4 in an empty state in advance, and to load the corresponding part of the application program into the assigned processing unit 4 in advance. When it is loaded in advance, the control unit 1 gives an execution start trigger to the processing unit 4 loading the task to be executed next with the end of the execution of the task A.

  Further, when the state of the processing unit 4 executing the task D is changed from the processing state to the free state, and there are three or more processing units 4 in the free state at that time, 3 Tasks E, F, and G are assigned to the respective processing units 4 and executed. If there are two or less, only a part of the tasks, for example, only the task E is assigned and executed, and the remaining tasks are executed each time the processing unit 4 being processed changes to an empty state. Finally, when all the tasks E, F, and G have been executed, the task H is executed.

  FIG. 5 is a process flow diagram of task management in the control unit 1. The control unit 1 grasps necessary resources for tasks existing in the task queue (S51), reads the state of each processing unit 4 held by the state notification unit 6 (S52), and exists in the task queue according to the scheduling rule. Among these, the task that can be assigned to the processing unit 4 and the processing unit 4 that is the assignment destination, that is, the task execution schedule are determined (S53). Subsequently, when the execution-destination processing unit 4 is determined to be ready for execution by the execution-destination processing unit 4, the task assigned to the processing unit 1 is executed (S54). ).

  As described above, the control unit 1 performs task execution control on the processing unit 4 by writing the task portion of the application program to be executed to the processing unit 4. On the other hand, it is also possible to notify the address of the shared memory 5 where the necessary application program is stored, and the processing unit 4 obtains the necessary application program from the shared memory 5. The control unit 1 can also divide a task and cause a plurality of processing units 4 to execute the task.

  FIG. 6 is a process flow diagram of task switching by the control unit 1. For simplicity, the state notification unit 6 that holds various states output by the processing unit 4 is omitted from FIG. When it is necessary to execute a high priority task and there is no idle processing unit 4, the control unit 1 issues an interruption request to the processing unit 4 executing the low priority task (S61). ). Upon receiving the interruption request, the processing unit 4 saves the context, which is information necessary for resuming the task currently being executed, in the shared memory 5, interrupts the processing, and sets the interruption state to the state notification unit 6 via the line 71. Output (S62).

  After confirming the interruption of processing via the status notification unit 6, the control unit 1 instructs the processing unit 4 that has issued the interruption request to execute the generated high priority task. The processing unit 4 that has been instructed to execute starts the processing of the high priority task, and outputs a free state to the state notification unit 6 through the line 71 when the execution is completed (S63). The control unit 1 confirms the end of processing via the status notification unit 6 and then instructs the processing unit 4 to resume the task. The processing unit 4 that has received the task resumption instruction reads the context from the shared memory 5 and interrupts the task. Is resumed (S64).

  The interruption request made by the control unit 1 includes information specifying the storage position of the context, or the position of the context stored by the processing unit 4 that interrupted the processing of the low priority task is transmitted via the state notification unit 6 to the control unit. 1, and the control unit 1 notifies the processing unit 4 of the position of the context stored in the restart instruction, so that the processing unit 4 that interrupts the task is different from the processing unit 4 that restarts the interrupted task. Can be a thing.

  There are various methods for determining the priority of each task by the control unit 1, but there is a method of setting a higher priority to a task found earlier by reading an application program. For example, in the application program shown in FIG. 4, when tasks E, F, and G are read in the order, priority is assigned in the order of tasks E, F, and G. In this case, when the compiler compiles the application program, it is possible to recognize the number of operation data, the number of loops, and the like, and to prioritize at the compilation stage.

  There is also a method of increasing the priority as the processing amount of the task increases. For example, in the application program shown in FIG. 4, when task F has twice the processing amount of tasks E and G and there are two processing units 4, first, task F and task E are assigned to processing unit 4 and executed. Then, instead of assigning and executing the task F and the task G to the processing unit 4, the task F is first divided and executed by the two processing units 4, and then the tasks E and G are executed.

  Further, in the arithmetic device according to the present invention, a plurality of application programs can be executed simultaneously by using a plurality of processing units 4, but it is naturally possible to determine the priority for each application program.

  FIG. 7 is a process flow diagram of shared memory management in the control unit 1. The input / output management is the same by simply replacing the memory with hardware resources for input / output. Memory and input / output management manages access to hardware resources (not shown) for input / output to / from the shared memory 5 and an external device (not shown), and the individual processing units 4 are independent of the shared memory 5 and the like. This is necessary to prevent the loss of data due to the adverse effects of accessing the data, for example, when one processing unit 4 writes other data at the same position as the data written by another processing unit 4.

  The control unit 1 manages the allocation area of the shared memory 5 to each processing unit 4. When a memory request is received from the processing unit 4 via the status notification unit 6, the allocation status of the shared memory 5 is displayed. After confirming (S71), the area requested from the unallocated area is allocated to the processing unit 4 that has requested the memory (S72). The processing unit 4 having received the allocation of the area of the shared memory 5 and / or the allocation of the hardware resource for input / output accesses only the area or the hardware resource and does not access the other area or the hardware resource. . When the use of the allocated memory area or the like is finished, the processing unit 4 notifies the control unit 1 of a memory release request via the state notification unit 6.

  FIG. 2 is a block diagram of a second embodiment of the arithmetic device according to the present invention. In the following description, the same components as those described in the first embodiment are given the same reference numerals, and description thereof is omitted. According to FIG. 2, the processing unit 4 and the shared memory 5 are connected to the bus 81, the control unit 1, the nonvolatile memory 2 and the memory 3 are connected to the bus 82, and the bus 81 and the bus 82 are connected by the bus connection unit 9. .

  The bus connection unit 9 has a function of restricting the processing unit 4 from accessing the memory 3 and the nonvolatile memory 2, and the processing unit 4 destroys the control program or the control unit 1 stores the memory in the memory 3. Prevent overwriting of existing control data. Further, by providing a conversion function between the bus 81 and the bus 82, different bus protocols can be used.

  FIG. 3 is a block diagram of a third embodiment of the arithmetic device according to the present invention. According to FIG. 3, the processing unit 4 is connected to the bus 81, the control unit 1, the nonvolatile memory 2 and the memory 3 are connected to the bus 82, and the shared memory 5 is connected to the bus 81 and the bus 82. The control unit 1 is connected to each processing unit 4 by a line 73.

  In the present embodiment, the control unit 1 notifies the processing unit 4 of various controls for the processing unit 4 using a line 73. Further, the shared memory 5 is, for example, a two-port memory, and can be accessed from both the bus 81 and the bus 82, so that the bus connected to the processing unit 4 can be connected to the bus connected to the nonvolatile memory 2 and the memory 3. It is completely separated, and access from the processing unit 4 to the nonvolatile memory 2 and the memory 3 is completely prevented.

It is a block diagram of 1st Embodiment of the arithmetic unit by this invention. It is a block diagram of 2nd Embodiment of the arithmetic unit by this invention. It is a block diagram of 3rd Embodiment of the arithmetic unit by this invention. It is a figure which shows the relationship between the application program and task which a process part performs. It is a processing flow figure of the task management in a control part. It is a processing flow figure of the task switching by a control part. It is a processing flow figure of memory management in a control part. 1 is a configuration diagram of a multiprocessor system according to a conventional technique. FIG. It is another block diagram of the multiprocessor system by a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Control part 2 Non-volatile memory 3 Memory 4 Processing part 5 Shared memory 6 Status notification part 71, 72, 73 Line 8, 81, 82 Bus 9 Bus connection part

Claims (5)

By reading and executing the program for the control means, the control means for allocating the tasks constituting the application program to each processing means based on the status of each processing means held by the status notification means,
A plurality of processing means for executing a task assigned to the control means and outputting a status related to the execution of the task;
State notification means for holding the state output by the processing means;
An arithmetic device comprising: First storage means used only by the control means;
Second storage means used by the control means and the processing means;
The arithmetic unit according to claim 1, wherein: The control means allocates the area of the second storage means and / or hardware resources for input / output based on the request from the processing means to the requested processing means,
The processing means accesses only the area of the second storage means allocated from the control means and / or hardware resources for input / output;
The arithmetic unit according to claim 2, wherein: The control means and the first storage means are connected to the first bus,
The plurality of processing means and the second storage means are connected to the second bus,
Having bus conversion means for connecting the first bus and the second bus and preventing access from the processing means to the first storage means;
The arithmetic unit according to any one of claims 1 to 3, wherein: The control means and the first storage means are connected to the first bus,
The plurality of processing means are connected to the second bus,
The second storage means is connected to the first bus and the second bus;
The arithmetic unit according to any one of claims 1 to 3, wherein:

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