JP2007115895A - Compound semiconductor switch circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem wherein a high-frequency signal leaks from a vertical metal layer to the others and vice versa due to a depletion layer extended into a substrate, when different high-frequency signals are propagated to adjacent vertical metal layers in a switch MMIC (monolithic microwave integrated circuit), where a switching element on the first main surface of the substrate and the electrode pad on the second main surface are connected by a via hole penetrating the substrate and the vertical metal layer on its inner wall. <P>SOLUTION: A vertical n<SP>+</SP>-type region is provided between the vertical metal layers to which different high-frequency signals are applied, thus preventing the depletion layer extended from one vertical metal layer from reaching the other and suppressing the leakage of high-frequency signals. An occupation area on a control resistance chip can be reduced by connecting a vertical resistor based on the vertical n<SP>+</SP>-type region to one portion of the control resistor. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a compound semiconductor switch circuit device, and more particularly to a compound semiconductor switch circuit device that prevents leakage of a high-frequency signal.

  Mobile communication devices such as mobile phones often use microwaves in the GHz band, and switching elements for switching these high-frequency signals are used in antenna switching circuits and transmission / reception switching circuits. There are many cases. As the element, a field effect transistor (hereinafter referred to as FET) using gallium arsenide (GaAs) is often used because it handles high frequency, and accordingly, the monolithic microwave integration in which the switch circuit itself is integrated. A circuit (MMIC) is being developed.

  On the other hand, as devices are highly integrated, a method is known in which elements are formed on the substrate surface, electrode pads are formed on the back surface, and these are connected via via holes penetrating the substrate. Such an electrode structure using via holes is also employed in compound semiconductor substrates.

  For example, in FIG. 21, a hole 41 h that penetrates the GaAs substrate 41 is provided, and the inner wall of the hole 41 h is covered with a gold film 62. And the electrode of the capacitor | condenser 49 provided, for example on the surface of the board | substrate 41 is connected to the output terminal 55 of the board | substrate 41 back surface via the gold film 62 (for example, refer patent document 1).

FIG. 22 shows a case where an embedded PHS (Plated Heat Sink) structure is used. An FET 251 having a drain 251d, a source 251s, and a gate 251g is formed on the surface, and the source 251s is connected to a PHS 253 serving as a back electrode through a via hole 252 (see, for example, Non-Patent Document 1).
JP 2002-83936 A (FIG. 11) Yoshihiro Tsukahara et al., 4 persons, “X-band operation high output MMIC amplifier using embedded PHS structure”, Mitsubishi Electric Technical Report, Mitsubishi Electric Corporation, 2000, Vol. 74, no. 6, P51-54

  In the structure of FIG. 21, the gold film 62 and the semi-insulating substrate 41 form a Schottky junction on the surface of the semi-insulating substrate 41 in the hole 41h. Therefore, the depletion layer greatly extends from the Schottky junction toward the substrate 41 and reaches the adjacent hole 41f. That is, there is a problem that a high frequency signal leaks between the metal layers of adjacent holes.

  In FIG. 22, only the electrode connected to the ground potential (GND) is connected to the heat sink and grounded. That is, only the source 251 s of the FET 251 constituting the high output MMIC is grounded by the PHS 253 on the rear surface of the substrate through the via hole 252 to reduce the parasitic source inductance component. In such a case, since all the via holes 252 are at the ground potential, the high frequency signal does not leak between the adjacent via holes 252. However, as described above, the electrodes can be formed on the back surface of the substrate by connecting via vias 252 from the front surface electrode only to the GND potential electrode (source 251s) in the device having the entire substrate back surface GND potential. Not all pads of the device can be formed on the back side of the substrate.

  In the above structure, it is necessary to form electrode pads on each of the front surface and the back surface of the substrate, and there are problems such as an increase in manufacturing steps and complicated mounting. That is, it is necessary to form all electrode pads having a potential other than the GND potential on the substrate surface, and even if the number of steps such as the formation of the via hole 252 and the PHS 253 is increased, the area for arranging the electrode pads on the substrate surface is greatly reduced. I can't.

  The present invention has been made in view of the various circumstances described above, and corresponds to a compound semiconductor substrate, a switching element provided on the first main surface of the substrate, and constituting a switch circuit device, and a terminal of the switch circuit device. A first electrode pad and a second electrode pad which are provided on the second main surface of the substrate and through which the first high-frequency signal and the second high-frequency signal propagate, respectively, are provided so as to penetrate the substrate and are adjacent to each other. The first and second via holes, provided on the sidewalls of the first via holes, the first metal layer connecting the first electrode pad and the switching element, and provided on the sidewalls of the second via holes; A second metal layer connecting the second electrode pad and the switching element; a conductive region provided between the first metal layer and the second metal layer and reaching the second main surface from the first main surface; It solves By providing.

  Second, a compound semiconductor substrate, a switching element provided on the first main surface of the substrate and constituting a switch circuit device, a common input terminal of the switch circuit device provided on the second main surface of the substrate, A common input terminal pad, an output terminal pad, and a control terminal pad that are connected to the output terminal and the control terminal, respectively, a connection means that connects the control terminal pad and the switching element, and the board is provided so as to be adjacent to each other. First and second via holes, a first metal layer that is provided on a side wall of the first via hole and propagates a first high-frequency signal, and a second high-frequency signal provided on a side wall of the second via hole. A second metal layer that propagates through the first metal layer and a conductive region that is provided between the first metal layer and the second metal layer and reaches the second main surface from the first main surface. It is intended to attain.

  According to the present invention, the following effects can be obtained.

  First, a depletion layer extending from one side of a vertical metal layer that is provided on a side wall of a via hole and propagates a high-frequency signal to at least one and a vertical metal layer adjacent to the vertical metal layer reaches the other. Can be prevented. The metal layer forms a Schottky junction with the semi-insulating substrate on the side wall of the via hole, but the depletion layer generated by the Schottky junction extends beyond the conduction region provided between two adjacent via holes to the semi-insulating substrate. It does not spread. This prevents high-frequency signals from leaking between adjacent via hole metal layers.

  Second, all the pads can be placed on the back side. While the element region of the switch MMIC is becoming finer, the electrode pad must ensure the diameter of the gold wire to be connected. Therefore, for example, in a single-stage SPDT, the pad occupies 50% or more of the chip size, and there is a limit to miniaturization of the chip. Further, when the number of electrode pads such as SP3T increases, there is a problem that the chip size naturally increases. However, according to the present embodiment, all the electrode pads can be arranged on the back surface of the chip. In addition, via holes can increase the degree of freedom of electrode pad placement. Therefore, the chip size can be reduced.

  Third, a part of the control resistor is constituted by a conductive region that penetrates the substrate. The control resistance of the switch MMIC requires a high resistance value of 5 KΩ or more. Therefore, it is necessary to route the control resistor on the chip surface in order to obtain a predetermined resistance value, which also prevents the chip from being downsized. However, according to the present embodiment, the vertical resistor can be formed using the thickness of the substrate in the vertical direction. As a result, the area occupied by the control resistor on the chip surface can be reduced, so that the chip can be downsized.

  Further, since the vertical resistor and the conductive region have the same structure and can be formed in the same process, it can be carried out without adding a new man-hour for the vertical resistor.

  With reference to FIGS. 1 to 20, an embodiment of the present invention will be described by taking SP3T (Single Pole Throw Throw) having three switching elements as an example.

  First, a first embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 is a circuit diagram showing an example of SP3T.

  The switch MMIC is composed of a first FET group F1, a second FET group F2, and a third FET group F3 that connect FETs in series in three stages and serve as switching elements. Further, the source electrode (or drain electrode) of the FET at one end of the first FET group F1, the source electrode (or drain electrode) of the FET at one end of the second FET group F2, and the FET at one end of the third FET group F3 Source electrodes (or drain electrodes) are connected to the common input terminal IN. In addition, the gate electrodes of the three FETs of the first FET group F1 are connected to the first control terminal Ctl1 through the first control resistor CR1, respectively, and the three gate electrodes of the second FET group F2 are respectively connected to the second control terminal Ctl1. The resistor CR2 is connected to the second control terminal Ctl2. The three gate electrodes of the third FET group F3 are connected to the third control terminal Ctl3 through the third control resistor CR3.

  A part of the first control resistor CR1 is composed of resistors VR1-1, VR1-2, VR1-3 connected to the respective gate electrodes of the first FET group F1, and a part of the second control resistor CR2 is the second control resistor CR2. The resistors VR2-1, VR2-2, and VR2-3 are connected to the gate electrodes of the FET group F2. A part of the third control resistor CR3 is a resistor VR3 that is connected to the gate electrodes of the third FET group F3. -1, VR3-2 and VR3-3.

  Furthermore, the drain electrode (or source electrode) of the FET at the other end of the first FET group F1 is connected to the first output terminal OUT1. Further, the drain electrode (or source electrode) of the FET at the other end of the second FET group F2 is connected to the second output terminal OUT2, and the drain electrode (or source electrode) of the FET at the other end of the third FET group F3 is connected. This is connected to the third output terminal OUT3.

  FET group in which one of the control signals applied to the first, second and third control terminals Ctl1, Ctl2, Ctl3 is a combination of H level and the other is L level, and the H level signal is applied Is turned ON, and a high-frequency analog signal input to the common input terminal IN is transmitted to one of the output terminals. The resistors are arranged for the purpose of preventing leakage of high-frequency signals via the gate electrodes with respect to the DC potentials of the control terminals Ctl1, Ctl2, and Ctl3 that are AC grounded.

  FIG. 2 is a plan view of a switch MMIC in which the circuit of FIG. 1 is integrated on one chip. In the present embodiment, the switching element is disposed on the first main surface (front surface) S1 of the GaAs substrate 11, and all of the second main surface (back surface) S2 facing the first main surface S1 are connected to the switching element. Electrode pads are arranged. FIG. 2 is a diagram in which plan views of the first main surface S1 and the second main surface S2 are superimposed.

  Three FET groups serving as switching elements are arranged on the first main surface S1 of the GaAs substrate 11. The first FET group F1 is formed by, for example, connecting three FETs of FET1-1, FE1-2, and FET1-3 in series. The second FET group F2 is formed by connecting FET2-1, FET2-2, and FET2-3 in series. The third FET group F3 is formed by connecting FET3-1, FET3-2, and FET3-3 in series.

  A first control resistor CR1, a second control resistor CR2, and a third control resistor CR3 are connected to the nine gate electrodes constituting each FET group.

  A surface ohmic metal layer (AuGe / Ni / Au) 10s, which is a first metal layer and is in ohmic contact with the substrate, forms a source electrode, a drain electrode, and the like of each FET. In FIG. Since it overlaps with the surface wiring metal layer (Ti / Pt / Au) 30s of the layer, it is not shown in the figure.

  The wiring of the second metal layer indicated by the dotted line is a gate metal layer (for example, Pt / Mo) 20 formed simultaneously with the formation of the gate electrode of each FET, and the surface wiring metal layer 30s indicated by the solid line is Wiring and electrode pads for connecting elements are formed.

  The electrode pads are the common input terminal pad I, the first output terminal pad O1, the second output terminal pad O2, the third output terminal pad O3, the first control terminal pad C1, the second control terminal pad C2, and the third control terminal pad. C3, a common input terminal IN, a first output terminal OUT1, a second output terminal OUT2, a third output terminal OUT3, a first control terminal Ctl1, a second control terminal Ctl2, and a third control terminal Ctl3 of the switch circuit device, respectively. Connecting.

  All the electrode pads are provided on the second main surface (back surface) S2 facing the first main surface (front surface) S1. Via holes 55 penetrating the substrate 11 from the first main surface S1 to the second main surface S2 are provided corresponding to each electrode pad, and the common input terminal pad I, the first input layer I are formed by the metal layer 65 covering the side wall of the via hole 55. One output terminal pad O1, a second output terminal pad O2, and a third output terminal pad O3 are connected to each FET group.

  FIG. 3 is a plan view showing the first main surface S1.

  Since the first FET group F1, the second FET group F2, and the third FET group F3 have the same configuration, the first FET group F1 will be mainly described below. The FET 1-1 is a source electrode 35 (or drain electrode) in which three comb-like surface wiring metal layers 30 s extending from the upper side are connected to the common input terminal pad I, and a surface ohmic metal layer is formed below the source electrode 35. Source electrode (or drain electrode). Further, the three comb-like surface wiring metal layers 30s extending from the lower side are the drain electrode 36 (or source electrode) of the FET 1-1, and the drain electrode (or source electrode) formed of the surface ohmic metal layer therebelow. ) Both electrodes are arranged in a shape in which comb teeth are engaged, and a gate electrode 27 formed of the gate metal layer 20 is arranged in the shape of five comb teeth therebetween.

  In the FET 1-2, three source electrodes 35 (or drain electrodes) extending from the upper side are connected to the drain electrode 36 of the FET 1-1. Here, since this electrode is only a high-frequency signal passing point and generally does not need to be led out, no pad is provided. Further, the three drain electrodes 36 (or source electrodes) extending from the lower side are connected to the source electrode 35 of the FET 1-3. Similarly, this electrode is just a high-frequency signal passing point and generally does not need to be led to the outside, and therefore no pad is provided. There is a surface ohmic metal layer under both electrodes. These are arranged in a shape in which comb teeth are engaged, and a gate electrode 27 formed of the gate metal layer 20 is arranged in the shape of five comb teeth in the meantime.

  A switch circuit device in which FETs are connected in series in multiple stages is a high output switch circuit device because it can withstand a larger voltage amplitude when the FET group is OFF, as compared with a switch circuit device having one FET. At that time, it is not necessary to provide the source electrode or the drain electrode of the FET that becomes a connection portion when connecting the FETs in series, and therefore it is not necessary to provide a pad.

  In the FET 1-3, three comb-like surface wiring metal layers 30 s extending from the upper side are source electrodes 35 (or drain electrodes), and below these are source electrodes (or drain electrodes) formed of surface ohmic metal layers. is there. Further, the three comb-like surface wiring metal layers 30s extending from the lower side are the drain electrodes 36 (or source electrodes) connected to the output terminal pads O1, and the drain electrodes formed by the surface ohmic metal layers therebelow. (Or source electrode). Both electrodes are arranged in a shape in which comb teeth are engaged, and a gate electrode 27 formed of the gate metal layer 20 is arranged in the shape of five comb teeth therebetween. Each gate electrode 27 is bundled with comb teeth by a gate wiring 21 which is also formed of the gate metal layer 20.

  The operation region 100 is a region in which, for example, an n-type impurity is selectively ion-implanted into the GaAs substrate 11 like a one-dot chain line, and the source region and the drain region, which are high-concentration n-type impurity regions, are included in the operation region 100. Selectively formed.

  A via hole 55 penetrating the substrate 11 is provided around the substrate 11 from the first main surface S1 to the second main surface S2. The via hole 55 is arranged corresponding to the electrode pad (common input terminal pad I, first to third output terminal pads O1 to O3) arranged on the second main surface S2 and through which the high frequency signal propagates. Further, at least the side wall of the via hole 55 is covered with a metal layer (hereinafter referred to as a vertical metal layer) 65.

  A conductive region 155 is provided between each FET group. The conductive region 155 is an n-type impurity region 155 (hereinafter referred to as a vertical n + type region 155) provided from the first main surface S1 to the second main surface S2 of the substrate 11. The vertical n + type regions 155 are arranged adjacent to each other and are arranged between the vertical metal layers 65 through which different high-frequency signals propagate. This can prevent a high-frequency signal leaking between the vertical metal layers 65, which will be described later.

A floating impurity region 170 is provided on the surface of the first main surface S1 of the substrate 11 between the first FET group F1, the second FET group F2, and the third FET group F3. The floating impurity region 170 is an n-type impurity region provided in an island shape without any potential applied from the outside, and has an impurity concentration of about 1 to 5 × 10 ¹⁸ cm ⁻³ . In the figure, a part of the floating impurity region 170 and the vertical n + type region 155 are provided so as to overlap each other. Although it is not necessary to overlap the two, since both are disposed between the FET groups, they are disposed at substantially the same position.

  In a region where FETs are connected in series, that is, between FET 1-1 and FET 1-2, and between FET 1-2 and FET 1-3, a surface wiring metal layer 30s is formed on a nitride film (not shown) provided on the surface of the substrate 11. Is extended. In the region where the first FET group F1 and the second FET group F2 are adjacent, the surface wiring metal layers 30s are close to each other on the nitride film. Since a high-frequency analog signal propagates to the surface wiring metal layer 30s, the underlying nitride film becomes a capacitive component, and the high-frequency signal passes through the nitride film and reaches the semi-insulating substrate 11. Further, charge and discharge of charges due to the high frequency signal leaking in the semi-insulating substrate 11 occurs, and the high frequency signal leaks between the adjacent surface wiring metal layers 30s. Similarly, in the region between the conduction region (for example, the operation region 100) on the first FET group F1 side and the conduction region (for example, the operation region 100) on the second FET group F2 side in the semi-insulating substrate 11, a high frequency signal is similarly applied. As a result, charging and discharging of electric charges occur, and leakage of high-frequency signals occurs between adjacent conductive regions. However, by arranging the floating impurity region 170 as shown in the figure, even when a high-frequency signal leaks into the semi-insulating substrate 11, charge and discharge are caused between adjacent surface wiring metal layers 30s and between conductive regions. It is possible to prevent high-frequency signal leakage.

  The gate wirings 21 of the FET 1-1, FET1-2, and FET1-3 are connected to the resistor VR1 (resistors VR1-1, VR1-2, VR1-3) outside the operation region 100, respectively. The resistor VR1 is another conductive region provided from the first main surface S1 to the second main surface S2 of the substrate 11, and is specifically an n-type impurity region having a resistance value of about 10 KΩ. The resistor VR1 (hereinafter referred to as the vertical resistor VR1) is wired on the second main surface S2 and connected to the first control terminal pad C1. That is, the vertical resistor VR1 is a resistor that forms part of the first control resistor CR1.

  Similarly, the gate wiring 21 of the second FET group F2 is connected to the vertical resistor VR2 (resistors VR2-1, VR2-2, VR2-3), and the gate wiring 21 of the third FET group F3 is also connected to the vertical resistor VR3. (Resistors VR3-1, VR3-2, VR3-3).

  4 is a cross-sectional view taken along the line aa in FIG.

  A p-type region 13 and an n-type channel layer 12 are provided on a non-doped GaAs substrate 11, and high-concentration n-type impurity regions for forming a source region 18 and a drain region 19 are provided on both sides thereof. A gate electrode 27 forms a Schottky junction with the channel layer 12. The periphery of the gate electrode 27 is covered with a nitride film 60s serving as a passivation film. The source region 18 and the drain region 19 are provided with a source electrode 15 and a drain electrode 16 formed of the surface ohmic metal layer 10s. Further, a nitride film 60sa is provided thereon, and the source electrode 35 and the drain electrode 36 formed of the surface wiring metal layer 30s through the opening of the nitride film 60sa are connected to the source electrode 15 and the drain electrode 16 in the first layer. Contact. The surface wiring metal layer 30s connecting the FET 1-1, FET 1-2, and FET 1-3 respectively extends on the nitride film 60sa. Further, the surface wiring metal layers 30s of adjacent FET groups (for example, the first FET group F1 and the second FET group F2) are arranged close to each other on the nitride film 60sa (see FIG. 6). The surface of the substrate 11 is covered with a nitride film 60sb serving as a jacket coat film.

  FIG. 5 is a plan view of the second main surface S2.

  On the second main surface S2, the common input terminal pad I, the first control terminal pad C1, the second control terminal pad C2, the third control terminal pad C3, the first output terminal pad O1, Seven electrode pads of 2 output terminal pad O2 and 3rd output terminal pad O3 are arranged. Each electrode pad is formed of a back surface wiring metal layer 30r having the same configuration as that of the front surface wiring metal layer 30s.

  The common input terminal pad I and the first to third output terminal pads O1 to O3 are provided corresponding to the via hole 55, and the vertical metal layer 65 on the side wall of the via hole 55 is provided with the common input terminal pad I and the first to third third input pads. Electrically connected to the output terminal pads O1 to O3. Although an example in which the via hole 55 is provided so as to overlap with the electrode pad is shown here, a wiring connected to the electrode pad may be provided, and the wiring and the via hole 55 may be overlapped. A plurality of via holes 55 may be provided on one wiring (or electrode pad).

  A vertical n + type region 155 that penetrates the substrate 11 is disposed between the vertical metal layers 65 that are electrically connected to the first, second, and third output terminal pads O1, O2, and O3, respectively. . In this way, different high-frequency signals propagate and the vertical n + region 155 is disposed between the adjacent vertical metal layers 65, thereby preventing high-frequency signals leaking between the vertical metal layers 65.

  Further, when the vertical metal layer 65 is brought into contact with the wiring connected to the common input terminal pad I and the first to third output terminal pads O1 to O3 as described above, different high-frequency signals propagate and are adjacent to each other. A vertical n + type region 155 is disposed between the vertical metal layers 65.

  Further, the vertical resistors VR1, VR2, and VR3 reach the second main surface S2, and are connected to the corresponding first to third control terminal pads C1 to C3. For example, in the first FET group F1, the vertical resistor VR1-1 is directly connected to the first control terminal pad C1, and the vertical resistors VR1-2 and VR1-3 are connected to the first control terminal pad via the back surface wiring W. Connect to C1. The back surface wiring W is formed by a back surface wiring metal layer 30r constituting each electrode pad.

  The vertical metal layer 65 and the vertical n + type region 155 will be described with reference to FIG. The figure is a cross-sectional view taken along line bb of FIG. Although the first output terminal pad O1 portion will be described, the other via holes 55 and the vertical metal layer 65 have the same configuration.

  The first via hole 55a and the second via hole 55b are disposed adjacent to each other, and the first vertical metal layer 65a and the second vertical metal layer 65b are provided on the side walls of the respective via holes 55a and 55b. The first vertical metal layer 65a connects the first electrode pad (first output terminal pad O1) and the switching element, and the second vertical metal layer 65b connects the second electrode pad (second output terminal pad O2) and the switching element. Connect.

  Hereinafter, the first via hole 55a and the second via hole 55b, and the first vertical metal layer 65a and the second vertical metal layer 65b have the same structure, and will be described with the same reference numerals.

  As described above, the via hole 55 reaches the second main surface S2 from the first main surface S1 of the substrate 11 and is provided through the substrate 11. The via hole 55 is provided corresponding to the first output terminal pad O1, and overlaps with the first output terminal pad O1 here. The size of the via hole 55 is sufficient if it is about 10 μm × 10 μm. The front surface wiring metal layer 30s is a third metal layer constituting the drain electrode 36 of the FET 1-3 in the first FET group F1, and the back surface wiring metal layer 30r has the same configuration as the front surface wiring metal layer 30s. It is a metal layer.

  The sidewall of the via hole 55 is covered with the vertical metal layer 65. Here, a case where the vertical metal layer 65 is filled in the via hole 55 is shown, but it is sufficient that at least the side wall of the via hole 55 is covered, whereby the surface wiring metal layer 30s (the drain electrode 36 of the FET 1-3). ) And the backside wiring metal layer 30r (first output terminal pad O1) are electrically connected by the vertical metal layer 65.

  The vertical metal layer 65 is in contact with the front wiring metal layer 30s and the back wiring metal layer 30r through the front ohmic metal layer 10s and the back ohmic metal layer 10r, respectively, in order to improve ohmic properties. The surface ohmic metal layer 10 s is a metal layer that constitutes the source electrode 15 and the drain electrode 16 of the first layer of each FET. The back ohmic metal layer 10r is a metal layer having the same configuration as that of the front ohmic metal layer 10s. The front ohmic metal layer 10 s and the back ohmic metal layer 10 r may be larger than the via hole 55.

  The surface wiring metal layer 30s is in contact with the surface ohmic metal layer 10s through an opening provided in the nitride film 60sa serving as a passivation film. The surface wiring metal layer 30s is covered with a nitride film 60sb serving as a jacket coat film.

  Similarly, the back wiring metal layer 30r is in contact with the back ohmic metal layer 10r through an opening provided in the nitride film 60ra serving as a passivation film. The back wiring metal layer 30r is covered with a nitride film 60rb serving as a jacket coat film.

  A high frequency analog signal propagates between the common input terminal pad I and the first output terminal pad O1 (the same applies to the second output terminal pad O2 and the third output terminal pad O3). Further, for example, the vertical metal layer 65 connected to the first output terminal pad O1 forms a Schottky junction with the substrate 11 in the via hole 55.

  The potentials of the common input terminal pad I and the first to third output terminal pads O1 to O3 change from time to time by the high-frequency signals that propagate, that is, the potential of the vertical metal layer 65 connected to each electrode pad also changes. To do. Further, even on the same metal wiring, the high-frequency signal propagates a certain distance, and if the position is different, the phase is different, so the potentials are also different. As described above, when the vertical metal layers 65 through which different high-frequency signals propagate are arranged adjacent to each other, if the separation distance is short, the vertical metal layer 65 adjacent to the depletion layer extending from the Schottky junction to the substrate 11 is used. The high frequency signal leaks between them.

  Therefore, in the present embodiment, when the first and second vertical metal layers 65 that are respectively connected to the first and second electrode pads and the first and second high-frequency signals propagate are arranged adjacent to each other, A vertical n + type region 155 is disposed between them.

The impurity concentration of the vertical n + type region 155 is 1 to 50 × 10 ¹⁷ cm ⁻³ . Therefore, unlike the substrate 11 which is not doped with impurities (which is semi-insulating but has a substrate resistance value of about 1 × 10 ⁷ Ω · cm), the depletion layer hardly spreads in the vertical n + region 155. . That is, even when the depletion layer spreads from the vertical metal layer 65 to the substrate 11 in the horizontal direction, the vertical n + region 155 can prevent the depletion layer from reaching the adjacent vertical metal layer 65. Therefore, it is possible to prevent a high-frequency signal leaking between the adjacent vertical metal layers 65 and to improve isolation of the switch circuit device.

  For this reason, the length of the vertical n + type region 155 on the first main surface S1 (the same applies to the second main surface S2) is at least equal to or greater than the length of the vertical metal layer 65.

  Further, on the surfaces of the first main surface S1 and the second main surface S2 of the substrate 11 to which the front surface ohmic metal layer 10s and the back surface ohmic metal layer 10r contact, for example, a surface n + type region 130s, which is an n-type impurity region, and A back surface n + type region 130r is provided. These protrude from the front surface ohmic metal layer 10s and the back surface ohmic metal layer 10r and are provided in the vicinity thereof. In particular, the back surface n + type region 130r is provided outside the first output terminal pad O1 and around the first output terminal pad O1.

  Similarly to the vertical n + type region 155, the front surface n + type region 130s and the back surface n + type region 130r are formed from the surface wiring metal layer 30s and the back surface wiring metal layer 30r through the surface ohmic metal layer 10s and the back surface ohmic metal layer 10r. 11 to suppress the depletion layer extending. That is, it is possible to prevent a high frequency signal from leaking into a conductive region (metal layer or impurity region) arranged close to each other and improve isolation.

  That is, both the front surface n + type region 130s and the back surface n + type region 130r may be arranged in a pattern larger than each pad or each wiring.

  Here, the floating impurity region 170 is provided on the surface of the first main surface S1 of the vertical n + type region 155. Then, leakage of a high-frequency signal between the surface wiring metal layer 30s of the first FET group F1 and the surface wiring metal layer 30s of the second FET group F2 that extends and is close to the nitride film 60sa serving as a passivation film is prevented. To do.

  FIG. 7 is a diagram illustrating the vertical resistance VR. FIG. 7A is a perspective plan view of the first main surface S1 and the second main surface S2, and the front ohmic metal layer 10s and the back ohmic metal layer 10r are omitted. FIG. 7B is a cross-sectional view taken along the line cc of FIG. 2 (and FIG. 7A).

  For example, the gate wiring 21 in which the gate electrodes 27 of the FET 1-1 are bundled is connected to the vertical resistor VR1-1 through the surface wiring metal layer 30s and the surface ohmic metal layer 10s outside the operation region 100. The surface wiring metal layer 30s is in contact with the surface ohmic metal layer 10s and the gate wiring 21 through an opening provided in the nitride film 60sa. The surface wiring metal layer 30s is covered with a nitride film 60sb.

  The vertical resistor VR1-1 is provided to reach the second main surface S2 from the first main surface S1, and is connected to the back wiring metal layer 30r via the back ohmic metal layer 10r on the surface of the second main surface S2. Back wiring metal layer 30r is in contact with back ohmic metal layer 10r through an opening provided in nitride film 60ra, and the surface of back wiring metal layer 30r is covered with nitride film 60rb. The back wiring metal layer 30r is a part of the first control terminal pad C1. In the vertical resistors VR1-2 and VR1-3, the back surface wiring metal layer 30r is a part of the back surface wiring W, and is connected to the first control terminal pad C1 through the back surface wiring W. That is, the vertical resistor VR1 and the back surface wiring W constitute a part of the first control resistor CR1.

The vertical resistor VR1 has an area of about several μm ^{2 on} the surface of the first main surface S1, and the resistance value is about 10 KΩ. The vertical resistor VR1 constitutes a part of the first control resistor CR1.

  For the same reason as the vertical n + type region 155, the surface of the first main surface S1 and the second main surface S2 are provided with a front surface n + type region 130s and a back surface n + type region 130r to improve isolation. The surface n + -type region 130 s is provided continuously and below the surface ohmic metal layer 10 s and the gate wiring 21. Further, the back surface n + type region 130r is provided so as to protrude from the back surface ohmic metal layer 10r.

  The control resistance of the switch MMIC requires a high resistance value of 5 KΩ or more. Therefore, it is necessary to route the control resistor on the chip surface in order to obtain a predetermined resistance value, which prevents the chip from being downsized. However, according to the present embodiment, the vertical resistor VR1 can be formed using the thickness of the substrate 11 in the vertical direction. As a result, the area occupied by the first control resistor CR1 on the chip surface can be reduced, so that the chip can be downsized.

  Further, since the vertical resistor VR1 and the other conductive regions have the same structure and can be formed in the same process, it can be carried out without adding a new man-hour for forming the vertical resistor VR1.

  FIG. 8 is a diagram showing the common input terminal pad I and the vertical metal layer 65 connected to the common input terminal pad I, and is a sectional view taken along the line dd of FIG.

  The common input terminal pad I is provided on the second main surface S2, and the surface wiring metal layer 30s of the first main surface S1 is provided via the via hole 55 penetrating the substrate 11 and the vertical metal layer 65 provided on the side wall thereof. Connect electrically. Also in this case, the vertical metal layer 65 is filled in the via hole 55. In this case, the vertical n + type region 155 is in contact with the vertical metal layer 65 on the sidewall of the via hole 55 and is provided along the vertical metal layer 65. Since the other configuration is the same as that of the first output terminal pad O1, the description thereof will be omitted.

  The vertical resistor VR <b> 1-1 (as well as other vertical resistors) is an impurity diffusion region, and no junction is formed with the semi-insulating substrate 11. The depletion layer is generated from the junction when a reverse bias is applied to the junction, and the spread distance increases as the reverse bias voltage applied to the junction increases. Therefore, no depletion layer is generated from the side surface of the vertical resistor VR1-1.

  On the other hand, a depletion layer spreads from the Schottky junction between the vertical metal layer 65 connected to the common input terminal pad I and the substrate 11. Here, as described above, the potential of the high-frequency signal propagating through the vertical metal layer 65 of the common input terminal pad I and the potential applied to the first control terminal pad C1 change from moment to moment. The depletion layer spreads from the vertical metal layer 65 to the substrate 11 only when the potential of the high-frequency signal propagating through the common input terminal pad I is lower than the potential of the first control terminal pad C1.

  For example, when the control signal of the first control terminal pad C1 changes at 3V / 0V, the bias potential of the common input terminal pad I is about 2.4V. Accordingly, when the first control terminal pad C1 is 3V, a high frequency signal propagates to the common input terminal pad I, but there is a time zone in which the potential of the common input terminal pad I is lower than that of the first control terminal pad C1. To do. In this time zone, when the depletion layer from the vertical metal layer 65 connected to the common input terminal pad I reaches the first control terminal pad C1 (or the vertical resistor VR1-1 connected thereto), the common input terminal pad I The high-frequency signal propagated to the first control terminal pad C1 having the GND potential (hereinafter referred to as the high-frequency GND potential) leaks as a high-frequency signal, and the insertion loss increases.

  In such a case, the vertical n + type region 155 is disposed between the vertical metal layer 65 through which the high-frequency signal propagates and the vertical resistor VR having the high-frequency GND potential (or DC potential). Thereby, since the spread of the depletion layer from the vertical metal layer 65 can be suppressed, a high-frequency signal leaking to the adjacent vertical resistor VR (conduction region) can be prevented. As shown, the vertical n + type region 155 may be provided in contact with the vertical metal layer 65.

  9 and 10 are views showing the via hole 55 and the vertical metal layer 65. FIG.

  FIG. 9A shows the case where the vertical metal layer 65 is filled in the via hole 55. The front surface n + -type region 130 s and the back surface n + -type region 130 r are connected to the front surface wiring metal layer 30 s and the back surface wiring metal layer 30 r in a state where a direct current flows (hereinafter referred to as direct current connection), and are provided so as to protrude from these metal layers. It is done. For example, when the surface wiring metal layer 30s is connected to the surface n + type region 130s via the surface ohmic metal layer 10s as in the first to third output terminal pads O1 to O3 shown in FIG. is there.

  In this case, the vertical n + type region 155 is spaced from the vertical metal layer 65 and disposed between the adjacent vertical metal layers 65.

  FIG. 9B shows the case where the vertical n + type region 155 contacts the vertical metal layer 65 as shown in FIG. The vertical n + type region 155 is provided to reach the second main surface S2 from the first main surface S1 by implanting and diffusing impurities into the substrate 11 on the side wall of the via hole 66. Then, it is continuous with the front surface n + type region 130s and the back surface n + type region 130r. In such a case, the thickness d of the vertical n + type region 155 may be about several thousand mm.

  With this structure, even if the depletion layer extends in any direction from the via hole 55 (vertical metal layer 65), the vertical n + region 155 can suppress the spread.

  Further, as shown in FIG. 9C, the vertical metal layer 65 may be provided so as to cover only the side wall without filling the via hole 55.

  FIG. 10 is different from FIG. 9 in the shape of the via hole 55. In the case of FIG. 9, the via hole 55 is a trench type formed by anisotropic etching, but FIG. 10 is a shape etched in a mortar shape. Also in this case, the vertical metal layer 65 may be filled in the via hole 55 (FIG. 10A), or may be provided so as to cover only the side wall of the via hole 55 (FIG. 10B). .

  In each of FIGS. 9B to 10B, the vertical n + region 155 is in contact with the vertical metal layer 65. However, as shown in FIG. 9A, what is the vertical metal layer 65? You may arrange | position between the vertical metal layers 65 spaced apart and adjacent.

  Further, two adjacent vertical metal layers 65 (and via holes 55) do not have to have the same shape, and one of them may be a vertical resistance VR.

  Next, a second embodiment will be described with reference to FIGS. In the second embodiment, a vertical n + type region 155 is brought into contact with the vertical metal layer 65 connected to the first to third output terminal pads O1 to O3 as shown in FIG. 9B. Since the other configuration is the same as that of the first embodiment, the description thereof is omitted.

  11 is a plan view in which the patterns of the first main surface S1 and the second main surface S2 are superimposed, FIG. 12 is a plan view of the first main surface S1, and FIG. 13 is a plan view of the second main surface S2. It is.

  Via holes 55 are respectively provided so as to overlap with part of the first output terminal pad O1, the second output terminal pad O2, and the third output terminal pad O3, and the via hole 55 is filled with the vertical metal layer 65. A vertical n + region 155 that contacts the vertical metal layer 65 is also provided. That is, all of the vertical metal layers 65 connected to the common input terminal pad I and the first to third output terminal pads O1 to O3 are in contact with the vertical n + type region 155.

  Each electrode pad, via hole 55 and vertical metal layer 65, and vertical n + type region 155 are the same as the common input terminal pad I portion of FIG.

  That is, the vertical n + region 155 is provided along the via hole 55 side wall by implanting and diffusing n-type impurities into the substrate 11 on the side wall of the via hole 55. The via hole 55 is filled with a vertical metal layer 65 to contact the vertical metal layer 65 and the vertical n + type region 155. A sectional view of the vertical resistor VR1-1 (a sectional view taken along line c'-c 'in FIG. 11) is the same as FIG.

  14 is a cross-sectional view taken along the line ee of FIG.

  As in the present embodiment, by providing the vertical n + region 155 that contacts the outside of each vertical metal layer 65, the vertical n + region 155 is always disposed between the adjacent vertical metal layers 65. That is, even if the depletion layer extends in any direction, the spread can be suppressed. As shown in FIG. 2, since there is no restriction on the pattern by providing the vertical n + type region 155 separated from the vertical metal layer 65, it is suitable when the patterns are densely packed.

  Further, a vertical n + type region 155 may be provided between the vertical metal layers 65 as indicated by a broken line. As a result, the effect of preventing leakage of high-frequency signals is increased, and leakage of high-frequency signals with higher power can be prevented.

  A third embodiment will be described with reference to FIGS. 15 to 18.

  In the third embodiment, via holes 55 (third via holes) corresponding to the first to third control terminal pads C1 to C3 (third electrode pads), respectively, and the vertical metal layer 65 electrically connected to each other. (Third vertical metal layer) is provided.

  15 is a plan view in which the patterns of the first main surface S1 and the second main surface S2 are superimposed, FIG. 16 is a plan view of the first main surface S1, and FIG. 17 is a plan view of the second main surface S2. FIG.

  Except for the first control resistor CR1 to the third control resistor CR3, the second embodiment is the same as the second embodiment, and a detailed description thereof will be omitted.

  Since the first control resistor CR1 to the third control resistor CR3 have the same configuration, the first control resistor CR1 will be described.

The gate lines 21 of the FET 1-1, FET1-2, and FET1-3 are connected to the high resistor HR1 (high resistors HR1-1, HR1-2, HR1-3) outside the operation region 100, respectively. The high resistance element HR1 is obtained by extending a conductor having a high sheet resistance to the first main surface S1 of the substrate 11 as shown in FIG. For example, it is an n-type impurity region having a relatively low concentration (peak concentration: 2 to 4 × 10 ¹⁷ cm ⁻³ ) (high sheet resistance) comparable to that of the channel layer 12 in the operation region 100, and the sheet resistance is 1 KΩ / □. The resistance value is about 5 KΩ or more (for example, about 10 KΩ). The high resistance elements HR1-1, HR1-2, and HR1-3 are wired on the second main surface S2 through via holes 55 provided corresponding to the FET1-1, FET1-2, and FET1-3, respectively. The A vertical metal layer 65 is provided on the side wall of the via hole 55.

  The back surface wiring W extending to the second main surface S2 is constituted by the back surface wiring metal layer 30r. The back surface wiring W connects all the vertical metal layers 65 connected to the gate wiring 21 of the first FET group F1 to the first control terminal pad C1 (see FIG. 18).

  That is, the high resistor HR1, the vertical metal layer 65 connected to the high resistor HR1, and the back surface wiring W each constitute a part of the first control resistor CR1.

  18A and 18B are diagrams showing the vertical metal layer 65 connected to the high resistance element HR1, in which FIG. 18A is a plan view, and FIG. 18B is an ff in FIG. 18A and FIG. It is line sectional drawing.

  A via hole 55 extending from the first main surface S1 to the second main surface S2 and penetrating the substrate 11 is provided. The via hole 55 in this case may be about 10 μm × 10 μm as the area of the first main surface S1 (the same applies to the second main surface S2). A vertical n + type region 155 is provided on the surface of the substrate 11 on the side wall in the via hole 55, and the vertical metal layer 65 is filled in the via hole 55. The thickness d of the vertical n + type region 155 is about several thousand mm. The vertical metal layer 65 forms a Schottky junction with the substrate 11 in the via hole 55.

  Vertical metal layer 65 is in contact with surface ohmic metal layer 10s and back ohmic metal layer 10r on first main surface S1 and second main surface S2, respectively. The surface ohmic metal layer 10s contacts the surface wiring metal layer 30s through an opening provided in the nitride film 60sa, and the nitride film 60sb covers the surface ohmic metal layer 10s. The back surface ohmic metal layer 10r is in contact with the back surface wiring metal layer 30r (back surface wiring W) through an opening provided in the nitride film 60ra, and the nitride film 60rb is covered thereon. A front surface n + -type region 130 s and a back surface n + -type region 130 r for improving isolation are provided on the surface of the substrate 11 to which the front and back ohmic metal layers 10 s and 10 r contact, respectively.

Each electrode pad, via hole 55 and vertical metal layer 65, and vertical n + type region 155 are the same as the common input terminal pad I portion of FIG.
The Further, the via hole 55, the vertical metal layer 65, and the vertical n + type region 155 may be configured as shown in FIGS.

  For example, in the vicinity of the first output terminal pad O1, a vertical metal layer 65a having a DC potential (or a high-frequency GND potential, the same applies hereinafter) and a vertical metal layer 65b through which a high-frequency signal propagates are arranged adjacent to each other. (See FIG. 15). In such a case, a depletion layer spreads in the substrate 11 from the lower one of the vertical metal layers 65a and 65b toward the higher one. That is, in the switch circuit device, both the high-frequency signal and the DC potential change from moment to moment, so that the depletion layer spreads from the lower potential to the higher potential according to the potential relationship. When the depletion layer reaches the adjacent vertical metal layer 65, the high frequency signal leaks.

  Therefore, also in the vertical metal layer 65 having a DC potential, a depletion layer extending between the vertical metal layers 65 is formed by providing a vertical n + region 155 between the vertical metal layers 65 through which a high-frequency signal propagates. It is possible to prevent leakage of high-frequency signals due to changes in the frequency.

  Here, the case where the vertical n + type region 155 is provided in contact with the vertical metal layer 65 is shown, but the vertical n + type between the adjacent vertical metal layers 65 spaced apart from the vertical metal layer 65 is shown. A region 155 may be provided (see FIG. 6).

  For example, when there is a vertical metal layer 65 connected to the first control resistor CR1 and the second control resistor CR2, and these are adjacent to each other, it is not necessary to provide the vertical n + -type region 155 between them. For example, when the potentials of the two are different, the depletion layer spreads from the lower potential to the higher potential and reaches the vertical metal layer on the higher potential side. At this time, a slight leak current of about several nA flows. However, even if such a leakage current flows between the first control terminal Ctl1 and the second control terminal Ctl2, for example, the switching of the switch MMIC is not affected at all. Further, since no high frequency propagates to the DC terminal pad such as the control terminal, the high frequency signal does not leak and the high frequency characteristics such as insertion loss and isolation are not deteriorated. Therefore, when the adjacent vertical metal layers 65 are both at DC potential, there is no need to provide the vertical n + -type region 155 between them.

  19 and 20 show a fourth embodiment. The fourth embodiment is a switch circuit device using a HEMT (High Electron Mobility Transistor) as a switching element. The plan view is the same as in the first to third embodiments. 19A is a cross-sectional view of the operation region 100 (corresponding to a cross section along line aa in FIG. 3), and FIG. 19B is a cross-sectional view of the via hole 55 and the vertical metal layer 65 (g in FIG. 2). FIG. 19C is a cross-sectional view of a vertical resistor (corresponding to a cross section taken along the line cc of FIG. 2), FIG. 20 is a cross-sectional view of a high-resistance element, and FIG. A) corresponds to the cross section along the line hh in FIG. 15, and FIG. 20B corresponds to the cross section along the line ii in FIG. 15. Explanation of the same configuration as in the first to third embodiments is omitted.

  As shown in FIG. 19A, the substrate 11 is formed by laminating a non-doped buffer layer 132 on a semi-insulating GaAs substrate 131, and an n + type AlGaAs layer 133 serving as an electron supply layer on the buffer layer 132, a channel (electron traveling). ), A non-doped InGaAs layer 135 serving as a layer, and an n + type AlGaAs layer 133 serving as an electron supply layer are sequentially stacked. A spacer layer 134 is disposed between the electron supply layer 133 and the channel layer 135.

The buffer layer 132 is a high-resistance layer to which no impurity is added, and its film thickness is about several thousand Å. A non-doped layer is stacked on the upper electron supply layer 133 to ensure a predetermined breakdown voltage and pinch-off voltage. Here, for example, a first non-doped layer (AlGaAs layer) 141, a second non-doped layer (InGaP layer) 142, and a third non-doped layer (AlGaAs layer) 143 are stacked. A chemically stable stable layer (InGaP layer) 140 is disposed thereon, and an n + -type GaAs layer 137 serving as a cap layer is laminated on the uppermost layer. A high concentration impurity is added to the cap layer 137, and the impurity concentration is about 1 to 5 × 10 ¹⁸ cm ⁻³ .

The electron supply layer 133, the first to third non-doped layers 141, 142, 143, and the spacer layer 134 are made of a material having a larger band gap than the channel layer 135. Further, an n-type impurity (for example, Si) is added to the electron supply layer 133 at about 2 to 4 × 10 ¹⁸ cm ⁻³ .

  With such a structure, electrons generated from the donor impurity of the n + -type AlGaAs layer that is the electron supply layer 133 move to the channel layer 135 side, and a channel serving as a current path is formed. As a result, electrons and donor ions are spatially separated with the heterojunction interface as a boundary. Although electrons travel through the channel layer 135, since there are no donor ions, the influence of Coulomb scattering is very small and high electron mobility can be obtained.

  The operating region 100 of the HEMT is separated from other regions as shown by a one-dot chain line by an insulating region 50 reaching the buffer layer 132. The insulating region 50 is not electrically completely insulated, but is a region where carrier traps are provided in the epitaxial layer by ion implantation of impurities (B +). That is, impurities are also present in the insulating region 50 as an epitaxial layer, but are inactivated by B + implantation for insulation.

  A source region 137 s and a drain region 137 d are provided by partially removing the cap layer 137 to which the high concentration impurity is added in the operation region 100. A source electrode 15 and a drain electrode 16 formed of a surface ohmic metal layer 10s are connected to the source region 137s and the drain region 137d, and a source electrode 35 and a drain electrode 36 are formed on the upper layer thereof by a surface wiring metal layer 30s. .

  Further, in the operation region 100 of the first main surface S1, the cap layer 137 and the stable layer 140 where the gate electrode 27 is disposed are removed by etching, the third non-doped layer 143 is exposed, and the gate metal layer 20 is removed. A gate electrode 27 is formed by Schottky connection. The gate electrode 27 is formed by depositing Pt / Po. After vapor deposition, the lowermost layer metal (Pt) is buried by heat treatment until it reaches the first non-doped layer 41. For this reason, a high breakdown voltage characteristic can be obtained.

The HEMT epitaxial structure includes a cap layer 137. Since the impurity concentration of the cap layer 137 is as high as about 1 to 5 × 10 ¹⁸ cm ⁻³ , it can be said that the region where the cap layer 137 is disposed is functionally a high concentration (n + type) impurity region.

  As shown in FIG. 19B, each electrode pad is provided on the second main surface S2 by the back surface wiring metal layer 30r. Corresponding to each electrode pad, via holes 55 penetrating the substrate 11 are provided from the first main surface S1 to the second main surface S2. At least the side wall of the via hole 55 is covered with the vertical metal layer 65, whereby each electrode pad and the switching element (HEMT) are connected.

  Further, a vertical n + region 155 that contacts the vertical metal layer 65 is provided. Vertical n + type region 155 is provided by ion implantation and diffusion of n-type impurities into the substrate. The thickness d of the vertical n + type region 155 may be about several thousand mm. Further, as described above, the vertical n + type region 155 may be separated from the vertical metal layer 65.

  In the HEMT, the surface n + type region 130 s for improving isolation is also separated by the insulating region 50, and is constituted by a semiconductor layer including the cap layer 137. On the other hand, the back surface n + type region 130r is formed by ion-implanting impurities into the surface of the second main surface S2.

  The same applies when the vertical metal layer 65 connected to the first to third control resistors CR1 to CR3 is provided.

  FIG. 19C is a cross-sectional view showing the vertical resistance VR.

  Similarly to the gate electrode 27, the gate wiring 21 is provided on the third undoped layer 143, and a part of the lowermost layer metal (Pt) is buried to reach the first undoped layer 141. The surface ohmic metal layer 10s is provided on the cap layer 137, and the surface wiring metal layer 30s is in contact with the gate wiring 21 and the surface ohmic metal layer 10s through an opening provided in the nitride film 60sa serving as a passivation film. A nitride film 60sb serving as a jacket coat film is provided so as to cover them.

The vertical resistance VR is a conductive region that reaches the second main surface S2 from the first main surface S1, and an n-type impurity region in which n-type impurities are ion-implanted and diffused (concentration 1 to 50 × 10 ¹⁷ cm ⁻³ ). It is.

  The first control resistor CR1 (same as the second control resistor CR2 and the third control resistor CR3) is separated from the other regions by the insulating region 50 while securing a distance (length) and width having a desired resistance value. The The first control resistor CR1 may be constituted by a vertical resistor VR1 as shown in FIG. 2 or FIG. 11, or may be constituted by a low resistor LR1 and a high resistor HR1 as shown in FIG. You may mix them.

  FIG. 20 is a cross-sectional view showing the high resistor HR. 20A corresponds to a cross section taken along line hh in FIG. 15, and FIG. 20B corresponds to a cross section taken along line ii in FIG. Here, the second control resistor CR2 will be described, but the same applies to the first control resistor CR1 and the third control resistor CR3.

  The high resistance element HR2 is separated by the insulating region 50, and includes a region where the cap layer 137 is removed and the semiconductor layer below the cap layer 137 is exposed.

  That is, the high resistance element HR2 has the recess portion 101 obtained by etching the cap layer 137, and the cap layer 137 that becomes the contact portion 102 for connection remains at both ends of the recess portion 101. As shown in the figure, the contact portion 102 is continuously connected to the cap layer 137 of the low resistance LR2 as it is, or a resistance element electrode (not shown) is provided and connected to a wiring or the like as a part of the second control resistor CR2. It is an area. When the resistance element electrode is provided, it can be formed in the same manner as the source electrode and the drain electrode by the surface ohmic metal layer 10s and the surface wiring metal layer 30s of the HEMT.

  In the case of the figure, the third non-doped layer 143 is exposed at the bottom of the recess 101. As described above, by providing the recess portion 101 where the third non-doped layer 143 is exposed, the contact portion 102 and the channel layer 135 serve as a current path of the resistor, and the channel layer 135 serves as a substantial resistance layer. Since the channel layer 135 has a sheet resistance several times higher than that of the cap layer 137 (for example, 400Ω / □), a high resistance HR2 having a high resistance value can be obtained at a short distance. In the present embodiment, by providing the recess portion 101, the high resistance HR2 having a sheet resistance Rs = about 400Ω / □ is obtained. The recess portion 101 has a length of about 50 μm, for example.

  The main current path of the low resistance element LR2 is a cap layer 137 having a high impurity concentration and a large film thickness. The sheet resistance of the cap layer 137 is about Rs = 100Ω / □. In order to obtain a high resistance value (5 KΩ or more) with only the low resistance element LR2, it is necessary to sufficiently narrow the width or to ensure a sufficient length. Actually, since there is a limit to the miniaturization of patterning, it is necessary to secure a desired resistance value by the length. Therefore, when the resistance is increased, it is necessary to prepare a special space only for arranging the resistor without being able to fit in the gap between the pad and the element on the chip, and there is a problem that the chip area is increased. Therefore, in the present embodiment, the high resistance HR2 is employed in which the channel layer 135 having a high sheet resistance is removed by removing the cap layer 137, and the substantial resistance layer is used. As a result, it can be sufficiently accommodated in an empty space such as the periphery of the chip, so that it is not particularly necessary to increase the chip size.

  Note that the high-resistance element HR2 does not have to be an impurity implantation region or a region in which the lower semiconductor layer is exposed by etching the cap layer, and may be a metal resistor formed by, for example, deposited NiCr.

  Further, the front surface n + -type region 130 s and the back surface n + -type region 130 r are metal layers (surface ohmic metal layer 10 s, back ohmic metal layer 10 r, surface wiring metal layer 30 s, back surface wiring metal layer 30 r, or gate wiring 21, which are in contact therewith. However, it may be provided so as to protrude beyond the metal layer at the lower peripheral part of these metal layers. Further, it may be provided around the metal layer at a distance of about 5 μm or less from the metal layer.

When the semiconductor chip of this embodiment is mounted, bumps made of solder or the like are formed on the electrode pads made of the back surface metal layer 30r provided on the second main surface S2. Then, the bump is fixed to a conductive pattern provided on, for example, a glass epoxy substrate or a ceramic substrate.

It is a circuit diagram for demonstrating this invention. It is a top view for demonstrating this invention. It is a top view for demonstrating this invention. It is sectional drawing for demonstrating this invention. It is a top view for demonstrating this invention. It is sectional drawing for demonstrating this invention. It is (A) top view and (B) sectional view for explaining the present invention. It is sectional drawing for demonstrating this invention. It is sectional drawing for demonstrating this invention. It is sectional drawing for demonstrating this invention. It is a top view for demonstrating this invention. It is a top view for demonstrating this invention. It is a top view for demonstrating this invention. It is sectional drawing for demonstrating this invention. It is a top view for demonstrating this invention. It is a top view for demonstrating this invention. It is a top view for demonstrating this invention. It is (A) top view and (B) sectional view for explaining the present invention. It is sectional drawing for demonstrating this invention. It is sectional drawing for demonstrating this invention. It is sectional drawing for demonstrating a prior art. It is a perspective view for demonstrating a prior art.

Explanation of symbols

10s surface ohmic metal layer 10r back surface ohmic metal layer 11 substrate 12 channel layer 15, 35 source electrode 16, 36 drain electrode 27 gate electrode 18, 137s source region 19, 137d drain region 20 gate metal layer 21 gate wiring 30s surface wiring metal layer 30r Backside metal layer 55 Via hole 65 Vertical metal layer 130s Surface n + type region 130r Backside n + type region 170 Floating impurity region 131 GaAs substrate 132 Buffer layer 133 Electron supply layer 134 Spacer layer 135 Channel layer 137 Cap layer 140 Stabilization layer 141 First non-doped layer 142 Second non-doped layer 143 Third non-doped layer 155 Vertical n + type region 50 Insulating region 60 sa, 60 sb, 60 ra, 60 rb, 60 s, 60 r Nitride film 100 Operation Area 101 Recessed portion 102 Contact portion VR1, VR2, VR3, VR Vertical resistor HR1, HR2, HR3, HR High resistor LR1, LR2, LR3 Low resistor IN Common input terminal Ctl1 First control terminal Ctl2 Second control terminal Ctl3 Third control terminal OUT1 First output terminal OUT2 Second output terminal OUT3 Second output terminal I Common input terminal pad C1 First control terminal pad C2 Second control terminal pad C3 Third control terminal pad O1 First output terminal pad O2 First 2 output terminal pad O3 3rd output terminal pad CR control resistance CR1 1st control resistance CR2 2nd control resistance CR3 3rd control resistance F1 1st switching element F2 2nd switching element F3 3rd switching element W Back surface wiring

Claims (16)

A compound semiconductor substrate;
A switching element provided on the first main surface of the substrate and constituting a switch circuit device;
A first electrode pad and a second electrode pad which are provided on the second main surface of the substrate corresponding to the terminals of the switch circuit device and through which the first high frequency signal and the second high frequency signal propagate, respectively;
First and second via holes provided through the substrate and adjacent to each other;
A first metal layer provided on a sidewall of the first via hole and connecting the first electrode pad and the switching element;
A second metal layer provided on a sidewall of the second via hole and connecting the second electrode pad and the switching element;
A conductive region provided between the first metal layer and the second metal layer and extending from the first main surface to the second main surface;
A compound semiconductor switch circuit device comprising:   A third electrode pad to which a DC potential or a high-frequency GND potential is applied to the second main surface; another electrode pad connected to the third electrode pad and extending from the first main surface to the second main surface; The compound semiconductor switch circuit device according to claim 1, further comprising a conductive region.   3. The compound semiconductor switch circuit device according to claim 2, wherein the conductive region is provided between the adjacent first via hole and the other conductive region.   The compound semiconductor switch circuit device according to claim 1, wherein the conductive region is provided apart from the first metal layer.   The compound semiconductor switch circuit device according to claim 1, wherein the conductive region is provided in contact with the first metal layer.   A third electrode pad to which a DC potential or a high-frequency GND potential is applied to the second main surface; a third via hole provided corresponding to the third electrode pad and penetrating the substrate; A third metal layer is provided on a side wall and connects the third electrode pad and the switching element, and the conductive region is disposed between the adjacent first metal layer and the third metal layer. The compound semiconductor switch circuit device according to claim 1. A compound semiconductor substrate;
A switching element provided on the first main surface of the substrate and constituting a switch circuit device;
A common input terminal pad, an output terminal pad, and a control terminal pad connected to the common input terminal, the output terminal, and the control terminal of the switch circuit device, respectively, provided on the second main surface of the substrate;
Connection means for connecting the control terminal pad and the switching element;
First and second via holes provided through the substrate and adjacent to each other;
A first metal layer provided on a sidewall of the first via hole and through which a first high-frequency signal propagates;
A second metal layer provided on a side wall of the second via hole and through which a second high-frequency signal propagates;
A conductive region provided between the first metal layer and the second metal layer and reaching the second main surface from the first main surface;
A compound semiconductor switch circuit device comprising:   8. The compound semiconductor switch circuit device according to claim 7, wherein the first metal layer and the second metal layer are connected to the common input terminal pad and the output terminal pad, respectively.   8. The compound semiconductor switch circuit device according to claim 7, wherein the conductive region is provided apart from the first metal layer.   8. The compound semiconductor switch circuit device according to claim 7, wherein the conductive region is provided in contact with the first metal layer.   8. The compound semiconductor switch circuit device according to claim 7, wherein a part of the connection means is configured by another conductive region provided from the first main surface to the second main surface.   12. The compound semiconductor switch circuit device according to claim 11, wherein the conductive region is disposed between the adjacent first metal layer and the other conductive region.   8. The compound semiconductor switch circuit device according to claim 7, wherein the connecting means is a control resistor that connects the control terminal pad and a gate of the switching element.   The compound semiconductor switch circuit device according to claim 7, wherein the via hole is filled with the metal layer.   8. The compound semiconductor switch circuit device according to claim 7, wherein a high-frequency analog signal propagates to the common input terminal pad.   A third via hole reaching from the first main surface to the second main surface; a third metal layer provided on a side wall of the third via hole and connected to the control terminal pad; The compound semiconductor switch circuit device according to claim 7, wherein the conductive region is arranged between the adjacent first metal layers.

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