JP2007199859A - Data transfer system - Google Patents

Abstract

An object of the present invention is to provide a data transfer system capable of improving data transfer performance between subsystems while suppressing an increase in circuit scale and a decrease in operating frequency as much as possible.
A data transfer system includes: a first crossbar switch connected to a plurality of masters; a second crossbar switch connected to a plurality of slaves; and a first crossbar switch and a second crossbar switch. A first data transfer path that couples the first data transfer path and a second data transfer path that is provided in parallel with the first data transfer path and that couples between the first crossbar switch and the second crossbar switch, One crossbar switch is configured so that at least one of the plurality of slaves can dynamically select one of the first and second data transfer paths as an access path according to a request. It is characterized by that.
[Selection] Figure 6

Description

  The present invention generally relates to a data transfer system, and more particularly to a data transfer system using a crossbar switch.

  The system LSI is configured by combining a plurality of circuit modules having different functions such as a CPU and a memory module and mounting them on a single chip. In the system LSI, circuit modules are connected by a system bus.

  FIG. 1 is a diagram showing a typical configuration example of circuit module connection by a system bus. In FIG. 1, the master modules 101 to 103 serving as system masters such as a CPU, a DMA (Dynamic Memory Access) controller, a DSP (Digital Signal Processor), etc., and various memory interfaces and USB (Universal Serial Bus) functions are realized. Slave modules 104 to 106 are provided as slaves. The master modules 101 to 103 and the slave modules 104 to 106 are connected by a system bus 111. On the system bus 111, only one data transfer can be executed at the same time.

  In the system bus configuration as shown in FIG. 1, when the data transfer performance of the system LSI is to be improved, the system bus 111 portion may hinder the improvement of the system performance. For example, when the master module 101 tries to access the slave module 106 and the master module 102 tries to access the slave module 104 at the same time, only one data can be transferred on the system bus 111 at the same time. The other transfer is stopped until the transfer ends, and the transfer performance deteriorates. This is called “bus right competition”. In order to improve the data transfer performance of the entire system, it is necessary to have a system configuration in which there is little competition for bus rights.

  There is a crossbar switch circuit as a system bus configuration for avoiding the above-mentioned bus contention. FIG. 2 is a diagram illustrating a typical configuration example of circuit module connection by a crossbar switch. In FIG. 2, the master modules 201 to 203 and the slave modules 204 to 206 are connected by a crossbar switch 251. The crossbar switch 251 includes interfaces 211 to 216. Interfaces 211 to 213 are connected to master modules 201 to 203, and interfaces 214 to 216 are connected to master modules 204 to 206. By configuring the system bus connection to be switchable by these interfaces 211 to 216, for example, data transfer from the master module 201 to the slave module 205 and data transfer from the master module 202 to the slave module 204 can be executed simultaneously. Is possible.

  FIG. 3 is a diagram showing a general configuration example of a bus bridge circuit assuming an AHB (Advanced High-performance Bus) protocol of the AMBA (Advanced Microcontroller Bus Architecture) standard. In FIG. 3, the crossbar switch 251 is connected to three master modules 201 to 203 and three slave modules 204 to 206 via buses 221 to 226 including address signal lines, data signal lines, and control signal lines. Yes. Similarly, the interfaces 211 to 216 are connected by a bus 263 including an address signal line, a data signal line, and a control signal line. In the buses 221 to 226 and 263, solid lines represent signals that flow from the master direction to the slave direction (for example, address signals, write data signals, control signals, etc.), and broken lines represent bus signals that flow from the slave direction to the master direction (for example, read). Data signal, response signal, etc.).

  The interfaces 211 to 213 select I / F control circuits 284 to 286 that control bus signals from the master module, address decoders 281 to 283 that decode address signals on the bus, read data signals, response signals, and the like. Selection circuits 287 to 289 are included. The I / F control modules 284 to 286 monitor control signals transmitted from the master module to the bus 263. When a control signal for requesting bus transfer is detected in a situation where a new transfer cannot be sent to the bus, the I / F control modules 284 to 286 detect response signals (for the buses 221 to 223 that suppress the issuance of new transfer to the bus). (Broken line) is returned to the master module. The I / F control modules 284 to 286 further have a function of temporarily holding the current bus value.

  Address decoders 281 to 283 decode address data on the bus according to the address map. The address decoders 281 to 283 send a transfer request signal 261 to the access destination interfaces 214 to 216 indicated by the address data according to the decoding result. The selection circuits 287 to 289 select a data signal, a response signal, and the like from the access destination indicated by the address data according to the decoding results of the address decoders 281 to 283.

  On the other hand, the interfaces 214 to 216 include arbitration circuits 291 to 293 and selection circuits 294 to 296. The arbitration circuits 291 to 293 receive the transfer request signal 261 from the interfaces 211 to 213 and return a transfer enable / disable response signal 262 indicating transfer permission / non-permission to the interfaces 211 to 213 and select a signal indicating the arbitration result as a selection circuit. 294-296. The selection circuits 294 to 296 select a bus signal in accordance with the arbitration results from the arbitration circuits 291 to 293.

  When the circuit configuration using the crossbar switch described above is used, bus contention does not occur, so that the data transfer performance is improved as a whole system. That is, for example, even when the master module 201 tries to access the slave module 206 and the master module 202 tries to access the slave module 204 at the same time, the data transfer paths are overlapped because a plurality of buses are provided in parallel. No bus right conflicts occur.

  In recent years, the scale of LSIs has increased, and the number of modules connected to the crossbar switch has increased, and it has been required to keep the system operating frequency high. In such a circuit, the circuit configuration of the crossbar switch as shown in FIG. 3 is not always effective, and an increase in the number of modules may cause a reduction in data performance of the entire system.

  For example, in order to prevent any bus contention from occurring among a plurality of master modules, it is necessary to provide the same number of parallel buses as the number of master modules in the crossbar switch. Since a set of buses is composed of a large number of wires such as data lines, address lines, and control lines, a crossbar switch circuit including a large number of buses requires a large number of wires when LSI is mounted. Therefore, when the number of modules increases, the wiring arrangement restriction inside the LSI becomes severe, and as a result, the LSI circuit area increases and the operating frequency decreases, and the data transfer performance of the entire system decreases.

  There is a configuration using a bus bridge as a configuration that realizes a situation in which bus right contention hardly occurs while preventing an increase in circuit area. FIG. 4 is a diagram showing a typical configuration example of circuit module connection by a crossbar switch using a bus bridge.

  The system shown in FIG. 4 is divided into two sub-systems, and includes a first sub-system composed of master modules 301 to 303 and a slave module 305, and a master module 304 and slave modules 306-308. A second subsystem is provided. The crossbar switch 351 of the first subsystem and the crossbar switch 352 of the second subsystem are coupled by a single bus bridge 331. Reference numerals 311 to 315 and 321 to 325 are interfaces. This configuration is disclosed in Patent Document 1, for example.

  The configuration shown in FIG. 4 has an advantage that transfer performance can be kept high while suppressing an increase in circuit area. For example, for data transfer within each subsystem, not only does bus contention not occur, but data transfer via the bus bridge 331 can be performed simultaneously. Thus, while keeping the transfer performance high by avoiding bus contention at a certain level, the circuit area is increased without providing bus wiring for all combinations between the plurality of master modules and the plurality of slave modules. Can be suppressed.

  However, the portion of the bus bridge 331 that connects the two crossbar switches 351 and 352 regulates the data transfer performance of the entire system, which may cause a problem when the number of modules connected to the crossbar switch increases. is there. For example, when a transfer that needs to maintain a certain level of data transfer performance, such as data transfer such as image processing, sound processing, and communication processing, is performed via the bus bridge 331, the bus bridge is single. Therefore, if a bus right conflict occurs with another transfer, the data transfer performance may not be satisfied.

FIG. 5 is a diagram showing a configuration of an address map when viewed from the master 301 in the configuration of FIG. As shown in FIG. 5, the slaves 306 to 308 can be accessed only via the bus bridge 331. That is, the address range 0xFFFF5001 to 0xFFFF8000 of the slaves 306 to 308 is assigned to the bus bridge 331. Therefore, for example, when the master 301 tries to access the slave 306 and the master 302 tries to access the slave 307, bus contention for the bus bridge 331 occurs.
JP 2000-339269 A JP 2001-197228 A JP-A-11-110342

  In view of the above, an object of the present invention is to provide a data transfer system capable of improving data transfer performance between subsystems while suppressing an increase in circuit scale and a decrease in operating frequency as much as possible.

  A data transfer system includes a first crossbar switch connected to a plurality of masters, a second crossbar switch connected to a plurality of slaves, and between the first crossbar switch and the second crossbar switch. A first data transfer path to be coupled, and a second data transfer path that is provided in parallel with the first data transfer path and couples between the first crossbar switch and the second crossbar switch, The first crossbar switch can dynamically select one of the first and second data transfer paths as an access path for at least one of the plurality of slaves according to a request. It is comprised by this.

  According to at least one embodiment of the present invention, in the data transfer system, the first crossbar switch and the second data transfer path are provided by providing multiple data transfer paths of the first data transfer path and the second data transfer path. The data transfer performance between the crossbar switches can be improved. That is, data transfer can be executed simultaneously in parallel via multiple data transfer paths. In addition, by configuring the first crossbar switch so that at least one of the slaves can be accessed through a data transfer path that is dynamically selected according to a request among multiple data transfer paths, Data transfer performance can be improved by improving the flexibility and flexibility of data transfer while suppressing an increase in circuit area.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 6 is a diagram showing a basic configuration of a system using a crossbar switch and bus bridge configuration according to the present invention. In the present invention, the number of modules having the configuration shown in FIG. 6, the number of crossbar switches, the number of bus bridges, the number of subsystems, etc. are examples, and are not limited to the numbers shown here.

  In the configuration shown in FIG. 6, the master modules 401 to 403 and the slave module 405 are connected to the crossbar switch 451, and the master module 404 and the slave modules 406 to 408 are connected to the crossbar switch 452. The crossbar switch 451 and the crossbar switch 452 are connected to each other by multiple bus bridges 431 and 432. The crossbar switch 451 includes interfaces 411 to 416, and the crossbar switch 452 includes interfaces 421 to 426.

  By providing the multiple bus bridges 431 and 432, the data transfer performance between the crossbar switch 451 and the crossbar switch 452 is improved. For example, if the bus bridge 431 is used for data transfer to the slave 406 and the bus bridge 432 is used for data transfer to the slave 407 and the slave 408, these data transfers should be executed simultaneously in parallel. Can do. Note that which of the two bus bridges 431 and 432 is used for data transfer is determined by an address decoder inside the crossbar switch.

  FIG. 7 is a diagram showing an example of the configuration of the address map when viewed from the master 401, 402, or 403 in the configuration of FIG. In the example illustrated in FIG. 7, the slave 406 can be accessed only via the bus bridge 431. That is, the address range 0xFFFF5001 to 0xFFFF6000 of the slave 406 is assigned to the bus bridge 431. The slaves 407 and 408 can be accessed only via the bus bridge 432. That is, the address range 0xFFFF 6001 to 0xFFFF 8000 of the slaves 407 and 408 is assigned to the bus bridge 432.

  Therefore, in the example shown in FIG. 7, the bus bridge 431 is used for data transfer from the master 401 to the slave 406, and the bus bridge 432 is used for data transfer from the master 402 to the slave 408. Transfers can be performed concurrently in parallel. However, even if an attempt is made to transfer data from the master 401 to the slave 407 and simultaneously an attempt to transfer data from the master 402 to the slave 408, bus contention occurs in the bus bridge 432. In such a case, for example, if the data transfer to the slave 408 is a high-priority data transfer that requires a high transfer capability, there is a problem.

  In consideration of such a case, in the present invention, at least one of the slave modules 406 to 408 is connected to the multiple bus bridges 431 and 432 via a bus bridge that is dynamically selected according to a request. The crossbar switch 451 is configured to be accessible. This improves the degree of freedom and flexibility of data transfer and increases data transfer performance.

  In order to configure at least one of the slave modules 406 to 408 to be accessible via a bus bridge dynamically selected according to a request from among the multiple bus bridges 431 and 432, the present invention is provided. Then, the configuration of the first embodiment or the configuration of the second embodiment is used. In the configuration of the first embodiment, the decoder inside the crossbar switch is configured to be dynamically changeable. In the second embodiment, the arbitration circuit unit in the crossbar switch is configured to dynamically assign multiple bus bridges in response to a data transfer request.

  First, the first embodiment will be described. In the first embodiment, bus bridges connecting a plurality of crossbar switches constituting the system LSI are multiplexed so that one bus bridge of the multiplexed bus bridges is dedicated to data transfer for a specific address area. The decoder inside the crossbar switch is dynamically changed. As a result, it is possible to eliminate bus contention and achieve high data transfer performance for data transfer with high priority that particularly requires high transfer capability.

  FIG. 8 is a diagram showing a first embodiment of a system using a crossbar switch and bus bridge configuration according to the present invention.

  In the configuration shown in FIG. 8, master modules 501 to 503 and decoder control module 505 are connected to crossbar switch 551, and master module 504 and slave modules 506 to 508 are connected to crossbar switch 552. The crossbar switch 551 and the crossbar switch 552 are connected to each other by multiple bus bridges 531 and 532. The crossbar switch 551 includes interfaces 511 to 516, and the crossbar switch 552 includes interfaces 521 to 526.

  The decoder control module 505 is a module accessible from a master module such as a CPU. In response to an instruction from the master module, the decoder control module 505 transmits a mode signal 571 for dynamically changing the decoder in the crossbar switch.

  FIG. 9 is a diagram illustrating an example of the configuration of the crossbar switch 551 in FIG. 9, the same components as those of FIG. 8 are referred to by the same numerals, and a description thereof will be omitted.

  The crossbar switch 551 shown in FIG. 9 includes three master modules 501 to 503, a decoder control module 505, and bus bridges 531 and 532 via buses 621 to 626 including address signal lines, data signal lines, and control signal lines. It is connected to the. Similarly, the interfaces 511 to 516 are connected by a bus 663 including an address signal line, a data signal line, and a control signal line. Note that in the buses 621 to 626 and 663, solid lines represent signals that flow from the master direction to the slave direction (for example, address signals, write data signals, control signals, etc.), and broken lines represent bus signals that flow from the slave direction to the master direction (for example, read). Data signal, response signal, etc.).

  Interfaces 511 to 513 receive I / F control circuits 684 to 686 that control bus signals from the master module, controllable address decoders 681 to 683 that decode address signals on the bus, read data signals, response signals, and the like. Selection circuits 687 to 689 for selecting are included. The I / F control modules 684 to 686 monitor control signals transmitted from the master module to the bus 663. When a control signal for requesting bus transfer is detected in a situation where a new transfer cannot be sent to the bus, the I / F control modules 684 to 686 detect response signals (for the buses 621 to 623 to suppress the issuance of new transfer to the bus). (Broken line) is returned to the master module. The I / F control modules 684 to 686 further have a function of temporarily holding the current bus value.

  FIG. 10 is a diagram illustrating an example of the configuration of the I / F control module 684. 10, the same components as those of FIG. 9 are referred to by the same numerals, and a description thereof will be omitted. Although the configuration of the I / F control module 684 is shown as a representative example, the I / F control modules 685 and 686 also have the same configuration.

  The I / F control module 684 includes a bus transfer / holding determination circuit 1104, a selection circuit 1105, and a bus holding register 1106. The bus transfer / holding determination circuit 1104 observes control signals flowing through the buses 621, 662, and 663. When a control signal for requesting bus transfer is detected on the bus 621 in a situation where a new transfer cannot be sent to the bus 663, the bus transfer / holding determination circuit 1104 outputs a signal 1136 and inhibits the bus 621 from issuing a new transfer The response signal to be transmitted is transmitted via the combinational circuit 1107. Further, the bus transfer / holding determination circuit 1104 causes the selection circuit 1105 to select the bus holding register 1106 via the signal 1138. The bus holding register 1106 holds the current bus value, and the value of the bus 663 is held as it is by the selection operation.

  When the bus 621 detects a control signal for requesting bus transfer in a situation where it is appropriate to transfer the data to the bus 663 appropriately, the bus transfer / holding determination circuit 1104 causes the selection circuit 1105 to select the bus 621 via the signal 1138. As a result, the bus 621 and the bus 663 are connected to enable new data transfer. Following the change in the value of the bus 663, the latest value of the bus 663 is stored in the bus holding register 1106.

  Referring again to FIG. 9, controllable address decoders 681 to 683 decode address data on the bus according to the address map. The controllable address decoders 681 to 683 send a transfer request signal 661 to the access destination interfaces 514 to 516 indicated by the address data according to the decoding result. The selection circuits 687 to 689 select a data signal, a response signal, and the like from the access destination indicated by the address data according to the decoding result of the controllable address decoders 681 to 683.

  On the other hand, the interfaces 514 to 516 include arbitration circuits 691 to 693 and selection circuits 694 to 696. Arbitration circuits 691 to 693 receive transfer request signals 661 from the interfaces 511 to 513 and return transfer enable / disable response signals 662 indicating transfer permission / non-permission to the interfaces 511 to 513 and select signals indicating arbitration results as selection circuits. 694-696. The selection circuits 694 to 696 select a bus signal according to the arbitration result by the arbitration circuits 691 to 693.

  The crossbar switch 551 shown in FIG. 9 operates in the same way as a conventional crossbar switch circuit, but is configured such that the controllable address decoders 681 to 683 can change the address decode setting. As a result, the address decoding setting can be dynamically switched even while the system is operating. Specifically, the controllable address decoders 681 to 683 respond to the mode signal 571 supplied from the decoder control module 505 at an appropriate timing based on the monitoring of the bus transfer in the crossbar switch, and the address map of the address decoder. Convert.

  FIG. 11 is a diagram showing an example of the configuration of the controllable address decoder 681 together with the peripheral configuration. In FIG. 11, the same components as those of FIG. 9 are referred to by the same numerals, and a description thereof will be omitted. The configuration of the controllable address decoder 681 is shown as a representative example, but the controllable address decoders 682 and 683 have the same configuration.

  The decoder control module 505 includes a bus interface 1002 and a mode setting register 1003. A value set in the mode setting register 1003 by the bus master via the bus 624 and the bus interface 1002 is supplied to the controllable address decoder 681 as a mode signal 571. The controllable address decoder 681 includes a selection circuit 1015, a register 1016, a bus observation circuit 1017 for observing a bus control signal 1039 and a bus response signal 1037, a plurality of address decoders 1018 to 1020 incorporated as a circuit, and a plurality of address decoders. A selection circuit 1021 for selecting one of the two.

  FIG. 12 is a diagram illustrating an example of an address map viewed from the masters 501 to 503. FIG. 13 is a flowchart illustrating an example of an address map switching control operation. The operation of changing the address mapping configuration from the address map 1 (left of the drawing) to the address map 2 (right of the drawing) according to the control flow of FIG. 13 will be described below.

  In the state of the address map 1 which is an initial state, data transfer from the crossbar switch 551 area to the crossbar switch 552 area is set to be executed via the bus bridge 531 for any address. From this state, the control operation of FIG. 13 is started.

In step S1, the master 501 shown in FIG. 9 sets a mode number of a desired address map (address map after switching) in the mode setting register 1003 of the decoder control module 505. In step S2, the decoder control module 505 sends the mode signal 571 to the controllable address decoders 681, 682 and 683 inside the bus bridge. In step S3, the controllable address decoder 681 sends the control signal on the bus 663 to the bus observation circuit. Observe (monitor) at 1017. In step S4, it is determined whether there is data transfer on the bus based on the observation result in step S3. If there is data transfer (Yes in step S3), after waiting for a predetermined time, it is determined again whether there is data transfer on the bus.

  If there is no data transfer (No in step S3), one of the address decoders 1018 to 1020 is selected by the selection circuit 1021 in accordance with the mode signal in step S4. Specifically, the selection circuit 1015 selects the mode signal 571 from the decoder control module 505 in accordance with the signal 1042 from the bus observation circuit 1017 and supplies it to the selection circuit 1021. As a result, a decoder corresponding to the mode signal 571 is selected. The mode signal 571 used for selection is stored in the register 1016. The stored value of the register 1016 is steadily supplied to the selection circuit 1021 when the selection circuit 1015 then selects the register 1016. With the above operation, the address map in the interface 511 is switched from the address map 1 to the address map 2 (see FIG. 12).

  Similarly, with respect to the other controllable address decoders 682 and 683, the address map is switched from the address map 1 to the address map 2 at a timing when there is no data transfer on the bus. In step S5, it is determined whether or not the address map has been switched for all controllable address decoders 681, 682 and 683. If it has not been switched (No in step S5), it waits until all switching is completed.

  In the case of Yes in step S5, all of the controllable address decoders 681 to 683 are set in the new address map 2. That is, as described in step S6, in the address map 2, the bus bridge 532 is assigned exclusively for data transfer to the slave 508, so that bus contention does not occur for data transfer to the slave 508. Therefore, even if the data transfer to the slave 508 is a high-priority data transfer that requires a high transfer capability, the necessary data transfer performance can be maintained.

  When the address map 2 shown in FIG. 12 is set by the address map switching described above, the slave 508 can be handled as if it were a slave module directly connected to the crossbar switch 551. Therefore, it is possible to continue to maintain the data transfer quality (QoS: quality of service) even for high-priority data transfer requiring particularly high transfer capability.

  In the above description, an address map is prepared and set so that there is no bus right conflict for the slave 508. Similarly, an address map is prepared and set for other slave modules so that there is no bus right conflict. Is possible. In this way, it is possible to eliminate bus contention for data transfer to a specific slave module in accordance with system requirements and to maintain data transfer quality.

  The second embodiment of the present invention will be described below. In the second embodiment, the arbitration circuit unit in the crossbar switch is configured to dynamically allocate multiple bus bridges in response to a data transfer request.

  In other words, the bus bridge connecting the two crossbar switches constituting the system LSI is multiplexed, and the arbitration circuit unit inside the crossbar switch is configured so that a plurality of data can be transferred simultaneously to the multiplexed bus bridge. As a result, particularly for high-priority data transfer that requires high transfer capacity, bus contention can be minimized and data transfer performance can be maintained.

  FIG. 14 is a diagram showing a second embodiment of the system using the crossbar switch and bus bridge configuration according to the present invention.

  In the configuration shown in FIG. 14, the master modules 801 to 803 and the slave module 805 are connected to the crossbar switch 851, and the master module 804 and the slave modules 806 to 808 are connected to the crossbar switch 852. The crossbar switch 851 and the crossbar switch 852 are connected to each other by multiple bus bridges 831 and 832. The crossbar switch 851 includes interfaces 811 to 815, and the crossbar switch 852 includes interfaces 821 to 826.

  In the crossbar switch 851, the interfaces 811 to 813 are connected to the master modules 801 to 803, respectively, and the interface 814 is connected to the slave module 805. An interface 815 is connected to both the bus bridges 831 and 832.

  As described above, in the configuration of FIG. 14, two buses (bus bridges 831 and 832) are provided by one interface 815. As described below, the bus use right acquisition request for the two buses (bus bridges 831 and 832) is arbitrated by one arbitration circuit provided in the interface 815.

  FIG. 15 is a diagram showing a configuration of an address map when viewed from the master 801 in the configuration of FIG. As shown in FIG. 15, the slaves 806 to 808 can be accessed via any of the bus bridges 831 and 832. That is, the address ranges 0xFFFF 5001 to 0xFFFF 8000 of the slaves 806 to 808 are assigned to the bus bridges 831 and 832 in a multiple manner.

  For example, consider a case where a master 801 attempts to access a slave 806 and a master 802 attempts to access a slave 807. In this case, for example, a bus bridge 831 is assigned to access to the slave 806 and a bus bridge 832 is assigned to access to the slave 807, for example, so that access operations can be executed in parallel without bus contention with each other. become.

  FIG. 16 is a diagram illustrating an example of the configuration of the crossbar switch 851 in FIG. In FIG. 16, the same components as those of FIG. 14 are referred to by the same numerals, and a description thereof will be omitted.

  The crossbar switch 851 shown in FIG. 16 is connected to three master modules 801 to 803, a slave module 805, and bus bridges 831 and 832 via buses 921 to 926 including address signal lines, data signal lines, and control signal lines. It is connected. Similarly, the interfaces 811 to 815 are connected by a bus 963 including an address signal line, a data signal line, and a control signal line. Note that in the buses 921 to 926 and 963, a solid line represents a signal (for example, an address signal, a write data signal, or a control signal) that flows from the master direction to the slave direction, and a broken line represents a bus signal (for example, a read signal) that flows from the slave direction to the master direction. Data signal, response signal, etc.).

  The interfaces 811 to 813 select I / F control circuits 984 to 986 that control bus signals from the master module, address decoders 981 to 983 that decode address signals on the bus, read data signals, response signals, and the like. Selection circuits 987 to 989 are included. The I / F control modules 984 to 986 monitor control signals transmitted from the master module to the bus 963. When a control signal for requesting bus transfer is detected in a situation where a new transfer cannot be sent to the bus, the I / F control modules 984 to 986 detect response signals (for the buses 921 to 923 to suppress the issuance of new transfer to the bus). (Broken line) is returned to the master module. The I / F control modules 984 to 986 further have a function of temporarily holding the current bus value.

  Address decoders 981 to 983 decode address data on the bus according to the address map. The address decoders 981 to 983 send a transfer request signal 961 to the access destination interface 814 or 815 indicated by the address data in accordance with the decoding result. Selection circuits 987 to 989 select a data signal, a response signal, and the like from the access destination indicated by the address data in accordance with the decoding results of address decoders 981 to 983.

  The interface 814 includes an arbitration circuit 991 and a selection circuit 994. The arbitration circuit 991 receives the transfer request signal 961 from the interfaces 811 to 813 and returns a transfer enable / disable response signal 962 indicating transfer permission / non-permission to the interfaces 811 to 813, and sends a signal indicating the arbitration result to the selection circuit 994. Supply. The selection circuit 994 selects a bus signal according to the arbitration result by the arbitration circuit 991.

  The interface 815 includes an arbitration circuit 992 and selection circuits 995, 996. The arbitration circuit 992 receives the transfer request signal 961 from the interfaces 811 to 813 and returns a transfer enable / disable response signal 962 indicating transfer permission / non-permission to the interfaces 811 to 813, and receives a signal indicating the arbitration result as a selection circuit 995. 996. The selection circuits 995 and 996 select the bus signal according to the arbitration result by the arbitration circuit 992.

  FIG. 17 is a flowchart showing an example of the arbitration operation of the arbitration circuit for the multiple bus bridge. With the arbitration operation shown in FIG. 17, the arbitration circuit 992 shown in FIG. 16 assigns data transfer to the bus bridges 831 and 832.

  First, in step S1, a new transfer request signal 961 is supplied from the address decoders 981 to 983. In step S2, the arbitration circuit 992 determines the occupation status of the buses 925 and 926. If both buses 925 and 926 are in use, the process proceeds to step S3. In step S3, the arbitration circuit 992 sends a transfer standby signal as a transfer enable / disable response signal 962 that is a response to the new transfer request signal 961. Thereafter, the process returns to step S1.

  If one of the buses 925 and 926 is in use as a result of the determination in step S2, the process proceeds to step S4. In step S <b> 4, the arbitration circuit 992 transmits a transfer request permission signal as a transfer enable / disable response signal 962 that is a response to the new transfer request signal 961 for a new access with the highest priority. Further, the arbitration circuit 992 sends a transfer standby signal as a transfer enable / disable response signal 962 for other new access requests.

  As a result of the determination in step S2, if both buses 925 and 926 are available, the process proceeds to step S5. In step S5, the arbitration circuit 992 accepts a transfer request as a transfer enable / disable response signal 962 that is a response to the new transfer request signal 961 for the new access having the highest priority and the second highest access. Is sent out. Further, the arbitration circuit 992 sends a transfer standby signal as a transfer enable / disable response signal 962 for other new access requests.

  After the arbitration operation in either step S4 or S5, the data transfer operation is executed in step S6. After the data transfer operation, the process returns to step S1.

  As described above, in the second embodiment, by using the crossbar switch 851 in which the arbitration circuit 992 is mounted, the data transfer via the bus bridges 831 and 832 can be performed simultaneously up to two data transfers in parallel. Become executable. Accordingly, in the data transfer via the bus bridges 831 and 832, the possibility of bus contention can be suppressed to a certain low level. Therefore, it is relatively easy to maintain data transfer quality (QoS: quality of service) even for data transfer that requires high transfer capability.

  As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.

  For example, a bus bridge is a term that generally refers to a circuit that performs protocol conversion. However, in this application, a bus bridge circuit is not necessary if protocol conversion is not required between subsystems. That is, when protocol conversion between subsystems is not necessary, in the description of the above embodiments, the data transfer path via the bus bridge circuit can be replaced with a data transfer path between subsystems by simply connecting the system bus directly. .

  The crossbar switch may also be referred to by various different names such as, for example, a cross bus switch, a bus matrix, a multi-layer bus, an interconnect, and a bus switch. In the present invention, the crossbar switch may be any circuit that can set a plurality of data transfer paths in parallel between a plurality of modules by making the path selectable, and has a specific structure specified by a specific name. It is not intended to have a circuit.

It is a figure which shows the typical structural example of the circuit module connection by a system bus | bath. It is a figure which shows the typical structural example of the circuit module connection by a crossbar switch. It is a figure which shows the general structural example of the bus bridge circuit supposing the AHB protocol of AMBA standard. It is a figure which shows the typical structural example of the circuit module connection by the crossbar switch using a bus bridge. FIG. 5 is a diagram showing a configuration of an address map when viewed from a master in the configuration of FIG. 4. It is a figure which shows the basic composition of the system using the crossbar switch and bus bridge structure by this invention. It is a figure which shows an example of a structure of the address map at the time of seeing from a master in the structure of FIG. It is a figure which shows the 1st Example of the system using the crossbar switch and bus bridge structure by this invention. It is a figure which shows an example of a structure of a crossbar switch. It is a figure which shows an example of a structure of an I / F control module. It is a figure which shows an example of a structure of a controllable address decoder with a periphery structure. It is a figure which shows an example of address map switching. It is a flowchart which shows an example of the control operation of address map switching. It is a figure which shows the 2nd Example of the system using the crossbar switch and bus bridge structure by this invention. It is a figure which shows the structure of the address map at the time of seeing from a master in the structure of FIG. It is a figure which shows an example of a structure of a crossbar switch. It is a flowchart which shows an example of the arbitration operation | movement of the arbitration circuit with respect to a multiplex bus bridge.

Explanation of symbols

401-404 Master module 405-408 Slave module 411-416, 421-426 Interface 431, 432 Bus bridge 451, 452 Crossbar switch 501-504 Master module 505 Decoder control module 506-508 Slave module 511-516 Interface 521-526 interface 531,532 Bus bridge 551,552 Crossbar switch 681-683 Controllable address decoder 684-686 I / F control circuit 687-689 Selection circuit 691-693 Arbitration circuit 694-696 Selection circuit

Claims (5)

A first crossbar switch connected to a plurality of masters;
A second crossbar switch connected to the plurality of slaves;
A first data transfer path coupling between the first crossbar switch and the second crossbar switch;
A second data transfer path that is provided in parallel with the first data transfer path and connects between the first crossbar switch and the second crossbar switch; Data configured so that at least one of the slaves can dynamically select one of the first and second data transfer paths as an access path in response to a request Transfer system.   2. The data transfer system according to claim 1, wherein each of the first data transfer path and the second data transfer path includes a bus bridge.   The first crossbar switch includes a controllable address decoder that determines an access destination by decoding addresses supplied from the plurality of masters according to address mapping, and the address mapping in the controllable address decoder is in response to the request. The data transfer system according to claim 1, wherein the data transfer system is configured to be dynamically changeable. The controllable address decoder
A plurality of different address decoder circuits corresponding to a plurality of different address mappings;
4. The data transfer system according to claim 3, further comprising a selection circuit that selects one of the plurality of address decoder circuits in response to the request. The first crossbar switch is
An arbitration circuit that arbitrates data transfer requests supplied from the plurality of masters as the request;
2. The data transfer according to claim 1, further comprising a selection circuit that dynamically and selectively couples the plurality of masters and the first and second data transfer paths in accordance with an arbitration result by the arbitration circuit. system.

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