JP2007194955A - Image processing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable a high-speed dithering processing from a plurality of directions, corresponding to parallel line processing for high-speed processing. <P>SOLUTION: The image processing device includes a plurality of address counter control sections 50 for counting the synchronizing signals in an individual main scanning direction and a sub-scanning direction of a plurality of divided image data, a plurality of threshold table control sections 51 each outputting a threshold for an individual dither matrix of each of the plurality of divided image data from a threshold table, based on the values respectively counted in the plurality of address counter control sections 50, and a plurality of comparison circuits 52 performing a dither processing by comparing each of the plurality of divided image data with the threshold generated from each of the plurality of threshold tables. The address counter control sections 50 count according to each main scanning processing direction of the plurality of image data, and the threshold table control sections 51 perform the main scanning processing according to the dither size so as to maintain the continuity of the processing on the boundary of the divided image data. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an image processing apparatus for dithering image data, and is particularly suitable for an image forming apparatus such as a copying machine, a printer, and a facsimile.

In an image processing apparatus that is applied to an image forming apparatus such as a copying machine, a printer, or a facsimile, and performs dither processing of image data, when controlling input image data, sub-scanning indicates an image range in the sub-scanning direction and the main scanning direction, respectively. This is performed based on the range signal, the main scanning range signal, and the main scanning synchronization signal indicating the starting point in the main scanning direction.
This operation will be described with reference to an overview of the digital copying machine shown in FIG. 9 and a side view of the reading optical system shown in FIG.
The document on the document table 1 shown in FIGS. 9 and 10 is set so that the reading surface faces downward, and is illuminated by the light source 2. The reflected light is successively converged and reflected through the mirror 3 and the lens and relay mirror group 4 and is read by an image line sensor (hereinafter referred to as CCD) 5.

11 and 12 show the relationship between the data read on the document table and the image control signal.
In FIG. 11, the sub-scanning range signal (FGATE) is a signal indicating the image range in the scanning direction of the light source 2 and the mirror 3 in FIG. 10, that is, the sub-scanning direction, and the main scanning synchronization signal (LSYNC) is the CCD 5 in FIG. The main scanning synchronization signal indicates the starting point of the line in the reading direction, that is, the main scanning direction, and the main scanning range signal (LGATE) is a signal indicating the image range in the main scanning direction.
As shown in FIG. 12, the reading of the original in the main scanning direction is performed by the CCD 5 for each line (line1, line2, line3) in the main scanning direction.
The temporal relationship among these sub-scanning range signal (FGATE), main scanning synchronization signal (LSYNC), and main scanning range signal (LGATE) is as shown in FIG. 13, and the two-dimensional document image data is represented on the time axis. Processing is performed by replacing with image data.

FIG. 14 is a block diagram showing the overall configuration of a digital copying machine as an image forming apparatus.
In FIG. 14, the CPU 10 governs overall instructions, and sends processing and setting instructions to each block. The image data read by the CCD 5 is first sent to the scanner 11 and A / D conversion is performed to correct the scanner characteristics. Next, after predetermined image quality processing such as dithering and error diffusion is performed in the image processing unit 12, it is output in accordance with the image format of the lower block and sent to the image storage unit 13.
The image storage unit 13 has a temporary memory area for image editing for at least one copy output paper (hereinafter referred to as transfer paper) and a large-capacity storage medium such as a hard disk (HD). Image data can be stored, and a compression / decompression function of image data is provided to further increase the storage amount of image information. The printer 14 receives the image data from the image storage unit 13 and outputs it to transfer paper.

FIG. 15 is a block diagram showing the configuration of the image processing unit 12.
In FIG. 15, the γ correction processing unit 20 adjusts density modulation of image quality through a plurality of conversion tables stored in advance in a storage area such as a RAM. The dither processing unit 21 performs halftone processing with an emphasis on gradation while reducing the quantization level of one pixel (one dot) using a plurality of reference tables. The error diffusion processing unit 22 performs processing for preserving the density by distributing the error generated when the quantization level is lowered during the surrounding quantization. The output selection unit 23 selects input image data from the error diffusion processing unit 22 or the dither processing unit 21 and outputs the selected image data to the image storage unit 13.

FIG. 16 is a block diagram showing the configuration of the γ correction processing unit 20.
For example, in order to γ-convert 8-bit image data, the data selection unit 30 is brought down to the CPU address side in advance by a download switching signal, the chip select and write enable of the RAM 31 are activated, and addresses 0 to 255 of the RAM 31 are activated. In the normal operation, the data selection unit 30 is switched to the input image data side by the download switching signal to obtain the address of the RAM 31, and the data output for the address is taken out as the data after the γ conversion. With this configuration, by downloading various data from the CPU 10 to the RAM 31 before the γ conversion processing, γ conversion corresponding to the output request can be performed.

FIG. 17 is a block diagram showing the configuration of the error diffusion processing unit 22.
The error adder 40 receives the input image data DFij having the number of gradations M (M is a natural number) to be processed and the peripheral error information E of DFij from the error calculator 41, and sums them to obtain N The input pixel data SFij after error correction having the number of gradations (N ≦ M natural number) is output. The quantization unit 42 receives the input pixel data SFij after error correction and the quantization threshold value TFij that matches the number of quantizations received from the CPU 10 (N bits for input image data M bits, but M> N), Gradation processing is performed and output image data GFij is output. The error calculation unit 43 receives the input pixel data SFij after error correction and the output image data GFij, and obtains a quantization error EFij when the input image data DFij is quantized. The quantization error EFij is written / read out to / from a storage element such as a line memory in the error matrix storage unit 44. The error calculation unit 41 generates an error diffusion matrix having a shape as shown in FIG. 18 obtained from the error matrix storage unit 44, and calculates peripheral error information E of the input image data DFij to be processed pixels according to each matrix coefficient. .

In the case of an error matrix and its coefficients as shown in FIG. 18, the peripheral error information E for the pixel of interest Dij is
E = (Di-2, j-1 + 2 * Di-1, j-1 + 4 * Di, j-1 + 2 * Di + 1, j-1 + Di + 2, j-1 + 2 * Di-2, j + 4 * Di-1, j) / 16
Given in.

FIG. 19 is a block diagram showing the configuration of the dither processing unit 21.
In FIG. 19, the address counter control unit 50 receives xlgate and xfgate, which are image data control signals, and counts the main scanning side and the sub-scanning side. The count value is sent to the threshold table control unit 51. hand over. Here, the count value in the main scanning and sub-scanning directions indicates the position of the corresponding image data.
As shown in the dither matrix example shown in FIG. 20, the threshold table control unit 51 selects a matrix according to the size of the selected threshold table, for example, 4 × 4, 6 × 6, 8 × 8, etc. Then, by comparing with the count value in the main scanning / sub-scanning direction received from the address counter control unit 50, threshold data matching the position of the image data to be processed is selected from the matrix and sent to the comparison circuit 52.

For example, when a 4 × 4 matrix as shown in FIG. 20A is selected, the threshold value of the head line is aa → ab → ac → ad → aa → ab → ac → ad → in the main scanning direction. The threshold value is repeated in the flow of aa → ab →... and the leading pixel in the main scanning direction is aa → ba → ca → da → aa → ba → ca → da → aa → ba →. The threshold is repeated in the flow.
In this example, a binarization process is performed in which quantization is performed with a single threshold value. However, it is possible to perform a multi-value process by performing quantization with a matrix having a plurality of threshold value tables. Is disclosed. Patent Document 2 discloses speeding up by parallel processing.
JP-A-10-173925 JP 2000-244738

  In recent years, with an increase in processing capability and an increase in copy speed of an image forming apparatus such as a copying machine, an increase in clock speed, which is a reference time for processing, has become severe. Along with this, the image data format in image processing and the relationship between the image data synchronization signal and the image data are improved, and the quantization number of the image data is reduced so that a plurality of pixels are bundled (packed). By processing, processing for a plurality of pixels is executed at a time, and image processing speed is being improved by performing parallel processing.

However, Patent Document 1 does not describe improvement in processing speed by parallel processing, and Patent Document 2 describes speeding up by parallel processing. It has become.
The present invention has been made in view of the above-described points, and provides an image processing apparatus capable of speeding up dither processing from a plurality of directions in response to line parallel processing for speeding up. With the goal. It is another object of the present invention to provide an image processing apparatus that can easily prevent a failure in which processing mismatch occurs at a boundary surface where processing from a plurality of directions collides.

  In order to achieve the above object, an invention according to claim 1 is an image processing apparatus for dithering each image data in which one line is divided into a plurality of lines, and each main scanning direction of the divided plurality of image data. And a plurality of counting means for counting synchronization signals in the sub-scanning direction, and threshold values for individual dither matrices of the plurality of divided image data based on values counted by the plurality of counting means, respectively. A plurality of threshold value table control means for outputting from a threshold value table, and each of the divided plurality of image data is compared with a threshold value generated by each of the plurality of threshold value tables, and is dithered. A plurality of comparison units, wherein the counting unit counts the plurality of image data according to each main scanning processing direction, and controls the threshold value table. Stage and performing main scanning process in accordance with the dither size to maintain the continuity of the process in the boundary of the image data of the divided.

According to a second aspect of the present invention, in the image processing apparatus according to the first aspect, the set main scanning effective area setting is compared with the selected threshold value table, and the image data on the front side in the main scanning direction is compared with the image data. It is characterized by comprising counter initial value setting means for controlling the address counter so that the dither matrices at the point where the image data on the rear end side in the main scanning direction are merged.
According to a third aspect of the present invention, in the image processing apparatus according to the second aspect, the counter initial value setting means compares the set sub-scanning effective area setting with the selected threshold value table, and The address counter is controlled so that the dither matrix at the point where the image data on the front end side in the scanning direction and the image data on the rear end side in the sub-scanning direction coincide with each other.

According to the present invention, the counting means counts according to the main scanning processing direction of each of the plurality of image data, and the threshold value table is maintained so that the processing continuity at the boundary line of the divided image data is maintained. By setting the number of main scanning processes according to the dither size, it is possible to increase the speed of the dither process from different directions from a high speed.
Further, according to the present invention, the counter initial value setting means compares the set main scanning effective area setting with the selected threshold value table, and compares the image data at the leading end in the main scanning direction with the trailing end in the main scanning direction. Control the address counter so that the dither matrices match at the point where the image data on the side meet, or compare the set sub-scanning effective area setting with the selected threshold value table to check the sub-scanning direction By controlling the address counter so that the dither matrix coincides at the point where the image data on the front end side and the image data on the rear end side in the sub-scanning direction merge, the boundary surface where the processing from multiple directions contacts It is possible to prevent inconsistencies in processing.

Hereinafter, embodiments of the image processing apparatus of the present invention will be described.
When reading an image at high speed, as shown in FIGS. 9 and 10, the document is set on the document table 1 so that the reading surface faces downward and is illuminated by the light source 2. Then, the reflected light is successively converged and reflected through the mirror 3 and the lens and relay mirror group 4 and read by the CCD 5. Here, in order to increase the reading speed in an image forming apparatus such as a copying machine, it is possible to read a line at double speed by arranging two CCDs 5 in the opposite direction.
FIG. 1 and FIG. 2 are diagrams showing the relationship between the data read on the document table of the image forming apparatus provided with the image processing apparatus of this embodiment and the image control signal.
FIGS. 1 and 2 show the relationship between the data read on the document table and the image control signal when one line is divided into two in the main scanning direction.

In FIG. 1, the sub-scanning effective area (hereinafter referred to as “xfgate”) is a signal representing the image range in the scanning direction of the light source 2 and the mirror 3 shown in FIG. Hereinafter, “xflsync”) and a main scanning synchronization signal (hereinafter referred to as xllsync) are signals indicating the reading direction of the CCD 5 shown in FIG. 10, that is, a starting point of a line in the main scanning direction. The “xflgate”) and main scanning effective area (hereinafter referred to as “xlgate”) are signals indicating the image range in the main scanning direction.
However, in the present embodiment, since one scan line is divided into a plurality of parts by the CCD, in FIG. 2 showing an example in which the main scan line is divided into two, the first half line (F side) and the second half line (L side) are two. Image data is generated in opposite directions.
In reading the original in the main scanning direction, as shown in FIG. 3, the CCD 5 scans the lines A and C on the F side, the line F, and the lines B, D and F on the L side separately. Become.

FIG. 4 is a diagram showing the configuration of the dither processing unit as the first embodiment of the present invention.
Note that the image processing apparatus of the present invention is characterized by the configuration of the dither processing unit, and the other configurations are the same as those of the image processing device shown in FIGS. 15 to 18. Therefore, in the present embodiment, the configuration of the dither processing unit. Only will be described.
The dither processing unit shown in FIG. 4 shows a case where one line is divided into two parts on the F side and the L side as shown in FIGS.
The dither processing unit 21 shown in FIG. 4 includes an F-side dither processing unit 21F and an L-side dither processing unit 21L. The F-side dither processing unit 21F and the L-side dither processing unit 21L have the same configuration as the dither processing unit shown in FIG. 19, and are respectively address counter control units 50F and 50L and threshold value table control units 51F and 51L. And comparison circuits 52F and 52L.

The address counter control units 50F and 50L receive xlgate and xfgate, which are control signal groups for image data, respectively, perform counting for the main scanning side and the sub-scanning side, and use the count values as threshold table control units 51F and 51L. To pass.
Here, the count values in the main scanning direction and the sub-scanning direction indicate the position of the corresponding image data. As shown in the dither matrix example in FIG. 20, the threshold value table control units 51F and 51L are arranged in a matrix according to the size of the selected threshold value table, for example, 4 × 4, 6 × 6, 8 × 8, etc. Select. However, since the threshold values of the L-side dither processing unit 21L and the F-side dither processing unit 21F are opposite, the actual contents of the table are reversed.

  The threshold value table control units 51F and 51L are compared with the count values in the main scanning / sub-scanning directions received from the respective address counter control units 50F and 50L, and the threshold value data matches the position of the image data to be processed. Are selected from the matrix and sent to the respective comparison circuits 52F and 52L. For example, when a 4 × 4 matrix is selected, the threshold value of the head line is a flow of aa → ab → ac → ad → aa → ab → ac → ad → aa → ab → in the main scanning direction. The value is repeated, and the first pixel in the main scanning direction repeats the threshold in the sub-scanning direction in the order of aa → ba → ca → da → aa → ba → ca → da → aa → ba →.

Further, when processing is performed with the 4 × 4 dither matrix, the necessary count value is repeated in the size of 4 × 4 in the main scanning / sub-scanning direction, which is the matrix size, so that the address counter control units 50F and 50L The counter to count does not need to handle the actual position of the image data, and it is sufficient if the pixel position of the data corresponding to the dither matrix is relatively indicated.
The comparison circuits 52F and 52L compare the input image data with the threshold values received from the respective threshold value table control units 51F and 51L, and divide the input image data into cases where the input image data is greater than the threshold value and cases where the input image data is not. The output value is judged to be “1” or “0” and output. In this embodiment, the binarization process in which quantization is performed with one threshold value has been described as an example. However, if a matrix having a plurality of threshold value tables is prepared, multilevel processing can be performed. .

Further, in the case of the first embodiment shown in FIG. 4, the structures of the F-side dither processing unit 21F and the L-side dither processing unit 21L are not changed, and the ease of design is to create one dither processing unit. No change. However, the table matrix stored in the threshold value table control units 51F and 51L is reversed so as to obtain a mirror image in advance because the process is reversed. Alternatively, when the same data is input, the address counter control units 50F and 50L decrement on the L side to realize the same processing.
In addition, in order to continuously perform dither processing on images processed in parallel in the main scanning direction, it is a condition that the continuity of the dither matrix is maintained at the boundary of each processing. In other words, when using a 4 × 4 dither matrix, the length of xflgate in the main scanning direction is a multiple of 4, so that the top pixel of each divided process coincides with the top of the dither matrix on the main scanning side. In the case of 6 × 6, the length needs to be a multiple of 6, and in the case of 8 × 8, the length needs to be a multiple of 8.

FIG. 5 is a diagram showing a configuration of a dither processing unit as a second embodiment of the present invention. In addition, the same code | symbol is attached | subjected to the same site | part as FIG. 4, and detailed description is abbreviate | omitted.
The dither processing unit 21 shown in FIG. 5 is different from the dither processing unit shown in FIG. 4 in that a counter initial value determination unit 53 is provided in the L-side dither processing unit 21L.
In this case, the counter initial value determination unit 53 of the L-side dither processing unit 21L compares the main scanning effective area setting set by the CPU 10 with the selected threshold value table, and the main scanning front end side (F side) The address counter is controlled so that the dither matrices match at the point where the main scanning rear end side (L side) processes merge. For example, if the number of main scanning pixels is designated as 7000 pixels and a 6 × 6 dither matrix is selected, 7000/6 = 1166, and the remainder is 4, so the data of the dither matrix on both sides of F / L are merged In point, the address counter on the L side is advanced by the number of remainder / 2. As a result, the continuity of the matrix at the junction is maintained. Actually, the realization method by the counter initial value determination unit 53 can be practiced not only on the L side but also on the F side.

  Further, as a method of not using the counter initial value determination unit 53, a method of directly substituting the initial value into the address counter control unit 50 by the CPU 10, or not simply inverting the threshold value table and putting it on the L side, is shifted. If the amount is also set, smooth dither processing can be realized even at the dividing boundary surface.

Next, a third embodiment of the present invention will be described.
FIG. 6 is a two-dimensional representation of an image in which image data is stored in a memory, and shows an example of how to read the image for image processing. FIG. 7 shows the read procedure shown in FIG. It is the figure which showed the relationship with the control signal at the time of processing the read image data.
When the image data is stored in the memory as shown in FIG. 6, it is not affected by the reading device structure, and can be freely selected from where the image data is taken from, so the first line side (U side) It is possible to simultaneously read from not only from but also from the last line side (D side).

FIG. 8 is a diagram illustrating a configuration of a dither processing unit according to the third embodiment. The same parts as those in FIGS. 4 and 5 are denoted by the same reference numerals, and detailed description thereof is omitted.
In the dither processing unit 21 shown in FIG. 8, the U side can be read simultaneously from not only the first line side (U side) but also the last line side (D side) so that the image data shown in FIG. 7 can be received. In addition to the dither processing units 21UF and 21UL, the D-side dither processing units 21DF and 21DL are provided. As a result, it is possible to further increase the speed.
In this case, in the D-side dither processing units 21DF and 21DL, in order to maintain boundary continuity with respect to the U-side dither processing units 21UF and 21UL, an initial value determination that also performs initial value determination on the sub-scanning side in addition to main scanning is performed. By providing the sections 53DF and 53DL, it is possible to perform dither processing simultaneously with the main scanning and the sub scanning, and to increase the speed.

The figure which showed the relationship between a manuscript and a control signal. The figure which showed the specific example of the image scanning of a digital copying machine in case one line is divided into 2 in the main scanning direction. The figure which showed the timing relationship between image data and each control signal. The figure which showed the structure of the dither processing part as the 1st Embodiment of this invention. The figure which showed the structure of the dither processing part as the 2nd Embodiment of this invention. FIG. 10 is a diagram illustrating a specific example of image scanning of a digital copying machine according to a third embodiment. The figure which showed the timing relationship of the image data and each control signal in 3rd Embodiment. The figure which showed the structure of the dither processing part as the 3rd Embodiment of this invention. The figure which showed an example of the general view of a digital copying machine. The side view of a reading optical system. Diagram showing relationship between manuscript and control signal The figure which showed the specific example of the image scanning of a digital copying machine. The figure which showed the timing relationship of the synchronizing signal group. The figure which showed the structural example of the whole block of a digital copying machine. The block diagram which showed the structure of the image process part. The block diagram which showed the structure of the gamma correction process part. The block diagram which showed the structure of the error diffusion process part. The figure which showed the example of an error diffusion matrix. The block diagram which showed the structure of the dither processing part. The figure which showed an example of the dither matrix.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Original plate, 2 ... Light source, 3 ... Mirror, 4 ... Mirror group, 5 ... CCD, 10 ... CPU, 11 ... Scanner, 12 ... Image processing part, 13 ... Image storage part, 14 ... Printer, 20 ... Correction process , 21 ... dither processing unit, 22 ... error diffusion processing unit, 23 ... output selection unit, 30 ... data selection unit, 31 ... RAM, 40 ... error addition unit, 41 ... error calculation unit, 42 ... quantization unit, 43 ... Error calculation unit, 44 ... Error matrix storage unit, 50 ... Address counter control unit, 51 ... Threshold table control unit, 52 ... Comparison circuit, 53 ... Counter initial value determination unit

Claims (3)

  An image processing apparatus for dithering each image data obtained by dividing one line into a plurality of pieces, and a plurality of counting means for counting individual main scanning direction and sub-scanning direction synchronization signals of the plurality of divided image data And a plurality of threshold value table control means for outputting threshold values for individual dither matrices of the plurality of divided image data from the threshold value table based on the values counted by the plurality of counting means, respectively. And a plurality of comparison means for dithering each of the divided plurality of image data by comparing with each of the threshold values generated by each of the plurality of threshold value tables, Counting is performed in accordance with the main scanning processing direction of each of the plurality of image data, and the threshold value table control means is arranged at the boundary line of the divided image data. The image processing apparatus characterized by performing the main scanning process in accordance with the dither size to keep the physical continuity.   2. The image processing apparatus according to claim 1, wherein the set main scanning effective area setting is compared with the selected threshold value table to compare the image data on the leading end side in the main scanning direction and the image on the trailing end side in the main scanning direction. An image processing apparatus comprising counter initial value setting means for controlling an address counter so that dither matrices coincide at the point where data merge.   3. The image processing apparatus according to claim 2, wherein the counter initial value setting means compares the set sub-scanning effective area setting with the selected threshold value table, An image processing apparatus which controls an address counter so that dither matrices coincide at a point where image data on the rear end side in the sub-scanning direction merge.

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