JP2007179041A - Semiconductor device, display device, and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device which can suppress variations in current value caused by the variations in the threshold voltage of the transistor, has small deviations from the luminance specified by the video signal, and has high duty ratio. <P>SOLUTION: A load, a transistor which controls a current value supplied to the load, a capacitor, a power supply line, and first to third switches are provided. After the threshold voltage of the transistor has been held by the capacitor, a potential corresponding to a video signal is input, and a voltage that is the sum of the threshold voltage and the potential is held. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device provided with a function of controlling a current supplied to a load with a transistor, and includes a pixel formed of a current-driven display element whose luminance changes according to a signal, a signal line driving circuit for driving the pixel, The present invention relates to a display device including a scan line driver circuit. Further, the present invention relates to the driving method. The present invention also relates to an electronic device having the display device in a display portion.

  2. Description of the Related Art In recent years, a self-luminous display device using a light emitting element such as an electroluminescence (EL) pixel, that is, a so-called light emitting device has attracted attention. As light-emitting elements used in such self-luminous display devices, organic light-emitting diodes (OLEDs) and EL elements are attracting attention and have been used for EL displays and the like. Yes. Since these light emitting elements emit light by themselves, the visibility of pixels is higher than that of a liquid crystal display, and a backlight is unnecessary. In addition, there are advantages such as a high response speed. Note that the luminance of a light emitting element is often controlled by the value of a current flowing through the light emitting element.

  In addition, an active matrix display device in which a transistor for controlling light emission of a light emitting element is provided for each pixel is being developed. Active matrix display devices not only enable high-definition and large-screen display, which is difficult with passive matrix display devices, but also operate with lower power consumption than passive matrix display devices. Yes.

  FIG. 46 shows a pixel configuration of a conventional active matrix display device (Patent Document 1). The pixel shown in FIG. 46 includes a thin film transistor (TFT) 11, a TFT 12, a capacitor element 13, and a light emitting element 14, and is connected to a signal line 15 and a scanning line 16. Note that a power supply potential Vdd is supplied to one of the source and drain electrodes of the TFT 12 and one electrode of the capacitor 13, and a ground potential is supplied to the counter electrode of the light emitting element 14.

  At this time, when amorphous silicon is used for the TFT 12 that controls the current value supplied to the light emitting element, that is, the semiconductor layer of the driving TFT, the threshold voltage (Vth) varies due to deterioration or the like. In this case, even though the same potential is applied to the different pixels from the signal line 15, the current flowing through the light emitting element 14 is different for each pixel, and the displayed luminance is nonuniform among the pixels. Note that even when polysilicon is used for the semiconductor layer of the driving TFT, the characteristics of the transistor deteriorate or vary.

  In order to improve this problem, Patent Document 2 proposes an operation method using the pixel of FIG. The pixel shown in FIG. 47 includes a transistor 21, a driving transistor 22 that controls a current value supplied to the light emitting element 24, a capacitor 23, and a light emitting element 24. The pixel is connected to the signal line 25 and the scanning line 26. ing. Note that the driving transistor 22 is an NMOS transistor, and a ground potential is supplied to either the source electrode or the drain electrode of the driving transistor 22, and Vca is supplied to the counter electrode of the light emitting element 24.

  A timing chart in the operation of this pixel is shown in FIG. In FIG. 48, one frame period is divided into an initialization period 31, a threshold (Vth) writing period 32, a data writing period 33, and a light emitting period 34. Note that one frame period corresponds to a period during which an image for one screen is displayed, and the initialization period, the threshold (Vth) writing period, and the data writing period are collectively referred to as an address period.

  First, in the threshold writing period 32, the threshold voltage of the driving transistor 22 is written into the capacitor. Thereafter, in the data writing period 33, a data voltage (Vdata) indicating the luminance of the pixel is written into the capacitor, and Vdata + Vth is accumulated in the capacitor. In the light emission period, the driving transistor 22 is turned on, and the light emitting element 24 is turned on with the luminance specified by the data voltage by changing Vca. By such an operation, variation in luminance due to variation in the threshold value of the driving transistor is reduced.

Also in Patent Document 3, the voltage obtained by adding the data potential to the threshold voltage of the driving TFT becomes the gate-source voltage, and the flowing current does not change even when the threshold voltage of the TFT fluctuates. It is disclosed.
JP-A-8-234683 JP 2004-295131 A JP 2004-280059 A

  In any case, the operation methods described in Patent Documents 2 and 3 perform the above-described initialization, threshold voltage writing, and light emission by changing the potential of Vca to several degrees per frame period. It was. In these pixels, one electrode of the light emitting element to which Vca is supplied, that is, the counter electrode is formed in the entire pixel region. Therefore, in addition to initialization and threshold voltage writing, data writing operation is performed. If even one pixel is present, the light emitting element cannot emit light. Therefore, as shown in FIG. 49, the ratio of the light emission period in one frame period (that is, the duty ratio) becomes small.

  When the duty ratio is low, it is necessary to increase a current value flowing through the light emitting element and the driving transistor, so that a voltage applied to the light emitting element increases and power consumption increases. In addition, since the light emitting element and the driving transistor are likely to be deteriorated, more electric power is required to obtain the same luminance as that before the deterioration.

  In addition, since the counter electrode is connected to all pixels, the light-emitting element functions as an element having a large capacitance. Therefore, high power consumption is required to change the potential of the counter electrode.

  In view of the above problems, an object of the present invention is to provide a display device with low power consumption and high duty ratio. It is another object of the present invention to obtain a pixel structure, a semiconductor device, and a display device with little deviation from the luminance specified by the data potential.

  Note that the present invention is not limited to a display device including a light-emitting element, and an object of the present invention is to suppress variation in current value caused by variation in threshold voltage of a transistor. Therefore, the destination to which the current controlled by the driving transistor is supplied is not limited to the light emitting element.

  One embodiment of the present invention includes a pixel including a transistor, a first switch, and a second switch, and one of a source electrode and a drain electrode of the transistor is connected to a gate of the transistor through the first switch. The other of the source electrode and the drain electrode of the transistor is electrically connected to the pixel electrode, and the other of the source electrode and the drain electrode of the transistor is electrically connected to the second switch. The semiconductor device is characterized in that a signal in accordance with the gradation of the pixel is input to the gate electrode of the transistor.

  One embodiment of the present invention includes a storage capacitor, a transistor, a first switch, a second switch, and a third switch, and one of the source electrode and the drain electrode of the transistor is connected to the first wiring. The other of the source electrode and the drain electrode of the transistor is electrically connected to the pixel electrode, and the other of the source electrode and the drain electrode of the transistor is connected to the second wiring through the third switch. The transistor is electrically connected, the gate electrode of the transistor is electrically connected to a third wiring via the first switch, and the gate electrode of the transistor is electrically connected to the first wiring via the second switch. And the other of the source electrode and the drain electrode of the transistor is electrically connected to the gate electrode through the storage capacitor. Which is a semiconductor device to be.

  One embodiment of the present invention includes a capacitor, a transistor, a first switch, a second switch, and a third switch, and one of the source electrode and the drain electrode of the transistor is connected to the first wiring. The other of the source electrode and the drain electrode of the transistor is electrically connected to the pixel electrode, and the other of the source electrode and the drain electrode of the transistor is connected to the second wiring through the third switch. The transistor is electrically connected, the gate electrode of the transistor is electrically connected to a third wiring via the first switch, and the gate electrode of the transistor is electrically connected to the first wiring via the second switch. And the other of the source electrode and the drain electrode of the transistor is electrically connected to the gate electrode through the capacitor. Which is a semiconductor device to be.

  One embodiment of the present invention includes a transistor, a capacitor, a first switch, a second switch, a third switch, and a fourth switch, and one of the source electrode and the drain electrode of the transistor Is electrically connected to the first wiring through the fourth switch, the other of the source electrode and the drain electrode of the transistor is electrically connected to the pixel electrode, and the other of the source electrode and the drain electrode of the transistor Is electrically connected to the second wiring through the third switch, and the gate electrode of the transistor is electrically connected to the third wiring through the first switch. Is electrically connected to the first wiring through the second switch, and the other of the source electrode and the drain electrode of the transistor is connected to the front through the capacitor. Is a semiconductor device according to claim which is electrically connected to the gate electrode.

  One embodiment of the present invention includes a transistor, a capacitor, a first switch, a second switch, a third switch, and a fourth switch, and one of the source electrode and the drain electrode of the transistor Is electrically connected to the first wiring, the other of the source electrode and the drain electrode of the transistor is electrically connected to the pixel electrode through the fourth switch, and the other of the source electrode and the drain electrode of the transistor Is electrically connected to the second wiring through the fourth switch and the third switch, and the gate electrode of the transistor is electrically connected to the third wiring through the first switch. The gate electrode of the transistor is electrically connected to the first wiring through the second switch, and the other of the source electrode and the drain electrode of the transistor is Is a semiconductor device which is characterized in that through the serial fourth switch and said capacitor element is electrically connected to the gate electrode.

  The second wiring may be the same as the wiring that controls the third switch.

  The second wiring may be any one of scanning lines for controlling the first to third switches in the previous row or the next row.

  The transistor may be an N-channel transistor. The semiconductor layer of the transistor may be formed of an amorphous semiconductor film. Furthermore, the semiconductor layer of the transistor may be made of amorphous silicon.

  The semiconductor layer of the transistor may be formed of a crystalline semiconductor film.

  In the above invention, the potential input to the first wiring is a binary value of V1 or V2, and takes the value of V2 only when the first switch to the third switch are in a non-conductive state, and V1 is The potential may be higher than the potential input to the second wiring, the difference may be larger than the threshold voltage of the transistor, and V2 may be higher than V1.

  The transistor may be a P-channel transistor. In that case, in the above invention, the potential input to the first wiring takes a binary value of V1 or V2, and is the value of V2 only when the first switch to the third switch are non-conductive. , V1 is a potential lower than the potential input to the second wiring, the difference is larger than the absolute value of the threshold voltage of the transistor, and V2 is a value lower than V1. Good.

  One embodiment of the present invention is a transistor in which one of a source electrode and a drain electrode is electrically connected to a first wiring and the other of the source electrode and the drain electrode is electrically connected to a second wiring; A storage capacitor for holding a gate-source voltage and a first potential input to the first wiring are applied to the gate electrode of the transistor, and a second potential input to the second wiring is Means for applying a first voltage to the storage capacitor by applying to the source electrode of the transistor; means for discharging the voltage of the storage capacitor to a second voltage; and a third voltage at the first potential. Is applied to the gate electrode of the transistor, a fifth voltage obtained by adding the second voltage and the fourth voltage is held in the storage capacitor, and the first wiring is connected to the first wiring. The first potential is a semiconductor device characterized by having a means for providing the current set by the transistor to a load by inputting a different third potential.

  One embodiment of the present invention is a transistor in which one of a source electrode and a drain electrode is electrically connected to a first wiring and the other of the source electrode and the drain electrode is electrically connected to a second wiring; A storage capacitor for holding a gate-source voltage and a first potential input to the first wiring are applied to the gate electrode of the transistor, and a second potential input to the second wiring is Applying to the source electrode of the transistor, means for holding the first voltage in the holding capacitor, means for discharging the voltage of the holding capacitor to the threshold voltage of the transistor, and the first potential to the first potential. 2 is applied to the gate electrode of the transistor, and a fourth voltage obtained by adding the threshold voltage of the transistor and the third voltage is held in the storage capacitor. And a means for supplying a current set to the transistor to a load by inputting a third potential different from the first potential to the first wiring. It is.

  The transistor may be an N-channel transistor. The semiconductor layer of the transistor may be formed of an amorphous semiconductor film. Furthermore, the semiconductor layer of the transistor may be made of amorphous silicon.

  The semiconductor layer of the transistor may be formed of a crystalline semiconductor film.

  In the above invention, the first potential is higher than the second potential, the difference is larger than the threshold voltage of the transistor, and the first potential is lower than the third potential. It may be characterized by a value.

  The transistor may be a P-channel transistor. In this case, the first potential is lower than the second potential, the difference is larger than the absolute value of the threshold voltage of the transistor, and the first potential is the third potential. It may be characterized by a higher value.

  Another embodiment of the present invention is a display device including the above-described semiconductor device. In addition, the electronic device includes the display device in a display portion.

  Note that the switch described in the specification is not particularly limited to an electrical switch or a mechanical switch as long as the current flow can be controlled. It may be a transistor, a diode, or a logic circuit combining them. In the case where a transistor is used as a switch, the transistor operates as a mere switch, and thus the polarity (conductivity type) of the transistor is not particularly limited. However, it is desirable to use a transistor having a polarity with a smaller off-state current. As a transistor with low off-state current, there are a transistor provided with an LDD region and a transistor having a multi-gate structure. When the transistor operates as a switch with the source electrode potential close to a low potential power source (Vss, GND, 0 V, etc.), the N channel type is used. On the contrary, the source electrode potential is high potential. When operating in a state close to the side power supply (Vdd or the like), it is desirable to use a P-channel type. This is because the absolute value of the voltage between the gate and the source can be increased, so that it can easily operate as a switch. Note that both N-channel and P-channel switches may be used as CMOS switches.

  In the present invention, being connected is synonymous with being electrically connected. Therefore, another element, a switch, or the like may be disposed between them.

  The load may be anything. For example, EL media (organic EL devices, inorganic EL devices or EL devices containing organic and inorganic materials), light-emitting devices such as electron-emitting devices, liquid crystal devices, electronic ink, and other display media whose contrast changes due to electromagnetic action Can be applied. Note that examples of a display device using an electron-emitting device include a field emission display (FED), a SED type flat display (SED: Surface-conduction Electron-emitter Display), and the like. There is electronic paper as a display device using electronic ink.

  In the present invention, there are no limitations on the types of transistors that can be used, and the transistor is formed using a thin film transistor (TFT) using a non-single-crystal semiconductor film typified by amorphous silicon or polycrystalline silicon, a semiconductor substrate, or an SOI substrate. Transistors, MOS transistors, junction transistors, bipolar transistors, transistors using organic semiconductors or carbon nanotubes, and other transistors can be used. There is no limitation on the kind of the substrate over which the transistor is provided, and the transistor can be provided on a single crystal substrate, an SOI substrate, a glass substrate, a plastic substrate, or the like.

  As described above, the transistor in the present invention may be any type of transistor and may be formed on any substrate. Therefore, the entire circuit may be formed on a glass substrate, may be formed on a plastic substrate or a single crystal substrate, may be formed on an SOI substrate, or on any substrate. It may be formed. Alternatively, a part of the circuit may be formed on a certain substrate, and another part of the circuit may be formed on another substrate. That is, all of the circuits may not be formed on the same substrate. For example, part of a circuit is formed using a TFT over a glass substrate, another part of the circuit is formed over a single crystal substrate, and the IC chip is connected with COG (Chip On Glass) to form glass. You may arrange | position on a board | substrate. Alternatively, the IC chip may be connected to the glass substrate using TAB (Tape Automated Bonding) or a printed board.

  In the present specification, one pixel represents a color element. Therefore, in the case of a full-color display device composed of R (red), G (green), and B (blue) color elements, one pixel is any one of the R color element, the G color element, and the B color element. It shall be said.

  Note that in this specification, the pixels are arranged in a matrix, not only in the case of a so-called grid pattern in which vertical stripes and horizontal stripes are combined, but also in full-color display with three color elements (for example, RGB). When performing the above, the case where pixels of three color elements representing the minimum element of one image are arranged in a so-called delta arrangement is also included. Further, the size of the pixel may be different for each color element.

  Note that in this specification, a semiconductor device refers to a device having a circuit including a semiconductor element (such as a transistor or a diode). The display device is not only a display panel body in which a plurality of pixels including a load and a peripheral drive circuit for driving these pixels are formed on a substrate, but also a flexible printed circuit (FPC) and a printed wiring board (PWB). ) Is also included.

  According to the present invention, variation in current value due to variation in threshold voltage of transistors can be suppressed. Therefore, a desired current can be supplied to a load such as a light emitting element. In particular, when a light-emitting element is used as a load, a display device with little variation in luminance and a high duty ratio can be provided.

  Hereinafter, one embodiment of the present invention will be described. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of the embodiment. Note that in the structures of the present invention described below, the same reference numerals are used in common in different drawings.

(Embodiment 1)
The basic configuration of the pixel of the present invention will be described with reference to FIG. The pixel illustrated in FIG. 1 includes a transistor 111, a first switch 112, a second switch 113, a third switch 114, a capacitor 115, and a light-emitting element 116. Note that the pixel is connected to the signal line 117, the first scan line 118, the second scan line 119, the third scan line 120, the power supply line 121, and the potential supply line 122. In this embodiment, the transistor 111 is an N-channel transistor and is turned on when its gate-source voltage (Vgs) exceeds a threshold voltage (Vth). The pixel electrode of the light emitting element 116 is an anode, and the counter electrode 123 is a cathode. Note that the gate-source voltage of the transistor is Vgs, the drain-source voltage is Vds, the threshold voltage is Vth, the voltage accumulated in the capacitor element is Vcs, a power supply line 121, a potential supply line 122, a signal line 117 is also referred to as a first wiring, a second wiring, and a third wiring, respectively.

  The first electrode (one of the source electrode and the drain electrode) of the transistor 111 is connected to the pixel electrode of the light-emitting element 116, the second electrode (the other of the source electrode and the drain electrode) is connected to the power supply line 121, and the gate The electrode is connected to the power supply line 121 via the second switch 113. The gate electrode of the transistor 111 is also connected to the signal line 117 through the first switch 112, and the first electrode is also connected to the potential supply line 122 through the third switch 114.

  Further, the capacitor 115 is connected between the gate electrode of the transistor 111 and the first electrode. That is, the first electrode of the capacitor 115 is connected to the gate electrode of the transistor 111, and the second electrode is connected to the first electrode of the transistor 111. The capacitor 115 may be formed by sandwiching an insulating film with a wiring, a semiconductor layer, or an electrode, or may be omitted using the gate capacitance of the transistor 111. A means for holding these voltages is called a holding capacitor.

  Note that by inputting signals to the first scanning line 118, the second scanning line 119, and the third scanning line 120, the first switch 112, the second switch 113, and the third switch 114 are turned on and off, respectively. Is controlled.

  A signal in accordance with the gradation of a pixel corresponding to a video signal, that is, a potential corresponding to luminance data is input to the signal line 117.

  Next, the operation of the pixel shown in FIG. 1 will be described with reference to the timing chart of FIG. 2 and FIG. In FIG. 2, one frame period corresponding to a period for displaying an image for one screen is divided into an initialization period, a threshold writing period, a data writing period, and a light emission period. The initialization period, threshold write period, and data write period are collectively referred to as an address period. There is no particular limitation on the period of one frame, but it is preferable to set it to at least 1/60 second or less so that a person viewing the image does not feel flicker.

  Note that a potential of V1 is input to the counter electrode 123 of the light-emitting element 116, and a potential of V1-Vth-α (α: an arbitrary positive number) is input to the potential supply line 122. The power supply line 121 is supplied with a potential of V1 during the address period and V2 during the light emission period. However, V2> V1.

Here, in order to explain the operation, the potential of the counter electrode 123 of the light-emitting element 116 is the same as the potential of the power supply line 121 in the address period, but at least a potential difference necessary for the light-emitting element 116 to emit light is determined. _Assuming V _EL , the potential of the counter electrode 123 only needs to be higher than the potential of V 1 −Vth−α−V _EL . In addition, the potential V2 of the power supply line 121 in the light emission period may be a value larger than a value obtained by adding the potential of the counter electrode 123 and at least the potential difference (V _EL ) necessary for the light emitting element 116 to emit light. Here, for the sake of explanation, the potential of the counter electrode 123 is V1, so that V2 may be larger than V1 + _VEL .

  First, as shown in FIGS. 2A and 3A, in the initialization period, the first switch 112 is turned off, and the second switch 113 and the third switch 114 are turned on. At this time, the first electrode of the transistor 111 serves as a source electrode, and the potential thereof is equal to that of the potential supply line 122, so that V1−Vth−α. On the other hand, the potential of the gate electrode is V1. Therefore, the gate-source voltage Vgs of the transistor 111 is Vth + α, and the transistor 111 is turned on. Then, Vth + α is held in the capacitor 115 provided between the gate electrode and the first electrode of the transistor 111. That is, the potential supply line 122 only needs to have a potential at which the transistor 111 is turned on, and the third switch 114 has a function of selecting whether to supply a potential at which the transistor 111 is turned on to the first electrode of the transistor. I need it.

  Next, in the threshold writing period illustrated in FIGS. 2B and 3B, the third switch 114 is turned off. Therefore, the potential of the first electrode or the source electrode of the transistor 111 gradually increases to V1−Vth, that is, when the gate-source voltage Vgs of the transistor 111 reaches the threshold voltage (Vth). 111 becomes a non-conduction state. Therefore, the voltage held in the capacitor 115 is Vth.

In the subsequent data writing period shown in FIGS. 2C and 3C, after the second switch 113 is turned off, the first switch 112 is turned on, and the signal line 117 responds to the luminance data. A potential (V1 + Vdata) is input. At this time, the voltage Vcs held in the capacitor 115 can be expressed as in Expression (1) when the capacitances of the capacitor 115 and the light emitting element 116 are C1 and C2, respectively.

However, since the light emitting element 116 is thinner than the capacitor 115 and has a larger electrode area, C2 >> C1. Therefore, from C2 / (C1 + C2) ≈1, the voltage Vcs held in the capacitor 115 is expressed by Expression (2), and the transistor 111 is turned on. Note that in the case where a potential of Vdata ≦ 0 is input, a non-conduction state occurs and light emission is not possible.

  Next, in the light emission period shown in FIGS. 2D and 3D, the first switch 112 is turned off and the potential of the power supply line 121 is set to V2. At this time, the gate-source voltage of the transistor 111 is Vgs = Vth + Vdata, and a current corresponding to the voltage flows through the transistor 111 and the light-emitting element 116, so that the light-emitting element 116 emits light.

Note that the current I flowing through the light-emitting element is expressed by Expression (3) when the transistor 111 is operated in the saturation region.

Further, when the transistor 111 is operated in a linear region, the current I flowing through the light emitting element is expressed by Expression (4).

  Here, W is the channel width of the transistor 111, L is the channel length, μ is the mobility, and Cox is the storage capacitance.

  From the equations (3) and (4), the current flowing through the light-emitting element 116 does not depend on the threshold voltage (Vth) of the transistor 111 when the operation region of the transistor 111 is either the saturation region or the linear region. . Accordingly, variation in current value due to variation in threshold voltage of the transistor 111 can be suppressed, and a current value corresponding to luminance data can be supplied to the light-emitting element 116.

  As described above, variation in luminance due to variation in threshold voltage of the transistor 111 can be suppressed. In addition, since the counter electrode is operated at a constant potential, power consumption can be reduced.

Further, when the transistor 111 is operated in the saturation region, variation in luminance due to deterioration of the light-emitting element 116 can be suppressed. When the light-emitting element 116 deteriorates, V _{EL of the} light-emitting element 116 increases, and the potential of the first electrode of the transistor 111, that is, the source electrode increases. At this time, the source electrode of the transistor 111 is connected to the second electrode of the capacitor 115, the gate electrode of the transistor 111 is connected to the first electrode of the capacitor 115, and the gate electrode side is in a floating state. . Therefore, as the source potential increases, the gate potential of the transistor 111 also increases by the same potential. Accordingly, Vgs of the transistor 111 does not change, so that even if the light-emitting element deteriorates, the current flowing through the transistor 111 and the light-emitting element 116 is not affected. Note that also in Equation (3), the current I flowing through the light-emitting element does not depend on the source potential or the drain potential.

  Thus, when the transistor 111 is operated in the saturation region, variation in threshold voltage of the transistor 111 and variation in current flowing in the transistor 111 due to deterioration of the light-emitting element 116 can be suppressed.

  Note that in the case where the transistor 111 is operated in the saturation region, as the channel length L is shorter, a large amount of current tends to flow when the drain voltage is significantly increased due to a breakdown phenomenon.

  When the drain voltage is increased above the pinch-off voltage, the pinch-off point moves to the source side, and the effective channel length that functions as a substantial channel decreases. As a result, the current value increases. This phenomenon is called channel length modulation. Note that the pinch-off point is a boundary where the channel disappears and the channel thickness becomes 0 under the gate, and the pinch-off voltage indicates a voltage when the pinch-off point becomes the drain end. This phenomenon is more likely to occur as the channel length L is shorter. For example, FIG. 5 shows a model diagram of voltage-current characteristics by channel length modulation. In FIG. 5, the channel length L of the transistor is (a)> (b)> (c).

  From the above, when the transistor 111 is operated in the saturation region, if the current I is constant with respect to the drain-source voltage Vds, the influence of deterioration of the light emitting element 116 can be further reduced as described above. The current I with respect to the drain-source voltage Vds is preferably closer to a constant value. Therefore, the channel length L of the transistor 111 is preferably longer. For example, the channel length L of the transistor is preferably larger than the channel width W. The channel length L is preferably 10 μm or more and 50 μm or less, more preferably 15 μm or more and 40 μm or less. However, the channel length L and the channel width W are not limited to this.

  In addition, since a reverse bias voltage is applied to the light-emitting element 116 in the initialization period, a short-circuit portion in the light-emitting element can be insulated and deterioration of the light-emitting element can be suppressed. Therefore, the lifetime of the light emitting element can be extended.

  Note that since variation in current value due to variation in threshold voltage of a transistor can be suppressed, a supply destination of current controlled by the transistor is not particularly limited. Therefore, an EL element (an organic EL element, an inorganic EL element, or an EL element containing an organic substance and an inorganic substance), an electron-emitting element, a liquid crystal element, electronic ink, or the like can be used as the light-emitting element 116 illustrated in FIG.

  The transistor 111 only needs to have a function of controlling a current value supplied to the light-emitting element 116, and the type of the transistor is not particularly limited. Therefore, a thin film transistor (TFT) using a crystalline semiconductor film, a thin film transistor using a non-single crystal semiconductor film typified by amorphous silicon or polycrystalline silicon, a transistor formed using a semiconductor substrate or an SOI substrate, MOS Type transistors, junction type transistors, bipolar transistors, transistors using organic semiconductors or carbon nanotubes, and other transistors can be used.

  The first switch 112 selects a timing at which a signal in accordance with the gradation of the pixel is input to the capacitor, and controls a signal supplied to the gate electrode of the transistor 111. The second switch 113 The timing at which a predetermined potential is applied to the gate electrode is selected and whether or not the predetermined potential is supplied to the gate electrode of the transistor 111 is controlled. The third switch 114 changes the potential written in the capacitor 115. The timing for applying a predetermined potential for initialization is selected, or the potential of the first electrode of the transistor 111 is lowered. Therefore, the first switch 112, the second switch 113, and the third switch 114 are not particularly limited as long as they have the above functions. For example, a transistor or a diode may be used, or a logic circuit combining them may be used. Note that the first to third switches are not particularly required as long as a signal or a potential can be given to the pixel at the above timing. For example, in the case where a signal in accordance with the gray scale of the pixel can be input to the gate electrode of the transistor 111, the first switch 112 is not necessarily provided as illustrated in FIG. The pixel illustrated in FIG. 45 includes a transistor 111, a second switch 113, a third switch 114, and a pixel electrode 4540. A first electrode (one of a source electrode and a drain electrode) of the transistor 111 is connected to the pixel electrode 4540 and the third switch 114, and a gate electrode is connected to the second electrode of the transistor 111 through the second switch 113. It is connected to the electrode. Note that since the gate capacitor 4515 of the transistor 111 is used as a storage capacitor, the capacitor 115 in FIG. 1 is not particularly necessary. Even in such a pixel, each switch is operated in accordance with the timing chart shown in FIG. 2 and a desired potential is supplied to each electrode, so that variation in current value caused by variation in threshold voltage of the transistor 111 can be reduced. Can be suppressed. Therefore, a desired current can be supplied to the pixel electrode 4540.

  Next, FIG. 4 illustrates the case where N-channel transistors are used for the first switch 112, the second switch 113, and the third switch 114. Note that portions common to the configuration in FIG. 1 are denoted by common reference numerals and description thereof is omitted.

  The first switching transistor 412 corresponds to the first switch 112, the second switching transistor 413 corresponds to the second switch 113, and the third switching transistor 414 corresponds to the third switch 114. Note that the channel length of the transistor 111 is preferably longer than the channel length of any of the first switching transistor 412, the second switching transistor 413, and the third switching transistor 414.

  The gate electrode of the first switching transistor 412 is connected to the first scanning line 118, the first electrode is connected to the signal line 117, and the second electrode is the first electrode of the capacitor 115 and the gate of the transistor 111. Connected to the electrode.

  The second switching transistor 413 has a gate electrode connected to the second scan line 119, a first electrode connected to the first electrode of the capacitor 115 and the gate electrode of the transistor 111, and the second electrode The power supply line 121 and the second electrode of the transistor 111 are connected.

  The third switching transistor 414 has a gate electrode connected to the third scanning line 120, and a first electrode connected to the second electrode of the capacitor 115, the first electrode of the transistor 111, and the pixel electrode of the light emitting element 116. The second electrode is connected to the potential supply line 122.

  Each switching transistor is turned on when the signal input to each scanning line is at the H level, and is turned off when the input signal is at the L level.

  One mode of a top view of the pixel shown in FIG. 4 is shown in FIG. The conductive layer 3810 includes a portion that functions as the first scan line 118 and the gate electrode of the first switching transistor 412, and the conductive layer 3811 functions as the signal line 117 and the first electrode of the first switching transistor 412. Including parts. The conductive layer 3812 functions as a portion functioning as the second electrode of the first switching transistor 412, a portion functioning as the first electrode of the capacitor 115, and a first electrode of the second switching transistor 413. Including parts. The conductive layer 3813 includes a portion functioning as a gate electrode of the second switching transistor 413 and is connected to the second scan line 119 through a wiring 3814. The conductive layer 3822 includes a portion functioning as the second electrode of the second switching transistor 413 and a portion functioning as the second electrode of the transistor 111, and is connected to the power supply line 121 through the wiring 3815. The conductive layer 3816 includes a portion functioning as the first electrode of the transistor 111 and is connected to the pixel electrode 3844 of the light-emitting element. The conductive layer 3817 includes a portion functioning as a gate electrode of the transistor 111 and is connected to the conductive layer 3812 through a wiring 3818. In addition, the conductive layer 3819 includes a portion which functions as the third scan line 120 and the gate electrode of the third switching transistor 414. The conductive layer 3820 includes a portion functioning as the first electrode of the third switching transistor 414 and is connected to the pixel electrode 3844. In addition, the conductive layer 3821 including a portion functioning as the second electrode of the third switching transistor 414 is connected to the potential supply line 122 through the wiring 3823.

  Note that portions of each conductive layer functioning as the gate electrode, the first electrode, and the second electrode of the first switching transistor 412 are formed so as to overlap with the semiconductor layer 3833, and thus the second switching transistor The portion functioning as the gate electrode, the first electrode, and the second electrode of the transistor 413 is a portion overlapping with the semiconductor layer 3834, and the gate electrode, the first electrode, and the second electrode of the third switching transistor 414 are formed. The portion functioning as the second electrode is a portion formed so as to overlap with the semiconductor layer 3835. Further, a portion functioning as the gate electrode, the first electrode, and the second electrode of the transistor 111 is a conductive layer portion which overlaps with the semiconductor layer 3836. The capacitor 115 is formed in a portion where the conductive layer 3812 and the pixel electrode 3844 overlap.

  Also in the pixel configuration of FIG. 4, variation in current value due to variation in threshold voltage of the transistor 111 can be suppressed by the same operation method as in FIG. Therefore, a current corresponding to the luminance data can be supplied to the light emitting element 116, and variations in luminance can be suppressed. In addition, when the transistor 111 is operated in the saturation region, variation in luminance due to deterioration of the light-emitting element 116 can be suppressed.

  In addition, since a pixel can be formed using only N-channel transistors, the manufacturing process can be simplified. In addition, an amorphous semiconductor such as an amorphous semiconductor or a semi-amorphous semiconductor (or a microcrystalline semiconductor) can be used for a semiconductor layer of a transistor included in the pixel. For example, amorphous silicon (a-Si: H) can be given as an amorphous semiconductor. By using these amorphous semiconductors, the manufacturing process can be further simplified. Therefore, the manufacturing cost can be reduced and the yield can be improved.

  Note that the first switching transistor 412, the second switching transistor 413, and the third switching transistor 414 operate as mere switches, and thus the polarity (conductivity type) of the transistors is not particularly limited. However, it is preferable to use a transistor with low off-state current. As a transistor with low off-state current, there are a transistor provided with an LDD region and a transistor having a multi-gate structure. Further, a CMOS switch may be used by using both an N channel type and a P channel type.

  Next, a display device having the pixel of the present invention will be described with reference to FIG.

  The display device includes a signal line driver circuit 611, a scan line driver circuit 612, and a pixel portion 613, and the pixel portion 613 has a plurality of signal lines S <b> 1 to S1 arranged extending from the signal line driver circuit 611 in the column direction. Sm and a plurality of first scanning lines G1_1 to Gn_1, second scanning lines G1_2 to Gn_2, third scanning lines G1_3 to Gn_3, and a power supply line P1_1 that are arranged extending in the row direction from the scanning line driver circuit 612. To Pn_1 and a plurality of pixels 614 arranged in a matrix corresponding to the signal lines S1 to Sm. In addition, a plurality of potential supply lines P1_2 to Pn_2 are provided in parallel with the first scanning lines G1_1 to Gn_1. Each pixel 614 includes a signal line Sj (any one of the signal lines S1 to Sm), a first scanning line Gi_1 (any one of the scanning lines G1_1 to Gn_1), a second scanning line Gi_2, 3 scanning line Gi_3, power supply line Pi_1, and potential supply line Pi_2.

  Note that the signal line Sj, the first scanning line Gi_1, the second scanning line Gi_2, the third scanning line Gi_3, the power supply line Pi_1, and the potential supply line Pi_2 are the signal line 117 and the first scanning line in FIG. 1, respectively. Reference numeral 118 denotes a second scanning line 119, a third scanning line 120, a power supply line 121, and a potential supply line 122.

  A row of pixels to be operated is selected by a signal output from the scan line driver circuit 612, and the operation shown in FIG. 2 is simultaneously performed on each pixel belonging to the same row. Note that in the data writing period in FIG. 2, the video signal output from the signal line driver circuit 611 is written to the pixel in the selected row. At this time, a potential corresponding to the luminance data of each pixel is input to each of the signal lines S1 to Sm.

  As shown in FIG. 40, for example, when the data writing period of the i-th row ends, a signal is written to the pixel belonging to the i + 1-th row. Note that FIG. 40 shows only the operation of the first switch 112 in FIG. 2 that can faithfully represent the data writing period in each row. Further, the pixel that has completed the data writing period in the i-th row moves to the light emission period, and emits light according to the signal written to the pixel.

  Therefore, if even the data writing period in each row does not overlap, the initialization start time can be set freely for each row. In addition, since each pixel can emit light except its own address period, the ratio of the light emission period in one frame period (that is, the duty ratio) can be very large, and can be almost 100%. . Therefore, a display device with a small luminance variation and a high duty ratio can be obtained.

  Further, since the threshold writing period can be set long, the threshold voltage of the transistor can be written to the capacitor more accurately. Therefore, the reliability as a display device is improved.

  Note that the configuration of the display device illustrated in FIG. 6 is an example, and the present invention is not limited to this. For example, the potential supply lines P1_2 to Pn_2 do not have to be arranged in parallel to the first scanning lines G1_1 to Gn_1, and may be arranged in parallel to the signal lines S1 to Sm.

    In addition, the variation in threshold voltage includes a change in threshold voltage over time when attention is paid to one transistor in addition to a difference in threshold voltage of each transistor between pixels. Further, the difference in threshold voltage of each transistor includes a difference in transistor characteristics at the time of manufacturing the transistor. Note that the transistor here refers to a transistor having a function of supplying current to a load such as a light emitting element.

(Embodiment 2)
In this embodiment mode, a pixel having a different structure from that in Embodiment Mode 1 is shown in FIG. Note that components similar to those in Embodiment 1 are denoted by common reference numerals, and detailed description of the same portions or portions having similar functions is omitted.

  A pixel illustrated in FIG. 39A includes a transistor 111, a first switch 112, a second switch 113, a rectifier element 3914, a capacitor element 115, and a light-emitting element 116. Note that the pixel is connected to the signal line 117, the first scan line 118, the second scan line 119, the third scan line 3920, and the power supply line 121. The pixel illustrated in FIG. 39A has a structure in which the rectifier element 3914 is used for the third switch 114 in FIG. 1, and the second electrode of the capacitor 115, the first electrode of the transistor 111, and light emission. The pixel electrode of the element 116 is connected to the third scanning line 3920 through the rectifying element 3914. That is, the rectifier element 3914 is connected so that a current flows from the first electrode of the transistor 111 to the third scan line 3920. Needless to say, as described in Embodiment Mode 1, transistors or the like may be used for the first switch 112 and the second switch 113. As the rectifier element 3914, diode-connected transistors 3954, 3955, and the like can be used in addition to the Schottky barrier type 3951, PIN type 3952, and PN type 3953 diodes shown in FIG. Note that the polarity of the transistors 3954 and 3955 needs to be selected as appropriate depending on the direction of current flow.

  In the rectifier element 3914, no current flows when an H level signal is input to the third scanning line 3920, and an electric current flows in the rectifier element 3914 when an L level signal is input. Therefore, when the pixel in FIG. 39 is operated in the same manner as in FIG. 1, an L level signal is input to the third scanning line 3920 in the initialization period, and an H level signal is input in other periods. . However, in the case of the L level signal, not only the current flows through the rectifying element 3914 but also the potential of the second electrode of the capacitor 115 needs to be lowered to V1−Vth−α (α: any positive number). Therefore, the potential is V1-Vth-α-β (α: any positive number). Note that β indicates a threshold voltage in the forward direction of the rectifying element 3914.

  In consideration of the above matters, the pixel configuration in FIG. 39 can also be operated in the same manner as in FIG. 1, whereby variation in current value due to variation in threshold voltage of the transistor 111 can be suppressed. Therefore, a current corresponding to the luminance data can be supplied to the light emitting element 116, and variations in luminance can be suppressed. In addition, when the transistor 111 is operated in the saturation region, variation in luminance due to deterioration of the light-emitting element 116 can be suppressed. Further, by using the rectifying element 3914, the number of wirings can be reduced and the aperture ratio can be improved.

  Further, the pixel shown in this embodiment mode can be applied to the display device in FIG. As in the first embodiment, the initialization start time can be set freely for each row as long as even the data writing periods in each row do not overlap. Further, since each pixel can emit light except its own address period, the ratio of the light emission period in one frame period (that is, the duty ratio) can be very large, and can be almost 100%. Therefore, a display device with a small luminance variation and a high duty ratio can be obtained.

  Further, since the threshold writing period can be set long, the threshold voltage of the transistor that controls the value of the current flowing through the light-emitting element can be written into the capacitor more accurately. Therefore, the reliability as a display device is improved.

  In addition to the above-described FIG. 1, this embodiment mode can be freely combined with the pixel structures shown in other embodiment modes. That is, the rectifying element 3914 can be applied to the pixels described in other embodiments.

(Embodiment 3)
In this embodiment mode, a pixel having a structure different from that in Embodiment Mode 1 is shown in FIGS. Note that components similar to those in Embodiment 1 are denoted by common reference numerals, and detailed description of the same portions or portions having similar functions is omitted.

  A pixel 700 illustrated in FIG. 7 includes a transistor 111, a first switch 112, a second switch 113, a third switch 114, a capacitor 115, and a light-emitting element 116. Note that the pixel 700 is connected to the signal line 117, the first scan line 718, the second scan line 119, the third scan line 120, the power supply line 121, and the first scan line 718 in the next row.

  In the pixel in FIG. 1 described in Embodiment Mode 1, the first electrode of the transistor 111 is connected to the potential supply line 122 through the third switch 114, whereas in FIG. A scan line 718 can be connected. This is because it is only necessary to supply a predetermined potential to the first electrode of the transistor 111 in the initialization period, not limited to the potential supply line 122. Therefore, if a predetermined potential can be supplied to the first electrode of the transistor 111 in the initialization period, the wiring to be supplied does not always need to have a constant potential. Therefore, the first scanning line 718 in the next row can be used instead of the potential supply line. Thus, by sharing the wiring with the next row, the number of wirings can be reduced, and the aperture ratio can be improved.

  Note that in the pixel configuration illustrated in FIG. 7 as well, by performing the same operation as in Embodiment 1, variation in current value due to variation in threshold voltage of the transistor 111 can be suppressed. Therefore, a current corresponding to the luminance data can be supplied to the light emitting element 116, and variations in luminance can be suppressed. In addition, since the counter electrode is operated at a constant potential, power consumption can be reduced. Note that the operation region of the transistor 111 is not particularly limited, but the effect is more remarkable in the saturation region. Further, when the transistor 111 is operated in the saturation region, variation in current flowing in the transistor 111 due to deterioration of the light-emitting element 116 can be suppressed.

  Note that a signal for turning off the first switch 112 in the first scan line 718 has a potential of V1−Vth−α (α: an arbitrary positive number). Therefore, it is necessary to use the first switch 112 that is turned off at a potential of V1−Vth−α (α: an arbitrary positive number). In addition, the initialization period of the row to which the pixel 700 belongs needs to be operated so as not to overlap with the data writing period of the row sharing the wiring.

  Note that in the case where an N-channel transistor is used for the third switch 114, the potential at which the third switch 114 is turned off in the third scan line 120 turns off the first switch 112 in the first scan line 718. The voltage may be lower than the potential of the signal V1-Vth-α. In this case, the gate-source voltage when the transistor is turned off can be a negative value. Therefore, current leakage when the third switch 114 is turned off can be reduced.

  Further, as shown in the pixel 800 in FIG. 8, the potential supply line 122 in FIG. 1 may be shared with the second scanning line 819 in the next row. The pixel 800 can also perform the same operation as that in Embodiment 1. Note that a signal for turning off the second switch 113 in the second scanning line 819 has a potential of V1−Vth−α (α: an arbitrary positive number). Therefore, it is necessary to use the second switch 113 that is turned off at a potential of V1−Vth−α (α: an arbitrary positive number). In addition, the initialization period of the row to which the pixel 800 belongs needs to be operated so as not to overlap with the threshold writing period of the row sharing the wiring.

  Note that in the case where an N-channel transistor is used for the third switch 114, a signal for turning off the third switch 114 in the third scanning line 120 turns off the second switch 113 in the second scanning line 819. The potential may be lower than the potential of the signal V1-Vth-α. In this case, current leakage when the third switch 114 is turned off can be reduced.

  Further, as shown in the pixel 900 in FIG. 9, the potential supply line 122 in FIG. 1 may be shared with the third scanning line 920 in the previous row. The pixel 900 can also operate in the same manner as in the first embodiment. Note that a signal for turning off the third switch 114 in the third scanning line 920 has a potential of V1−Vth−α (α: an arbitrary positive number). Therefore, it is necessary to use the third switch 114 that is turned off at a potential of V1−Vth−α (α: an arbitrary positive number). Further, the initialization period of the row to which the pixel 900 belongs needs to be operated so as not to overlap with the initialization period of the row sharing the wiring. This is particularly true when the initialization period is set shorter than the data writing period. No problem.

  Note that although the case where the potential supply line 122 in FIG. 1 is shared with the next row or the previous row scan line is shown in this embodiment mode, V1−Vth−α (α: any positive number) is set in the initialization period. Any other wiring may be used as long as it can supply a potential.

  Furthermore, the pixel shown in this embodiment mode can be applied to the display device in FIG. Note that in the display device, the initialization start time can be freely set for each row within a range in which the operation restrictions for each pixel described in FIGS. 7 to 9 and the data writing period in each row do not overlap. In addition, since each pixel can emit light except its own address period, the ratio of the light emission period in one frame period (that is, the duty ratio) can be very large, and can be almost 100%. . Therefore, a display device with a small luminance variation and a high duty ratio can be obtained.

  Further, since the threshold writing period can be set long, the threshold voltage of the transistor that controls the value of the current flowing through the light-emitting element can be written into the capacitor more accurately. Therefore, the reliability as a display device is improved.

  Further, this embodiment mode can be freely combined with the pixel structures shown in Embodiment Modes 1 and 2 other than FIG. 1 described above.

(Embodiment 4)
In this embodiment mode, a pixel having a structure different from that in Embodiment Mode 1 is shown in FIG. Note that components similar to those in Embodiment 1 are denoted by common reference numerals, and detailed description of the same portions or portions having similar functions is omitted.

  10 includes a transistor 1011, a first switch 112, a second switch 113, a third switch 114, a capacitor 115, and a light-emitting element 116. Note that the pixel is connected to the signal line 117, the first scan line 118, the second scan line 119, the third scan line 120, the power supply line 121, and the potential supply line 122.

  The transistor 1011 in this embodiment is a multi-gate transistor in which two transistors are connected in series, and is provided at the same position as the transistor 111 in Embodiment 1. However, the number of transistors connected in series is not particularly limited.

  By operating the pixel shown in FIG. 10 as in Embodiment Mode 1, variation in current value due to variation in threshold voltage of the transistor 1011 can be suppressed. Therefore, a current corresponding to the luminance data can be supplied to the light emitting element 116, and variations in luminance can be suppressed. In addition, since the counter electrode is operated at a constant potential, power consumption can be reduced. Note that the operation region of the transistor 1011 is not particularly limited, but the effect is more remarkable in the saturation region.

  Further, when the transistor 1011 is operated in the saturation region, variation in current flowing in the transistor 1011 due to deterioration of the light-emitting element 116 can be suppressed.

  The channel length L of the transistor 1011 in this embodiment acts as the sum of the channel lengths of the transistors when the channel widths of two transistors connected in series are equal. Therefore, it is easy to obtain a current value closer to a constant value regardless of the drain-source voltage Vds in the saturation region. In particular, the transistor 1011 is effective when it is difficult to manufacture a transistor having a long channel length L. Note that the connection portion of the two transistors functions as a resistor.

  Note that the transistor 1011 only needs to have a function of controlling a current value supplied to the light-emitting element 116, and the type of the transistor is not particularly limited. Therefore, a thin film transistor (TFT) using a crystalline semiconductor film, a thin film transistor using a non-single crystal semiconductor film typified by amorphous silicon or polycrystalline silicon, a transistor formed using a semiconductor substrate or an SOI substrate, MOS Type transistors, junction type transistors, bipolar transistors, transistors using organic semiconductors or carbon nanotubes, and other transistors can be used.

  10 can use transistors for the first switch 112, the second switch 113, and the third switch 114, similarly to the pixel shown in FIG.

  Furthermore, the pixels shown in this embodiment can be applied to the display device in FIG. 6, and as in Embodiment 1, if the data writing period in each row does not overlap, the initialization start time is set freely in each row. be able to. In addition, since each pixel can emit light except its own address period, the ratio of the light emission period in one frame period (that is, the duty ratio) can be very large, and can be almost 100%. . Therefore, a display device with a small luminance variation and a high duty ratio can be obtained.

  Further, since the threshold writing period can be set long, the threshold voltage of the transistor that controls the value of the current flowing through the light-emitting element can be written into the capacitor more accurately. Therefore, the reliability as a display device is improved.

  Note that the transistor 1011 is not limited to a transistor connected in series, and may have a structure in which transistors are connected in parallel as illustrated in a transistor 1111 in FIG. With the transistor 1111, a larger current can be supplied to the light-emitting element 116. In addition, since the characteristics of the transistors are averaged by the two transistors connected in parallel, the original characteristic variation of the transistors constituting the transistor 1111 can be further reduced. When the variation is small, the operation shown in FIG. 2 can more easily suppress the variation in the current value caused by the variation in the threshold voltage of the transistor.

  Further, this embodiment mode can be applied not only to the above-described FIG. 1 but also to pixel configurations shown in other embodiment modes.

(Embodiment 5)
In this embodiment mode, a pixel configuration in which deterioration over time of a transistor is averaged by switching a transistor for controlling a current value supplied to a light emitting element for each period in the pixel of the present invention will be described with reference to FIG. .

  The pixel illustrated in FIG. 12 includes a first transistor 1201, a second transistor 1202, a first switch 1212, a second switch 1213, a third switch 1214, a fourth switch 1203, a fifth switch 1204, a capacitor An element 1215 and a light-emitting element 1216 are included. Note that the pixel is connected to a signal line 1217, a first scan line 1218, a second scan line 1219, a third scan line 1220, a power supply line 1221, and a potential supply line 1222. Further, although not shown in FIG. 12, the fourth switch 1203 and the fifth switch 1204 are also connected to fourth and fifth scanning lines for controlling on and off. In this embodiment, the first transistor 1201 and the second transistor 1202 are N-channel transistors, and each transistor becomes conductive when the gate-source voltage (Vgs) exceeds the threshold voltage. And The pixel electrode of the light emitting element 1216 is an anode, and the counter electrode 1223 is a cathode. Note that the gate-source voltage of the transistor is denoted as Vgs, and the voltage accumulated in the capacitor is denoted as Vcs. The threshold voltage of the first transistor 1201 is denoted as Vth1, and the threshold voltage of the second transistor 1202 is denoted as Vth2. The power supply line 1221, the potential supply line 1222, and the signal line 1217 are also referred to as a first wiring, a second wiring, and a third wiring, respectively.

  The first transistor 1201 has a first electrode connected to the pixel electrode of the light-emitting element 1216 through the fourth switch 1203, a second electrode connected to the power supply line 1221, and a gate electrode connected to the second switch 1213. It is connected to the power line 1221 through. The gate electrode of the first transistor 1201 is also connected to the signal line 1217 via the first switch 1212, and the first electrode is supplied with a potential via the fourth switch 1203 and the third switch 1214. A line 1222 is also connected.

  The second transistor 1202 has a first electrode connected to the pixel electrode of the light-emitting element 1216 through the fifth switch 1204, a second electrode connected to the power supply line 1221, and a gate electrode connected to the second switch 1213. It is connected to the power line 1221 through. The gate electrode of the second transistor 1202 is also connected to the signal line 1217 via the first switch 1212, and the first electrode is connected to the potential supply line via the fifth switch 1204 and the third switch 1214. 1222 is also connected. Note that the gate electrodes of the first transistor 1201 and the second transistor 1202 and the second electrodes of the first transistor 1201 and the second transistor 1202 are connected to each other, and the first transistor 1201 and the second transistor 1202 are connected to each other. The first electrode of the transistor 1202 is also connected through the fourth switch 1203 and the fifth switch 1204.

  Further, the gate electrodes of the first transistor 1201 and the second transistor 1202 that are connected are connected to the first electrode of the first transistor 1201 through the capacitor 1215 and the fourth switch 1203, and the capacitor The first electrode of the second transistor 1202 is connected to the first transistor 1202 through 1215 and the fifth switch 1204. That is, the first electrode of the capacitor 1215 is connected to the gate electrodes of the first transistor 1201 and the second transistor 1202, and the second electrode is connected to each of the first transistor 1201 and the second transistor 1202 through each switch. Connected to the first electrode. Note that the capacitor 1215 may be formed by sandwiching an insulating film with a wiring, a semiconductor layer, or an electrode, or may be omitted using the gate capacitors of the first transistor 1201 and the second transistor 1202.

  Note that by inputting signals to the first scan line 1218, the second scan line 1219, and the third scan line 1220, the first switch 1212, the second switch 1213, and the third switch 1214 are turned on and off, respectively. Is controlled. In FIG. 12, scanning lines for controlling on and off of the fourth switch 1203 and the fifth switch 1204 are omitted.

  A signal in accordance with the gradation of a pixel corresponding to a video signal, that is, a potential corresponding to luminance data is input to the signal line 1217.

  Next, the operation of the pixel shown in FIG. 12 will be described with reference to the timing chart of FIG. In FIG. 13, one frame period corresponding to a period for displaying an image for one screen is divided into an initialization period, a threshold writing period, a data writing period, and a light emitting period.

  Note that a potential of V1 is supplied to the counter electrode 1223 of the light-emitting element 1216, and when the larger value of Vth1 and Vth2 is Vth, the potential supply line 1222 has V1-Vth-α (α: any positive value) Number) of potentials. The power supply line 1221 is supplied with a potential of V1 during the address period and V2 during the light emission period. However, V2> V1.

Here, in order to explain the operation, the potential of the counter electrode 1223 of the light-emitting element 1216 is the same as the potential of the power supply line 1221 in the address period; however, at least a potential difference necessary for the light-emitting element 1216 to emit light is determined. If V _EL , the potential of the counter electrode 1223 may be higher than the potential of V 1 −Vth−α−V _EL . In addition, the potential V2 of the power supply line 1221 during the light emission period may be larger than a value obtained by adding the potential of the counter electrode 1223 and at least the potential difference (V _EL ) necessary for the light emitting element 1216 to emit light. Here, for the purpose of explanation, the potential of the counter electrode 1223 is V1, so that V2 may be larger than V1 + _VEL .

  First, as shown in FIG. 13A, in the initialization period, the first switch 1212 and the fifth switch 1204 are turned off, and the second switch 1213, the third switch 1214, and the fourth switch 1203 are turned on. And At this time, the first electrode of the first transistor 1201 serves as a source electrode, and the potential thereof is V1−Vth−α. On the other hand, the potential of the gate electrode is V1. Accordingly, the gate-source voltage Vgs of the first transistor 1201 is Vth + α, and the first transistor 1201 is turned on. Then, Vth + α is held in the capacitor 1215 arranged between the gate electrode and the first electrode of the first transistor 1201.

  Next, in the threshold writing period illustrated in FIG. 13B, the third switch 1214 is turned off. Therefore, when the potential of the first electrode, that is, the source electrode of the first transistor 1201 is gradually increased to V1-Vth1, the first transistor 1201 is turned off. Therefore, the voltage held in the capacitor 1215 is Vth1.

  After that, in the data writing period illustrated in FIG. 13C, after the second switch 1213 is turned off, the first switch 1212 is turned on, and a potential (V1 + Vdata) corresponding to luminance data is input from the signal line 1217. To do. At this time, the voltage Vcs held in the capacitor 1215 is Vth1 + Vdata, and the first transistor 1201 is turned on. Note that in the case where a potential of Vdata ≦ 0 is input, a non-conduction state occurs and light emission is not possible.

  Next, in the light-emitting period illustrated in FIG. 13D, the first switch 1212 is turned off and the potential of the power supply line 1221 is set to V2. At this time, the gate-source voltage of the first transistor 1201 is Vgs = Vth1 + Vdata, and a current corresponding thereto flows to the first transistor 1201 and the light-emitting element 1216, so that the light-emitting element 1216 emits light.

  With such an operation, the current flowing through the light-emitting element 1216 depends on the threshold voltage (Vth1) of the first transistor 1201 regardless of whether the operation region of the first transistor 1201 is the saturation region or the linear region. do not do.

  Further, in the initialization period in the next one frame period illustrated in FIG. 13E, the fourth switch 1203 is turned off, and the second switch 1213, the third switch 1214, and the fifth switch 1204 are turned on. . At this time, the first electrode of the second transistor 1202 serves as a source electrode, and the potential thereof is V1−Vth−α. On the other hand, the potential of the gate electrode is V1. Therefore, the gate-source voltage Vgs of the second transistor 1202 is Vth + α, and the second transistor 1202 is turned on. Then, Vth + α is held in the capacitor 1215 arranged between the gate electrode and the first electrode of the second transistor 1202.

  Next, in the threshold value writing period illustrated in FIG. 13F, the third switch 1214 is turned off. Therefore, when the potential of the first electrode, that is, the source electrode of the second transistor 1202 is gradually increased to V1-Vth2, the second transistor 1202 is turned off. Therefore, the voltage held in the capacitor 1215 is Vth2.

  After that, in the data writing period illustrated in FIG. 13G, after the second switch 1213 is turned off, the first switch 1212 is turned on, and a potential (V1 + Vdata) corresponding to the luminance data is input from the signal line 1217. To do. At this time, the voltage Vcs held in the capacitor 1215 is Vth2 + Vdata, so that the second transistor 1202 is turned on.

  Next, in the light-emitting period illustrated in FIG. 13H, the first switch 1212 is turned off and the potential of the power supply line 1221 is set to V2. At this time, the gate-source voltage of the second transistor 1202 is Vgs = Vth2 + Vdata, and a current corresponding to the voltage flows through the second transistor 1202 and the light-emitting element 1216, so that the light-emitting element 1216 emits light.

  In addition, in the case where the operation region of the second transistor 1202 is either the saturation region or the linear region, the current flowing through the light-emitting element 1216 does not depend on the threshold voltage (Vth2).

  Therefore, even if the current supplied to the light-emitting element is controlled using any of the first transistor 1201 and the second transistor 1202, variation in current value due to variation in threshold voltage of the transistor is suppressed, A current value corresponding to the luminance data can be supplied to the light emitting element 1216. Note that by changing the use of the first transistor 1201 and the second transistor 1202 and reducing the load applied to one transistor, change in threshold value of the transistor with time can be reduced.

  From the above, variation in luminance due to the threshold voltages of the first transistor 1201 and the second transistor 1202 can be suppressed. In addition, since the potential of the counter electrode is kept constant, power consumption can be reduced.

  Further, when the first transistor 1201 and the second transistor 1202 are operated in the saturation region, variation in current flowing to each transistor due to deterioration of the light-emitting element 1216 can be suppressed.

  Note that in the case where the first transistor 1201 and the second transistor 1202 are operated in the saturation region, it is preferable that the channel length L of these transistors be long.

  In addition, since a reverse bias voltage is applied to the light-emitting element 1216 in the initialization period, a short-circuit portion in the light-emitting element can be insulated and deterioration of the light-emitting element can be suppressed. Therefore, the lifetime of the light emitting element can be extended.

  Note that since variation in current value due to variation in threshold voltage of a transistor can be suppressed, a supply destination of current controlled by the transistor is not particularly limited. Therefore, an EL element (an organic EL element, an inorganic EL element, or an EL element containing an organic substance and an inorganic substance), an electron-emitting element, a liquid crystal element, electronic ink, or the like can be used as the light-emitting element 1216 illustrated in FIG.

  The first transistor 1201 and the second transistor 1202 only have a function of controlling a current value supplied to the light-emitting element 1216, and the type of the transistor is not particularly limited. Therefore, a thin film transistor (TFT) using a crystalline semiconductor film, a thin film transistor using a non-single crystal semiconductor film typified by amorphous silicon or polycrystalline silicon, a transistor formed using a semiconductor substrate or an SOI substrate, MOS Type transistors, junction type transistors, bipolar transistors, transistors using organic semiconductors or carbon nanotubes, and other transistors can be used.

  The first switch 1212 selects a timing at which a signal in accordance with the gray scale of the pixel is input to the capacitor, and the second switch 1213 has a predetermined connection to the gate electrode of the first transistor 1201 or the second transistor 1202. The third switch 1214 selects the timing for applying a predetermined potential for initializing the potential written in the capacitor 1215. Therefore, the first switch 1212, the second switch 1213, and the third switch 1214 are not particularly limited as long as they have the above functions. For example, a transistor or a diode may be used, or a logic circuit combining them may be used. Note that the first to third switches are not particularly required as long as a signal or a potential can be given to the pixel at the above timing. Further, the fourth switch 1203 and the fifth switch 1204 are not particularly limited, and may be, for example, a transistor or a diode, or a logic circuit combining them.

  In the case where N-channel transistors are used for the first switch 1212, the second switch 1213, the third switch 1214, the fourth switch 1203, and the fifth switch 1204, a pixel is formed using only the N-channel transistors. Therefore, the manufacturing process can be simplified. In addition, an amorphous semiconductor such as an amorphous semiconductor or a semi-amorphous semiconductor (or a microcrystalline semiconductor) can be used for a semiconductor layer of a transistor included in the pixel. For example, amorphous silicon (a-Si: H) can be given as an amorphous semiconductor. By using these amorphous semiconductors, the manufacturing process can be further simplified. Therefore, the manufacturing cost can be reduced and the yield can be improved.

  Note that when transistors are used for the first switch 1212, the second switch 1213, the third switch 1214, the fourth switch 1203, and the fifth switch 1204, the polarity (conductivity type) of the transistor is not particularly limited. However, it is preferable to use a transistor with low off-state current.

  Further, the first transistor 1201 and the fourth switch 1203, and the second transistor 1202 and the fifth switch 1204 may be interchanged as shown in FIG. In other words, the first electrodes of the first transistor 1201 and the second transistor 1202 are connected to the gate electrodes of the first transistor 1201 and the second transistor 1202 through the capacitor 1215. The second electrode of the first transistor 1201 is connected to the power supply line 1221 through the fourth switch 1203, and the second electrode of the second transistor 1202 is connected to the power supply line 1221 through the fifth switch 1204. It is connected.

    12 and 41, when the transistor and the switch are set, that is, the first transistor 1201 and the fourth switch 1203, the second transistor 1202 and the fifth switch 1204 are set, and the parallel number is two. However, the number arranged in parallel is not particularly limited.

  In addition, by applying the pixel shown in this embodiment to the display device of FIG. 6, the initialization start time can be freely set in each row as long as the data writing period in each row does not overlap as in the first embodiment. Can do. In addition, since each pixel can emit light except its own address period, the ratio of the light emission period in one frame period (that is, the duty ratio) can be very large, and can be almost 100%. . Therefore, a display device with a small luminance variation and a high duty ratio can be obtained.

  Further, since the threshold writing period can be set long, the threshold voltage of the transistor that controls the value of the current flowing through the light-emitting element can be written into the capacitor more accurately. Therefore, the reliability as a display device is improved.

  Note that as in Embodiment 3, the potential supply line 1222 can be shared with wirings in other rows. As in Embodiment 4, a multigate transistor in which transistors are connected in series or a transistor arranged in parallel may be used for each of the first transistor 1201 and the second transistor 1202. The present embodiment is not limited to these, and can also be applied to the pixel structures described in Embodiments 1 to 4.

(Embodiment 6)
In this embodiment, a pixel having a structure different from that in Embodiment 1 is shown. Components similar to those in Embodiment 1 are denoted by common reference numerals, and detailed description of the same portions or portions having similar functions is omitted. These operations are the same as in the first embodiment.

  In the present embodiment, a pixel configuration in which current is not forced to flow through the light emitting element 116 will be described. That is, it is an object of the present invention to obtain a display device that is difficult to see an afterimage and has excellent moving image characteristics by forcibly creating a non-light emitting state.

  One such pixel configuration is shown in FIG. 29 includes a fourth switch 2901 in addition to the transistor 111, the first switch 112, the second switch 113, the third switch 114, the capacitor 115, and the light-emitting element 116 included in the pixel in FIG. Have In addition, the pixel is connected to the fourth scanning line 2902 in addition to the signal line 117, the first scanning line 118, the second scanning line 119, the third scanning line 120, the power supply line 121, and the potential supply line 122. Has been.

  In FIG. 29, the fourth switch 2901 is connected in parallel with the capacitor 115. Therefore, when the fourth switch 2901 is turned on, the gate electrode and the first electrode of the transistor 111 are short-circuited. Then, since the gate-source voltage of the transistor 111 held in the capacitor 115 can be 0 V, the transistor 111 is turned off and the light-emitting element 116 can be made non-light-emitting. Note that on / off control of the fourth switch 2901 is performed by scanning pixel by row in accordance with a signal input to the fourth scan line 2902.

  By such an operation, the signal written in the pixel is erased. Therefore, an erasing period in which the light emission is forcibly stopped is provided until the next initialization period. That is, a black display is inserted. Therefore, it is difficult to see the afterimage, and the moving image characteristics can be improved.

  Incidentally, there are an analog gray scale method and a digital gray scale method as drive methods for expressing the gray scale of the display device. The analog gradation method includes a method of analog control of the light emission intensity of the light emitting element and a method of analog control of the light emission time of the light emitting element. In the analog gradation method, a method of analog control of the light emission intensity of the light emitting element is often used. On the other hand, in the digital gradation method, gradation is expressed by turning on and off the light emitting element by digital control. In the digital gradation method, since it can be processed with a digital signal, there is a merit of being resistant to noise. However, since there are only two states of light emission and non-light emission, only two gradations can be expressed as it is. In view of this, multi-gradation is being achieved by combining different methods. As a method for multi-gradation, there are an area gradation method in which gradation display is performed by weighting the light emitting area of the pixel and selection is performed, and a time in which gradation display is performed by weighting the light emission time and selected. There is a gradation method.

When the digital gradation method and the time gradation method are combined, one frame period is divided into a plurality of subframe periods (SFn) as shown in FIG. Each subframe period includes an address period (Ta) having an initialization period, a threshold value writing period and a data writing period, and a light emission period (Ts). Note that a number corresponding to the number n of display bits is provided in one frame period in the subframe period. In addition, the ratio of the lengths of the light emitting periods in each subframe period is set to 2 ^(n-1) : 2 ^(n-2) :. Is selected, and gradation expression is performed using a difference in total time during one frame period in which the light emitting element emits light. In one frame period, the luminance is high if the total emission time is long, and the luminance is low if it is short. Note that FIG. 42 shows an example of 4-bit gradation, and one frame period is divided into four subframe periods, and 2 ⁴ = 16 gradations can be expressed by a combination of light emission periods. Note that gradation expression is possible even if the ratio of the lengths of the light emission periods is not particularly a power-of-two ratio. Further, a certain subframe period may be further divided.

  Note that when multi-gradation is performed using the time gray scale method as described above, since the light emission period of the lower bits is short, the data writing operation for the next subframe period starts immediately after the light emission period ends. Attempting to do so overlaps the data write operation in the previous subframe period, and normal operation cannot be performed. Therefore, by providing such an erasing period in the subframe period, light emission shorter than the data writing period required for all rows can be expressed. That is, the light emission period can be set freely.

  The present invention is particularly effective for analog gray scales. In addition, a light emission period can be freely set even in a system that combines a digital gray scale method and a time gray scale method, and therefore an erasing period is provided. Is valid.

  In addition, a new switch is provided in a current path from the power supply line 121 to the pixel electrode of the light emitting element 116 through the transistor 111, and an erase period is provided by scanning the pixels row by row and turning off the switch. May be.

  One such configuration is shown in FIG. 30, in addition to the pixel configuration in FIG. 1, a fourth switch 3001 is connected between the second electrode of the transistor 111 and the power supply line 121. Then, on / off of the fourth switch 3001 is controlled by a signal input to the fourth scan line 3002.

  Further, when a connection point between the first electrode of the transistor 111 and the pixel electrode of the light-emitting element 116 is a node 3003, the fourth switch 3701 is connected between the node 3003 and the first electrode of the transistor 111 as illustrated in FIG. You may connect between them. On / off of the fourth switch 3701 is controlled by a signal input to the fourth scan line 3702.

  Therefore, an erasing period can be provided by turning off the fourth switch. Further, similarly to Embodiment Mode 1, when the pixel illustrated in FIGS. 30 and 37 is operated, power consumption can be reduced by turning off the fourth switch in the initialization period.

  Note that the erasing period can be provided even when the fourth switch 4301 is connected between the node 3003 and the pixel electrode of the light-emitting element 116 as shown in FIG. As shown in FIG. 44, an erasing period is provided even if the fourth switch 4401 is connected between the connection point between the second electrode of the transistor 111 and the second switch 113 and the power supply line 121. Is possible.

  Further, an erasing period may be forcibly provided by inputting a potential to the gate electrode of the transistor 111.

  One such configuration is shown in FIG. 31 includes a rectifying element 3101 in addition to the pixel structure of FIG. 1, and the gate electrode of the transistor 111 and the fourth scanning line 3102 are connected through the rectifying element 3101. Note that when the transistor 111 is an N-channel transistor, the rectifier element 3101 is connected so that a current flows from the gate electrode of the transistor 111 to the fourth scan line 3102. The fourth scanning line 3102 receives an L level signal only when the transistor 111 is forcibly turned off, and otherwise inputs an H level signal. Then, when the fourth scanning line is at the H level, no current flows through the rectifier element 3101, and when the fourth scanning line is at the L level, a current flows from the transistor 111 to the fourth scanning line 3102. In this manner, by passing a current through the fourth scan line 3102, the voltage held in the capacitor 115 is made lower than the threshold voltage (Vth) of the transistor 111, and the transistor 111 is forcibly turned off. Note that the L-level potential must be determined in consideration of the fact that the potential of the gate electrode of the transistor 111 does not become lower than the potential of the forward threshold voltage of the rectifying element 3101 than the L-level potential. In addition, when the switch in which the first switch 112 and the second switch 113 are turned off at this L level potential is used for each switch, the fourth scanning line 3102 is replaced with the first scanning line 118 or the first scanning line 118. The second scanning line 119 may be substituted.

  Note that the pixel configuration is not particularly limited to the above-described configuration because if the pixel configuration has a means for forcibly turning off light emission, an afterimage can be made difficult to see by inserting a black display.

  Note that as the rectifying element 3101, a diode-connected transistor or the like can be used in addition to the Schottky barrier type, PIN type, or PN type diode shown in FIG.

  Note that the switch for providing the erasing period described in this embodiment mode is not limited to the above-described FIG. 1 and can be applied to pixel configurations shown in other embodiment modes.

  Further, by setting a long initialization period without providing such a switch, the initialization period can also serve as an erasing period. Therefore, when the pixels described in Embodiments 1 to 5 are operated, the period for which black display is performed in order to make an afterimage difficult to see is set as the length of the initialization period, so that the moving image characteristics can be improved. . Further, black display may be inserted by making the potential of the power supply line 121 the same as the potential of the counter electrode 123 during the light emission period.

  Note that in the pixel structure illustrated in FIG. 30, when the transistor 111 is turned on in the data writing period, the current to the transistor 111 can be cut off by turning off the fourth switch 3001. Therefore, variation in potential of the second electrode of the capacitor 115 connected to the source electrode of the transistor 111 can be suppressed, so that the capacitor 115 can hold the voltage of Vth + Vdata more accurately. . Therefore, a more accurate current corresponding to the luminance data can be supplied to the light emitting element 116.

  In the pixel structure illustrated in FIG. 37, the variation in the potential of the second electrode of the capacitor 115 can be suppressed by turning off the fourth switch 3701 in the data writing period; The capacitor 115 can hold a voltage of Vth + Vdata. Therefore, a more accurate current corresponding to the luminance data can be supplied to the light emitting element 116.

  Note that the pixel described in this embodiment can be applied to the display device described in Embodiment 1. From the above, it is possible to obtain a display device with little variation in luminance and excellent moving image characteristics.

(Embodiment 7)
In this embodiment, the case where a P-channel transistor is applied to a transistor for controlling a current value supplied to a light emitting element will be described with reference to FIG.

  The pixel illustrated in FIG. 14 includes a transistor 1411, a first switch 1412, a second switch 1413, a third switch 1414, a capacitor element 1415, and a light-emitting element 1416. Note that the pixel is connected to a signal line 1417, a first scan line 1418, a second scan line 1419, a third scan line 1420, a power supply line 1421, and a potential supply line 1422. In this embodiment, the transistor 1411 is a P-channel transistor. When the absolute value (| Vgs |) of the gate-source voltage exceeds the threshold voltage (| Vth |) (Vgs falls below Vth). )). The pixel electrode of the light-emitting element 1416 is a cathode, and the counter electrode 1423 is an anode. Note that the absolute value of the gate-source voltage of the transistor is denoted as | Vgs |, the absolute value of the threshold is denoted as | Vth |, and the power supply line 1421, the potential supply line 1422, and the signal line 1417 are connected to the first wiring, It is also called a second wiring or a third wiring.

  A first electrode (one of a source electrode and a drain electrode) of the transistor 1411 is connected to the pixel electrode of the light-emitting element 1416, a second electrode (the other of the source electrode and the drain electrode) is connected to a power supply line 1421, and a gate The electrode is connected to the power supply line 1421 through the second switch 1413. The gate electrode of the transistor 1411 is also connected to the signal line 1417 through the first switch 1412, and the first electrode is also connected to the potential supply line 1422 through the third switch 1414.

  Further, a capacitor 1415 is connected between the gate electrode of the transistor 1411 and the first electrode. That is, the first electrode of the capacitor 1415 is connected to the gate electrode of the transistor 1411, and the second electrode is connected to the first electrode of the transistor 1411. Note that the capacitor 1415 may be formed by sandwiching an insulating film with a wiring, a semiconductor layer, or an electrode, or may be omitted using the gate capacitance of the transistor 1411.

  Note that by inputting signals to the first scan line 1418, the second scan line 1419, and the third scan line 1420, the first switch 1412, the second switch 1413, and the third switch 1414 are turned on and off, respectively. Is controlled.

  A signal according to the gradation of a pixel corresponding to a video signal, that is, a potential corresponding to luminance data is input to the signal line 1417.

  Next, the operation of the pixel shown in FIG. 14 will be described with reference to the timing chart of FIG. 15 and FIG. In FIG. 14, one frame period corresponding to a period for displaying an image for one screen is divided into an initialization period, a threshold writing period, a data writing period, and a light emission period. The initialization period, threshold write period, and data write period are collectively referred to as an address period. There is no particular limitation on the period of one frame, but it is preferable to set it to at least 1/60 second or less so that a person viewing the image does not feel flicker.

  Note that a potential of V1 is input to the counter electrode 1423 of the light-emitting element 1416, and a potential of V1 + | Vth | + α (α: an arbitrary positive number) is input to the potential supply line 1422. The power supply line 1421 is supplied with a potential of V1 during the address period and V2 during the light emission period. However, V2 <V1.

Here, in order to explain the operation, the potential of the counter electrode 1423 of the light-emitting element 1416 is the same as the potential of the power supply line 1421 in the address period; however, at least a potential difference necessary for the light-emitting element 1416 to emit light is determined. _Assuming V _EL , the potential of the counter electrode 1423 may be a value equal to or higher than V1 and lower than the potential of V1 + | Vth | + α + V _EL . Further, the potential V2 of the power supply line 1421 in the light emission period may be a value smaller than a value obtained by subtracting at least a potential difference (V _EL ) necessary for the light emitting element 1416 to emit light from the potential of the counter electrode 1423. Here, since the potential of the counter electrode 1423 is set to V1, V2 may be a value smaller than V1- _VEL .

  First, as shown in FIGS. 15A and 16A, in the initialization period, the first switch 1412 is turned off and the second switch 1413 and the third switch 1414 are turned on. At this time, the first electrode of the transistor 1411 serves as a source electrode, and the potential thereof is equal to that of the potential supply line 1422, so that V1 + | Vth | + α. On the other hand, the potential of the gate electrode is V1. Therefore, the absolute value | Vgs | of the gate-source voltage of the transistor 1411 is | Vth | + α, and the transistor 1411 is turned on. Then, | Vth | + α is held in the capacitor 1415 provided between the gate electrode and the first electrode of the transistor 1411.

  Next, in the threshold writing period illustrated in FIGS. 15B and 16B, the third switch 1414 is turned off. Therefore, when the potential of the first electrode, that is, the source electrode of the transistor 1411 gradually decreases to V1 + | Vth |, the transistor 1411 is turned off. Therefore, the voltage held in the capacitor 1415 is | Vth |.

In the subsequent data writing period shown in FIGS. 15C and 16C, after the second switch 1413 is turned off, the first switch 1412 is turned on, and the signal line 1417 responds to the luminance data. The potential (V1-Vdata) is input. At this time, the voltage Vcs held in the capacitor 1415 can be expressed as Equation (5), where C1 and C2 are the capacitances of the capacitor 1415 and the light emitting element 1416, respectively.

However, the light-emitting element 1416 is thinner than the capacitor 1415 and has a larger electrode area, and thus C2 >> C1. Therefore, from C2 / (C1 + C2) ≈1, the voltage Vcs held in the capacitor 1415 is expressed by Equation (6), and the transistor 1411 is turned on.

  Next, in the light-emitting period illustrated in FIGS. 15D and 16D, the first switch 1412 is turned off and the potential of the power supply line 1421 is set to V2. At this time, the gate-source voltage of the transistor 1411 is Vgs = −Vdata− | Vth |, and a current corresponding thereto flows to the transistor 1411 and the light-emitting element 1416, so that the light-emitting element 1416 emits light.

Note that the current I flowing through the light-emitting element is expressed by Expression (7) when the transistor 1411 is operated in the saturation region.

Since the transistor 1411 is a P-channel transistor, Vth <0. Therefore, equation (7) can be transformed into equation (8).

Further, when the transistor 1411 is operated in a linear region, the current I flowing through the light emitting element is expressed by Expression (9).

From Vth <0, equation (9) can be transformed into equation (10).

  Here, W is the channel width of the transistor 1411, L is the channel length, μ is the mobility, and Cox is the storage capacitance.

  From the equations (8) and (10), the current flowing through the light-emitting element 1416 does not depend on the threshold voltage (Vth) of the transistor 1411 when the operation region of the transistor 1411 is either the saturation region or the linear region. . Accordingly, variation in current value due to variation in threshold voltage of the transistor 1411 can be suppressed, and a current value corresponding to luminance data can be supplied to the light-emitting element 1416.

  From the above, variation in luminance due to variation in threshold voltage of the transistor 1411 can be suppressed. In addition, since the potential of the counter electrode is kept constant, power consumption can be reduced.

Further, in the case where the transistor 1411 is operated in the saturation region, variation in luminance due to deterioration of the light-emitting element 1416 can be suppressed. When the light-emitting element 1416 is deteriorated, V _{EL of the} light-emitting element 1416 is increased and the potential of the first electrode of the transistor 1411, that is, the potential of the source electrode is decreased. At this time, the source electrode of the transistor 1411 is connected to the second electrode of the capacitor 1415, the gate electrode of the transistor 1411 is connected to the first electrode of the capacitor 1415, and the gate electrode side is in a floating state. . Therefore, as the source potential decreases, the gate potential of the transistor 1411 also decreases by the same potential. Therefore, since Vgs of the transistor 1411 does not change, even if the light-emitting element is deteriorated, the current flowing through the transistor 1411 and the light-emitting element 1416 is not affected. Note that also in the equation (8), the current I flowing through the light emitting element does not depend on the source potential or the drain potential.

  Therefore, when the transistor 1411 is operated in the saturation region, variation in threshold voltage of the transistor 1411 and variation in luminance due to deterioration of the light-emitting element 1416 can be suppressed.

  Note that in the case where the transistor 1411 is operated in the saturation region, it is preferable that the channel length L of the transistor 1411 be long in order to suppress increase in current amount due to breakdown phenomenon or channel length modulation.

  In addition, since a reverse bias voltage is applied to the light-emitting element 1416 in the initialization period, a short-circuit portion in the light-emitting element can be insulated and deterioration of the light-emitting element can be suppressed. Therefore, the lifetime of the light emitting element can be extended.

  Note that there is no particular limitation on the light-emitting element 1416 illustrated in FIG. 14, and an EL element (an organic EL element, an inorganic EL element, or an EL element including an organic substance and an inorganic substance), an electron-emitting element, a liquid crystal element, electronic ink, or the like is applied. be able to.

  The transistor 1411 only needs to have a function of controlling a current value supplied to the light-emitting element 1416, and the type of the transistor is not particularly limited. Therefore, a thin film transistor (TFT) using a crystalline semiconductor film, a thin film transistor using a non-single crystal semiconductor film typified by amorphous silicon or polycrystalline silicon, a transistor formed using a semiconductor substrate or an SOI substrate, MOS Type transistors, junction type transistors, bipolar transistors, transistors using organic semiconductors or carbon nanotubes, and other transistors can be used.

  The first switch 1412 selects timing for inputting a signal in accordance with the gray scale of the pixel to the capacitor, and the second switch 1413 selects timing for applying a predetermined potential to the gate electrode of the transistor 1411. The third switch 1414 selects timing for applying a predetermined potential for initializing the potential written in the capacitor element 1415. Therefore, the first switch 1412, the second switch 1413, and the third switch 1414 are not particularly limited as long as they have the above functions. A transistor, a diode, or a logic circuit combining them may be used.

  Note that when a transistor is used, the polarity (conductivity type) is not particularly limited. However, it is preferable to use a transistor with low off-state current. As a transistor with low off-state current, there are a transistor provided with an LDD region and a transistor having a multi-gate structure. Further, a CMOS switch may be used by using both an N channel type and a P channel type.

  For example, when a P-channel transistor is applied to the first switch 1412, the second switch 1413, and the third switch 1414, an L level signal is used to turn on the scanning line that controls the on / off of each switch. However, when it is desired to turn it off, an H level signal is input.

  In this case, since a pixel can be formed using only P-channel transistors, the manufacturing process can be simplified.

  Furthermore, the pixels shown in this embodiment can be applied to the display device in FIG. 6, and as in Embodiment 1, if the data writing period in each row does not overlap, the initialization start time can be set freely in each row. Can do. Further, since each pixel can emit light except its own address period, the ratio of the light emission period in one frame period (that is, the duty ratio) can be very large, and can be almost 100%. Therefore, a display device with a small luminance variation and a high duty ratio can be obtained.

  Further, since the threshold writing period can be set long, the threshold voltage of the transistor that controls the value of the current flowing through the light-emitting element can be written into the capacitor more accurately. Therefore, the reliability as a display device is improved.

  Note that as in Embodiment 3, the potential supply line 1422 can be shared with wirings in other rows. Further, the transistor 1411 can have the transistor structure described in Embodiments 4 and 5. In addition, the configuration and operation described in Embodiment 6 can be applied. In this embodiment, the transistor 1411 can be applied to the pixel structure described in any of Embodiments 1 to 6.

  However, when a rectifying element is used to provide an erasing period, it is necessary to change the direction of the current flowing through the rectifying element depending on the polarity of the transistor that controls the current flowing through the light emitting element. This will be described with reference to FIG.

  In the case where the transistor 1411 is a P-channel transistor, the rectifier element 3201 is connected so that current flows from the fourth scan line 3202 to the gate electrode of the transistor 1411. The fourth scanning line 3202 receives an H level signal only when the transistor 1411 is forcibly turned off, and receives an L level signal otherwise. Then, when the fourth scanning line 3202 is at the L level, no current flows through the rectifier element 3201, and when it is at the H level, a current flows from the transistor 1411 to the fourth scanning line 3202. By flowing current through the fourth scan line 3202 in this manner, the potential held in the capacitor 1415 is set to be equal to or lower than the absolute value (| Vth |) of the threshold voltage of the transistor 1411 and the transistor 1411 is forcibly turned off. To. Note that the H level potential must be determined in consideration of the fact that the potential of the gate electrode of the transistor 1411 does not become equal to or higher than the potential of the forward threshold voltage of the rectifier element 3201 than the H level potential. By such an operation, a black display is inserted and an afterimage becomes difficult to see, and the moving image characteristics can be improved.

(Embodiment 8)
In this embodiment, one embodiment of a partial cross-sectional view of a pixel of the present invention is described with reference to FIG. Note that the transistor illustrated in the partial cross-sectional view in this embodiment is a transistor having a function of controlling a current value supplied to the light-emitting element.

  First, the base film 1712 is formed over the substrate 1711 having an insulating surface. As the substrate 1711 having an insulating surface, a glass substrate, a quartz substrate, a plastic substrate (polyimide, acrylic, polyethylene terephthalate, polycarbonate, polyarylate, polyethersulfone, etc.), an insulating substrate such as a ceramic substrate, a metal substrate (tantalum) In addition, an insulating film formed on the surface of a semiconductor substrate or the like can also be used. However, it is necessary to use a substrate that can withstand at least the heat generated during the process.

As the base film 1712, an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (SiO _x N _y ) is used, and these insulating films are formed as a single layer or two or more layers. Note that the base film 1712 may be formed by a sputtering method, a CVD method, or the like. In this embodiment, the base film 1712 is a single layer, but of course, two or more layers may be used.

  Next, a transistor 1713 is formed over the base film 1712. The transistor 1713 includes at least a semiconductor layer 1714, a gate insulating film 1715 formed over the semiconductor layer 1714, and a gate electrode 1716 formed over the semiconductor layer 1714 with the gate insulating film 1715 interposed therebetween. 1714 has a source region and a drain region.

  The semiconductor layer 1714 includes an amorphous semiconductor (a-Si: H), an amorphous semiconductor mainly containing silicon, silicon germanium (SiGe), or the like, and a semi-amorphous semiconductor in which an amorphous state and a crystalline state are mixed. , And a film having an amorphous state selected from microcrystalline semiconductors capable of observing crystal grains of 0.5 nm to 20 nm in an amorphous semiconductor (that is, an amorphous semiconductor film) or poly A crystalline semiconductor film such as silicon (p-Si: H) can be used. Note that a microcrystalline state in which crystal grains of 0.5 nm to 20 nm can be observed is called a so-called microcrystal. Note that when an amorphous semiconductor film is used for the semiconductor layer 1714, a sputtering method, a CVD method, or the like may be used. When a crystalline semiconductor film is used, for example, an amorphous semiconductor film is formed. Further crystallization may be performed later. Further, if necessary, a small amount of impurity elements (phosphorus, arsenic, boron, etc.) may be included in addition to the main component in order to control the threshold value of the transistor.

  Next, a gate insulating film 1715 is formed so as to cover the semiconductor layer 1714. The gate insulating film 1715 is formed by stacking a single layer or a plurality of films using, for example, silicon oxide, silicon nitride, silicon nitride oxide, or the like. Note that a CVD method, a sputtering method, or the like can be used as a film formation method.

  Subsequently, a gate electrode 1716 is formed over the semiconductor layer 1714 with a gate insulating film 1715 interposed therebetween. The gate electrode 1716 may be formed as a single layer or a stack of a plurality of metal films. The gate electrode is not only a metal element selected from tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), etc. Also, it can be formed of an alloy material or a compound material containing the element as a main component. For example, tantalum nitride (TaN) may be used as the first conductive layer and tungsten (W) may be used as the second conductive layer, and the gate electrode may be formed of a first conductive film and a second conductive film.

  Next, an impurity imparting n-type or p-type conductivity is selectively added to the semiconductor layer 1714 using the gate electrode 1716 or a resist formed in a desired shape as a mask. In this manner, a channel formation region and an impurity region (including a source region, a drain region, a GOLD region, and an LDD region) are formed in the semiconductor layer 1714. In addition, an n-channel transistor or a p-channel transistor can be distinguished from each other depending on the conductivity type of the added impurity element.

  In FIG. 17, in order to manufacture the LDD region 1720 in a self-aligned manner, a silicon compound such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed so as to cover the gate electrode 1716, and then etched back. Thus, a sidewall 1717 is formed. After that, an impurity imparting conductivity is added to the semiconductor layer 1714, whereby the source region 1718, the drain region 1719, and the LDD region 1720 can be formed. Therefore, the LDD region 1720 is located below the sidewall 1717. Note that the sidewall 1717 is provided in order to form the LDD region 1720 in a self-aligning manner, and is not necessarily provided. Note that phosphorus, arsenic, boron, or the like is used as the impurity imparting conductivity.

Next, a first insulating film 1721 and a second insulating film 1722 are stacked and formed as the first interlayer insulating film 1730 so as to cover the gate electrode 1716. As the first insulating film 1721 and the second insulating film 1722, an inorganic insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (SiO _x N _y ), or an organic resin film having a low dielectric constant (photosensitive) Or non-photosensitive organic resin film) can be used. Alternatively, a film containing siloxane may be used. Note that siloxane is a material having a skeleton structure formed of a bond of silicon (Si) and oxygen (O), and an organic group (for example, an alkyl group or aromatic hydrocarbon) is used as a substituent. Further, the substituent may contain a fluoro group.

  Note that an insulating film of the same material may be used for the first insulating film 1721 and the second insulating film 1722. In this embodiment, the first interlayer insulating film 1730 has a two-layer structure, but may have a single layer structure or a three-layer structure or more.

  Note that the first insulating film 1721 and the second insulating film 1722 may be formed by a sputtering method, a CVD method, a spin coating method, or the like. When an organic resin film or a film containing siloxane is used, a coating method is used. What is necessary is just to form using.

  Thereafter, a source electrode and a drain electrode 1723 are formed over the first interlayer insulating film 1730. Note that the source electrode and the drain electrode 1723 are connected to a source region 1718 and a drain region 1719 through contact holes, respectively.

  Note that the source and drain electrodes 1723 are formed of silver (Ag), gold (Au), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), rhodium (Rh), Tungsten (W), aluminum (Al), tantalum (Ta), molybdenum (Mo), cadmium (Cd), zinc (Zn), iron (Fe), titanium (Ti), silicon (Si), germanium (Ge), A metal such as zirconium (Zr) or barium (Ba) or an alloy thereof, a metal nitride thereof, or a stacked film thereof can be used.

  Next, a second interlayer insulating film 1731 is formed so as to cover the source and drain electrodes 1723. As the second interlayer insulating film 1731, an inorganic insulating film, a resin film, or a stacked layer thereof can be used. As the inorganic insulating film, a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a film in which these are stacked can be used. As the resin film, polyimide, polyamide, acrylic, polyimide amide, epoxy, or the like can be used.

  A pixel electrode 1724 is formed over the second interlayer insulating film 1731. Next, an insulator 1725 is formed so as to cover an end portion of the pixel electrode 1724. The insulator 1725 is preferably formed so that the upper end portion or the lower end portion of the insulator 1725 has a curved surface in order to improve the formation of the layer 1726 containing a light-emitting substance to be formed later. For example, in the case where positive photosensitive acrylic is used as a material for the insulator 1725, it is preferable that only the upper end portion of the insulator 1725 has a curved surface with a curvature radius (0.2 μm to 3 μm). As the insulator 1725, either a negative type that becomes insoluble in an etchant by photosensitive light or a positive type that becomes soluble in an etchant by light can be used. Furthermore, the material of the insulator 1725 is not limited to an organic material, and an inorganic material such as silicon oxide or silicon oxynitride can also be used.

  Next, a layer 1726 containing a light-emitting substance and a counter electrode 1727 are formed over the pixel electrode 1724 and the insulator 1725.

  Note that a light-emitting element 1728 is formed in a region where the layer 1726 containing a light-emitting substance is sandwiched between the pixel electrode 1724 and the counter electrode 1727.

  Next, details of the light-emitting element 1728 will be described with reference to FIGS. Note that the pixel electrode 1724 and the counter electrode 1727 in FIG. 17 correspond to the pixel electrode 1801 and the counter electrode 1802 in FIG. 18, respectively. In FIG. 18A, the pixel electrode is an anode and the counter electrode is a cathode.

  As shown in FIG. 18A, between the pixel electrode 1801 and the counter electrode 1802, in addition to the light emitting layer 1813, a hole injection layer 1811, a hole transport layer 1812, an electron transport layer 1814, and an electron injection layer 1815. Etc. are also provided. In these layers, holes are injected from the pixel electrode 1801 side and electrons are injected from the counter electrode 1802 side when a voltage is applied so that the potential of the pixel electrode 1801 is higher than the potential of the counter electrode 1802. Are stacked.

  In such a light-emitting element, holes injected from the pixel electrode 1801 and electrons injected from the counter electrode 1802 are recombined in the light-emitting layer 1813 so that the light-emitting substance is excited. Then, light is emitted when the excited light-emitting substance returns to the ground state. Note that the light-emitting substance may be any substance that can obtain luminescence (electroluminescence).

  There is no particular limitation on the substance forming the light-emitting layer 1813, and a layer formed using only the light-emitting substance may be used. However, when concentration quenching occurs, a substance having an energy gap larger than that of the light-emitting substance ( A layer in which a light emitting substance is dispersed in a layer made of a host is preferable. Thereby, concentration quenching of the luminescent material can be prevented. Note that the energy gap is an energy difference between the lowest unoccupied molecular orbital (LUMO) level and the highest occupied molecular orbital (HOMO) level.

  There is no particular limitation on the light-emitting substance, and a substance that can emit light with a desired emission wavelength may be used. For example, to obtain red light emission, 4-dicyanomethylene-2-isopropyl-6- [2- (1,1,7,7-tetramethyljulolidin-9-yl) ethenyl] -4H-pyran ( Abbreviation: DCJTI), 4-dicyanomethylene-2-methyl-6- [2- (1,1,7,7-tetramethyljulolidin-9-yl) ethenyl] -4H-pyran (abbreviation: DCJT), 4 -Dicyanomethylene-2-tert-butyl-6- [2- (1,1,7,7-tetramethyljulolidin-9-yl) ethenyl] -4H-pyran (abbreviation: DCJTB), periflanthene, 2,5 -Dicyano-1,4-bis [2- (10-methoxy-1,1,7,7-tetramethyljulolidin-9-yl) ethenyl] benzene, etc., emission spectrum from 600 nm to 680 nm It can be used and a substance which exhibits emission with a peak. When green light emission is desired, N, N′-dimethylquinacridone (abbreviation: DMQd), coumarin 6 or coumarin 545T, tris (8-quinolinolato) aluminum (abbreviation: Alq), N, N′-diphenyl A substance exhibiting light emission having a peak of an emission spectrum from 500 nm to 550 nm, such as quinacridone (abbreviation: DPQd), can be used. When blue light emission is desired, 9,10-bis (2-naphthyl) -tert-butylanthracene (abbreviation: t-BuDNA), 9,9′-bianthryl, 9,10-diphenylanthracene (abbreviation) : DPA), 9,10-bis (2-naphthyl) anthracene (abbreviation: DNA), bis (2-methyl-8-quinolinolato) -4-phenylphenolato-gallium (BGaq), bis (2-methyl-8) -Quinolinolato) -4-phenylphenolato-aluminum (BAlq) or the like can be used a substance that emits light having an emission spectrum peak from 420 nm to 500 nm.

There is no particular limitation on a substance used for dispersing the light-emitting substance, for example, an anthracene derivative such as 9,10-di (2-naphthyl) -2-tert-butylanthracene (abbreviation: t-BuDNA), or In addition to carbazole derivatives such as 4,4′-bis (N-carbazolyl) biphenyl (abbreviation: CBP), bis [2- (2-hydroxyphenyl) pyridinato] zinc (abbreviation: Znpp ₂ ), bis [2- (2 Metal complexes such as -hydroxyphenyl) benzoxazolate] zinc (abbreviation: ZnBOX) can be used.

  The anode material for forming the pixel electrode 1801 is not particularly limited, but it is preferable to use a metal, an alloy, an electrically conductive compound, a mixture thereof, or the like having a high work function (work function of 4.0 eV or more). As specific examples of such an anode material, as an oxide of a metal material, indium tin oxide (abbreviation: ITO), ITO containing silicon oxide, 2-20 wt% zinc oxide (ZnO) in indium oxide. ) In addition to indium zinc oxide (abbreviation: IZO), gold (Au), platinum (Pt), nickel (Ni), tungsten (W), chromium (Cr), molybdenum ( Mo), iron (Fe), cobalt (Co), copper (Cu), palladium (Pd), a nitride of a metal material (for example, TiN), and the like can be given.

  On the other hand, as a material for forming the counter electrode 1802, a metal, an alloy, an electrically conductive compound, a mixture thereof, or the like having a low work function (work function of 3.8 eV or less) can be used. Specific examples of such a cathode material include elements belonging to Group 1 or Group 2 of the periodic table, that is, alkali metals such as lithium (Li) and cesium (Cs), magnesium (Mg), calcium (Ca), strontium ( Alkaline earth metals such as Sr) and alloys containing them (Mg: Ag, Al: Li). Further, by providing a layer having excellent electron-injecting properties between the counter electrode 1802 and the light-emitting layer 1813 so as to be stacked with the counter electrode, Al, Ag, ITO, silicon oxide, regardless of the work function. Various conductive materials including the materials mentioned as the material of the pixel electrode 1801 such as ITO containing ITO can be used as the counter electrode 1802. Further, the same effect can be obtained by using a material having an excellent function of injecting electrons for the electron injection layer 1815 described later.

  Note that in order to extract emitted light to the outside, one or both of the pixel electrode 1801 and the counter electrode 1802 are formed with a transparent electrode such as ITO, or with a thickness of several to several tens of nm so that visible light can be transmitted. It is preferable that the electrode is made.

  A hole transport layer 1812 is provided between the pixel electrode 1801 and the light emitting layer 1813 as shown in FIG. The hole transport layer is a layer having a function of transporting holes injected from the pixel electrode 1801 to the light emitting layer 1813. In this manner, by providing the hole transport layer 1812 and separating the pixel electrode 1801 and the light-emitting layer 1813, it is possible to prevent the light emission from being quenched due to the metal.

Note that the hole-transport layer 1812 is preferably formed using a substance having a high hole-transport property, and particularly, a substance having a hole mobility of 1 × 10 ⁻⁶ cm ² / Vs or higher. It is preferable. Note that a substance having a high hole-transport property refers to a substance having a higher hole mobility than electrons. Specific examples of a substance that can be used for forming the hole-transport layer 1812 include 4,4′-bis [N- (1-naphthyl) -N-phenylamino] biphenyl (abbreviation: NPB), 4, 4′-bis [N- (3-methylphenyl) -N-phenylamino] biphenyl (abbreviation: TPD), 4,4 ′, 4 ″ -tris (N, N-diphenylamino) triphenylamine (abbreviation: TDATA), 4,4 ′, 4 ″ -tris [N- (3-methylphenyl) -N-phenylamino] triphenylamine (abbreviation: MTDATA), 4,4′-bis {N- [4- ( N, N-di-m-tolylamino) phenyl] -N-phenylamino} biphenyl (abbreviation: DNTPD), 1,3,5-tris [N, N-di (m-tolyl) amino] benzene (abbreviation: m -MTDAB), 4, 4 ', 4 " Tris (N- carbazolyl) triphenylamine (abbreviation: TCTA), phthalocyanine _{(abbreviation:} H 2 Pc), copper phthalocyanine (abbreviation: CuPc), or vanadyl phthalocyanine (abbreviation: VOPc), and the like. Further, the hole transport layer 1812 may be a layer having a multilayer structure formed by combining two or more layers made of the above-described substances.

  Further, an electron transport layer 1814 may be provided between the counter electrode 1802 and the light emitting layer 1813 as shown in FIG. Here, the electron transporting layer is a layer having a function of transporting electrons injected from the counter electrode 1802 to the light emitting layer 1813. In this manner, by providing the electron transport layer 1814 and separating the counter electrode 1802 and the light-emitting layer 1813, the light emission can be prevented from being quenched due to the metal.

The electron-transport layer 1814 is not particularly limited, and tris (8-quinolinolato) aluminum (abbreviation: Alq), tris (4-methyl-8-quinolinolato) aluminum (abbreviation: Almq ₃ ), bis (10-hydroxybenzo [h] -Quinolinato) beryllium (abbreviation: BeBq ₂ ), bis (2-methyl-8-quinolinolato) -4-phenylphenolato-aluminum (abbreviation: BAlq), etc. Can be used. In addition, bis [2- (2-hydroxyphenyl) -benzoxazolate] zinc (abbreviation: Zn (BOX) ₂ ), bis [2- (2-hydroxyphenyl) -benzothiazolate] zinc (abbreviation: Zn (BTZ) ) ₂ ) and the like may be formed by a metal complex having an oxazole-based or thiazole-based ligand. In addition, 2- (4-biphenylyl) -5- (4-tert-butylphenyl) -1,3,4-oxadiazole (abbreviation: PBD), 1,3-bis [5- (p-tert- Butylphenyl) -1,3,4-oxadiazol-2-yl] benzene (abbreviation: OXD-7), 3- (4-tert-butylphenyl) -4-phenyl-5- (4-biphenylyl)- 1,2,4-triazole (abbreviation: TAZ), 3- (4-tert-butylphenyl) -4- (4-ethylphenyl) -5- (4-biphenylyl) -1,2,4-triazole (abbreviation) : P-EtTAZ), bathophenanthroline (abbreviation: BPhen), bathocuproin (abbreviation: BCP), or the like. The electron transport layer 1814 is preferably formed using a substance having higher electron mobility than the hole mobility described above. The electron transport layer 1814 is more preferably formed using a substance having an electron mobility of 10 ⁻⁶ cm ² / Vs or higher. Note that the electron-transport layer 1814 may have a multilayer structure formed by combining two or more layers formed of the substances described above.

  Further, a hole injection layer 1811 may be provided between the pixel electrode 1801 and the hole transport layer 1812 as shown in FIG. Here, the hole injection layer is a layer having a function of promoting injection of holes from the electrode functioning as an anode into the hole transport layer 1812.

The hole injection layer 1811 is not particularly limited, and metal oxides such as molybdenum oxide (MoOx), vanadium oxide (VOx), ruthenium oxide (RuOx), tungsten oxide (WOx), and manganese oxide (MnOx) Can be used. In addition, phthalocyanine compounds such as phthalocyanine (abbreviation: H ₂ Pc) and copper phthalocyanine (CuPc), 4,4-bis (N- (4- (N, N-di-m-tolylamino) phenyl) -N -Hole injection by aromatic amine compounds such as phenylamino) biphenyl (abbreviation: DNTPD) or polymers such as poly (ethylenedioxythiophene) / poly (styrenesulfonic acid) aqueous solution (PEDOT / PSS) A layer 1811 can be formed.

  Alternatively, a mixture of the metal oxide and a substance having a high hole-transport property may be provided between the pixel electrode 1801 and the hole-transport layer 1812. Since such a layer does not increase the driving voltage even when it is thickened, an optical design utilizing the microcavity effect or the light interference effect can be performed by adjusting the film thickness of the layer. Therefore, a high-quality light-emitting element with excellent color purity and a small color change depending on the viewing angle can be manufactured. In addition, a film thickness that prevents the pixel electrode 1801 and the counter electrode 1802 from being short-circuited by the influence of unevenness generated on the surface of the pixel electrode 1801 or a minute residue remaining on the electrode surface can be selected.

  Further, an electron injection layer 1815 may be provided between the counter electrode 1802 and the electron transport layer 1814 as shown in FIG. Here, the electron injection layer is a layer having a function of promoting injection of electrons from the electrode functioning as a cathode into the electron transport layer 1814. Note that in the case where an electron transport layer is not particularly provided, an electron injection layer may be provided between the electrode functioning as a cathode and the light emitting layer to assist the injection of electrons into the light emitting layer.

The electron injection layer 1815 is not particularly limited, and is formed using an alkali metal or alkaline earth metal compound such as lithium fluoride (LiF), cesium fluoride (CsF), calcium fluoride (CaF ₂ ), or the like. Things can be used. In addition, a substance having a high electron transport property such as Alq or 4,4-bis (5-methylbenzoxazol-2-yl) stilbene (BzOs), and an alkali metal or alkaline earth such as magnesium or lithium. A material mixed with a similar metal can also be used as the electron injection layer 1815.

  Note that the hole injection layer 1811, the hole transport layer 1812, the light-emitting layer 1813, the electron transport layer 1814, and the electron injection layer 1815 can be formed by any method such as an evaporation method, an inkjet method, or a coating method, respectively. I do not care. Further, the pixel electrode 1801 or the counter electrode 1802 may be formed by any method such as a sputtering method or an evaporation method.

  In addition, the layer structure of the light-emitting element is not limited to that illustrated in FIG. 18A, and may be sequentially formed from an electrode functioning as a cathode as illustrated in FIG. In other words, the pixel electrode 1801 is used as a cathode, and an electron injection layer 1815, an electron transport layer 1814, a light emitting layer 1813, a hole transport layer 1812, a hole injection layer 1811, and a counter electrode 1802 are stacked in this order on the pixel electrode 1801. good. Note that the counter electrode 1802 functions as an anode.

  Note that although the light-emitting element has a single light-emitting layer, it may have a plurality of light-emitting layers. White light can be obtained by providing a plurality of light emitting layers and mixing light emitted from the respective light emitting layers. For example, in the case of a light-emitting element having two light-emitting layers, an interval layer, a layer that generates holes, and a layer that generates electrons may be provided between the first light-emitting layer and the second light-emitting layer. preferable. With such a configuration, each light emitted to the outside is visually mixed and visually recognized as white light. Therefore, white light can be obtained.

  Light emission is extracted to the outside through one or both of the pixel electrode 1724 and the counter electrode 1727 in FIG. Accordingly, one or both of the pixel electrode 1724 and the counter electrode 1727 are formed using a light-transmitting substance.

  When only the counter electrode 1727 is made of a light-transmitting substance, light emission is extracted from the opposite side of the substrate through the counter electrode 1727 as shown in FIG. In the case where only the pixel electrode 1724 is made of a light-transmitting substance, light emission is extracted from the substrate side through the pixel electrode 1724 as shown in FIG. In the case where both the pixel electrode 1724 and the counter electrode 1727 are made of a light-transmitting substance, light emission passes through the pixel electrode 1724 and the counter electrode 1727 as shown in FIG. Taken from both sides.

  Next, a transistor with a staggered structure in which an amorphous semiconductor film is used for the transistor 1713 as a semiconductor layer is described. A partial cross-sectional view of the pixel is shown in FIG. Note that in FIG. 20, a forward staggered transistor is shown, and a capacitor included in the pixel is also described.

  As illustrated in FIG. 20, a base film 2012 is formed over a substrate 2011. Further, a pixel electrode 2013 is formed on the base film 2012. A first electrode 2014 made of the same material is formed in the same layer as the pixel electrode 2013.

  Further, a wiring 2015 and a wiring 2016 are formed over the base film 2012, and an end portion of the pixel electrode 2013 is covered with the wiring 2015. Over the wiring 2015 and the wiring 2016, an N-type semiconductor layer 2017 and an N-type semiconductor layer 2018 having an N-type conductivity are formed. A semiconductor layer 2019 is formed over the base film 2012 between the wiring 2015 and the wiring 2016. A part of the semiconductor layer 2019 extends to the N-type semiconductor layer 2017 and the N-type semiconductor layer 2018. Note that this semiconductor layer is formed of an amorphous semiconductor film such as an amorphous semiconductor such as amorphous silicon (a-Si: H), a semi-amorphous semiconductor, or a microcrystalline semiconductor. A gate insulating film 2020 is formed over the semiconductor layer 2019. An insulating film 2021 made of the same material and in the same layer as the gate insulating film 2020 is also formed over the first electrode 2014.

  Further, a gate electrode 2022 is formed over the gate insulating film 2020, and a transistor 2025 is formed. A second electrode 2023 made of the same material and in the same layer as the gate electrode 2022 is formed over the first electrode 2014 with an insulating film 2021 interposed therebetween, and the insulating film 2021 is formed of the first electrode 2014 and the second electrode 2023. A capacitor element 2024 having a structure sandwiched between and is formed. An interlayer insulating film 2026 is formed so as to cover the end portion of the pixel electrode 2013, the transistor 2025, and the capacitor 2024.

  A region 2027 containing a light emitting substance and a counter electrode 2028 are formed over the interlayer insulating film 2026 and the pixel electrode 2013 located in the opening, and the layer 2027 containing the light emitting substance is sandwiched between the pixel electrode 2013 and the counter electrode 2028. Thus, a light emitting element 2029 is formed.

  20A. The first electrode 2014 shown in FIG. 20A is formed of the same material in the same layer as the wirings 2015 and 2016 as shown in FIG. 20B, and the insulating film 2021 is formed with the first electrode 2030 and the second electrode. The capacitor 2031 may be sandwiched between the electrodes 2023. In FIG. 20, an N-channel transistor is used as the transistor 2025; however, a P-channel transistor may be used.

  The materials used for the substrate 2011, the base film 2012, the pixel electrode 2013, the gate insulating film 2020, the gate electrode 2022, the interlayer insulating film 2026, the layer 2027 containing the light-emitting substance, and the counter electrode 2028 are the substrate 1711 and the base film described in FIG. 1712, the pixel electrode 1724, the gate insulating film 1715, the gate electrode 1716, the interlayer insulating films 1730 and 1731, the layer 1726 containing a light-emitting substance, and the counter electrode 1727 can be used. The wiring 2015 and the wiring 2016 may be formed using a material similar to that of the source and drain electrodes 1723 in FIG.

  Next, as another structure of a transistor using an amorphous semiconductor film as a semiconductor layer, a structure in which a gate electrode is sandwiched between a substrate and a semiconductor layer, that is, a bottom gate in which the gate electrode is located under the semiconductor layer FIG. 21 is a partial cross-sectional view of a pixel having a type transistor.

  A base film 2112 is formed over the substrate 2111. Further, a gate electrode 2113 is formed over the base film 2112. A first electrode 2114 made of the same material is formed in the same layer as the gate electrode 2113. The material of the gate electrode 2113 may be polycrystalline silicon to which phosphorus is added or silicide which is a compound of metal and silicon, in addition to the material used for the gate electrode 1716 in FIG.

  A gate insulating film 2115 is formed so as to cover the gate electrode 2113 and the first electrode 2114.

  A semiconductor layer 2116 is formed over the gate insulating film 2115. In addition, a semiconductor layer 2117 made of the same material as the semiconductor layer 2116 is formed over the first electrode 2114. Note that this semiconductor layer is formed of an amorphous semiconductor film such as an amorphous semiconductor such as amorphous silicon (a-Si: H), a semi-amorphous semiconductor, or a microcrystalline semiconductor.

  An N-type semiconductor layer 2118 and an N-type semiconductor layer 2119 having an N-type conductivity are formed over the semiconductor layer 2116, and an N-type semiconductor layer 2120 is formed over the semiconductor layer 2117.

  A wiring 2121 and a wiring 2122 were formed over the N-type semiconductor layer 2118 and the N-type semiconductor layer 2119, respectively, and a transistor 2129 was formed. A conductive layer 2123 made of the same material as the wiring 2121 and the wiring 2122 is formed over the N-type semiconductor layer 2120, and the conductive layer 2123, the N-type semiconductor layer 2120, and the semiconductor layer 2117 are second layers. The electrode is comprised. Note that a capacitor 2130 having a structure in which the gate insulating film 2115 is sandwiched between the second electrode and the first electrode 2114 is formed.

  One end of the wiring 2121 extends, and a pixel electrode 2124 is formed in contact with the upper part of the extended wiring 2121.

  An insulator 2125 is formed so as to cover an end portion of the pixel electrode 2124, the transistor 2129, and the capacitor 2130.

  A layer 2126 containing a light-emitting substance and a counter electrode 2127 are formed over the pixel electrode 2124 and the insulator 2125, and a light-emitting element 2128 is formed in a region where the layer 2126 containing a light-emitting substance is sandwiched between the pixel electrode 2124 and the counter electrode 2127. Has been.

  The semiconductor layer 2117 and the N-type semiconductor layer 2120 which are part of the second electrode of the capacitor 2130 are not necessarily provided. That is, the capacitor may have a structure in which the second electrode is the conductive layer 2123 and the gate insulating film 2115 is sandwiched between the first electrode 2114 and the conductive layer 2123.

  Further, although an N-channel transistor is used as the transistor 2129, a P-channel transistor may be used.

  Note that in FIG. 21A, the pixel electrode 2124 is formed before the wiring 2121 is formed, so that the second electrode 2131 made of the same material as that of the pixel electrode 2124 as shown in FIG. A capacitor 2132 having a structure in which the gate insulating film 2115 is sandwiched between the first electrode 2114 and the first electrode 2114 can also be formed.

  Although an inverted staggered channel etch transistor has been described, a channel protection transistor may of course be used. Next, the case of a transistor having a channel protective structure will be described with reference to FIGS. Note that in FIG. 22, the same components as those in FIG. 21 are denoted by common reference numerals.

  The transistor 2201 having a channel protection structure illustrated in FIG. 22A is different from the transistor 2129 having a channel etch structure illustrated in FIG. 21A as an etching mask over a region where a channel is formed in the semiconductor layer 2116. The difference is that an object 2202 is provided.

  Similarly, the transistor 2201 having a channel protection structure illustrated in FIG. 22B is different from the transistor 2129 having a channel etching structure illustrated in FIG. 21B in an etching mask over a region where a channel is formed in the semiconductor layer 2116. This is different in that an insulator 2202 is provided.

  By using an amorphous semiconductor film for a semiconductor layer of a transistor included in the pixel of the present invention, manufacturing cost can be reduced. In addition, what was demonstrated in FIG. 17 can be used for each material.

  Further, the structure of the transistor and the structure of the capacitor are not limited to those described above, and transistors and capacitors having various structures or configurations can be used.

  In addition, the semiconductor layer of the transistor includes amorphous semiconductor such as amorphous silicon (a-Si: H), non-crystalline semiconductor film such as semi-amorphous semiconductor, microcrystalline semiconductor, and polysilicon (p-Si: H). A crystalline semiconductor film such as) may be used.

  FIG. 23 is a partial cross-sectional view of a pixel including a transistor using a crystalline semiconductor film as a semiconductor layer, which will be described below. Note that the transistor 2318 illustrated in FIG. 23 is the multi-gate transistor illustrated in FIG.

  As shown in FIG. 23, a base film 2302 is formed on a substrate 2301, and a semiconductor layer 2303 is formed thereon. Note that the semiconductor layer 2303 is formed by patterning a crystalline semiconductor film into a desired shape.

  An example of a method for manufacturing a crystalline semiconductor film is described below. First, an amorphous silicon film is formed over the substrate 2301 by a sputtering method, a CVD method, or the like. The film forming material need not be limited to an amorphous silicon film, but may be an amorphous semiconductor film such as an amorphous semiconductor, a semi-amorphous semiconductor, or a microcrystalline semiconductor. Alternatively, a compound semiconductor film including an amorphous structure such as an amorphous silicon germanium film may be used.

  Then, the amorphous silicon film thus formed is crystallized using a thermal crystallization method, a laser crystallization method, a thermal crystallization method using a catalyst element such as nickel, or the like to obtain a crystalline semiconductor film. In addition, you may crystallize combining these crystallization methods.

  In the case of forming a crystalline semiconductor film by a thermal crystallization method, a heating furnace, laser irradiation, RTA (Rapid Thermal Annealing), or a combination thereof can be used.

In the case of forming a crystalline semiconductor film by a laser crystallization method, a continuous wave laser beam (CW laser beam) or a pulsed laser beam (pulse laser beam) can be used. The laser beam that can be used here is a gas laser such as an Ar laser, a Kr laser, or an excimer laser, single crystal YAG, YVO ₄ , forsterite (Mg ₂ SiO ₄ ), YAlO ₃ , GdVO ₄ , or polycrystalline ( (Ceramics) YAG, Y ₂ O ₃ , YVO ₄ , YAlO ₃ , GdVO ₄ with one or more of Nd, Yb, Cr, Ti, Ho, Er, Tm, Ta added as dopants A laser oscillated from one or more of laser, glass laser, ruby laser, alexandrite laser, Ti: sapphire laser, copper vapor laser, or gold vapor laser as a medium can be used. By irradiating the fundamental wave of such a laser beam and the second to fourth harmonic laser beams of these fundamental waves, a crystal having a large grain size can be obtained. For example, a second harmonic (532 nm) or a third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm) can be used. Energy density of the laser is about 0.01 to 100 MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation is performed at a scanning speed of about 10 to 2000 cm / sec.

Note that single crystal YAG, YVO ₄ , forsterite (Mg ₂ SiO ₄ ), YAlO ₃ , GdVO ₄ , or polycrystalline (ceramic) YAG, Y ₂ O ₃ , YVO ₄ , YAlO ₃ , GdVO ₄ , dopants Nd, Yb, Cr, Ti, Ho, Er, Tm, Ta, a laser using a medium added with one or more, an Ar ion laser, or a Ti: sapphire laser should oscillate continuously It is also possible to perform pulse oscillation at an oscillation frequency of 10 MHz or more by performing Q switch operation, mode synchronization, or the like. When the laser beam is oscillated at an oscillation frequency of 10 MHz or more, the semiconductor film is irradiated with the next pulse during the period from when the semiconductor film is melted by the laser to solidification. Therefore, unlike the case of using a pulse laser having a low oscillation frequency, the solid-liquid interface can be continuously moved in the semiconductor film, so that crystal grains continuously grown in the scanning direction can be obtained.

  In the case where a crystalline semiconductor film is formed by a thermal crystallization method using a catalyst element such as nickel, it is preferable to perform a gettering process for removing the catalyst element such as nickel after crystallization.

  By the above crystallization, a partially crystallized region is formed in the amorphous semiconductor film. This partially crystallized crystalline semiconductor film is patterned into a desired shape to form an island-shaped semiconductor film. This semiconductor film is used for the semiconductor layer 2303 of the transistor.

  The crystalline semiconductor layer is used for the channel formation region 2304 of the transistor 2318 and the impurity region 2305 to be a source region or a drain region, and also to the semiconductor layer 2306 and the impurity region 2308 to be a lower electrode of the capacitor 2319. . Note that the impurity region 2308 is not necessarily provided. In addition, channel doping may be performed on the channel formation region 2304 and the semiconductor layer 2306.

  Next, a gate insulating film 2309 is formed over the semiconductor layer 2303 and the lower electrode of the capacitor 2319. Further, a gate electrode 2310 is formed over the semiconductor layer 2303 through a gate insulating film 2309, and an upper electrode made of the same material as the gate electrode 2310 is formed over the semiconductor layer 2306 of the capacitor 2319 through the gate insulating film 2309. 2311 is formed. In this manner, the transistor 2318 and the capacitor 2319 are manufactured.

  Next, an interlayer insulating film 2312 is formed so as to cover the transistor 2318 and the capacitor 2319, and a wiring 2313 in contact with the impurity region 2305 is formed over the interlayer insulating film 2312 through a contact hole. A pixel electrode 2314 is formed on the interlayer insulating film 2312 so as to be in contact with the wiring 2313, and an insulator 2315 is formed so as to cover an end portion of the pixel electrode 2314 and the wiring 2313. Further, a layer 2316 containing a light-emitting substance and a counter electrode 2317 are formed over the pixel electrode 2314, and a light-emitting element 2320 is formed in a region where the layer 2316 containing a light-emitting substance is sandwiched between the pixel electrode 2314 and the counter electrode 2317. .

  FIG. 24 shows a partial cross section of a pixel having a bottom-gate transistor using a crystalline semiconductor film such as polysilicon (p-Si: H) as a semiconductor layer.

  A base film 2402 is formed over a substrate 2401, and a gate electrode 2403 is formed thereon. The first electrode 2404 of the capacitor 2423 made of the same material is formed in the same layer as the gate electrode 2403.

  A gate insulating film 2405 is formed so as to cover the gate electrode 2403 and the first electrode 2404.

  In addition, a semiconductor layer is formed over the gate insulating film 2405. Note that the semiconductor film may be an amorphous semiconductor film such as an amorphous semiconductor, a semi-amorphous semiconductor, or a microcrystalline semiconductor, a thermal crystallization method, a laser crystallization method, or a thermal crystallization method using a catalytic element such as nickel. Is then crystallized and patterned into a desired shape to form a semiconductor layer.

  Note that the semiconductor layer is used to form a channel formation region 2406, an LDD region 2407, and an impurity region 2408 to be a source region or a drain region of the transistor 2422, a region 2409 to be a second electrode of the capacitor 2423, an impurity region 2410, and an impurity region. 2411 is formed. Note that the impurity region 2410 and the impurity region 2411 are not necessarily provided. Further, the channel formation region 2406 and the region 2409 may be doped with impurities.

  Note that the capacitor 2423 has a structure in which the gate insulating film 2405 is sandwiched between the first electrode 2404 and the second electrode including the region 2409 formed of the semiconductor layer.

  Next, a first interlayer insulating film 2412 is formed to cover the semiconductor layer, and a wiring 2413 that is in contact with the impurity region 2408 through a contact hole is formed over the first interlayer insulating film 2412.

  An opening 2415 is formed in the first interlayer insulating film 2412. A second interlayer insulating film 2416 is formed so as to cover the transistor 2422, the capacitor 2423, and the opening 2415. A pixel electrode 2417 connected to the wiring 2413 through a contact hole is formed over the second interlayer insulating film 2416. Is formed. In addition, an insulator 2418 is formed to cover an end portion of the pixel electrode 2417. A layer 2419 containing a light-emitting substance and a counter electrode 2420 are formed over the pixel electrode 2417, and a light-emitting element 2421 is formed in a region where the layer 2419 containing a light-emitting substance is sandwiched between the pixel electrode 2417 and the counter electrode 2420. . Note that an opening 2415 is located below the light emitting element 2421. In other words, when light emitted from the light-emitting element 2421 is extracted from the substrate side, the transmittance can be increased because the opening 2415 is provided in the first interlayer insulating film 2412.

  By using a crystalline semiconductor film for a semiconductor layer of a transistor included in the pixel of the present invention, for example, the scan line driver circuit 612 and the signal line driver circuit 611 in FIG. 6 can be easily formed integrally with the pixel portion 613. .

  Note that the structure of a transistor including a crystalline semiconductor film as a semiconductor layer is not limited to the above structure, and various structures can be employed. The same applies to the capacitive element. Moreover, in this embodiment, the material in FIG. 17 can be used suitably unless there is particular notice.

  The transistor described in this embodiment can be used as a transistor for controlling a current value supplied to a light-emitting element in the pixel described in any of Embodiments 1 to 7. Therefore, by operating a pixel as described in Embodiments 1 to 7, variation in current value due to variation in threshold voltage of a transistor can be suppressed. Therefore, a current corresponding to the luminance data can be supplied to the light emitting element, and variations in luminance can be suppressed. In addition, since the counter electrode is operated at a constant potential, power consumption can be reduced.

  Further, by applying such a pixel to the display device of FIG. 6, each pixel can emit light except its own address period, and therefore the ratio of the light emission period in one frame period (that is, the duty ratio). Can be made very large and can be made to be almost 100%. Therefore, a display device with a small luminance variation and a high duty ratio can be obtained.

  Further, since the threshold writing period can be set long, the threshold voltage of the transistor that controls the value of the current flowing through the light-emitting element can be written into the capacitor more accurately. Therefore, the reliability as a display device is improved.

(Embodiment 9)
In this embodiment, one embodiment of a display device of the present invention will be described with reference to FIGS.

  FIG. 25A is a top view showing the display device, and FIG. 25B is a cross-sectional view taken along the line A-A ′ in FIG. 25A (a cross-sectional view cut along A-A ′). The display device includes a signal line driver circuit 2501, a pixel portion 2502, a first scan line driver circuit 2503, and a second scan line driver circuit 2506 which are indicated by dotted lines in the drawing over a substrate 2510. Further, a sealing substrate 2504 and a sealing material 2505 are provided, and a space 2507 is formed inside the display device surrounded by these.

  Note that a wiring 2508 is a wiring for transmitting a signal input to the first scan line driver circuit 2503, the second scan line driver circuit 2506, and the signal line driver circuit 2501, and is an FPC (flexible flexible terminal) serving as an external input terminal. Print circuit) 2509 receives a video signal, a clock signal, a start signal, and the like. IC chips (semiconductor chips on which a memory circuit, a buffer circuit, and the like are formed) 2518 and 2519 are mounted on a connection portion between the FPC 2509 and the display device using COG (Chip On Glass) or the like. Although only the FPC is shown here, a printed wiring board (PWB) may be attached to the FPC. The display device of the present invention includes not only the display device main body but also a state in which an FPC or PWB is attached. In addition, it is assumed that an IC chip or the like is mounted.

  A cross-sectional structure will be described with reference to FIG. A pixel portion 2502 and its peripheral driver circuits (a first scan line driver circuit 2503, a second scan line driver circuit 2506, and a signal line driver circuit 2501) are formed over a substrate 2510. Here, a signal line A driving circuit 2501 and a pixel portion 2502 are shown.

  Note that the signal line driver circuit 2501 includes unipolar transistors such as N-channel transistors 2520 and 2521. Of course, a CMOS circuit may be formed using not only a P-channel transistor or a unipolar transistor but also a P-channel transistor. In this embodiment, a display panel in which a peripheral drive circuit is integrally formed on a substrate is shown. However, this is not always necessary, and all or a part of the peripheral drive circuit is formed on an IC chip or the like, and COG or the like is used. May be implemented.

  The pixel described in any of Embodiments 1 to 7 is used for the pixel portion 2502. Note that FIG. 25B illustrates a transistor 2511 that functions as a switch, a transistor 2512 that controls a current value supplied to the light-emitting element, and a light-emitting element 2528. Note that the first electrode of the transistor 2512 is connected to the pixel electrode 2513 of the light-emitting element 2528. In addition, an insulator 2514 is formed so as to cover an end portion of the pixel electrode 2513. Here, the insulator 2514 is formed using a positive photosensitive acrylic resin film.

  In order to improve the coverage, a curved surface having a curvature is formed at the upper end portion or the lower end portion of the insulator 2514. For example, in the case where positive photosensitive acrylic is used as a material for the insulator 2514, it is preferable that only the upper end portion of the insulator 2514 has a curved surface with a curvature radius (0.2 μm to 3 μm). As the insulator 2514, either a negative type that becomes insoluble in an etchant by photosensitive light or a positive type that becomes soluble in an etchant by light can be used.

  In addition, over the pixel electrode 2513, a layer 2516 containing a light-emitting substance and a counter electrode 2517 are formed. The layer 2516 containing a light-emitting substance is not particularly limited and can be appropriately selected as long as at least a light-emitting layer is provided.

  Further, the sealing substrate 2504 and the substrate 2510 are attached to each other using the sealing material 2505, whereby the light emitting element 2528 is provided in the space 2507 surrounded by the substrate 2510, the sealing substrate 2504, and the sealing material 2505. ing. Note that the space 2507 includes a structure filled with a sealant 2505 in addition to a case where the space 2507 is filled with an inert gas (nitrogen, argon, or the like).

  Note that an epoxy-based resin is preferably used for the sealant 2505. Moreover, it is desirable that these materials are materials that do not transmit moisture and oxygen as much as possible. As a material used for the sealing substrate 2504, a plastic substrate made of FRP (Fiberglass-Reinforced Plastics), PVF (polyvinyl fluoride), Mylar, polyester, acrylic, or the like can be used in addition to a glass substrate or a quartz substrate.

  By operating the pixel portion 2502 using the pixel described in any of Embodiments 1 to 7, a high-quality display device with high duty ratio can be obtained. Obtainable. Further, in the present invention, the power consumption can be reduced because the potential of the counter electrode is kept constant.

  As shown in FIG. 25, the signal line driver circuit 2501, the pixel portion 2502, the first scan line driver circuit 2503, and the second scan line driver circuit 2506 are integrally formed, so that the cost of the display device can be reduced. In this case, the manufacturing process can be simplified by making the transistors used in the signal line driver circuit 2501, the pixel portion 2502, the first scan line driver circuit 2503, and the second scan line driver circuit 2506 unipolar. Therefore, further cost reduction can be achieved.

  As described above, the display device of the present invention can be obtained. The configuration described above is an example, and the configuration of the display device of the present invention is not limited to this.

  Note that the display device may have a structure in which a signal line driver circuit 2601 is formed over an IC chip and mounted on the display device by COG or the like as illustrated in FIG. Note that the substrate 2600, the pixel portion 2602, the first scan line driver circuit 2603, the second scan line driver circuit 2604, the FPC 2605, the IC chip 2606, the IC chip 2607, the sealing substrate 2608, and the sealing material in FIG. Reference numeral 2609 denotes a substrate 2510, a pixel portion 2502, a first scan line driver circuit 2503, a second scan line driver circuit 2506, an FPC 2509, an IC chip 2518, an IC chip 2519, a sealing substrate 2504, and a seal in FIG. It corresponds to the material 2505.

  That is, only the signal line driver circuit that requires high-speed operation of the driver circuit is formed on the IC chip using a CMOS or the like to reduce power consumption. Further, by using a semiconductor chip such as a silicon wafer as the IC chip, it is possible to achieve higher speed operation and lower power consumption.

  Note that cost reduction can be achieved by forming the first scan line driver circuit 2603 and the second scan line driver circuit 2604 integrally with the pixel portion 2602. Further, the first scan line driver circuit 2603, the second scan line driver circuit 2604, and the pixel portion 2602 are formed of unipolar transistors, so that cost can be further reduced. At that time, the use of a boot trap circuit for the first scan line driver circuit 2603 and the second scan line driver circuit 2604 can prevent the output potential from being lowered. Further, when amorphous silicon is used for a semiconductor layer of a transistor included in the first scan line driver circuit 2603 and the second scan line driver circuit 2604, a threshold value fluctuates due to deterioration. It is preferable to have.

  Note that when the pixel portion 2602 is operated using the pixel described in any of Embodiments 1 to 7, high-quality display with a high duty ratio can be achieved, and variation in luminance with time can be suppressed between pixels or between pixels. A device can be obtained. Further, in the present invention, the power consumption can be reduced because the potential of the counter electrode is kept constant. Further, by mounting an IC chip on which a functional circuit (memory or buffer) is formed at a connection portion between the FPC 2605 and the substrate 2600, the substrate area can be effectively used.

  In addition, the signal line driver circuit 2611, the first scan line driver circuit 2613, and the first scan line driver circuit 2613 corresponding to the signal line driver circuit 2501, the first scan line driver circuit 2503, and the second scan line driver circuit 2506 in FIG. The second scanning line driving circuit 2614 may be formed on an IC chip as shown in FIG. 26B and mounted on the display panel by COG or the like. Note that the substrate 2610, the pixel portion 2612, the FPC 2615, the IC chip 2616, the IC chip 2617, the sealing substrate 2618, and the sealant 2619 in FIG. 26B are the substrate 2510, the pixel portion 2502, the FPC 2509, and the like in FIG. It corresponds to an IC chip 2518, an IC chip 2519, a sealing substrate 2504, and a sealing material 2505.

  Further, by using an amorphous semiconductor film such as amorphous silicon (a-Si: H) for the semiconductor layer of the transistor in the pixel portion 2612, cost reduction can be achieved. Further, a large display panel can be manufactured.

  Further, the first scan line driver circuit, the second scan line driver circuit, and the signal line driver circuit may not be provided in the row direction and the column direction of the pixel. For example, as shown in FIG. 27A, the peripheral driving circuit 2701 formed on the IC chip is replaced with the first scanning line driving circuit 2613, the second scanning line driving circuit 2614, and the signal line shown in FIG. The driver circuit 2611 may have a function. Note that the substrate 2700, the pixel portion 2702, the FPC 2704, the IC chip 2705, the IC chip 2706, the sealing substrate 2707, and the sealant 2708 in FIG. 27A are respectively the substrate 2510, the pixel portion 2502, the FPC 2509, and the like. It corresponds to an IC chip 2518, an IC chip 2519, a sealing substrate 2504, and a sealing material 2505.

  FIG. 27B is a schematic diagram for explaining wiring connection of the display device in FIG. Note that FIG. 27B illustrates a substrate 2710, a peripheral driver circuit 2711, a pixel portion 2712, an FPC 2713, and an FPC 2714.

  The FPC 2713 and the FPC 2714 input an external signal and a power supply potential to the peripheral driver circuit 2711. An output from the peripheral driver circuit 2711 is input to a wiring in a row direction and a column direction connected to the pixel included in the pixel portion 2712.

  In the case where a white light emitting element is used as the light emitting element, full color display can be realized by providing a color filter on the sealing substrate. The present invention can also be applied to such a display device. FIG. 28 shows an example of a partial cross-sectional view of the pixel portion.

  As shown in FIG. 28, a base film 2802 is formed over a substrate 2800, a transistor 2801 for controlling a current value supplied to the light-emitting element is formed over the substrate 2800, and a pixel electrode 2803 is in contact with the first electrode of the transistor 2801. A layer 2804 containing a light-emitting substance and a counter electrode 2805 are formed thereover.

  Note that a light-emitting element is obtained by sandwiching a layer 2804 containing a light-emitting substance between the pixel electrode 2803 and the counter electrode 2805. In FIG. 28, white light is emitted. A red color filter 2806R, a green color filter 2806G, and a blue color filter 2806B are provided above the light-emitting element, so that full color display can be performed. A black matrix (also referred to as BM) 2807 is provided to isolate these color filters.

  The display device of this embodiment can be combined with not only Embodiments 1 to 7 but also the structure described in Embodiment 8 as appropriate. The configuration of the display device is not limited to the above, and the present invention can be applied to display devices having other configurations.

(Embodiment 10)
The display device of the present invention can be applied to various electronic devices. Specifically, it can be applied to a display portion of an electronic device. Electronic devices include video cameras, digital cameras, goggles type displays, navigation systems, sound playback devices (car audio, audio components, etc.), computers, game machines, portable information terminals (mobile computers, mobile phones, portable game machines) Or an electronic book or the like), an image reproduction device provided with a recording medium (specifically, a device equipped with a display capable of reproducing a recording medium such as Digital Versatile Disc (DVD) and displaying the image).

  FIG. 33A shows a display which includes a housing 3301, a support base 3302, a display portion 3303, a speaker portion 3304, a video input terminal 3305, and the like.

  Note that the pixel described in any of Embodiments 1 to 7 is used for the display portion 3303. According to the present invention, variation in luminance with time can be suppressed between pixels or between pixels, and a display having a high-quality display unit with a high duty ratio can be obtained. Further, in the present invention, the power consumption can be reduced because the potential of the counter electrode is kept constant. The display includes all display devices for displaying information such as for personal computers, for receiving television broadcasts, and for displaying advertisements.

  In recent years, as the need for an increase in the size of a display has become stronger, an increase in price has become a problem as the size of the display increases. Therefore, the issue is how to reduce manufacturing costs and keep high-quality products as low as possible.

  Since the pixel of the present invention can be manufactured using a unipolar transistor, the number of steps can be reduced and the manufacturing cost can be reduced. In addition, by using an amorphous semiconductor film such as amorphous silicon (a-Si: H) for the semiconductor layer of the transistor included in the pixel, the process can be simplified and the cost can be further reduced. In this case, a driver circuit around the pixel portion is preferably formed over an IC chip and mounted on the display panel by COG (Chip On Glass) or the like. Note that the signal line driver circuit having a high operation speed may be formed over an IC chip, and the scan line driver circuit having a relatively low operation speed may be integrally formed with a circuit formed of a unipolar transistor together with the pixel portion.

  FIG. 33B shows a camera, which includes a main body 3311, a display portion 3312, an image receiving portion 3313, operation keys 3314, an external connection port 3315, a shutter 3316, and the like.

  Note that the pixel described in any of Embodiments 1 to 7 is used for the display portion 3312. According to the present invention, it is possible to suppress a luminance variation with time between pixels or between pixels, and it is possible to obtain a camera having a high-quality display unit with a high duty ratio. Further, in the present invention, the power consumption can be reduced because the potential of the counter electrode is kept constant.

  In recent years, production competition has intensified along with the improvement in performance of digital cameras and the like. And how to keep high-performance products at low prices is important.

  Since the pixel of the present invention can be manufactured using a unipolar transistor, the number of steps can be reduced and the manufacturing cost can be reduced. In addition, by using an amorphous semiconductor film such as amorphous silicon (a-Si: H) for the semiconductor layer of the transistor included in the pixel, the process can be simplified and the cost can be further reduced. In this case, a driver circuit around the pixel portion is preferably formed over an IC chip and mounted on the display panel by COG or the like. Note that the signal line driver circuit having a high operation speed may be formed over an IC chip, and the scan line driver circuit having a relatively low operation speed may be integrally formed with a circuit formed of a unipolar transistor together with the pixel portion.

  FIG. 33C illustrates a computer, which includes a main body 3321, a housing 3322, a display portion 3323, a keyboard 3324, an external connection port 3325, a pointing mouse 3326, and the like. Note that the pixel described in any of Embodiments 1 to 7 is used for the display portion 3323. According to the present invention, a luminance variation with time can be suppressed between pixels or between pixels, and a computer having a high-quality display portion with a high duty ratio can be obtained. Further, in the present invention, the power consumption can be reduced because the potential of the counter electrode is kept constant. In addition, cost can be reduced by using a unipolar transistor for a transistor included in the pixel portion or an amorphous semiconductor film for a semiconductor layer of the transistor.

  FIG. 33D illustrates a mobile computer, which includes a main body 3331, a display portion 3332, a switch 3333, operation keys 3334, an infrared port 3335, and the like. Note that the pixel described in any of Embodiments 1 to 7 is used for the display portion 3332. According to the present invention, variation in luminance with time can be suppressed between pixels or between pixels, and a mobile computer having a high-quality display unit with a high duty ratio can be obtained. Further, in the present invention, the power consumption can be reduced because the potential of the counter electrode is kept constant. In addition, cost can be reduced by using a unipolar transistor for a transistor included in the pixel portion or an amorphous semiconductor film for a semiconductor layer of the transistor.

  FIG. 33E shows a portable image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 3341, a housing 3342, a display portion A 3343, a display portion B 3344, a recording medium (DVD, etc.). A reading unit 3345, operation keys 3346, a speaker unit 3347, and the like are included. The display portion A 3343 can mainly display image information, and the display portion B 3344 can mainly display character information. Note that the pixel described in any of Embodiments 1 to 7 is used for the display portion A 3343 and the display portion B 3344. According to the present invention, it is possible to suppress a variation in luminance with time between pixels or between pixels, and to obtain an image reproducing device having a high-quality display unit with a high duty ratio. Further, in the present invention, the power consumption can be reduced because the potential of the counter electrode is kept constant. In addition, cost can be reduced by using a unipolar transistor for a transistor included in the pixel portion or an amorphous semiconductor film for a semiconductor layer of the transistor.

  FIG. 33F illustrates a goggle type display which includes a main body 3351, a display portion 3352, and an arm portion 3353. Note that the pixel described in any of Embodiments 1 to 7 is used for the display portion 3352. According to the present invention, a variation in luminance with time can be suppressed between pixels or between pixels, and a goggle type display having a high-quality display unit with a high duty ratio can be obtained. Further, in the present invention, the power consumption can be reduced because the potential of the counter electrode is kept constant. In addition, cost can be reduced by using a unipolar transistor for a transistor included in the pixel portion or an amorphous semiconductor film for a semiconductor layer of the transistor.

  FIG. 33G illustrates a video camera, which includes a main body 3361, a display portion 3362, a housing 3363, an external connection port 3364, a remote control reception portion 3365, an image receiving portion 3366, a battery 3367, an audio input portion 3368, operation keys 3369, and an eyepiece. Part 3360 and the like. Note that the pixel described in any of Embodiments 1 to 7 is used for the display portion 3362. According to the present invention, it is possible to suppress a variation in luminance over time between pixels or between pixels, and to obtain a video camera having a high-quality display unit with a high duty ratio. Further, in the present invention, the power consumption can be reduced because the potential of the counter electrode is kept constant. In addition, cost can be reduced by using a unipolar transistor for a transistor included in the pixel portion or an amorphous semiconductor film for a semiconductor layer of the transistor.

  FIG. 33H illustrates a cellular phone, which includes a main body 3371, a housing 3372, a display portion 3373, an audio input portion 3374, an audio output portion 3375, operation keys 3376, an external connection port 3377, an antenna 3378, and the like. Note that the pixel described in any of Embodiments 1 to 7 is used for the display portion 3373. According to the present invention, a variation in luminance with time can be suppressed between pixels or between pixels, and a mobile phone having a high-quality display portion with a high duty ratio can be obtained. Further, in the present invention, the power consumption can be reduced because the potential of the counter electrode is kept constant. In addition, cost can be reduced by using a unipolar transistor for a transistor included in the pixel portion or an amorphous semiconductor film for a semiconductor layer of the transistor.

  Thus, the present invention can be applied to all electronic devices.

(Embodiment 11)
In this embodiment mode, a structural example of a mobile phone including the display device of the present invention in a display portion will be described with reference to FIG.

  A display panel 3410 is incorporated in a housing 3400 so as to be detachable. The shape and dimensions of the housing 3400 can be changed as appropriate in accordance with the size of the display panel 3410. A housing 3400 to which the display panel 3410 is fixed is fitted into a printed board 3401 and assembled as a module.

  The display panel 3410 is connected to the printed board 3401 through the FPC 3411. A signal processing circuit 3405 including a speaker 3402, a microphone 3403, a transmission / reception circuit 3404, a CPU, a controller, and the like is formed over the printed board 3401. Such a module is combined with the input means 3406 and the battery 3407 and housed in the housing 3409 and the housing 3412. Note that the pixel portion of the display panel 3410 is arranged so as to be visible from an opening window formed in the housing 3412.

  In the display panel 3410, a pixel portion and some peripheral driver circuits (a driver circuit having a low operating frequency among a plurality of driver circuits) are formed over a substrate using transistors, and another peripheral driver circuit (a plurality of peripheral driver circuits) May be formed on an IC chip, and the IC chip may be mounted on the display panel 3410 by COG (Chip On Glass). Alternatively, the IC chip may be connected to the glass substrate using TAB (Tape Automated Bonding) or a printed board. Alternatively, all peripheral drive circuits may be formed on an IC chip, and the IC chip may be mounted on the display panel using COG or the like.

  Note that the pixel described in any of Embodiments 1 to 7 is used for the pixel portion. According to the present invention, variation in luminance with time can be suppressed between pixels or between pixels, and a display panel 3410 having a high-quality display portion with a high duty ratio can be obtained. Further, in the present invention, the power consumption can be reduced because the potential of the counter electrode is kept constant. In addition, cost can be reduced by using a unipolar transistor for a transistor included in the pixel portion or an amorphous semiconductor film for a semiconductor layer of the transistor.

  The configuration shown in this embodiment is an example of a mobile phone, and is not limited to the mobile phone having such a configuration, and can be applied to mobile phones having various configurations.

(Embodiment 12)
In this embodiment, an EL module in which a display panel and a circuit board are combined will be described with reference to FIGS.

  As shown in FIG. 35, the display panel 3501 includes a pixel portion 3503, a scanning line driver circuit 3504, and a signal line driver circuit 3505. For example, a control circuit 3506, a signal dividing circuit 3507, and the like are formed on the circuit board 3502. Note that the display panel 3501 and the circuit board 3502 are connected by a connection wiring 3508. An FPC or the like can be used for the connection wiring 3508.

  In the display panel 3501, a pixel portion and some peripheral driver circuits (a driver circuit having a low operating frequency among a plurality of driver circuits) are formed over a substrate using transistors, and some other peripheral driver circuits (multiple driver circuits) May be formed on an IC chip, and the IC chip may be mounted on the display panel 3501 by COG (Chip On Glass). Alternatively, the IC chip may be connected to the glass substrate using TAB (Tape Automated Bonding) or a printed board. Alternatively, all peripheral drive circuits may be formed on an IC chip, and the IC chip may be mounted on the display panel using COG or the like.

  Note that the pixel described in any of Embodiments 1 to 7 is used for the pixel portion. According to the present invention, variation in luminance with time can be suppressed between pixels or between pixels, and a high-quality display panel 3501 with a high duty ratio can be obtained. Further, in the present invention, the power consumption can be reduced because the potential of the counter electrode is kept constant. In addition, cost can be reduced by using a unipolar transistor for a transistor included in the pixel portion or an amorphous semiconductor film for a semiconductor layer of the transistor.

  With such an EL module, an EL television receiver can be completed. FIG. 36 is a block diagram showing the main configuration of an EL television receiver. A tuner 3601 receives a video signal and an audio signal. The video signal includes a video signal amplification circuit 3602, a video signal processing circuit 3603 that converts a signal output from the signal to a color signal corresponding to each color of red, green, and blue, and uses the video signal as input specifications of the drive circuit. Processed by a control circuit 3506 for conversion. The control circuit 3506 outputs a signal to each of the scanning line side and the signal line side. In the case of digital driving, a signal dividing circuit 3507 may be provided on the signal line side so that an input digital signal is divided into m pieces and supplied.

  Of the signals received by the tuner 3601, the audio signal is sent to the audio signal amplification circuit 3604, and the output is supplied to the speaker 3606 via the audio signal processing circuit 3605. The control circuit 3607 receives control information on the receiving station (reception frequency) and volume from the input unit 3608 and sends a signal to the tuner 3601 and the audio signal processing circuit 3605.

  A television receiver can be completed by incorporating the EL module in FIG. 35 into the housing 3301 in FIG. 33A described in Embodiment 10.

  Of course, the present invention is not limited to a television receiver, and is applied to various uses, particularly as a display medium with a large area, such as a personal computer monitor, an information display board in a railway station or airport, and an advertisement display board in a street. can do.

3A and 3B illustrate a pixel structure described in Embodiment 1; 2 is a timing chart illustrating the operation of the pixel illustrated in FIG. 1. 2A and 2B illustrate an operation of the pixel illustrated in FIG. 1. 3A and 3B illustrate a pixel structure described in Embodiment 1; The model figure of the voltage-current characteristic by channel length modulation. 3A and 3B each illustrate a display device described in Embodiment 1; FIG. 6 illustrates a pixel structure described in Embodiment 3; FIG. 6 illustrates a pixel structure described in Embodiment 3; FIG. 6 illustrates a pixel structure described in Embodiment 3; FIG. 5 illustrates a pixel structure described in Embodiment 4; FIG. 5 illustrates a pixel structure described in Embodiment 4; FIG. 7 illustrates a pixel structure described in Embodiment 5; 13 is a timing chart for explaining the operation of the pixel shown in FIG. 12. FIG. 9 illustrates a pixel configuration described in Embodiment 7; FIG. 15 is a timing chart illustrating operation of the pixel illustrated in FIG. 14. FIG. 15 illustrates an operation of the pixel illustrated in FIG. 14. FIG. 9 is a partial cross-sectional view of a pixel shown in Embodiment Mode 8; 9A and 9B illustrate a light-emitting element described in Embodiment 8. 9A and 9B illustrate a light extraction direction shown in Embodiment Mode 8. FIG. 9 is a partial cross-sectional view of a pixel shown in Embodiment Mode 8; FIG. 9 is a partial cross-sectional view of a pixel shown in Embodiment Mode 8; FIG. 9 is a partial cross-sectional view of a pixel shown in Embodiment Mode 8; FIG. 9 is a partial cross-sectional view of a pixel shown in Embodiment Mode 8; FIG. 9 is a partial cross-sectional view of a pixel shown in Embodiment Mode 8; 10A and 10B illustrate a display device described in Embodiment 9. 10A and 10B illustrate a display device described in Embodiment 9. 10A and 10B illustrate a display device described in Embodiment 9. FIG. 10 is a partial cross-sectional view of a pixel described in Embodiment 9; FIG. 7 illustrates a pixel structure described in Embodiment 6; FIG. 7 illustrates a pixel structure described in Embodiment 6; FIG. 7 illustrates a pixel structure described in Embodiment 6; FIG. 9 illustrates a pixel configuration described in Embodiment 7; 8A and 8B illustrate electronic devices to which the present invention can be applied. The figure which shows the structural example of a mobile telephone. The figure which shows the example of EL module. The block diagram which shows the main structures of EL television receiver. FIG. 7 illustrates a pixel structure described in Embodiment 6; FIG. 5 is a top view of the pixel shown in FIG. 4. FIG. 5 illustrates a pixel structure shown in Embodiment Mode 2; 3A and 3B illustrate a writing operation of the display device described in Embodiment 1. FIG. 7 illustrates a pixel structure described in Embodiment 5; The figure explaining the drive system which combined the digital gradation system and the time gradation system. FIG. 7 illustrates a pixel structure described in Embodiment 6; FIG. 7 illustrates a pixel structure described in Embodiment 6; FIG. 5 illustrates a pixel structure described in Embodiment 1; FIG. 6 is a diagram illustrating a pixel configuration of a conventional technique. FIG. 6 is a diagram illustrating a pixel configuration of a conventional technique. 6 is a timing chart for operating pixels shown in the related art. The figure explaining the ratio of the light emission period in 1 frame period at the time of using a prior art.

Explanation of symbols

111 Transistor 112 First Switch 113 Second Switch 114 Third Switch 115 Capacitance Element 116 Light Emitting Element 117 Signal Line 118 First Scan Line 119 Second Scan Line 120 Third Scan Line 121 Power Line 122 Power Supply Line 123 Counter electrode 412 First switching transistor 413 Second switching transistor 414 Third switching transistor 611 Signal line driver circuit 612 Scan line driver circuit 613 Pixel portion 614 Pixel 700 Pixel 718 First scan line 800 Pixel 819 Second Scan line 900 pixel 920 third scan line 1011 transistor 1111 transistor 1201 first transistor 1202 second transistor 1203 fourth switch 1204 fifth switch 1212 first switch 1213 second switch Switch 1215 third switch 1215 capacitor 1216 light emitting element 1217 signal line 1218 first scan line 1219 second scan line 1220 third scan line 1221 power supply line 1222 potential supply line 1223 counter electrode 1411 transistor 1412 first Switch 1413 Second switch 1414 Third switch 1415 Capacitance element 1416 Light emitting element 1417 Signal line 1418 First scanning line 1419 Second scanning line 1420 Third scanning line 1421 Power supply line 1422 Potential supply line 1423 Counter electrode 2901 Second electrode 4 switch 2902 scan line 3001 fourth switch 3002 scan line 3003 node 3101 rectifier element 3102 scan line 3201 rectifier element 3202 scan line 3701 fourth switch 3702 scan line 3914 rectifier element 3920 third scan line 39 1 Schottky barrier type 3952 PIN type 3953 PN type 3954 transistor 3955 transistor 4301 fourth switch 4401 fourth switch 4515 a gate capacitance 4540 pixel electrode

Claims (27)

A pixel including a transistor, a first switch, and a second switch;
One of the source electrode and the drain electrode of the transistor is electrically connected to the gate electrode of the transistor through the first switch,
The other of the source electrode and the drain electrode of the transistor is electrically connected to the pixel electrode,
The other of the source electrode and the drain electrode of the transistor is electrically connected to the second switch,
The semiconductor device is characterized in that a signal in accordance with the gradation of the pixel is input to the gate electrode of the transistor. A holding capacitor, a transistor, a first switch, a second switch, and a third switch;
One of a source electrode and a drain electrode of the transistor is electrically connected to the first wiring;
The other of the source electrode and the drain electrode of the transistor is electrically connected to the pixel electrode,
The other of the source electrode and the drain electrode of the transistor is electrically connected to the second wiring through the third switch,
A gate electrode of the transistor is electrically connected to a third wiring through the first switch;
A gate electrode of the transistor is electrically connected to the first wiring through the second switch;
The other of the source electrode and the drain electrode of the transistor is electrically connected to the gate electrode through the storage capacitor. A capacitor, a transistor, a first switch, a second switch, and a third switch;
One of a source electrode and a drain electrode of the transistor is electrically connected to the first wiring;
The other of the source electrode and the drain electrode of the transistor is electrically connected to the pixel electrode,
The other of the source electrode and the drain electrode of the transistor is electrically connected to the second wiring through the third switch,
A gate electrode of the transistor is electrically connected to a third wiring through the first switch;
A gate electrode of the transistor is electrically connected to the first wiring through the second switch;
The other of the source electrode and the drain electrode of the transistor is electrically connected to the gate electrode through the capacitor. In claim 2 or claim 3,
The semiconductor device, wherein the second wiring is the same as a wiring for controlling the third switch. In any one of Claims 2 thru | or 4,
2. The semiconductor device according to claim 1, wherein the second wiring is one of scanning lines for controlling first to third switches in the previous row or the next row. In any one of Claims 2 thru | or 5,
The semiconductor device is a thin film transistor. In any one of Claims 2 thru | or 6,
The semiconductor device is an N-channel transistor. In any one of Claims 2 thru | or 7,
A semiconductor device, wherein the semiconductor layer of the transistor is made of an amorphous semiconductor film. In any one of Claims 2 thru | or 8,
A semiconductor device, wherein the semiconductor layer of the transistor is made of amorphous silicon. In any one of Claims 2 thru | or 7,
A semiconductor device, wherein the semiconductor layer of the transistor is made of a crystalline semiconductor film. In any one of Claims 2 thru | or 10,
The potential input to the first wiring is a binary value of V1 or V2,
It takes the value of V2 only when the first switch to the third switch are in the non-passing state,
V1 is a potential higher than the potential input to the second wiring, and the difference is larger than the threshold voltage of the transistor,
V2 is a value higher than V1. In any one of Claims 2 thru | or 6,
The semiconductor device is a P-channel transistor. In any one of Claim 2 thru | or Claim 6, and Claim 12,
The potential input to the first wiring takes a binary value of V1 or V2,
The value of V2 is only when the first switch to the third switch are in a non-operating state,
V1 is a potential lower than the potential input to the second wiring, and the difference is larger than the absolute value of the threshold voltage of the transistor,
V2 is a value lower than V1. In any one of Claims 2 thru / or Claim 13,
The semiconductor device, wherein the first to third switches are transistors. A transistor in which one of the source electrode and the drain electrode is electrically connected to the first wiring and the other of the source electrode and the drain electrode is electrically connected to the second wiring;
A holding capacitor for holding a gate-source voltage of the transistor;
By applying a first potential input to the first wiring to the gate electrode of the transistor and applying a second potential input to the second wiring to the source electrode of the transistor, Means for holding the first voltage in the holding capacitor;
Means for discharging the voltage of the holding capacitor to a second voltage;
Means for applying a potential obtained by adding a third voltage to the first potential to the gate electrode of the transistor and holding the fifth voltage obtained by adding the second voltage and the fourth voltage in the storage capacitor. When,
And a means for supplying a current set to the transistor to a load by inputting a third potential different from the first potential to the first wiring. A transistor in which one of the source electrode and the drain electrode is electrically connected to the first wiring and the other of the source electrode and the drain electrode is electrically connected to the second wiring;
A holding capacitor for holding a gate-source voltage of the transistor;
By applying a first potential input to the first wiring to the gate electrode of the transistor and applying a second potential input to the second wiring to the source electrode of the transistor, Means for holding the first voltage in the holding capacitor;
Means for discharging the voltage of the storage capacitor to the threshold voltage of the transistor;
A potential obtained by adding a second voltage to the first potential is applied to the gate electrode of the transistor, and a fourth voltage obtained by adding the threshold voltage of the transistor and a third voltage is held in the storage capacitor. Means to
And a means for supplying a current set to the transistor to a load by inputting a third potential different from the first potential to the first wiring. In claim 15 or claim 16,
The semiconductor device is a thin film transistor. In any one of Claims 15 thru / or Claim 17,
The semiconductor device is an N-channel transistor. In any one of Claims 15 thru / or Claim 18,
A semiconductor device, wherein the semiconductor layer of the transistor is made of an amorphous semiconductor film. In any one of claims 15 to 19,
A semiconductor device, wherein the semiconductor layer of the transistor is made of amorphous silicon. In any one of Claims 15 thru / or Claim 18,
A semiconductor device, wherein the semiconductor layer of the transistor is made of a crystalline semiconductor film. In any one of Claims 15 to 21,
The first potential is higher than the second potential, and the difference is larger than the threshold voltage of the transistor,
The semiconductor device is characterized in that the first potential is lower than the third potential. In any one of Claims 15 thru / or Claim 17,
The semiconductor device is a P-channel transistor. In any one of Claim 15 thru | or Claim 17, and Claim 23,
The first potential is lower than the second potential, and the difference is greater than the absolute value of the threshold voltage of the transistor,
The semiconductor device is characterized in that the first potential is higher than the third potential. In any one of Claims 15 thru | or 25,
The semiconductor device according to claim 1, wherein the load is a light emitting element. A display device comprising the semiconductor device according to any one of claims 1 to 25. An electronic apparatus comprising the display device according to claim 26 in a display portion.

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