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JP2007158194A - Wiring board, semiconductor device using same, and method of manufacturing them - Google Patents

Wiring board, semiconductor device using same, and method of manufacturing them Download PDF

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Publication number
JP2007158194A
JP2007158194A JP2005354049A JP2005354049A JP2007158194A JP 2007158194 A JP2007158194 A JP 2007158194A JP 2005354049 A JP2005354049 A JP 2005354049A JP 2005354049 A JP2005354049 A JP 2005354049A JP 2007158194 A JP2007158194 A JP 2007158194A
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Prior art keywords
conductor wiring
wiring
conductor
protruding electrode
semiconductor element
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Withdrawn
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JP2005354049A
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Japanese (ja)
Inventor
Kenji Tokushima
健志 徳島
Koichi Nagao
浩一 長尾
Nozomi Shimoishizaka
望 下石坂
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Priority to JP2005354049A priority Critical patent/JP2007158194A/en
Publication of JP2007158194A publication Critical patent/JP2007158194A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

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  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a means for suppressing damage or a break in wiring conductors caused by ultrasonic vibration or the like when the wiring conductors on a flexible insulating substrate are joined to element electrodes of a semiconductor element via projected electrodes in a structure having the insulating substrate and the semiconductor element. <P>SOLUTION: A wiring board 19 has an insulating substrate 10, a plurality of first wiring conductors 11 provided on the substrate, first projected electrodes 13 provided to the first wiring conductors, and one or more second wiring conductors 12 provided to be adjacent to the first wiring conductors outside thereof. A semiconductor chip 18 has a semiconductor element 20, element electrodes 21 provided on the element, and second projected electrodes 22 provided on the element electrodes. When the first projected electrodes of the wiring board are joined to the second projected electrodes of the semiconductor chip to be opposed to each other, electric connection from the first wiring conductors to the semiconductor element is attained. The second wiring conductors are insulated from the second projected electrodes and the semiconductor element because a gap is provided therebetween. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、テープキャリア基板のように可撓性を有する絶縁基材を用いて形成された配線基板、それを用いた半導体装置、及びその製造方法に関するものである。   The present invention relates to a wiring board formed using a flexible insulating base material such as a tape carrier board, a semiconductor device using the wiring board, and a method for manufacturing the same.

テープキャリア基板を使用したパッケージモジュールの一種として、TCP(Tape Carrier Package)が知られている。TCPは、フラットパネルディスプレイの駆動LSI用パッケージとして主に使用されている(例えば特許文献1を参照)。図7は、TCPの一例を示し、図7(a)はその平面図である。図7(b)は図7(a)のC−C’線に沿った断面図、図7(c)は図7(a)のD−D’線に沿った断面図である。   TCP (Tape Carrier Package) is known as a type of package module using a tape carrier substrate. TCP is mainly used as a driving LSI package for a flat panel display (see, for example, Patent Document 1). FIG. 7 shows an example of TCP, and FIG. 7 (a) is a plan view thereof. FIG. 7B is a cross-sectional view taken along line C-C ′ in FIG. 7A, and FIG. 7C is a cross-sectional view taken along line D-D ′ in FIG.

図7(a)に示すように、TCPは、可撓性を有する絶縁基材1を用いて作製される。絶縁基材1にはデバイスホール2が形成され、デバイスホール2に沿って、第1の導体配線3及び第2の導体配線4が設けられ、第1及び第2の導体配線3、4の端部には突起電極5が形成されている。半導体素子6はデバイスホール2中に配置される。   As shown to Fig.7 (a), TCP is produced using the insulating base material 1 which has flexibility. A device hole 2 is formed in the insulating base 1, and a first conductor wiring 3 and a second conductor wiring 4 are provided along the device hole 2, and ends of the first and second conductor wirings 3 and 4. A protruding electrode 5 is formed on the part. The semiconductor element 6 is disposed in the device hole 2.

図7(b)の断面図は、半導体素子6と第1の導体配線3との接続部分を拡大して示している。図7(b)に示すように、半導体素子6上に形成された複数の素子電極7と、第1の導体配線3の突起電極5とが接合されることにより、半導体素子6は、第1及び第2の導体配線3、4に支持された形態で、絶縁基材1上に実装されている。半導体素子6上の素子電極7の周囲には保護膜8が形成され、デバイスホール2中の、半導体素子6の接合面と第1及び第2の導体配線3、4とは、封止材9により保護されている。   The cross-sectional view of FIG. 7B shows an enlarged connection portion between the semiconductor element 6 and the first conductor wiring 3. As shown in FIG. 7B, the plurality of element electrodes 7 formed on the semiconductor element 6 and the protruding electrodes 5 of the first conductor wiring 3 are joined, so that the semiconductor element 6 includes the first element electrode 7. And it is mounted on the insulating substrate 1 in a form supported by the second conductor wirings 3 and 4. A protective film 8 is formed around the element electrode 7 on the semiconductor element 6, and the bonding surface of the semiconductor element 6 and the first and second conductor wirings 3, 4 in the device hole 2 are sealed with a sealing material 9. It is protected by

第2の導体配線4の幅は第1の導体配線3よりも太く設定され、1本以上の第2の導体配線4が最端部に配置されている。それにより、突起電極5との接続強度が増強され、熱応力による第1の導体配線3または第2の導体配線4の破損や断線などが発生し難い構造となっている。さらに、図7(c)に示すように、第2の導体配線4は半導体素子6と物理的に接続されているが、電気的に接続されていないことにより、第2の導体配線4の破損や断線などが発生しても、半導体装置の機能を損なわないようにされている。   The width of the second conductor wiring 4 is set to be thicker than that of the first conductor wiring 3, and one or more second conductor wirings 4 are arranged at the end. Thereby, the connection strength with the protruding electrode 5 is enhanced, and the first conductor wiring 3 or the second conductor wiring 4 is not easily damaged or disconnected due to thermal stress. Further, as shown in FIG. 7C, the second conductor wiring 4 is physically connected to the semiconductor element 6 but is not electrically connected, so that the second conductor wiring 4 is damaged. Even if a disconnection or the like occurs, the function of the semiconductor device is not impaired.

必要に応じて第1の導体配線3上または第2の導体配線4上には、金属めっき被膜および絶縁樹脂であるソルダーレジストの層が形成される。一般的に、絶縁基材1の材料としてはポリイミドフィルムが、第1の導体配線3および第2の導体配線4の材料としては銅が使用されている。   As necessary, a metal plating film and a solder resist layer that is an insulating resin are formed on the first conductor wiring 3 or the second conductor wiring 4. Generally, a polyimide film is used as the material of the insulating base material 1, and copper is used as the material of the first conductor wiring 3 and the second conductor wiring 4.

このようなTCPは省コスト化等に伴い、材料の薄型化が望まれており、近年、50μm以下の薄いテープ基材を用いたものが利用されている。
特開2003−197690号公報
Such TCPs are required to be made thinner as the cost is reduced. In recent years, TCPs using a thin tape substrate of 50 μm or less have been used.
JP 2003-197690 A

しかしながら、絶縁基材1上の導体配線3に、突起電極5を介して半導体素子6の素子電極7を電気接続した構造を持つ半導体装置において、以下のような問題が発生する。すなわち、絶縁基材1として柔軟なフィルムを用い、突起電極5と素子電極7との接合に超音波を用いた場合、半導体素子6から突起電極5を経由して印加した超音波の振動により、フィルム6が変形して導体配線3に応力がかかり、突起電極5と接合された導体配線3が破損する、または断線するといった問題が生じる。   However, the following problems occur in a semiconductor device having a structure in which the element electrode 7 of the semiconductor element 6 is electrically connected to the conductor wiring 3 on the insulating substrate 1 via the protruding electrode 5. That is, when a flexible film is used as the insulating substrate 1 and an ultrasonic wave is used for bonding the protruding electrode 5 and the element electrode 7, the vibration of the ultrasonic wave applied from the semiconductor element 6 via the protruding electrode 5 The film 6 is deformed and stress is applied to the conductor wiring 3, causing a problem that the conductor wiring 3 joined to the protruding electrode 5 is broken or disconnected.

従来例では、突起電極5と第1の導体配線3および第2の導体配線4との接合強度を増強しているが、フィルム6が変形して導体配線3に応力がかかることによる、第1の導体配線3または第2の導体配線4の破損や断線などの対策としては、十分に効果的ではなかった。   In the conventional example, the bonding strength between the protruding electrode 5 and the first conductor wiring 3 and the second conductor wiring 4 is enhanced. However, the film 6 is deformed and stress is applied to the conductor wiring 3. As a countermeasure against breakage or disconnection of the conductor wiring 3 or the second conductor wiring 4, it was not sufficiently effective.

本発明は、配線基板への半導体素子の実装時に、突起電極と素子電極との接合に超音波振動を利用した場合であっても、超音波振動により絶縁基材が変形して導体配線に応力がかかることによる、導体配線の破損や断線などを抑制することができる配線基板、それを用いた半導体装置、およびその製造方法を提供することを目的とする。   In the present invention, when the semiconductor element is mounted on the wiring board, even if the ultrasonic vibration is used for joining the protruding electrode and the element electrode, the insulating base material is deformed by the ultrasonic vibration and stress is applied to the conductor wiring. An object of the present invention is to provide a wiring board capable of suppressing breakage or disconnection of conductor wiring due to the above, a semiconductor device using the wiring board, and a manufacturing method thereof.

上記の課題を解決するために、本発明の配線基板は、可撓性を有する絶縁基材と、前記絶縁基材上に整列して設けられた複数の第1の導体配線と、前記第1の導体配線に設けられた第1の突起電極と、前記第1の導体配線の長手方向と垂直な方向における外端側にそれぞれ隣り合うように設けられた1本以上の第2の導体配線とを備えたことを特徴とする。   In order to solve the above problems, a wiring board of the present invention includes a flexible insulating base, a plurality of first conductor wirings arranged in alignment on the insulating base, and the first A first protruding electrode provided on the first conductor wiring, and one or more second conductor wirings provided adjacent to the outer end side in a direction perpendicular to the longitudinal direction of the first conductor wiring, It is provided with.

本発明の半導体装置は、可撓性を有する絶縁基材、前記絶縁基材上に整列して設けられた複数の第1の導体配線、前記第1の導体配線に設けられた第1の突起電極、および前記第1の導体配線の長手方向と垂直な方向の外端側にそれぞれ隣り合うように設けられた1本以上の第2の導体配線を有する配線基板と、半導体素子、前記半導体素子上に設けられた素子電極、および前記素子電極上に設けられた第2の突起電極を有する半導体チップとを備え、前記配線基板に前記半導体チップが搭載され、前記配線基板の前記第1の突起電極と前記半導体チップの前記第2の突起電極が対向して接合されることにより、前記第1の導体配線から前記半導体素子までが電気的に接続されており、前記第2の導体配線は、前記第2の突起電極および前記半導体素子との間に隙間が設けられ、絶縁されていることを特徴とする。   The semiconductor device of the present invention includes a flexible insulating base, a plurality of first conductor wirings arranged in alignment on the insulating base, and a first protrusion provided on the first conductor wiring. A wiring substrate having an electrode and one or more second conductor wirings provided adjacent to each other on the outer end side in a direction perpendicular to the longitudinal direction of the first conductor wiring; a semiconductor element; and the semiconductor element A semiconductor chip having a device electrode provided thereon and a second protruding electrode provided on the device electrode, wherein the semiconductor chip is mounted on the wiring substrate, and the first protrusion of the wiring substrate The electrode and the second projecting electrode of the semiconductor chip are bonded to face each other, so that the first conductor wiring to the semiconductor element are electrically connected, and the second conductor wiring is The second protruding electrode and the A gap is provided between the conductor elements, characterized in that it is insulated.

本発明の半導体装置の製造方法は、可撓性を有する絶縁基材、前記絶縁基材上に整列して設けられた複数の第1の導体配線、前記第1の導体配線に設けられた第1の突起電極、および前記第1の導体配線の長手方向と垂直な方向の外端側にそれぞれ隣り合うように設けられた1本以上の第2の導体配線を有する配線基板を準備する工程と、半導体素子、前記半導体素子上に設けられた素子電極、および前記素子電極上に設けられた第2の突起電極を有する半導体チップを準備する工程と、前記絶縁基材の前記第1の導体配線および前記第2の導体配線が形成されている面と、前記半導体素子の前記素子電極が配列されている面とを対向させ、前記絶縁基材上に前記半導体素子を載置して、前記半導体素子を経由して前記第1の導体配線の長手方向に振動する超音波振動を印加し、前記第1の突起電極と前記第2の突起電極とを超音波接合して前記第1の導体配線から前記半導体素子までを電気的に接続する工程とを含むことを特徴とする。   The method for manufacturing a semiconductor device of the present invention includes a flexible insulating base, a plurality of first conductor wirings arranged in alignment on the insulating base, and a first conductor wiring provided on the first conductor wiring. Preparing a wiring board having one protruding electrode and one or more second conductor wirings provided adjacent to each other on the outer end side in a direction perpendicular to the longitudinal direction of the first conductor wiring; Preparing a semiconductor chip having a semiconductor element, an element electrode provided on the semiconductor element, and a second protruding electrode provided on the element electrode, and the first conductor wiring of the insulating substrate The surface on which the second conductor wiring is formed and the surface on which the element electrodes of the semiconductor element are arranged are opposed to each other, and the semiconductor element is placed on the insulating substrate, and the semiconductor The length of the first conductor wiring via the element Applying ultrasonic vibration that vibrates in the direction, and ultrasonically joining the first protruding electrode and the second protruding electrode to electrically connect the first conductor wiring to the semiconductor element; It is characterized by including.

上記配線基板の構成によれば、絶縁基材上に第1の導体配線とは別に第2の導体配線が形成されることにより絶縁基材が補強され、絶縁基材が変形して導体配線に応力がかかることによる、第1の導体配線または第2の導体配線の破損や断線などを防止することができる。   According to the configuration of the wiring board, the insulating base is reinforced by forming the second conductive wiring separately from the first conductive wiring on the insulating base, and the insulating base is deformed to become the conductive wiring. Damage or disconnection of the first conductor wiring or the second conductor wiring due to the stress can be prevented.

上記半導体装置の構成によれば、絶縁基材上に第1の導体配線とは別に第2の導体配線が形成されることにより絶縁基材が補強され、配線基板と半導体チップとの超音波接合の際に、絶縁基材が変形して導体配線に応力がかかることによる、第1の導体配線または第2の導体配線の破損や断線などを防止することができる。   According to the configuration of the semiconductor device, the insulating base is reinforced by forming the second conductor wiring separately from the first conductor wiring on the insulating base, and ultrasonic bonding between the wiring board and the semiconductor chip is performed. In this case, it is possible to prevent damage or disconnection of the first conductor wiring or the second conductor wiring due to the deformation of the insulating base material and stress applied to the conductor wiring.

上記半導体装置の製造方法によれば、超音波振動の方向が第1の導体配線および第2の導体配線と同じであるため、第1の導体配線の変形が第2の導体配線で抑制され、第1の導体配線の破損や切断などを防止することができる。   According to the method for manufacturing a semiconductor device, since the direction of ultrasonic vibration is the same as that of the first conductor wiring and the second conductor wiring, deformation of the first conductor wiring is suppressed by the second conductor wiring, It is possible to prevent the first conductor wiring from being damaged or cut.

上記本発明の配線基板において、前記第2の導体配線の幅が前記第1の導体配線の幅よりも広いことが好ましい。この構成によれば、第2の導体配線の幅が広いことにより、絶縁基材と第2の導体配線との密着力が向上し、絶縁基材の変形が拘束され、導体配線内に加わる応力が減少し、断線し難くなる。さらに、配線形成時の配線幅の配線幅ばらつきにより、例えば所定の配線幅より細くなった場合に断線しやすくなる、といった不具合を少なくすることができる。   In the wiring board of the present invention, it is preferable that the width of the second conductor wiring is wider than the width of the first conductor wiring. According to this configuration, since the width of the second conductor wiring is wide, the adhesion between the insulating base material and the second conductor wiring is improved, the deformation of the insulating base material is restrained, and the stress applied to the conductor wiring Decreases, making disconnection difficult. Further, it is possible to reduce problems such as disconnection easily when the wiring width becomes narrower than a predetermined wiring width due to wiring width variation in wiring width at the time of wiring formation.

また、上記本発明の半導体装置において、前記第2の導体配線に第3の突起電極が設けられ、前記第3の突起電極に対向する位置の前記半導体素子の前記素子電極上には、前記第2の突起電極が設けられていない構成とすることができる。この構成によれば、第3の突起電極が形成されることにより、封止材の形成時に、封止材と第3の突起電極との密着力が向上し、半導体装置の信頼性を向上させることができる。   In the semiconductor device of the present invention, a third protruding electrode is provided on the second conductor wiring, and the element electrode of the semiconductor element at a position facing the third protruding electrode is positioned on the element electrode. It can be set as the structure where the 2 protruding electrode is not provided. According to this configuration, by forming the third protruding electrode, the adhesion between the sealing material and the third protruding electrode is improved when the sealing material is formed, and the reliability of the semiconductor device is improved. be able to.

以下に、本発明の実施の形態について、図面を参照して詳細に説明する。   Embodiments of the present invention will be described below in detail with reference to the drawings.

(実施の形態1)
図1は、本発明の実施の形態1における半導体装置に使用される配線基板の構成を示す平面図である。
(Embodiment 1)
FIG. 1 is a plan view showing a configuration of a wiring board used in the semiconductor device according to the first embodiment of the present invention.

図1(a)に示す配線基板は、可撓性を有する絶縁基材10と、絶縁基材10上に整列して設けられた複数の第1の導体配線11と、第1の導体配線11の長手方向と垂直な方向の外端にそれぞれ隣り合うように設けられた1本以上の第2の導体配線12とを有する。第1の導体配線11には、第1の突起電極13が設けられている。   The wiring board shown in FIG. 1A includes a flexible insulating base material 10, a plurality of first conductor wirings 11 arranged in alignment on the insulating base material 10, and a first conductor wiring 11. And one or more second conductor wirings 12 provided so as to be adjacent to the outer ends in the direction perpendicular to the longitudinal direction. A first protruding electrode 13 is provided on the first conductor wiring 11.

以上のように、絶縁基材10上に、第1の導体配線11とは別に第2の導体配線12が形成されることで、絶縁基材10が補強される。従って、絶縁基材10に応力がかかることによる第1の導体配線11または第2の導体配線12の破損や断線などを防止することができ、配線基板の信頼性を高めることができる。   As described above, the insulating substrate 10 is reinforced by forming the second conductor wiring 12 separately from the first conductor wiring 11 on the insulating substrate 10. Therefore, it is possible to prevent the first conductor wiring 11 or the second conductor wiring 12 from being damaged or disconnected due to the stress applied to the insulating base material 10, and to improve the reliability of the wiring board.

なお、本発明の第1の実施形態における配線基板としては、図1(a)のような構成に限られず、実施の形態の要旨を逸脱しない範囲において種々の構成に変形可能である。例えば、図1(a)の長手方向に向かい合う2本の第2の導体配線12を繋げて、図1(b)に示すように、1本の第2の導体配線14とした構成を用いることができる。あるいは、図1(c)に示すように、第2の導体配線15を「く」の字に屈曲させた構成にしてもよい。さらに、図1(d)に示すように、第2の導体配線16上の、長手方向における位置が第1の突起電極13に対応する部分の幅を太くした構成にしてもよい。その他、屈曲部分に丸みを帯びるなど、種々の形状が考えられる。   The wiring board according to the first embodiment of the present invention is not limited to the configuration as shown in FIG. 1A, and can be modified to various configurations without departing from the gist of the embodiment. For example, a configuration in which two second conductor wires 12 facing each other in the longitudinal direction of FIG. 1A are connected to form one second conductor wire 14 as shown in FIG. 1B is used. Can do. Alternatively, as shown in FIG. 1C, the second conductor wiring 15 may be bent into a “<” shape. Further, as shown in FIG. 1D, the width of the portion of the second conductor wiring 16 corresponding to the first protruding electrode 13 at the position in the longitudinal direction may be increased. In addition, various shapes are conceivable, such as a rounded bent portion.

(実施の形態2)
図2は、本発明の実施の形態2における半導体装置に使用される配線基板の構成を示す平面図である。図2において、図1の配線基板と同一の構成要素については、同一の参照符号を付して説明の繰り返しを省略する。
(Embodiment 2)
FIG. 2 is a plan view showing a configuration of a wiring board used in the semiconductor device according to the second embodiment of the present invention. 2, the same components as those of the wiring board of FIG. 1 are denoted by the same reference numerals, and the description thereof will not be repeated.

本実施の形態においては、第2の導体配線17が、第1の導体配線11よりも幅を太くして形成されている。   In the present embodiment, the second conductor wiring 17 is formed to be wider than the first conductor wiring 11.

第2の導体配線17を第1の導体配線11よりも幅を太くすると、絶縁基材10と第2の導体配線17の密着性がさらに向上する。その結果、絶縁基材10が変形して第1の導体配線11または第2の導体配線17に応力がかかることによる破損や断線などを回避しやすくなり、配線基板の信頼性をより高めることができる。   When the width of the second conductor wiring 17 is larger than that of the first conductor wiring 11, the adhesion between the insulating substrate 10 and the second conductor wiring 17 is further improved. As a result, it becomes easy to avoid breakage or disconnection due to deformation of the insulating base material 10 and stress applied to the first conductor wiring 11 or the second conductor wiring 17, thereby further improving the reliability of the wiring board. it can.

(実施の形態3)
本発明の実施の形態3における半導体装置を図3に示す。図3(a)は同半導体装置の平面図、図3(b)は図3(a)のA−A’断面図、図3(c)は図3(a)のB−B’断面図である。この半導体装置に用いられる配線基板は、図1の配線基板と同一であり、同一の構成要素については同一の参照符号を付して、説明の繰り返しを省略する。
(Embodiment 3)
A semiconductor device according to Embodiment 3 of the present invention is shown in FIG. 3A is a plan view of the semiconductor device, FIG. 3B is a cross-sectional view taken along line AA ′ of FIG. 3A, and FIG. 3C is a cross-sectional view taken along line BB ′ of FIG. It is. The wiring board used in this semiconductor device is the same as the wiring board of FIG. 1, and the same components are denoted by the same reference numerals, and the description thereof will not be repeated.

図3(b)、図3(c)の断面図に、この半導体装置を構成する半導体チップ18と配線基板19の構成が示される。   3B and 3C show the configurations of the semiconductor chip 18 and the wiring substrate 19 that constitute the semiconductor device.

半導体チップ18は、半導体素子20に形成された素子電極21上に第2の突起電極22が設けられ、第2の突起電極22の周囲が保護膜23により被覆された構成を有する。第2の突起電極22は、第1の導体配線11に設けられた第1の突起電極13と接合されている。配線基板19には、絶縁基材10そのものを補強するために第2の導体配線12が、第1の導体配線11の長手方向と垂直な方向の外端にそれぞれ隣り合うように形成されているが、第2の導体配線12と対向する位置の素子電極21には、第2の突起電極22が設けられていない。配線基板19上における、半導体チップ18が搭載された領域は、封止材24により封止されている。   The semiconductor chip 18 has a configuration in which a second protruding electrode 22 is provided on an element electrode 21 formed on the semiconductor element 20, and the periphery of the second protruding electrode 22 is covered with a protective film 23. The second protruding electrode 22 is joined to the first protruding electrode 13 provided on the first conductor wiring 11. In the wiring board 19, the second conductor wiring 12 is formed adjacent to the outer ends in the direction perpendicular to the longitudinal direction of the first conductor wiring 11 in order to reinforce the insulating base material 10 itself. However, the second protruding electrode 22 is not provided on the element electrode 21 at a position facing the second conductor wiring 12. A region on the wiring substrate 19 where the semiconductor chip 18 is mounted is sealed with a sealing material 24.

配線基板19側の第1の突起電極13は、絶縁基材10上の第1の導体配線11の上面および両側面を覆うように形成されている。第1の突起電極13と第2の突起電極22との接合により、絶縁基材10上の第1の導体配線11は、半導体素子20上の素子電極21と電気的に接続されている。また、第2の突起電極22は、第1の導体配線11の上面および両側面を覆うように形成された第1の突起電極13に埋没した状態で接合され、半導体素子20と絶縁基材10は封止材24により固定されている。   The first protruding electrode 13 on the wiring board 19 side is formed so as to cover the upper surface and both side surfaces of the first conductor wiring 11 on the insulating base material 10. The first conductor wiring 11 on the insulating substrate 10 is electrically connected to the element electrode 21 on the semiconductor element 20 by joining the first protruding electrode 13 and the second protruding electrode 22. Further, the second protruding electrode 22 is joined in a state of being buried in the first protruding electrode 13 formed so as to cover the upper surface and both side surfaces of the first conductor wiring 11, and the semiconductor element 20 and the insulating base material 10. Is fixed by a sealing material 24.

以上のように、絶縁基材10上に補強のための第2の導体配線12が形成され、配線基板19側の第1の突起電極13と半導体チップ18側の第2の突起電極22とが接合されることにより、第1の実施形態と同様の効果を得られる。また、第2の導体配線12上には突起電極がなく、第2の導体配線12と半導体チップ18の間に物理的に隙間が存在するため、封止材24の充填時に封止材24の流動性が向上し、半導体装置の信頼性を高めることができる。   As described above, the second conductor wiring 12 for reinforcement is formed on the insulating base material 10, and the first protruding electrode 13 on the wiring board 19 side and the second protruding electrode 22 on the semiconductor chip 18 side are formed. By being joined, the same effect as the first embodiment can be obtained. In addition, there is no protruding electrode on the second conductor wiring 12 and there is a physical gap between the second conductor wiring 12 and the semiconductor chip 18. The fluidity is improved and the reliability of the semiconductor device can be improved.

(実施の形態4)
図4は、実施の形態4における半導体装置を示す断面図である。図3に示した実施の形態3における半導体装置と同一の構成要素については、同一の参照番号を付して説明の繰り返しを省略する。
(Embodiment 4)
FIG. 4 is a cross-sectional view showing the semiconductor device according to the fourth embodiment. The same components as those of the semiconductor device according to the third embodiment shown in FIG.

本実施の形態では、配線基板25の構成が、実施の形態3の場合と若干相違する。すなわち、実施の形態3の配線基板19では第2の導体配線12に突起電極が設けられていなかった(図3(b))のに対して、本実施の形態の配線基板25では、第2の導体配線12に第3の突起電極26が設けられている。一方、半導体チップ18では、第3の突起電極26に対向する位置の素子電極21には第2の突起電極22が設けられていない。   In the present embodiment, the configuration of the wiring board 25 is slightly different from that in the third embodiment. That is, in the wiring board 19 of the third embodiment, the protruding electrode is not provided on the second conductor wiring 12 (FIG. 3B), whereas in the wiring board 25 of the present embodiment, the second wiring is provided. A third protruding electrode 26 is provided on the conductor wiring 12. On the other hand, in the semiconductor chip 18, the second protruding electrode 22 is not provided on the element electrode 21 at a position facing the third protruding electrode 26.

以上の構成によれば、絶縁基材10が変形して第1の導体配線11または第2の導体配線12に応力がかかることによる、破損や断線などを抑制する効果がより向上し、半導体装置の信頼性を高めることができる。   According to the above configuration, the effect of suppressing breakage, disconnection, and the like due to the deformation of the insulating base material 10 and the stress applied to the first conductor wiring 11 or the second conductor wiring 12 is further improved. Can improve the reliability.

(実施の形態5)
図5は、実施の形態5における半導体装置の製造方法を示す断面図である。同図は、実施の形態3の半導体装置を製造する場合を例として図示されており、従って、図3に示した構成要素と同一の要素については、同一の参照番号を付して説明の繰り返しを省略する。
(Embodiment 5)
FIG. 5 is a cross-sectional view illustrating the method of manufacturing the semiconductor device in the fifth embodiment. This figure illustrates the case where the semiconductor device according to the third embodiment is manufactured as an example. Therefore, the same components as those shown in FIG. 3 are denoted by the same reference numerals and the description is repeated. Is omitted.

図5(a)に示すように、絶縁基材10の上に、複数の第1の導体配線11が設けられ、第1の導体配線11の長手方向と垂直な方向の外端にそれぞれ隣り合うように1本以上の第2の導体配線12が設けられ、第1の導体配線11に第1の突起電極13が設けられた配線基板19を準備する。   As shown in FIG. 5A, a plurality of first conductor wirings 11 are provided on the insulating base material 10 and are adjacent to the outer ends in the direction perpendicular to the longitudinal direction of the first conductor wirings 11. As described above, a wiring board 19 in which one or more second conductor wirings 12 are provided and the first protruding electrodes 13 are provided on the first conductor wirings 11 is prepared.

また、図5(b)に示すように、半導体素子20上に素子電極21が設けられ、素子電極21の上に半導体素子20ごと被覆して保護膜23が設けられ、素子電極21上の保護膜23に形成された開口部に第2の突起電極22が埋め込まれた半導体チップ18を準備する。   Further, as shown in FIG. 5B, an element electrode 21 is provided on the semiconductor element 20, and a protective film 23 is provided on the element electrode 21 so as to cover the semiconductor element 20, thereby protecting the element electrode 21. The semiconductor chip 18 in which the second protruding electrode 22 is embedded in the opening formed in the film 23 is prepared.

次に図5(c)に示すように、絶縁基材10の第1の導体配線11が形成されている面と、半導体素子20の素子電極21が配列されている面とを対向させる。第1の突起電極13と第2の突起電極22との位置合わせが終了した状態で、半導体素子20と絶縁基材10に対して、接合ツール27により、半導体素子20の裏面(図5(c)では上面)から半導体素子20への接合荷重を、徐々に増加させる。それにより、第1の突起電極13に、第2の突起電極22を埋没させた状態で接合させる。これにより、第1の導体配線11から半導体素子20までを電気的に接続することができる。   Next, as illustrated in FIG. 5C, the surface of the insulating base 10 on which the first conductor wiring 11 is formed and the surface on which the element electrodes 21 of the semiconductor element 20 are arranged are opposed to each other. In a state where the alignment between the first protruding electrode 13 and the second protruding electrode 22 is completed, the back surface of the semiconductor element 20 (see FIG. ) Gradually increases the bonding load from the upper surface) to the semiconductor element 20. As a result, the second protruding electrode 22 is bonded to the first protruding electrode 13 while being buried. As a result, the first conductor wiring 11 to the semiconductor element 20 can be electrically connected.

ここで、第1の突起電極13と第2の突起電極22の接合時に、接合ツール27に対して、第1の導体配線11または第2の導体配線12の長手方向に振動する超音波振動を発生させることにより、第1の突起電極13と第2の突起電極22同士の接合を、より早くかつ確実に行うことができる。また、超音波による接合ツール27の振動方向が第1の導体配線11または第2の導体配線12の長手方向であるため、第1の導体配線11または第2の導体配線12の破損や断線などを回避しやすくなり、半導体装置の信頼性を高めることができる。   Here, when the first protruding electrode 13 and the second protruding electrode 22 are bonded, ultrasonic vibration that vibrates in the longitudinal direction of the first conductor wiring 11 or the second conductor wiring 12 is applied to the bonding tool 27. By generating it, the first protruding electrode 13 and the second protruding electrode 22 can be joined more quickly and reliably. Further, since the vibration direction of the bonding tool 27 by the ultrasonic wave is the longitudinal direction of the first conductor wiring 11 or the second conductor wiring 12, the first conductor wiring 11 or the second conductor wiring 12 is damaged or disconnected. Can be avoided, and the reliability of the semiconductor device can be improved.

なお、実施の形態3の半導体装置に代えて、実施の形態4における半導体装置を製造する場合も、上述と同様に実施することができる。その場合の図5(c)に対応する断面図を図6に示す。この例では、第2の導体配線12に第3の突起電極26を設ける一方で、第3の突起電極26に対向する位置に第2の突起電極22が設けられていない半導体装置を製造する。   Note that the semiconductor device according to the fourth embodiment can be manufactured in the same manner as described above in place of the semiconductor device according to the third embodiment. FIG. 6 shows a cross-sectional view corresponding to FIG. In this example, a semiconductor device in which the second protruding electrode 22 is provided on the second conductor wiring 12 while the second protruding electrode 22 is not provided at a position facing the third protruding electrode 26 is manufactured.

ここで、第1の突起電極13の厚さは10μm程度に形成し、絶縁基材10としては厚さ40μm程度のポリイミドからなるフレキシブルテープを用いる。第1の導体配線11および第2の導体配線12は厚み8μm程度の銅で形成する。   Here, the first protruding electrode 13 is formed to a thickness of about 10 μm, and a flexible tape made of polyimide having a thickness of about 40 μm is used as the insulating substrate 10. The first conductor wiring 11 and the second conductor wiring 12 are made of copper having a thickness of about 8 μm.

第1の突起電極13の材質としては、無電解メッキにより膜形成が可能となる複数種類の金属、例えば、Ni(ニッケル)およびAu(金)を用い、それらの金属をNi、Auの順番(以下、Au/Niのように表記)に無電解メッキすることにより突起電極を層形成するのが一般的であるが、無電解メッキで膜形成が可能な金属であれはどのような金属でも良い。このため、Pd、Pt、Cu等の金属を用いることが考えられる。   As the material of the first protruding electrode 13, a plurality of kinds of metals that can be formed by electroless plating, for example, Ni (nickel) and Au (gold) are used, and these metals are arranged in the order of Ni and Au ( Hereinafter, the protruding electrode is generally formed by electroless plating to Au / Ni), but any metal that can form a film by electroless plating may be used. . For this reason, it is conceivable to use a metal such as Pd, Pt, or Cu.

一方、第2の突起電極22または第3の突起電極26の材質としては、一般的には、電解メッキで形成したAu/CuやAu/Ni/Cuによる突起電極が主となる。   On the other hand, the material of the second protruding electrode 22 or the third protruding electrode 26 is generally a protruding electrode made of Au / Cu or Au / Ni / Cu formed by electrolytic plating.

電解メッキを行う場合、第1の導体配線11を給電線として利用してメッキ材料を導電させる。図1〜図3に示した配線基板または半導体装置を製造する場合、第2の導体配線12は第1の導体配線11と電気的に接続されていないため、第2の導体配線12の上面および側面には突起電極は形成されない。これに対して、図4に示す半導体装置を製造する場合、第2の導体配線12と第1の導体配線11とを電気的に接続すれば、第2の導体配線12を利用してメッキ材料が導電されることにより、第2の導体配線12の上面および側面に第3の突起電極26が形成される。   When electrolytic plating is performed, the plating material is made conductive by using the first conductor wiring 11 as a power supply line. When manufacturing the wiring substrate or the semiconductor device shown in FIGS. 1 to 3, the second conductor wiring 12 is not electrically connected to the first conductor wiring 11. No protruding electrode is formed on the side surface. On the other hand, when the semiconductor device shown in FIG. 4 is manufactured, if the second conductor wiring 12 and the first conductor wiring 11 are electrically connected, the second conductor wiring 12 is used for the plating material. As a result, the third protruding electrode 26 is formed on the upper surface and the side surface of the second conductor wiring 12.

本発明によれば、例えば、導体配線の突起電極と半導体素子の素子電極を接合する際に超音波振動を利用した場合の、超音波振動による導体配線への機械的ダメージを低減する等、絶縁基材が変形して導体配線に応力がかかることを抑制できる。それにより、第1の導体配線または第2の導体配線の破損や断線などを防止することができ、半導体装置の信頼性を向上させるために有用である。   According to the present invention, for example, when ultrasonic vibration is used when the protruding electrode of the conductor wiring and the element electrode of the semiconductor element are joined, the mechanical damage to the conductor wiring due to the ultrasonic vibration is reduced. It can suppress that a base material deform | transforms and stress is applied to conductor wiring. Thereby, damage or disconnection of the first conductor wiring or the second conductor wiring can be prevented, which is useful for improving the reliability of the semiconductor device.

本発明の実施の形態1における半導体装置に使用される配線基板の構成を示す平面図The top view which shows the structure of the wiring board used for the semiconductor device in Embodiment 1 of this invention. 実施の形態2における半導体装置に使用される配線基板の構成を示す平面図A plan view showing a configuration of a wiring board used in a semiconductor device in a second embodiment 実施の形態3における半導体装置の構成を示し、(a)は平面図、(b)は(a)のA−A’断面図、(c)は(a)のB−B’断面図4A and 4B illustrate a structure of a semiconductor device in Embodiment 3, where FIG. 5A is a plan view, FIG. 5B is a cross-sectional view taken along the line A-A ′ in FIG. 実施の形態4における半導体装置の構成を示す断面図Sectional drawing which shows the structure of the semiconductor device in Embodiment 4 実施の形態5における半導体装置の製造方法を示す断面図Sectional drawing which shows the manufacturing method of the semiconductor device in Embodiment 5 同実施の形態の半導体装置の製造方法の変更例を示す断面図Sectional drawing which shows the example of a change of the manufacturing method of the semiconductor device of the embodiment 従来例の半導体装置の構造を示し、(a)は平面図、(b)は(a)のC−C’断面図、(c)は(a)のD−D’断面図2A and 2B show a structure of a conventional semiconductor device, in which FIG. 1A is a plan view, FIG. 1B is a cross-sectional view taken along the line C-C ′ in FIG.

符号の説明Explanation of symbols

1、10 絶縁基材
2 デバイスホール
3、11 第1の導体配線
4、12、14、15、16、17 第2の導体配線
5 突起電極
6、20 半導体素子
7、21 素子電極
8、23 保護膜
9、24 封止材
13 第1の突起電極
18 半導体チップ
19、25 配線基板
22 第2の突起電極
26 第3の突起電極
27 接合ツール
DESCRIPTION OF SYMBOLS 1, 10 Insulation base material 2 Device hole 3, 11 1st conductor wiring 4, 12, 14, 15, 16, 17 2nd conductor wiring 5 Protrusion electrode 6, 20 Semiconductor element 7, 21 Element electrode 8, 23 Protection Films 9 and 24 Sealing material 13 First protruding electrode 18 Semiconductor chip 19 and 25 Wiring substrate 22 Second protruding electrode 26 Third protruding electrode 27 Joining tool

Claims (5)

可撓性を有する絶縁基材と、前記絶縁基材上に整列して設けられた複数の第1の導体配線と、前記第1の導体配線に設けられた第1の突起電極と、前記第1の導体配線の長手方向と垂直な方向における外端側にそれぞれ隣り合うように設けられた1本以上の第2の導体配線とを備えた配線基板。   A flexible insulating base, a plurality of first conductor wirings arranged in alignment on the insulating base, a first protruding electrode provided on the first conductor wiring, and the first A wiring board comprising one or more second conductor wirings provided adjacent to the outer end sides in a direction perpendicular to the longitudinal direction of one conductor wiring. 前記第2の導体配線の幅が前記第1の導体配線の幅よりも広い請求項1に記載の配線基板。   The wiring board according to claim 1, wherein a width of the second conductor wiring is wider than a width of the first conductor wiring. 可撓性を有する絶縁基材、前記絶縁基材上に整列して設けられた複数の第1の導体配線、前記第1の導体配線に設けられた第1の突起電極、および前記第1の導体配線の長手方向と垂直な方向の外端側にそれぞれ隣り合うように設けられた1本以上の第2の導体配線を有する配線基板と、
半導体素子、前記半導体素子上に設けられた素子電極、および前記素子電極上に設けられた第2の突起電極を有する半導体チップとを備え、
前記配線基板に前記半導体チップが搭載され、前記配線基板の前記第1の突起電極と前記半導体チップの前記第2の突起電極が対向して接合されることにより、前記第1の導体配線から前記半導体素子までが電気的に接続されており、
前記第2の導体配線は、前記第2の突起電極および前記半導体素子との間に隙間が設けられ、絶縁されていることを特徴とする半導体装置。
A flexible insulating base, a plurality of first conductor wirings arranged in alignment on the insulating base, a first protruding electrode provided on the first conductor wiring, and the first A wiring board having one or more second conductor wirings provided adjacent to the outer end sides in the direction perpendicular to the longitudinal direction of the conductor wiring;
A semiconductor chip having a semiconductor element, an element electrode provided on the semiconductor element, and a second protruding electrode provided on the element electrode;
The semiconductor chip is mounted on the wiring board, and the first protruding electrode of the wiring board and the second protruding electrode of the semiconductor chip are bonded to face each other, so that the first conductor wiring The semiconductor elements are electrically connected,
The semiconductor device, wherein the second conductor wiring is insulated by providing a gap between the second protruding electrode and the semiconductor element.
前記第2の導体配線に第3の突起電極が設けられ、前記第3の突起電極に対向する位置の前記半導体素子の前記素子電極上には、前記第2の突起電極が設けられていない請求項3に記載の半導体装置。   A third protruding electrode is provided on the second conductor wiring, and the second protruding electrode is not provided on the element electrode of the semiconductor element at a position facing the third protruding electrode. Item 4. The semiconductor device according to Item 3. 可撓性を有する絶縁基材、前記絶縁基材上に整列して設けられた複数の第1の導体配線、前記第1の導体配線に設けられた第1の突起電極、および前記第1の導体配線の長手方向と垂直な方向の外端側にそれぞれ隣り合うように設けられた1本以上の第2の導体配線を有する配線基板を準備する工程と、
半導体素子、前記半導体素子上に設けられた素子電極、および前記素子電極上に設けられた第2の突起電極を有する半導体チップを準備する工程と、
前記絶縁基材の前記第1の導体配線および前記第2の導体配線が形成されている面と、前記半導体素子の前記素子電極が配列されている面とを対向させ、前記絶縁基材上に前記半導体素子を載置して、前記半導体素子を経由して前記第1の導体配線の長手方向に振動する超音波振動を印加し、前記第1の突起電極と前記第2の突起電極とを超音波接合して前記第1の導体配線から前記半導体素子までを電気的に接続する工程とを含む半導体装置の製造方法。
A flexible insulating base, a plurality of first conductor wirings arranged in alignment on the insulating base, a first protruding electrode provided on the first conductor wiring, and the first Preparing a wiring board having one or more second conductor wirings provided adjacent to the outer end sides in the direction perpendicular to the longitudinal direction of the conductor wiring;
Preparing a semiconductor chip having a semiconductor element, an element electrode provided on the semiconductor element, and a second protruding electrode provided on the element electrode;
The surface of the insulating substrate on which the first conductor wiring and the second conductor wiring are formed and the surface of the semiconductor element on which the element electrodes are arranged are opposed to each other on the insulating substrate. Place the semiconductor element, apply ultrasonic vibration that vibrates in the longitudinal direction of the first conductor wiring via the semiconductor element, and connect the first protruding electrode and the second protruding electrode. And a step of electrically connecting the first conductor wiring to the semiconductor element by ultrasonic bonding.
JP2005354049A 2005-12-07 2005-12-07 Wiring board, semiconductor device using same, and method of manufacturing them Withdrawn JP2007158194A (en)

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