JP2007143099A - Ramp signal generation circuit and electro-optical device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a ramp signal generation circuit and an electro-optical device with low power consumption. <P>SOLUTION: As a first process a single-throw switch S<SB>0</SB>is closed, and for double-throw switches S<SB>1-u</SB>, S<SB>1-d</SB>, S<SB>2</SB>a terminal a and a common terminal are closed. As a second process, the single-throw switch S<SB>0</SB>is opened, and for the double throw switches S<SB>1-u</SB>, S<SB>1-d</SB>, S<SB>2</SB>the terminal a and the common terminal are closed. As a third process, for the double-throw switches S<SB>1-u</SB>, S<SB>1-d</SB>, S<SB>2</SB>a terminal b and the common terminal are closed. Thereafter, the second and third processes are repeated. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a technique for generating a lamp waveform suitable for an electro-optical device.

An electro-optical device that performs display by an electro-optical change such as a liquid crystal displays a pixel by applying a voltage corresponding to a gradation to a pixel electrode through a data line during a period in which a selection voltage is applied to the scanning line. The gray scale display is performed by controlling the effective voltage value applied to. However, in this configuration, it is necessary to generate a positive polarity voltage and a negative polarity voltage according to the gradation, so that the voltage generation circuit becomes complicated, and simplification of the configuration is hindered.
Therefore, during the period when the selection voltage is applied to the scanning line, a ramp signal whose voltage gradually changes is applied to the common electrode facing the pixel electrode, and the data line is set to a predetermined potential only during the period corresponding to the gradation. A technique for bringing the state into a high impedance state after being kept at is proposed (see Patent Document 1).
As a technique for generating such a ramp signal, in addition to the above-mentioned document, a capacitor element (capacitor) is charged with a constant current source to change the holding voltage of the capacitor at a constant rate, and this is referred to as a ramp signal. (Refer to Patent Document 2).
JP-A-7-281642 JP-A-6-326565

By the way, in the electro-optical device, there is an extremely strong demand for low power consumption. For this reason,
The ramp signal generation circuit is also strongly required to have low power consumption when generating the ramp signal, but the above two techniques are not sufficient in terms of low power consumption.
The present invention has been made in view of such circumstances, and an object thereof is to provide a lamp signal generation circuit and an electro-optical device that achieve low power consumption.

To achieve the above object, the present invention includes a single throw switch, first, second and third double throw switches, first, second and third capacitive elements, a reference voltage source, and a buffer circuit. And a switch control circuit, wherein the first capacitive element is inserted at a common end of the first and second double throw switches, and the reference voltage source is connected to a first terminal of the first double throw switch. One pole is connected, one terminal of the second capacitive element is connected to the common end of the third double throw switch, and the third
One terminal of the single throw switch, one terminal of the third capacitive element, and an input terminal of the buffer circuit are connected to the first terminal of the double throw switch, and the first or second double throw switch The second terminal of the third double-throw switch is connected to one of the second terminals, and the first terminal of the second double-throw switch and the second capacitor element are connected to the other pole of the reference voltage source. The other terminal,
The other terminal of the single throw switch and the other terminal of the third capacitive element are connected in common, and the output terminal of the buffer circuit is connected to the other second terminal of the first or second double throw switch. The output of the voltage of the buffer circuit, and the switch control circuit closes the single throw switch as a first stroke and opens the single throw switch as a second stroke, and the first, For the second and third double throw switches, the first terminal and the common end are closed, respectively, and as the third stroke, for the first, second and third double throw switches,
The second terminal and the common end are respectively closed, and thereafter, the second and third steps are repeated.
According to this configuration, since the ramp signal is generated by repeating the charging to the first capacitor element and the distribution to the second and third capacitor elements, the consumed power is suppressed, and
The voltage change of the ramp signal can be controlled by the repetition period of the second and third strokes.

In the present invention, the second terminal of either the first or second double throw switch is selected and connected to the second terminal of the third double throw switch, and the first or second double throw switch It is good also as a structure which further has the switching circuit which selects the other 2nd terminal and connects to the output terminal of the said buffer circuit. With this configuration, the change direction of the ramp signal can be switched between the upward direction and the downward direction.
In the present invention, the buffer circuit further includes fourth and fifth double throw switches and a fourth capacitive element, and a fourth capacitive element is interposed at a common end of the fourth and fifth double throw switches. Is connected to the first terminal of the fourth double-throw switch, to the other terminal of the reference voltage source, to the second terminal of the fourth double-throw switch, and to the second terminal of the fifth double-throw switch. One terminal is connected, a second terminal of the fifth double-throw switch is connected to an input terminal of the buffer circuit, and the switch control circuit is connected to the fourth and fifth double-throw switches in the first step. The first terminal and the common end are closed, and after the second stroke, the second terminal and the common end are once closed for the fourth and fifth double throw switches, respectively. It is good also as a structure opened after a while.
In this configuration, when the third capacitive element is removed, the switch control circuit connects the one terminal and the common end to the fourth and fifth double throw switches in the first stroke, respectively. The second terminal and the common end may be closed with respect to the fourth and fifth double throw switches after the second stroke.
If the output voltage from the buffer circuit does not reach a predetermined voltage when the second and third steps are repeated a predetermined number of times by the switch control circuit, the capacitance value of the third capacitive element A capacitance changing circuit that changes at least one capacitance value of the first, second, and third capacitance elements so that the relative value of the capacitance values of the first or second capacitance elements becomes small;
And when the output voltage from the buffer circuit reaches a predetermined voltage before the switch control circuit repeats the second and third steps a predetermined number of times, the capacitance of the third capacitor element A capacitance changing circuit that changes at least one capacitance value of the first, second, and third capacitive elements so that the relative value of the capacitance value of the first, second, or third capacitive element is larger than the value. And may further include
On the other hand, if the output voltage from the buffer circuit does not reach a predetermined voltage when the second and third steps are repeated a predetermined number of times by the switch control circuit, the capacitance value of the fourth capacitive element A configuration may further include a capacitance changing circuit that changes at least one capacitance value of the first, second, and third capacitance elements so that the relative value of the capacitance values of the first or second capacitance elements becomes small. The second and third are controlled by the switch control circuit.
If the output voltage from the buffer circuit reaches a predetermined voltage before the process is repeated a predetermined number of times, the relative value of the capacitance value of the first or second capacitance element with respect to the capacitance value of the fourth capacitance element is It may be configured to further include a capacitance changing circuit that changes at least one capacitance value of the first, second, and third capacitance elements so as to increase.
The present invention can be conceptualized not only as a lamp signal generation circuit but also as an electro-optical device having the lamp signal generation circuit.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
First, the ramp signal generation circuit according to the first embodiment of the present invention will be described. FIG. 1 is a circuit diagram showing a configuration of the ramp signal generation circuit.
As shown in this figure, the ramp signal generation circuit 10 includes a single throw switch S ₀ , double throw switches S _{1 -u} , S _{1 -d} and S ₂ , capacitors 21, 22 and 23, and a reference voltage source. 30
And a buffer circuit 40 and a switch control circuit 50.
Among these, the single throw switch S ₀ is the reset signal R supplied from the switch control circuit 50.
Each of the double throw switches S _1-u , S _1-d, and S ₂ is closed when es is at the H level, and the clock signal Clk supplied from the switch control circuit 50 is at the H level. Sometimes closed between the common terminal and the terminal a (first terminal), while closed between the common terminal and the terminal b (second terminal) when the clock signal Clk is at L level It is. In the present embodiment, the double throw switches S _1-u , S _1-d, and S ₂ correspond to the first, second, and third double throw switches, respectively.

Between each common end of the double throw switches S1 _-u and S1 _-d , a capacitor 21 (first capacitance element)
Is inserted. Terminal a of double throw switch S _1-u is connected to the positive terminal of the reference voltage source 30 that generates a reference voltage Vref, the terminal b of the double throw switch S _1-u is double-throw switch S ₂
Is connected to terminal b.
The common terminal of the double-throw switch S ₂ is connected to one terminal of the capacitor 22 (second capacitor element), the terminal a of the double throw switch S ₂ is one terminal of the single-throw switches S _0, the capacitor 23 (
And the input terminal of the buffer circuit 40, respectively.
Of the terminals of the capacitor 21, the double throw switch S1 _-u side is _defined as one terminal m,
Of the terminals of the capacitor 22, to the side of the double throw switch S ₂ and the terminal n.

The buffer circuit 40 is a voltage amplification circuit with an amplification factor of “1”, and the output voltage thereof is the output voltage Vout of the ramp signal generation circuit 10. The output terminal is a double throw switch S _1.
-D is connected to the terminal b.
The terminal a of the double throw switch S _{1 -d} , the other terminal of the capacitor 22, the other terminal of the single throw switch S ₀ , and the other terminal of the capacitor 23 are commonly connected to the negative terminal of the reference voltage source 30. Has been. In the present embodiment, the common connection portion is set to a ground potential of zero voltage (the same applies to the second and third embodiments described later).

The switch control circuit 50 outputs a clock signal Clk and a reset signal Res. Here, as shown in FIG. 2, the reset signal Res becomes H level simultaneously with the clock signal Clk at the start of operation, but its pulse width is shorter than that of the clock signal Clk. Also,
The period of the clock signal Clk is constant in the present embodiment, but may change as described later.
Note that the single throw switch S ₀ and the double throw switches S _1-u , S _1-d, and S ₂ are described here as mechanical switches, but actually, a single transistor or a combination of transistors is used. It consists of an electronic switch composed of transmission gates.

Next, the operation of the ramp signal generation circuit 10 will be described. FIG. 3 is a diagram simply showing the configuration of the ramp signal generation circuit 10 divided into each period, and FIG. 4 shows the relationship between the switch state, the voltage at the terminal n, and the output voltage Vout in each period. FIG.
First, in the period (1) when the reset signal Res and the clock signal Clk are simultaneously at the H level at the start of operation, the single throw switch S ₀ is closed and the double throw switch S _1-u ,
S _1-d and _{S 2} is closed between the common terminal and the terminal a. For this reason, the ramp signal generation circuit 10 is configured so that the capacitor 21 is charged to the reference voltage Vref while both ends of the capacitors 22 and 23 are short-circuited as shown in FIG. The hold state is cleared.
Since the input terminal of the buffer circuit 40 is also grounded, the output voltage Vout is ideally zero.

Subsequently, the reset signal Res is the L level, in the period (2) of the clock signal Clk is maintained at H level, since the single-throw switch S ₀ is opened, simplified manner the circuit shown in FIG. 3 (2) It becomes. Although the input terminal of the buffer circuit 40 is not in the grounded state with the opening of the single throw switch S ₀ , the holding voltage of the capacitors 22 and 23 is zero in the period (2) immediately after the period (1). The output voltage Vout is still zero.

Next, in the period (3) when the clock signal Clk is at the L level, the double throw switches S _1-u , S
_1-d and S ₂ is closed between the common terminal and the terminal b. For this reason, the ramp signal generation circuit 10 is simply a circuit as shown in FIG. At this time, since the holding voltage of the capacitor 23 is zero, the output voltage Vout is still zero.
On the other hand, the terminal m of the capacitor 21 charged with the voltage Vref is connected to the terminal n of the capacitor 22, but the other terminal of the capacitor 21 is connected to the output terminal of the buffer circuit 40 having a voltage of zero, and the other terminal of the capacitor 22 is connected. Since the terminal is in a ground state of zero voltage, a part of the electric charge accumulated in the capacitor 21 moves to the capacitor 22.
Here, when the capacitance values of the capacitors 21 and 22 are respectively C ₁ and C ₂ , the holding voltage of the capacitor 22, that is, the voltage at the terminal n is Vref · C ₁ / (C ₁ + C ₂ ).

Subsequently, in the period (4) when the clock signal Clk is at the H level, the double throw switch S1 _-u.
Since S _1-d and S ₂ is closed between the common terminal and the terminal a, the same circuit configuration as the period (2).
However, the holding voltage of the capacitor 22 immediately before is Vref · C ₁ /
Since (C ₁ + C ₂ ), the voltage at the input terminal of the buffer circuit 40 becomes Vref · C ₁ / (C ₁ + C ₂ + C ₃ ), which is redistributed by the capacitance value C ₃ of the capacitor 23, and this voltage Is output as Vout. For convenience, Vref · C ₁ / (C ₁ + C ₂ + C ₃ ) is expressed as Δ
V.
On the other hand, the capacitor 21 charges the reference voltage Vref again with the terminal m as the high-order side.

In the period (5) when the clock signal Clk is at the L level, the double throw switches S _1-u , S _1-d
And since S ₂ is closed between the common terminal and the terminal b, the same circuit configuration as the period (3).
However, the output voltage Vout obtained by amplifying the holding voltage of the capacitor 23 with the amplification factor “1” by the buffer circuit 40 is ΔV, and this voltage is applied to the other terminal of the capacitor 21 charged with the voltage Vref, and Since the terminal m and the terminal n are connected and the other terminal of the capacitor 22 is grounded at a voltage of zero, a part of the electric charge accumulated in the capacitor 21 moves to the capacitor 22. At this time, the voltage at the terminal n is Vref · C ₁ / (C ₁ + C ₂ ) + Δ
V.
When the clock signal Clk becomes H level in the period (6), the double throw switches S _1-u , S
Since _1-d and S ₂ is closed between the common terminal and the terminal a, the voltage at the input terminal of the buffer circuit 40, [Delta] V + [Delta] V, i.e. 2ΔV next, which is the output voltage Vout.

Thereafter, the capacitor 21 is set to the reference voltage Vre during the period when the clock signal Clk is at the H level.
In the period when the clock signal Clk is at the L level, the charge voltage Vref of the capacitor 21 is increased by the output voltage Vout and distributed to the capacitor 22 during the period when the clock signal Clk is at the L level.
During the period in which lk becomes H level again, the operation of redistributing the charging voltage of the capacitor 22 to the capacitor 23 and outputting it through the buffer circuit 40, while charging the capacitor 21 to the reference voltage Vref is repeated.
As a result, in this embodiment, as shown in FIG. 2, the output voltage Vout increases by ΔV for each cycle of the clock signal Clk.

In the present embodiment, the reference voltage Vref charged in the capacitor 21 is distributed to the capacitor 22 in a state where the reference voltage Vref is raised by the output voltage Vout, and is further redistributed to the capacitor 23, which is output by the buffer circuit 40. is there. For this reason, D / A using resistance division or a constant current source
Compared with the configuration for conversion, it is possible to keep power consumption extremely low.
In this embodiment, since the output voltage Vout changes by ΔV in one cycle of the clock signal Clk, if the frequency of the clock signal Clk is constant, the rate of change of the output voltage Vout is also constant. In other words, this means that the rate of change of the output voltage Vout can be arbitrarily set by controlling the frequency of the clock signal Clk.
For example, as shown in FIG. 5A, after the output of the reset signal Res, the clock signal Clk
When the frequency of the output signal Vout is gradually reduced, the rate of change of the output voltage Vout can be gradually reduced. As shown in FIG. 5B, after the reset signal Res is output, the frequency of the clock signal Clk is gradually increased. When the output voltage Vout is increased, the rate of change of the output voltage Vout can be gradually increased.

In the first embodiment, the output voltage Vout is generated by increasing from zero. However, the output voltage Vout can be generated by lowering the structure by slightly changing the configuration. Regarding this change, (A) the connection of the reference voltage source 30 is changed, or (B) the terminal b and the output terminal of the buffer circuit 40 at the double throw switches S _1-u , S _1-d , S ₂ . The connection destination is changed.
Of these, (A) will be described. If the output voltage Vout is merely lowered from zero, it is only necessary to invert the polarity of the reference voltage source 30 as shown in FIG. However,
When the output voltage Vout is generated so as to be switchable in the descending direction and the ascending direction, the polarities 2 are different.
The configuration for selecting one of the two reference voltage sources 30 is not a good idea because two reference voltage sources 30 are required.
For this reason, a configuration in which the polarity of one reference voltage source 30 is switched and connected in accordance with the decreasing or increasing direction of the output voltage Vout is preferable. This configuration will be described in a fourth embodiment to be described later.

Next, the configuration (B) will be described with reference to FIG. As shown in this figure, double throw switches S _5-p and S _5-q are added to the configuration shown in FIG. 1, and a terminal b in double throw switch S _1-u is double throw switch S _{5- p} terminal a and double throw switch S _5-
is connected to the _q terminal b of the terminal b in the double throw switch _{S 1-d} is connected to the terminal a of the terminal b and sweeping switches _{S 5-q} of the double throw switch _{S 5-p,} in double-throw switch _{S 2} The terminal b is connected to the common terminal of the double throw switch S5 _-p , and the output terminal of the buffer circuit 40 is connected to the common terminal of the double throw switch S5 _-q .
Here, each of the double throw switches S _5-p and S _5-q is closed between the common terminal and the terminal a as indicated by a solid line when the polarity instruction signal Pol is at the H level. When the polarity instruction signal Pol is at the L level, the signal is closed between the common terminal and the terminal b as indicated by a broken line. For this reason, the double throw switches S _5-p and S _5-q correspond to the switching circuit.
Further, the polarity instruction signal Pol is a signal for designating the changing direction of the output voltage Vout here. Specifically, when the signal is at the H level, the descending direction is designated, and when the signal is at the L level, the raising direction is designated. .

In the configuration shown in FIG. 7, when the polarity indication signal Pol is at the L level, the terminal b in the double throw switch S _1-u is connected to the terminal b of the double-throw switch S _2, double throw switch S _1-d
1 is connected to the output terminal of the buffer circuit 40, the equivalent circuit thereof is the same as that shown in FIG.
On the other hand, when the polarity instruction signal Pol is at the H level, the terminal b in the double throw switch S1 _-u .
There is connected to the output terminal of the buffer circuit 40, the terminal b in the double throw switch S _1-d is connected to the terminal b of the double-throw switch S _2.
For this reason, as shown in FIG. 8, after the charging voltage of the capacitors 22 and 23 is reset to zero in the period (1), the capacitor 21 is charged to the reference voltage Vref in the period (2), and the period (3) , The charging voltage Vref of the capacitor 21 is distributed to the capacitor 22 while being lowered by the output voltage Vout, and the charging voltage of the capacitor 22 is redistributed to the capacitor 23 and output through the buffer circuit 40 in the period (3). On the other hand, since the operation of charging the capacitor 21 to the reference voltage Vref is repeated, the configuration shown in FIG.
The output voltage Vout decreases by ΔV every cycle of the clock signal Clk.

Second Embodiment
In the first embodiment described above, the buffer circuit 40 has been described as a voltage amplification circuit having an ideal amplification factor “1”, but actually, even if the voltage at the input end is zero, the voltage Vout at the output end is zero. Does not become zero, and an offset voltage is output to some extent.
Therefore, a description will be given of a second embodiment in which such an offset voltage is eliminated as much as possible to approximate ideal output characteristics.

FIG. 9 is a circuit diagram showing a configuration of a ramp signal generation circuit according to the second embodiment of the present invention.
The configuration shown in FIG. 9 differs from the first embodiment shown in FIG.
Are provided with double throw switches S _3-u and S _3-d , a capacitor 24 and a switch control circuit 51. Therefore, this difference will be mainly described below. The switch control circuit 51 outputs the clock signal Clk and the reset signal Res of the first embodiment, and further outputs a signal group Offset for controlling the double throw switches S _3-u and S _3-d .
Each of the double throw switches S3 _-u and S3 _-d is closed between the common terminal and the terminal a only when the reset signal Res is at the H level, and is common only for a predetermined period after changing to the L level. It is closed between the terminal and the terminal b. This predetermined period ends before the signal Clk becomes L level, and after this predetermined period, the double throw switches S _3-u and S _3-d are either “inactive” as follows:
Take a state. That is, (a) the double-throw switch S _3-u is closed with the terminal a, and the double-throw switch S _3-d is in an open state for both the terminals a and b. (B) the double-throw switch S _3-u Is terminal b
And the double throw switch S _3-d is closed with the terminal a or both terminals a and b are open, and (c) the double throw switch S _3-u is open with both terminals a and b. In addition, the double throw switch S3 _-d is closed with the terminal a or b, or both the terminals a and b are opened.
This control is performed by a signal Offset output from the switch control circuit 51. The double throw switches S3 _-u and S3 _-d correspond to the fourth and fifth double throw switches.
The terminal a of the double throw switch S3 _-u is connected to the output terminal of the buffer circuit 40. In addition, a capacitor 24 (fourth capacitive element) is provided between the common ends of the double throw switches S _3-u and S _3-d.
Is inserted. Here, of the terminals of the capacitor 24, the double throw switch S3 _-u side is defined as one terminal p.
The terminal b of the double throw switch S _{3 -d} is connected to the input terminal of the buffer circuit 40. On the other hand, the terminal b of the double throw switch S _{3-u and} the terminal a of the double throw switch S _3-d are commonly connected to the negative terminal of the reference voltage source 30.

In this configuration, the reset signal Res and the clock signal Clk are simultaneously at the H level (
In 1), since the double throw switches S _3-u and S _3-d are closed between the common terminal and the terminal a, the offset voltage Voff of the buffer circuit 40 when the input terminal has a voltage of zero.
Is held in the capacitor 24 with the terminal p as the high-order side. Incidentally, the capacitance value of the capacitor 24 and _{C 0.}
In the period (2) in which the reset signal Res is at the L level, the double throw switches S _3-u and S _{3
Since −d} is closed between the common terminal and the terminal b, one terminal p of the capacitor 24 is grounded, and the other terminal is connected to the input terminal of the buffer circuit 40. For this reason, the offset voltage Voff held in the capacitor 24 is applied to the input terminal of the buffer circuit 40 with the terminal p as the lower side, and is distributed to the capacitors 22 and 23. For this reason, the buffer circuit 4
A voltage reduced by Voff · C ₀ / (C ₀ + C ₂ + C ₃ ) is applied to the input terminal of 0 as compared to the first embodiment.
Here, if the capacitance value C ₀ is made sufficiently larger than the capacitance sum (C ₂ + C ₃ ), the voltage at the input terminal of the buffer circuit 40 becomes lower than the first embodiment by Voff, and eventually the buffer The offset voltage of the circuit 40 is canceled and the output voltage Vout becomes zero.
This state is canceled before the signal Clk becomes L level, and the subsequent operations are the same as in the first embodiment.

In the period (3) and after, the operation of charging the output voltage Vout to the capacitor 24 only consumes power wastefully. Therefore, in the period (3) and later, although the "inactive" state described above, while for closing especially for double-throw switch S _3-u between the common terminal and the terminal b, double throw switch S _{3 It} is desirable that the capacitor 24 be disconnected from the input / output end of the buffer circuit 40 by closing the common terminal and the terminal a with _respect to _−d . This is “inactive”
In this state, the potential across the fourth capacitive element becomes the ground potential, and the voltage across the fourth capacitive element is 0.
Therefore, malfunctions can be prevented.

In this embodiment, the capacitance value C ₀ of the capacitor 24 is larger than the capacitance sum (C ₂ + C ₃ ), but the charging voltage for the capacitor 24 is about the offset voltage of the buffer circuit 40 in the period (1). (Several tens of mV), the power consumption of the large-capacitance capacitor 24 is hardly a problem.
For example, the capacitance value C ₀ is 0.01 μF, and the offset voltage of the buffer circuit 40 is 50
When mV and the frequency of generation of the reset signal Res is 14.4 kHz, the capacitor 2
The power consumed by 4 is 0.36 μW (= 14400 × (0.05) ² × (0.01
× 10 ⁻⁶ )) only.
Further, the fourth capacitor element (capacitor 24) can also serve as the third capacitor element (capacitor 23). In other words, the capacitance value of the fourth capacitor element may be set to the capacitance value of the third capacitor element, and the third capacitor element may be removed.
In this configuration, the reset signal Res and the clock signal Clk are simultaneously at the H level (
In 1), since the double throw switches S _3-u and S _3-d are closed between the common terminal and the terminal a, the offset voltage Voff of the buffer circuit 40 when the input terminal has a voltage of zero.
Is held in the capacitor 24 with the terminal p as the high-order side. Incidentally, the capacitance value of the capacitor 24 and _{C 3.}
In the period (2) in which the reset signal Res is at the L level, the double throw switches S _3-u and S _{3
Since −d} is closed between the common terminal and the terminal b, one terminal p of the capacitor 24 is grounded, and the other terminal is connected to the input terminal of the buffer circuit 40. For this reason, the offset voltage Voff held in the capacitor 24 is applied to the input terminal of the buffer circuit 40 with the terminal p at the lower side, and only Voff is applied to the input terminal of the buffer circuit 40 than in the first embodiment. A reduced voltage will be applied.
Eventually, the offset voltage of the buffer circuit 40 is canceled and the output voltage Vout becomes zero.
Subsequent operations are the same as those in the first embodiment. As a result, the number of capacitive elements can be reduced, and control can be performed only with the signals Clk and Res as in the switch control circuit 50 of the first embodiment, so that the circuit configuration can be further simplified.

In the second embodiment as well, the output voltage Vout can be generated in the descending direction by configuring as shown in FIGS.

<Third Embodiment>
In the second embodiment described above, the offset voltage Voff in the buffer circuit 40 can be canceled, but the voltage change Δ of the output signal Vout due to the level inversion of the clock signal Clk.
V ′ is not the voltage ΔV in the first embodiment but a value as shown in the following equation.
ΔV ′ = ΔV + Voff · C ₁ / (C ₁ + C ₂ + C ₃ )
= (Vref + Voff) · C ₁ / (C ₁ + C ₂ + C ₃ )
Therefore, the output signal Vo is generated by the capacitance values C ₁ , C ₂ , C ₃ and the offset voltage Voff.
The change rate of ut may not match the initial target value. Therefore, a third embodiment in which the rate of change of the output signal Vout is automatically adjusted so as to match the initial target value as much as possible will be described.
In the ramp signal generation circuit 10, as a target value for the rate of change of the output signal Vout,
As shown in FIG. 12A or FIG. 12B, the rate of change is such that the reference voltage Vref is reached when the clock signal Clk has passed “256” cycles from the voltage zero due to the output of the reset signal Res. Suppose.

FIG. 10 is a circuit diagram showing a configuration of a ramp signal generation circuit according to the third embodiment of the present invention. The configuration shown in FIG. 10 is different from the second embodiment shown in FIG.
3 is variable, the arithmetic circuit 64 outputs the difference voltage between the output voltage Vout and the reference voltage Vref, and the capacitance change circuit 6 changes the capacitance value of the capacitor 23 according to the difference voltage.
In the point having 0. Therefore, this difference will be mainly described below.
First, with respect to the capacitor 23, in detail, as shown in FIG. 11, the capacitance value C _3a
And one capacitor, the capacitance value _{ΔC 3, 2ΔC 3, 4ΔC 3} , 8ΔC 3, 16ΔC 3, 3
6 capacitors of 2ΔC ₃ and 6 switches for turning on and off the capacitors related to the latter 6 respectively, and when the 6 switches are on, 7 capacitors are connected in parallel to each other It has a configuration. The six switches are individually turned on / off by signals d ₅ -d _{0 from} the capacitance changing circuit 60.
Therefore, the capacitance value C ₃ of the capacitor 23, the lowest value when all switches are off C
_{From 3a} to the highest value (C _3a + 63ΔC ₃ ) when all switches are on, ΔC ₃
Are variably set in 64 steps.

The capacity changing circuit 60 has a counter inside, resets the counter to zero when the reset signal Res becomes H level, up-counts at the rising edge of the clock signal Clk, and the count result becomes “256”. When the output voltage Vout reaches the reference voltage Vref, the capacitance value of the capacitor 23 is changed.
Specifically, as shown in FIG. 12A, the count result of the clock signal Clk is “25”.
When 6 is reached, it means that the current rate of change is smaller than the target value. Therefore, as the voltage Vd corresponding to the amount that the output voltage Vout is less than the reference voltage Vref increases, the capacitance changing circuit 60 increases the rate of change when the reset signal Res is output next time. The capacitance value of the capacitor 23 is changed to be small.
On the other hand, as shown in FIG. 12B, the count result of the clock signal Clk is “256”.
If the output voltage Vout is relative to the reference voltage Vref before reaching, this means that the current rate of change is greater than the target value. Therefore, the output voltage Vout from “256”
As the period Td corresponding to the value obtained by subtracting the count value at the time when the voltage is at the reference voltage Vref increases, the capacitance changing circuit 60 sets the capacitor so that the rate of change decreases when the reset signal Res is output next time. 23 is changed so as to increase the capacitance value.

Here, the capacity changing circuit 60 stores in advance a table corresponding to the capacity change of the capacitor 23 with respect to, for example, the voltage Vd and the period Td, and reads the capacity change with respect to the voltage Vd or the period Td from the table. Thus, a configuration in which the current capacity value is changed can be considered.
In this example, the capacitance value of the capacitor 23 is changed.
, 22 and 23, any configuration may be used as long as at least one capacitance value is changed. Further, as described above, the rate of change of the output voltage Vout depends on the capacitance values C ₁ , C ₂ , C _{3 of} the capacitor and the offset voltage Voff of the buffer circuit 40. Is determined by a specific target change rate, an actually generated offset voltage, and the like.

According to the third embodiment as described above, it is possible to make the change rate of the output voltage Vout coincide with the target value even if the capacitance value varies in the capacitor or the offset voltage Voff of the buffer circuit 40 exists.

<Fourth embodiment>
Next, an electro-optical device to which such a lamp signal generation circuit 10 is applied will be described.
FIG. 13 is a block diagram illustrating the overall configuration of the electro-optical device.
As shown in this figure, the electro-optical device 1 includes a display area 100, a data side control circuit 25.
0, a scanning line driving circuit 350, a control circuit 400, and a ramp signal generation circuit 10. Among these, in the display region 100, 320 scanning lines 311 extend in the row (X) direction, while 2
Forty data lines 211 are provided so as to extend in the column (Y) direction. The pixels 120 are arranged corresponding to the intersections of the scanning lines 311 of 320 rows and the data lines 211 of 240 columns, respectively. Therefore, in this embodiment, the pixels 120 are 320 rows long ×
Although it is arranged in a matrix form with 240 horizontal rows, the present invention is not intended to be limited to this arrangement.

Here, a detailed configuration of the pixel 120 will be described. FIG. 14 is a diagram illustrating the configuration of the pixel 120, i rows and (i + 1) rows adjacent thereto, j columns and adjacent thereto (j + 1).
) A configuration of a total of 4 pixels of 2 × 2 corresponding to the intersection with the column is shown.
Note that i and (i + 1) are symbols for generally indicating a row in which the pixels 120 are arranged, and are integers of 1 to 320, and j and (j + 1) are columns in which the pixels 120 are arranged. It is a symbol in the general case, and is an integer from 1 to 240.

As shown in FIG. 14, each pixel 120 includes a liquid crystal capacitor 130 and an n-channel thin film transistor (Thin Film Transistor) that functions as a switching element.
241). Since each pixel 120 has the same configuration, a description will be given by using a pixel located in i row and j column as a representative.
The gate of T241 is connected to the scanning line 311 in the i-th row, the source is connected to the data line 211 in the j-th column, and the drain is connected to the pixel electrode 231 that is one end of the liquid crystal capacitor 130.
The other end of the liquid crystal capacitor 130 is connected to the common electrode 110. This common electrode 1
In this embodiment, 10 is common to all the pixels 120 as shown in FIG. 13, and the output voltage Vout from the ramp signal generation circuit 10 is applied.

In the liquid crystal capacitor 130, the voltage difference between the pixel electrode 231 and the common electrode 110 is held, and the amount of light transmitted (or reflected) through the liquid crystal capacitor 130 changes according to the effective value of the hold voltage. .
Although it is considered that such a configuration does not need to be described in detail, a method in which the liquid crystal is sandwiched between the pixel electrode and the common electrode and the electric field direction applied to the liquid crystal is the substrate surface vertical direction, the pixel electrode, Examples include a method in which an insulating layer and a common electrode are stacked so that the direction of the electric field applied to the liquid crystal is the horizontal direction of the substrate surface.
In the present embodiment, for convenience of explanation, if the effective voltage value held in the liquid crystal capacitor 130 is close to zero, the light transmittance is maximized to display white, while the effective voltage value increases. The normally white mode in which the amount of light decreases and finally the black display with the minimum transmittance is achieved.

Returning to FIG. 13 again, the control circuit 400 controls the data side control circuit 250 by supplying the control signal CntX and also supplies the scanning line drive circuit 3 by supplying the control signal CntY.
50 controls the vertical scanning of the display area 100. Further, the control circuit 400 outputs the above-described polarity instruction signal Pol, reset signal Rse, and clock signal Clk to the ramp signal generation circuit 10.
To supply. That is, in the fourth embodiment, the control circuit 400 includes the switch control circuit 50 (
51).
Here, regarding the writing polarity with respect to the liquid crystal capacitor 130, when the potential of the pixel electrode 231 is high with respect to the common electrode, it is positive, and when it is low, it is negative. In the fourth embodiment, since the output voltage Vout is applied to the common electrode 110, the liquid crystal capacitance 13
The write polarity for 0 is positive when the output voltage Vout changes in the downward direction and negative when the output voltage Vout changes in the upward direction. Therefore, the polarity indication signal Pol is written to the liquid crystal capacitor 130. It can be said that the signal specifies the polarity.
As shown in FIG. 16, the polarity instruction signal Pol is used in one vertical scanning period (1F).
The polarity is inverted every horizontal scanning period (1H), and even if attention is paid to the same horizontal scanning period between adjacent vertical scanning periods (1F), the polarity is inverted. For this reason, in this embodiment, scanning line inversion (row inversion) is performed in which the writing polarity is inverted for each scanning line, but the present invention is not limited to this. The reason why the polarity is inverted in this way is to prevent deterioration due to application of a direct current component to the liquid crystal.

The scanning line driving circuit 350 sequentially selects the scanning lines 311 in the first, second, third,..., 320th rows in each horizontal scanning period (1H) according to the control signal CntY. The scanning signal corresponding to 311 is set to the selection voltage Vdd corresponding to the H level over the horizontal scanning period (1H), and the scanning signals corresponding to the other scanning lines 311 are set to the non-selection voltage Vss corresponding to the L level. Is. Here, the scanning signals supplied to the scanning lines 311 in the first, second, third,..., 320th rows are denoted as Y1, Y2, Y3,..., Y320, respectively. In the description, Yi is used for explanation.

Next, the data-side control circuit 250 has storage areas (not shown) corresponding to a matrix arrangement of 320 rows × 240 columns, and each storage area stores the gradation data Da of the corresponding pixel 120. To do. The gradation data Da is data that designates the gradation value (brightness) of the pixel 120. The gradation data Da is supplied from a host device (not shown) and is stored in a corresponding storage area when the display content is changed. The gradation data Da thus set is rewritten.
Further, when one scanning line 311 is selected by the scanning line driving circuit 350, the data-side control circuit 250, in accordance with the control signal CntX, outputs one row of the gradation data Da of the pixel located on the scanning line. Are read out in advance, and the switch control signals X1, X2, X3,..., X240 are applied to the scanning line for 1, 2, 3, 3 over the period during which the selection voltage Vdd is applied according to one row of the gradation data Da. ,..., And 240 lines of data lines 211 are output simultaneously.
Here, when the switch control signals X1, X2, X3,..., X240 are generally described as Xj when they are generally described without specifying a column, the data-side control circuit 250 scans the switch control signal Xj by one horizontal scan. Designated by the gradation data Da of the pixel corresponding to the intersection of the scanning line 311 selected in the horizontal scanning period and the data line 211 of the j-th column from the start end of the period (1H) to the rear side of the time axis. The H level is set only during the period corresponding to the gradation value, and the L level is set during the remaining period.

On the other hand, a single throw type switch 260 (data side switch) is provided corresponding to each column.
Here, one terminal of the switches 260 in each column is connected to the data line 211, and the other terminal is commonly connected to the potential line 281 maintained at the voltage Vc. For example, the switches 260 corresponding to the data line 211 in the j-th column are turned on when the switch control signal Xj is at the H level.

Here, the data line 211 in which the switch 260 is off is in a high impedance state, and the voltage is uncertain. Therefore, for convenience, the data line 2 in the 1, 2, 3,.
The voltage of 11 is expressed as S1, S2, S3,..., S240, and it is expressed as Sj when generally explaining without specifying a column.

As shown in FIG. 16, the voltage Vc corresponds to an intermediate value between the voltage Vdd corresponding to the H level and the voltage Vss corresponding to the L level, and the output voltage Vout is increased or decreased with reference to the voltage Vc. Generated in the descending direction.
That is, in the configuration shown in FIG. 6 (FIG. 7), the output voltage Vou is based on the ground potential Gnd.
Although t is changed in the upward or downward direction, the fourth embodiment is configured to change in the upward or downward direction based on the voltage Vc.

The ramp signal generation circuit 10 in the fourth embodiment has the configuration shown in FIG.
This is a configuration in which double throw switches S _4-u and S _4-d are added to the embodiment (see FIG. 10). Each of these double throw switches S4 _-u and S4 _-d is closed between the common terminal and the terminal a when the polarity indicating signal Pol is at the H level, while the polarity indicating signal Pol
Are closed between the common terminal and the terminal b, respectively.
Here, the terminal a (connection point g) of the double throw switch S1 _-u is connected to the terminal b of the double throw switch S4 _{-u and} the terminal a of the double throw switch S4 _-d , respectively, and an arithmetic circuit. 64 is connected to one input terminal.
Further, in FIG. 15, the terminal a of the double throw switch _{S 1-d,} the other terminal of the capacitor 22, the other terminal of the single-throw switches _{S 0,} the other terminal of the capacitor 23, double throw switch _{S 3-d}
The connection point h between the terminal a and the terminal b of the double throw switch S _3-u (the part corresponding to the connection point to the negative terminal of the reference voltage source 30 in FIG. 10) is the terminal of the double throw switch S _4-u . a and the double-throw switch S4 _-d are respectively connected to the terminal b and kept at the voltage Vc.
The positive terminal of the reference voltage source 30 is connected to the common terminal of the double throw switch S4 _-u , and the negative terminal of the reference voltage source 30 is connected to the common terminal of the double throw switch S4 _-d .
The control circuit 400 outputs a reset signal Res at the beginning of one horizontal scanning period (1H) and outputs a clock signal Clk having 256 cycles in one horizontal scanning period (1H).

In this configuration, when the polarity instruction signal Pol is at the L level, the double throw switch S _4-u ,
Since S4 _-d takes the position indicated by the broken line in FIG. 15, the equivalent circuit is the same as FIG. In this case, however, the connection point g, which is one input terminal of the arithmetic circuit 64, is connected to the voltage (Vc +
Vref), and the voltage at the connection point h corresponding to the start of change is fixed at Vc.
out is from the voltage Vc to the voltage (Vc +) from the start to the end of one horizontal scanning period (1H).
Vref) is adjusted to change.
On the other hand, when the polarity instruction signal Pol is at the H level, the double throw switches S _4-u and S _4-d are
The position indicated by the solid line in FIG. 15 is taken. In this case, since the connection point g is the voltage (Vc−Vref), the output voltage Vout changes from the voltage Vc to the voltage (Vc−Vref) from the start to the end of one horizontal scanning period (1H). Adjusted to
Therefore, the output signal Vout is as shown in FIG. 16 with respect to the polarity instruction signal Pol. That is, in the horizontal scanning period (1H) in which the polarity instruction signal Pol is at the L level, the output voltage Vout rises from the voltage Vc to the voltage (Vc + Vref), and on the contrary, the horizontal scanning period in which the polarity instruction signal Pol is at the H level. At (1H), the output voltage Vout drops from the voltage Vc to the voltage (Vc−Vref).
In FIG. 16, the vertical voltage scales of the scanning signals Y1 to Y320 and the output voltage Vout are different for convenience (the same applies to FIG. 17 to be described next).

Next, writing in the electro-optical device 1 having such a configuration will be described.
FIG. 17 is a diagram showing the writing of pixels in i rows and j columns and the writing of pixels in (i + 1) rows and j columns adjacent one row below this in relation to the scanning signals Yi and Y (i + 1). is there.
When the pixel in i row and j column is gray between white and black, the switch is switched in one horizontal scanning period (1H) in which the scanning signal Yi is H level when the polarity instruction signal Pol is L level. control signal Xj from the start of the 1 horizontal scanning period (1H), becomes only the H level period T ₁ corresponding to the gray. When the switch control signal Xj becomes H level, the switch 260 in the j-th column is turned on (conductive), so that the voltage Sj of the data line 211 in the j-th column is kept at the voltage Vc.
Further, when the scanning signal Yi becomes H level, the TFT 241 is turned on in the pixel 120 for one row located on the scanning line 311 of the i-th row. Therefore, pixel 120 in i row and j column
, The pixel electrode 231 becomes equal to the voltage Vc in the same way as the data line 211 in the j-th column.
On the other hand, when the polarity instruction signal Pol is at the L level in the one horizontal scanning period (1H), the voltage of the common electrode 110 is the output voltage Vout from the ramp signal generation circuit 10.
Rises from voltage Vc to voltage (Vc + Vref). For this reason, when the switch 260 in the j-th column is turned on, writing with the pixel electrode 231 at the high-order side is started in the liquid crystal capacitor 130 in the pixel in the i-th row and j-th column.

Next, when the elapse of time T ₁ corresponding to the gray scale of the pixel on the column i and the row j from the start of the one horizontal scanning period, the data signal Xj is changed from H level to L level. For this reason, the switch 26
Since 0 is in an off (non-conducting) state, the data line 211 in the j-th column is in a high impedance state.
Here, even if the switch 260 is turned off, the voltage Vout applied to the common electrode 110 continues to rise and TF during one horizontal scanning period in which the i-th scanning line 311 is at the H level.
Since the ON state of T241 continues, the voltage Sj of the data line 211 in the j-th column in the high impedance state decreases at the same rate of change as the output voltage Vout from the moment when the switch 260 is turned off. .
Therefore, the write voltage for the liquid crystal capacitor 130 in the i row and the j column is determined at the moment when the switch 260 in the j column is turned off during the period in which the scanning signal Yi is at the H level, and the polarity instruction signal Pol is at the L level. If so, the voltage V at the moment when the switch 260 in the j-th column is turned off.
The difference voltage between out and the voltage Vc (the voltage indicated by ↓ in FIG. 17) is held even after the switch 260 is turned off with the pixel electrode 231 at the lower side.
When the one horizontal scanning period (1H) ends and the scanning signal Yi changes to the L level, the TFTs 241 of the pixels for one row located in the i-th scanning line 311 are turned off. 231 is electrically disconnected from the corresponding data line 211 and enters a floating state. For this reason, the potential of the pixel electrode 231 in the i-th row and the j-th column also changes as the voltage of the common electrode 110 changes. The difference voltage between Vout and voltage Vc is the same even when the switch 260 is turned off.
Further, even if the scanning signal Yi changes to the L level, it is held.
In addition, although the operation is described as a representative of the pixels in the i-th row among the pixels in the i-th row, in the period in which the scanning signal Yi is at the H level, 1 to 240 positioned in the i-th row. Writing for the j-th column is executed simultaneously in parallel for all the pixels in one column.

In the next one horizontal scanning period (1H), since the scanning signal Y (i + 1) is at the H level, writing is similarly performed on the pixels for one row located in the (i + 1) th row. However, in this embodiment, since the writing polarity is inverted for each scanning line, as a result of the polarity instruction signal Pol being inverted to H level, the output voltage Vout is changed from the voltage Vc to the voltage (Vc−
Descends towards Vref).
Therefore, the write voltage for the liquid crystal capacitor 130 in (i + 1) rows and j columns is equal to the scanning signal Y (
i + 1) is determined at the moment when the switch 260 in the j-th column is turned off during the period when the switch 260 in the j-th column is turned off, and the difference voltage between the voltage Vout and the voltage Vc (in FIG. 17) The voltage indicated by ↑ is the switch 2 with the pixel electrode 231 at the higher side.
Even after 60 is turned off, it is held.

Here, the writing of the i and (i + 1) th rows adjacent to each other is described.
Such writing is executed for each horizontal scanning period in the order of the first, second, third,..., 320th row in one vertical scanning period (1F), and an image of one frame is displayed. . In the next one vertical scanning period (1F), the writing polarity is reversed in each row, and the same writing is executed.

In the fourth embodiment, the output voltage Vout is increased from the voltage Vc to the voltage (Vc + Vref) and then decreased from the voltage Vc to the voltage (Vc−Vref), but after being increased to the voltage (Vc + Vref), The voltage (Vc + Vref) may be lowered to the voltage Vc. In this configuration, when the voltage (Vc + Vref) is lowered from the voltage Vc, the potential line 281 is used.
Needs to be maintained at the voltage (Vc + Vref), but the voltage change range is the range from the voltage Vc to the voltage (Vc + Vref) compared to the range from the voltage (Vc−Vref) to the voltage (Vc + Vref). Become. For this reason, the voltage amplitude required for the logic signal of the scanning signal and the switch control signal can be suppressed, so that the withstand voltage of the scanning line driving circuit 350 and the data side control circuit 250 can be reduced, and the configuration can be simplified correspondingly. Can do. Note that the same effect can be obtained even when the voltage is changed in the range from the voltage (Vc−Vref) to the voltage Vc.
Furthermore, replacing a single-throw switch S ₀ to sweeping switch 15, not only the voltage Vc, may be configured to reset any voltage (Vc + Vref).

In the configuration shown in FIG. 13, the output voltage Vout, which is a ramp signal, is supplied to the common electrode 110 and the potential line 281 is kept constant at the voltage Vc. However, as shown in FIG. A configuration in which the voltage Vc is constant and the output voltage Vout is supplied to the potential line 281 may be employed.
Also, instead of switching the polarity of the reference voltage source 30 by the double throw switches S _4-u and S _4-d , as shown in FIG. 7, (B) double throw switches S _1-u and S _1-d , The connection destination of the terminal b and the output terminal of the buffer circuit 40 in S ₂ may be changed.

It is a figure which shows the structure of the ramp signal generation circuit which concerns on 1st Embodiment of this invention. It is a figure which shows the reset signal etc. in the same ramp signal generation circuit. It is a figure for demonstrating operation | movement of the ramp signal generation circuit. It is a figure for demonstrating operation | movement of the ramp signal generation circuit. It is a figure which shows the relationship between the clock signal Clk and the output voltage Vout. It is a figure which shows another structure (the 1) of the ramp signal generation circuit which concerns on 1st Embodiment. It is a figure which shows another structure (the 2) of the ramp signal generation circuit which concerns on 1st Embodiment. It is a figure for demonstrating operation | movement of another structure (the 2). It is a figure which shows the structure of the ramp signal generation circuit which concerns on 2nd Embodiment of this invention. It is a figure which shows the structure of the ramp signal generation circuit which concerns on 3rd Embodiment of this invention. It is a figure which shows an example of the varistor in the ramp signal generation circuit. It is a figure for demonstrating operation | movement of the ramp signal generation circuit. It is a figure which shows the structure of the electro-optical apparatus to which the lamp signal generation circuit which concerns on 4th Embodiment of this invention is applied. It is a figure which shows the structure of the pixel in the same electro-optical apparatus. It is a figure which shows the structure of the ramp signal generation circuit. FIG. 6 is a diagram for explaining an operation in the electro-optical device. FIG. 6 is a diagram for explaining an operation in the electro-optical device. It is a figure which shows another structure of the same electro-optical apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Electro-optical device, 10 ... Lamp signal generation circuit, 21, 22, 23 ... Capacitor, 30 ...
Reference voltage source, 40 ... buffer circuit, 50 ... switch control circuit, 60 ... capacitor, 70 ...
Capacitance changing circuit, 110 ... common electrode, 120 ... pixel, 211 ... data line, 231 ... pixel electrode, 241 ... TFT, 250 ... data side control circuit, 311 ... scan line, 350 ... scan line drive circuit, 400 ... control circuit

Claims (11)

A single throw switch, first, second and third double throw switches, first, second and third capacitive elements, a reference voltage source, a buffer circuit, a switch control circuit,
Comprising
The first capacitive element is inserted at a common end of the first and second double throw switches,
One pole of the reference voltage source is connected to the first terminal of the first double throw switch;
One terminal of the second capacitive element is connected to the common end of the third double throw switch,
The first terminal of the third double-throw switch is connected to one terminal of the single-throw switch, one terminal of the third capacitive element, and the input terminal of the buffer circuit,
A second terminal of the third double-throw switch is connected to a second terminal of either the first or second double-throw switch;
The other pole of the reference voltage source has a first terminal of the second double-throw switch, the other terminal of the second capacitive element, the other terminal of the single-throw switch, and the other terminal of the third capacitive element. The terminals are connected in common,
The output terminal of the buffer circuit is connected to the other second terminal of the first or second double throw switch,
The voltage of the buffer circuit is output,
The switch control circuit includes:
As the first stroke, the single throw switch is closed,
As the second stroke, the single throw switch is opened and the first, second and third
For the double throw switch, the first terminal and the common end are closed,
As the third stroke, the second terminal and the common end are closed for the first, second and third double throw switches, respectively.
Thereafter, the second and third steps are repeated. A ramp signal generation circuit characterized by: Selecting the second terminal of either the first or second double throw switch and connecting to the second terminal of the third double throw switch;
2. The ramp signal according to claim 1, further comprising a switching circuit that selects one of the second terminals of the first and second double-throw switches and connects the second terminal to the output terminal of the buffer circuit. Generation circuit. A fourth and fifth double-throw switch, and a fourth capacitive element;
A fourth capacitive element is inserted at the common end of the fourth and fifth double-throw switches;
A first terminal of the fourth double throw switch is connected to an output terminal of the buffer circuit;
A second terminal of the fourth double-throw switch and a first terminal of the fifth double-throw switch are connected to the other pole of the reference voltage source;
A second terminal of the fifth double-throw switch is connected to an input terminal of the buffer circuit;
The switch control circuit includes:
In the first stroke, the first terminal and the common end are closed for the fourth and fifth double throw switches, respectively.
2. The lamp according to claim 1, wherein after the second stroke, the second terminal and the common end are once closed with respect to the fourth and fifth double throw switches, respectively, and then opened. Signal generation circuit. When the third capacitive element is removed,
The switch control circuit includes:
In the first stroke, the first terminal and the common end are closed for the fourth and fifth double throw switches, respectively.
4. The ramp signal generation circuit according to claim 3, wherein the second terminal and the common end are closed for the fourth and fifth double throw switches after the second stroke, respectively. 5. When the second and third steps are repeated a predetermined number of times by the switch control circuit, if the output voltage from the buffer circuit does not reach a predetermined voltage, the capacitance value of the third capacitive element is A capacitance changing circuit that changes at least one capacitance value of the first, second, and third capacitance elements so that the relative value of the capacitance values of the first and second capacitance elements is reduced. The ramp signal generation circuit according to claim 3. When the output voltage of the buffer circuit reaches a predetermined voltage before the second and third steps are repeated a predetermined number of times by the switch control circuit, the first, A capacitance changing circuit that changes at least one capacitance value of the first, second, and third capacitance elements so that the relative value of the capacitance values of the second or third capacitance elements is increased. The ramp signal generation circuit according to claim 3. If the output voltage from the buffer circuit does not reach a predetermined voltage when the second and third strokes are repeated a predetermined number of times by the switch control circuit, the capacitance value of the fourth capacitor element is compared with the capacitance value of the fourth capacitor element. And a capacitance changing circuit that changes at least one capacitance value of the first, second, and third capacitance elements so that a relative value of the capacitance values of the first and second capacitance elements is reduced. Item 5. The ramp signal generation circuit according to Item 4. If the output voltage from the buffer circuit reaches a predetermined voltage before the switch control circuit repeats the second and third steps a predetermined number of times, the first or The first capacitance is set so that the relative value of the capacitance value of the second capacitance element is increased.
The ramp signal generation circuit according to claim 4, further comprising a capacitance changing circuit that changes at least one capacitance value of the second and third capacitive elements. A pixel electrode provided corresponding to the intersection of the plurality of scanning lines and the plurality of data lines;
A switching element that becomes conductive when a selection voltage is applied to the scan line between the data line and the pixel electrode;
An electro-optical device having a pixel including:
A scanning line driving circuit for selecting the plurality of scanning lines in a predetermined order and applying the selection voltage;
A plurality of data-side switches provided corresponding to each of the plurality of data lines, one end of which is connected to the data line and the other end of which is commonly connected to a potential line maintained at a predetermined potential;
Performing the first step at the start of a period in which the selection voltage is applied to the selected scanning line;
9. The device according to claim 1, wherein the second and third steps are repeated over a period in which the selection voltage is applied to the selected scanning line, and an output voltage is applied to the common electrode facing the pixel electrode. A ramp signal generation circuit;
In the period when the selection voltage is applied to the scanning line, the data-side switch is set to a period corresponding to the gradation of the pixel corresponding to the intersection of the scanning line to which the selection voltage is applied and the data line of the data-side switch. A data-side control circuit that controls the data-side switch to an off state,
An electro-optical device comprising: A pixel electrode provided corresponding to the intersection of the plurality of scanning lines and the plurality of data lines;
A switching element that becomes conductive when a selection voltage is applied to the scan line between the data line and the pixel electrode;
An electro-optical device having a pixel including:
A scanning line driving circuit for selecting the plurality of scanning lines in a predetermined order and applying the selection voltage;
A plurality of data-side switches provided corresponding to each of the plurality of data lines and having one end connected to the data line and the other end commonly connected;
Performing the first step at the start of a period in which the selection voltage is applied to the selected scanning line;
9. The second and third steps are repeated over a period in which the selection voltage is applied to a selected scanning line, and an output voltage is applied to the other end commonly connected between the plurality of data side switches. A ramp signal generation circuit according to any one of
In the period when the selection voltage is applied to the scanning line, the data-side switch is set to a period corresponding to the gradation of the pixel corresponding to the intersection of the scanning line to which the selection voltage is applied and the data line of the data-side switch. A data-side control circuit that controls the data-side switch to an off state,
An electro-optical device comprising: An electro-optical device comprising the ramp signal generation circuit according to claim 1.

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