JP2007027357A - Semiconductor light emitting device and substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a light emitting device for realizing reduction in size, high output and higher efficiency of a light emitting element provided with a protection circuit for inverse voltage. <P>SOLUTION: The semiconductor light emitting device comprises, in its semiconductor light emitting element, a bipolar transistor as a protection circuit for inverse voltage. This protection circuit is constituted to short-circuit the base and collector of the bipolar transistor, and in parallel connection with a semiconductor element circuit so that the polarity between the emitter and base is inverted for the polarity of the semiconductor light emitting element. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor light emitting device and a substrate used in the device. More particularly, the present invention relates to a substrate on which a protection circuit against a reverse voltage (including reverse overvoltage) of a semiconductor light emitting element is formed, and a light emitting device using the same.

  Due to the higher output and higher efficiency of LEDs, applications in which LEDs are used are expanding. In addition to conventional indicator applications and large outdoor display applications, usage is rapidly increasing to backlight light sources, headlights, and illumination light sources for mobile phones. These LED trends require not only higher output and higher efficiency, but also response to downsizing and upsizing.

For high output and high efficiency, wireless flip-chip mounting is best, with the two electrodes of the LED chip formed on the epi surface (epitaxial surface), the epi surface side as the mounting surface, and the transparent substrate side as the light exit surface. It is advantageous. In face-up mounting, in which the epi-surface side is the light-emitting surface, the substrate side is the mounting surface, and current is supplied from the outside through one or two wires from the epi-surface, the light is extracted through the translucent electrode. There are absorption and loss of the translucent electrode.
Further, in face-up mounting, one or two wires are bonded to the chip surface, which is the light emitting surface, so that it does not contribute to light emission by the area of one or two Au balls and electrode pads. Further, since one or two wires are applied in the direction of light emission, a loss is caused by being blocked by the wires. A defect that the shadow of the wire is projected has also been observed.
Therefore, flip chip mounting in which no wire is connected to the light emitting surface of the light emitting element has an advantage of avoiding these problems. In flip chip mounting, there is a type in which a single wire is connected to the transparent substrate side, which is the light exit surface, but this is not desirable for the above reasons. That is, flip-chip mounting without wires is most desirable for light-emitting element chips in order to achieve high output and high efficiency.

Furthermore, in LEDs, there is a case where a Zener diode that is a reverse overvoltage protection element of the LED is disposed in the vicinity of the LED chip. In this case, it is observed that the light output is reduced as compared with the case without the Zener diode. Yes. This is considered to be due to the light absorption of the Zener diode and the light emission being uneven because the LED chip is not arranged on the central axis with respect to the package. In view of the space where the Zener diode is placed, for example, in the current side view package, the LED chip is mounted off the central axis, and the Zener diode is disposed beside the LED chip (see FIG. 9). In disposing the chip in the package, the LED chip should be placed on the central axis of the package so as to suppress light loss as much as possible, and it is desirable to place the overvoltage protection element in a position that does not hinder light emission.
For example, Patent Document 1 is cited as an overvoltage protection element for a semiconductor light emitting element. The invention of this patent is such that a component having a power branch function is connected in parallel with the LED so that an overvoltage is not applied to the LED.

In miniaturizing a package having an LED and a Zener diode, it is necessary to reduce the space for mounting the Zener diode as much as possible because it is desired to maintain the size of the LED chip.
Patent document 2 is mentioned as an example which has arrange | positioned LED chip on a Zener diode. Here, an example in which LED chips are connected in parallel in the reverse polarity on the surface of a Zener diode chip is disclosed in FIGS. Also, Patent Document 3 discloses an example in which a diode or a field effect transistor is formed on a submount itself on which a flip-chip mounted LED chip is placed, and the LED chip is connected in reverse polarity and in parallel. However, there is a problem with the type in which these two diodes and field effect transistors are incorporated on the submount surface. When an LED chip is connected in parallel in reverse polarity on the surface of a submount on which a diode or a field effect transistor is formed, one from the junction between the submount and the LED chip, that is, the p-electrode pad and the n-electrode pad on the surface of the submount. It is necessary to connect the outside with a wire. If an electrode is formed on the back surface of the submount substrate and the top surface is a single wire, the current flows in the order of the n-type layer of the LED, the p-type layer of the LED, and the n-type layer of the substrate. This results in a circuit in which diodes are arranged in series. That is, in the diode-type submount, the n-type layer of the LED and the p-type layer of the Zener diode, and the p-type layer of the LED and the n-type layer of the Zener diode are connected by electrodes formed on the surface of the Zener diode, respectively. And a circuit in which diodes with opposite polarities are arranged in series. Such a circuit cannot perform the reverse overvoltage protection function of the LED. In the case of a field effect transistor, it is necessary to reduce the channel width, but there is a demerit that the withstand voltage is lower than that of a bipolar transistor type.
In the above three preceding examples, there is no specific disclosure of how to form a reverse overvoltage protection element inside the submount and how to connect it to the LED.
U.S. Pat. No. 5,914,501 and drawings US Pat. No. 6,054,714 and drawing Japanese Patent No. 3257455

The present invention provides a high-output and high-efficiency light-emitting device having a reverse voltage (including reverse overvoltage) protection function, particularly a single wire type submount with a reverse voltage protection function, LED chip Is located in the center of the package, enabling the package to be reduced in size and output.

The present invention has been made to solve the above-described problems, and comprises the inventions of the following items.
(1) A semiconductor light emitting device comprising a bipolar transistor as a protection circuit against a reverse voltage of the semiconductor light emitting element.
(2) The protection circuit is short-circuited between the base collectors of the bipolar transistor and connected in parallel with the semiconductor element circuit so that the polarity between the emitter and the base is opposite to the polarity of the semiconductor light emitting element. The semiconductor light-emitting device according to (1) above, characterized in that
(3) A substrate on which a semiconductor light emitting element is mounted, wherein a bipolar transistor having a shorted base collector is formed near the substrate surface, and an anode and a cathode of the semiconductor light emitting element can be connected to the emitter and collector of the bipolar transistor A substrate for a semiconductor light emitting device, comprising a pad on the surface of the substrate and further having electrode pads for external connection on the front and back surfaces of the substrate.
(4) The substrate for a semiconductor light-emitting element according to (3), wherein the substrate is Si.

(5) The semiconductor light-emitting element substrate according to (3) or (4) above, wherein a plurality of semiconductor light-emitting elements can be mounted on the substrate.
(6) A semiconductor light emitting device in which a semiconductor light emitting element is mounted on the semiconductor light emitting element substrate according to any one of (3) to (5) above, wherein the polarities of the bipolar transistor and the semiconductor light emitting element are reversed in parallel. The semiconductor light emitting device is characterized in that the anode and cathode of the semiconductor light emitting element are connected to the emitter and collector of the bipolar transistor.
(7) The semiconductor light-emitting device according to any one of (1) to (2) and (6), wherein the semiconductor light-emitting element is a III-V group compound semiconductor.
(8) The semiconductor light emitting device according to any one of (1), (2), (6), and (7), wherein the semiconductor light emitting element and the phosphor are combined.
(9) A semiconductor light-emitting element package or a semiconductor light-emitting element module on which the semiconductor light-emitting device according to any one of (1), (2), (6), (7), and (8) is mounted.

The light emitting device of the present invention is formed by forming an n-type electrode pad, a p-type electrode pad, and a bipolar transistor structure on the substrate surface, which can short-circuit the base collector and connect the semiconductor light-emitting element between the emitter and the base. Realization of a 2-wire system with 1 wire and a compact reverse voltage protection circuit space, especially for the side view package, the flip chip can be placed at the center, achieving high output and symmetric light distribution characteristics. Industrial utility value is extremely large.
By realizing a 1-wire submount with reverse voltage protection function, while maintaining the reliability against the electrostatic withstand voltage of light-emitting elements, it can achieve higher output for any type of package or module, regardless of size or size.・ Enables high efficiency. In particular, it is possible to maximize the potential of a light-emitting element for flip-chip mounting which is most advantageous for high output and high efficiency and has two electrodes on the epi-surface side and no electrode on the transparent substrate side.

Since the reverse voltage protection element is not separately provided inside the package, the internal space of the package can be effectively used for the semiconductor light emitting element. In addition, since it is possible to place the semiconductor light emitting element at the center of the package, an optical output loss is suppressed and an optical design of the package is facilitated. There is no reverse voltage protection element in the emission direction of the light emitting element, and the surface of the reverse voltage protection element can be covered with a metallic glossy surface, so there is no light absorption. Furthermore, since no wire is placed in the light emitting direction of the semiconductor light emitting device, light output loss can be further avoided.
In addition, as a secondary effect, the use of one wire reduces the time required for wire bonding by half, and has the effect of significantly improving mass productivity.
Furthermore, many package manufacturers have equipment for mounting a face-up type that uniformly adheres the back surface of the chip with a conductive paste, so a flip-chip type light emitting device that connects two electrodes to the mounting surface side. However, it can be applied to a face-up package manufacturing facility, and the use of a flip chip type light emitting element is promoted.

The semiconductor light-emitting device of the present invention (sometimes abbreviated as a light-emitting device) is used to protect an LED when a reverse voltage is applied to the semiconductor light-emitting element (sometimes abbreviated as a light-emitting element or LED). The LED includes a bipolar transistor (sometimes abbreviated as a transistor).
The present invention will be specifically described below with reference to the drawings.
1 is a plan view of the electrode surface on which the LED is placed, FIG. 2 is a plan view of the lower surface of the substrate, FIG. 3 is a sectional view of the light emitting device, and FIG. 4 is a plan view of the light emitting device.
As shown in FIG. 3, for example, an n-type Si epitaxial layer 21 is formed on an n ⁺ -type Si substrate 22. Then, the transistor 19 including the n ⁺ collector layer 20, the n ⁺ emitter layer 23, and the p ⁺ type base layer 24 is formed on the epitaxial layer 21. It is also possible to eliminate the epitaxial layer 21 and form a transistor directly on the substrate 22. Although the illustrated transistor is an n-pn type, a p-type epitaxial layer is formed on a p ⁺ -type substrate, and a p-n comprising a p ⁺ collector layer, a p ⁺ emitter layer, and an n ⁺ -type base layer is formed on this epitaxial layer. A -p type can also be used.
Electrode pads 12 are formed on the collector layer 20 and the emitter layer 23 of the transistor, respectively. The n ⁺ collector layer 20 and the p base layer 24 are electrically connected by the short-circuit portion 25 of the electrode pad 12, one of which is connected to the collector layer and the other is connected to the base layer. The electrode pad shown in the figure shows an example of three metal layers.

  The semiconductor light emitting element 26 is bonded to the front electrode pad 12 formed on the substrate so that the p-type electrode and the n-type electrode are not short-circuited. Reference numeral 27 denotes a gold bump for this purpose. This may be another connection method such as AuSn eutectic solder as described later. The position of the bump is determined by the bump forming marker 13. Next, the semiconductor light emitting element with the substrate is bonded onto the package substrate, the lead frame, the inner lead 28 formed on the printed circuit board or the film, or the wiring pattern 36 via a conductive paste or solder. A metal wire 30 connects from the external terminal connection electrode pad 12 formed on the substrate surface to the other inner lead 28 of the package and the other wiring pattern 36. 33 is an outer lead. In FIG. 1, 11 is an insulating film, 14 is a connection hole position to the emitter layer, 15 is a connection hole position to the base layer, 16 is a connection hole position to the collector layer, and 17 is an LED arrangement position. When mounting the semiconductor light emitting element with the substrate, it is desirable to perform bonding so that the central axis of the light emitting element coincides with the central axis of the package.

In the present invention, the transistor and the LED form a parallel circuit as is apparent from the figure. And it arrange | positions so that those polarities may become reverse. In the example of FIG. 3, the LED has a p-pole on the left side and an n-pole on the right side as viewed in the drawing. Thereby, the p-pole of the LED and the n ⁺ emitter layer of the transistor are connected, and the n-pole of the LED and the p base layer of the transistor are connected.
In the above configuration, when a voltage is applied to the LED in the forward (positive) direction, the current flows from the p-pole to the n-pole of the LED, through the collector layer of the transistor, and to the substrate side. Since no current flows from the n ⁺ emitter of the transistor to the p ⁺ base, no current flows in the transistor for the forward voltage. On the other hand, when a reverse voltage is applied, no current flows through the LED, and the back electrode pad of the substrate, the substrate, the epitaxial layer, the collector layer, the short-circuit portion, the p ⁺ base layer, the n ⁺ emitter layer, Current flows in the order of the surface electrode pads. This protects the LED from damage due to reverse voltage.

The bipolar transistor is designed according to the electrical characteristics of the semiconductor light emitting device. The resistance value of the reverse voltage application between the emitter and the base of the transistor is sufficiently higher than the resistance value of the semiconductor light emitting device with respect to the forward voltage application of the semiconductor light emitting device centered on the normal current region, It is desirable that the resistance value of the forward voltage application between the emitter and the base is sufficiently low with respect to the application of the directional voltage.
The semiconductor light emitting device substrate in the present invention is preferably a low-resistance Si substrate for reasons of substrate cost and stability of the bipolar transistor formation process. This is because the technology and equipment for forming a bipolar transistor on a Si substrate are mature in the Si electronic device industry such as IC, and it is advantageous to use this. The reason why low resistance is desirable is to reduce the resistance value between the front electrode and the back electrode as much as possible. Specifically, it is desirable to use a low resistance Si substrate having a resistivity ρ ≦ 0.01 Ωcm. Therefore, in the case of an n ⁺ type silicon substrate, the dopant contained in the substrate is preferably Sb or As. Further, the Si substrate is desirable in terms of heat dissipation and cutting workability into individual pieces. The thermal conductivity of typical semiconductor substrate materials is Si: 168 W / m · K, GaAs: 54 W / m · K, GaP: 110 W / m · K, InP: 70 W / m · K, AlN: 30 W / m · K .

In order to form a bipolar transistor structure in the substrate for a semiconductor light emitting device in the present invention, it is desirable to laminate a high resistance epi layer (epitaxial layer) on the surface of the low resistance substrate. For example, when an n ⁺ type Si substrate is used as the substrate, it is desirable to stack a high resistance n type Si epilayer. Monosilane (SiH ₄ ) is desirable as a raw material used for forming the epi layer. When silicon tetrachloride (SiCl ₄ ), which is another Si raw material, is used, it is necessary to increase the growth temperature by 200 ° C. compared to monosilane, and as a result, the degree of diffusion of impurities from the Si substrate to the Si epi layer is increased. Therefore, it is necessary to sufficiently increase the thickness of the Si epi film. On the other hand, in order to reduce the resistance value between the collector layer in the vicinity of the substrate surface and the substrate back electrode as much as possible, the carrier concentration of the Si epi layer cannot be increased, so it is advantageous to reduce the thickness. Therefore, it is desirable to use monosilane and reduce the thickness of the Si epi film as much as possible. Specifically, the film thickness of the Si epi film is desirably 5 to 10 μm. Further, for the purpose of forming a base layer having a conductivity type different from the conductivity type of the substrate, it is desirable that the resistivity of the Si epilayer be in the range of ρ = 1.5 Ωcm to 3.0 Ωcm.

  The thickness of the substrate with a reverse voltage protection function for the semiconductor light emitting device in the present invention is preferably as thin as possible in order to reduce the resistance value from the front surface to the back surface of the substrate and considering heat radiation from the semiconductor light emitting device. It is desirable to be thin to the extent that it does not break during the manufacturing process. For example, a thickness of 100 to 200 [mu] m is desirable as a guide for handling a Si substrate without breaking it in the manufacturing process. This thickness is also important for optical design. FIG. 8 shows a cross-sectional structure of a package example in which the reflector 38 is bonded. Due to the processing accuracy of the reflector, sagging occurs near the bottom surface of the concave portion of the reflector, and the designed slope cannot be formed. When the light emitting surface of the semiconductor light emitting device is buried in this portion, the function of the reflector is not exhibited for light emitted from the side surface of the semiconductor light emitting device. Therefore, the size and thickness of the substrate with a reverse voltage protection function of the present invention are important for light emitted from the side surface of the semiconductor light emitting device.

In FIG. 7, the width required for the gap of the wiring pattern is 0.15 mm, the wiring pattern width on the heat dissipating substrate side required for 2nd bonding of the wire bonding is 0.2 mm, and the light emitting surface of the light emitting element is 0.01 mm from the lower surface of the light emitting element. FIG. 5 is a view in which the height of the sag portion (vertical portion in the figure) near the bottom surface of the reflector is 0.05 mm, and the thickness of the substrate with a reverse voltage protection function of the present invention is 0.2 mm.
First, the surface (electrode surface) of the substrate with a reverse voltage protection function according to the present invention is made larger than the size of the semiconductor light emitting element, as shown in FIG. 8, in order to emit the light emitted from the side surface of the light emitting element in the emission direction without leaking. It is desirable to make it sufficiently large and to form a reflective metal film on almost the entire surface. The reflective metal film preferably contains Au, Ag, Ti, Ni, Cu, Cr, Al, Sn or the like. Second, for light that does not strike the surface of the substrate with voltage protection function of the present invention, the height of the sag portion is sufficiently low so that the light strikes the reflector portion that is not the sag portion (dotted line in FIG. 7). It is desirable to make the submount sufficiently thick.

As a method for forming a bipolar transistor on the surface of a substrate for a semiconductor light emitting device in the present invention, a thermal diffusion method is preferable to an ion implantation method. Unlike memories and central processing units (CPUs) that handle information, light emitting elements are energy conversion devices. Therefore, since the breakdown voltage of the transistor structure needs to be set high, the layer thickness of the transistor structure must be increased. When the layer thickness is increased, the thermal diffusion method is preferable because it can be formed at a lower cost than the ion implantation method.
Regarding the electrode of the substrate for semiconductor light emitting device in the present invention, when the substrate is an n ⁺ type Si substrate, the surface electrode is preferably Al / Ti in order to achieve ohmic contact. Al / Ti / Ag or Al / Ti / Al is desirable for providing a reflection function. The back electrode is preferably Cr / Au.

The edge portions of the surface electrodes in FIGS. 1, 5, and 8 are removed, but this is a street for use as a marker when cutting from the wafer state with a dicer or the like. If a marker is prepared separately, it is desirable in terms of cost or light reflection function that the streets are not formed but are cut together with a dicer or the like. Similarly, the back electrode is formed on the entire surface in FIG. 2, but a street may also be formed on the back surface in accordance with the pattern on the front surface.

The substrate for a semiconductor light emitting device in the present invention is not limited to a substrate on which a single light emitting device is placed, but may be a substrate on which a plurality of light emitting devices are placed. As shown in FIGS. 5 and 6, when the light emitting elements on the substrate are connected in series, the connection between the light emitting elements should be conducted by the front electrode pattern, and the connection to the back electrode should be made only by the light emitting element at the end. good. In the case where the light-emitting elements on the substrate are parallel circuits, an arrangement in which the structures of FIGS. 1 and 3 are arranged, that is, a structure in which each light-emitting element is connected to the back electrode may be formed. A matrix arrangement in which series and parallel are mixed may be combined with these series and parallel structures. The matrix arrangement is also effective for a structure in which semiconductor light emitting elements exhibiting red, green, and blue emission colors are arranged.
It is desirable for mass production that a plurality of semiconductor light emitting device substrates in the present invention are formed in advance on a substrate such as a silicon wafer, and the semiconductor light emitting devices are bonded and then cut into individual pieces. It is also desirable for mass production to bond the light emitting element to the substrate, and then form a phosphor in the vicinity of the light emitting element and then cut it into individual pieces.

  The bonding of the semiconductor light emitting device and the substrate with a reverse voltage protection function in the present invention, such as reflow bonding in the later process and reliability, thermosonic bonding via metal bumps such as Au, AuSn eutectic solder, etc. Pulse heat bonding and reflow bonding via high-temperature solder are desirable. If there is no problem in the subsequent process, lower melting point lead-free solder or conductive paste using resin as a binder may be used.

The semiconductor light emitting device in the present invention can be applied to all light emitting devices such as a light emitting diode (LED), a laser diode (LD), a super luminescent diode, and a surface emitting laser (VCSEL). As this light emitting element, a III-V group compound semiconductor is desirable.
Among these semiconductor light-emitting elements, it is desirable to apply to AlGaInN-based high-efficiency light-emitting elements that emit light from ultraviolet to blue and green, which are considered to be particularly vulnerable to electrostatic breakdown voltage. The present invention is also effective for AlGaInP-based high-efficiency light-emitting elements that emit orange to red light, AlGaAs-based, GaAsP-based, GaP-based visible light-emitting elements, and GaAs-based infrared light-emitting elements.

Furthermore, the semiconductor light emitting device according to the present invention is a flip chip that is laminated on a substrate transparent to the emission wavelength, and has a highly reflective anode electrode and cathode electrode formed on the epi surface side, and the substrate side is a light emitting surface. Is desirable. A flip chip from which a transparent or opaque substrate used for epitaxial growth of a semiconductor light emitting device is removed is also desirable. A flip chip with the substrate side as the light exit surface can be energized with one electrode on the epi surface side and one wire connected to the substrate side, or a face that emits light from the epi surface side with the substrate side as the mounting surface The present invention is also effective for up-type chips.
In addition, the present invention is effective for light emitting devices of any size and shape such as a square, rectangle, circle, ellipse, etc., having a chip size of 0.2 mm square or less to more than 1 mm square.
The semiconductor light emitting device according to the present invention may be combined with a phosphor. A white light-emitting element in which an appropriate amount of a yellow light-emitting phosphor is applied to a blue light-emitting element and a white light-emitting element in which an appropriate amount of red, green, and blue phosphors are applied to an ultraviolet light-emitting element are also highly effective.

The package in the present invention includes a shell type package (DOME), a surface mount diode package (SMD) using a printed circuit board (PCB substrate), SMD using a horizontal lead frame such as TOP type and SIDE view type, power It can be applied to any package or module such as a single package such as an LED package, can type package, or other custom package, chip-on-board (TOB), chip-on-film (TOF).
In the present invention, a package refers to an electronic component in the form of a point light source in which one or a plurality of light emitting element chips are placed on a plane or in a recess and separated into a single unit. This refers to an electronic component unit in the form of a line light source or a surface light source in which a plurality of light emitting element chips are distributedly mounted or a plurality of packages are arranged.

EXAMPLES The present invention will be specifically described below based on examples, but the present invention is not limited to these examples.
Example 1
1, 2, and 3, an n-type electrode pad, a p-type electrode pad, and a bipolar transistor structure formed in this example are used. A semiconductor light-emitting element substrate and a light-emitting device using the substrate are described. Show. This substrate was formed by the following procedure using a general thermal diffusion method.
First, an As-doped high-concentration n ⁺ -type Si substrate 22 produced by the CZ method was prepared. The plane orientation is the (111) plane, the substrate thickness is 450 μm, the front surface is a mirror, the back surface is a # 1200 lapping surface, and the resistivity ρ = 0.005 Ωcm. An n-type Si film 21 was epitaxially grown on the surface of the substrate by 7 μm by CVD using monosilane as a raw material. The growth temperature is 1000 ° C. The resistivity of the epi layer was ρ = 2 Ωcm.

Next, a SiO ₂ insulating film was formed on the epilayer surface by the following method. First, trade name OCD Si-Film type Si-11000 (SiO ₂ concentration: 11.0%) was dropped on the wafer surface and spin-coated at 2500 rpm for 15 seconds. Subsequently, it was kept at 800 ° C. or higher for 30 minutes in an oxygen atmosphere to form an oxide film. The SiO ₂ film thickness was about 5000 mm.
In order to form the p ⁺ -type base layer 24 on a part of the n-type Si epi layer of these substrates, patterning was performed by a photolithography technique. A negative type photoresist having a viscosity of 60 cp is used, and the resist is applied to the entire wafer surface by spin coating at 2500 rpm for 20 seconds. Thereafter, prebaking is performed at 100 ° C. for 10 minutes, and the pattern is exposed using a mask aligner. Next, a part of the photoresist film is removed by a dip method. Post baking is at 150 ° C. for 10 minutes.

After forming a patterned resist film in this manner, a mixed solution of HF: NH ₄ F = 1: 9 is prepared as an etchant for removing the SiO ₂ film and etched at 25 ° C. for 3 minutes. After overflow rinsing with ultrapure water for 5 minutes, etching was performed at 25 ° C. for 10 seconds with an etchant of HF: H ₂ O = 1: 12, and overflow rinsing was performed with ultrapure water for 5 minutes. Thereafter, the photoresist was removed.
A boron (B) diffusion source was applied to the resist pattern opening formed in this manner, and predeposition was performed in a thermal diffusion furnace. The sheet resistance ρs was adjusted to about 10Ω / □. The diffusion source was removed, and B was diffused to a predetermined depth of the n-type Si film in a driving process (oxygen atmosphere), and at the same time, an oxide film was re-formed on the entire surface of the substrate. This time, the diffusion depth was adjusted to 2.0 μm, and the sheet resistance was adjusted to 15Ω / □.

Next, in order to form the n ⁺ emitter layer 23 in the p ⁺ type base layer 24 and the n ⁺ collector layer 20 in another place on the substrate, photolithography is performed in the same manner as in the p ⁺ base layer formation. A resist film patterned by the technique was formed. After forming the resist film, the SiO ₂ insulating film was removed and the photoresist was removed.
A phosphorus (P) diffusion source was applied to the thus formed SiO ₂ mask pattern opening and predeposited in a thermal diffusion furnace. The sheet resistance ρs was adjusted to about 14Ω / □. The diffusion source was removed, and P was diffused to a predetermined depth in a driving process (oxygen atmosphere), and at the same time, an oxide film was re-formed on the entire surface of the substrate. This time, the diffusion depth was adjusted to 1.2 μm and the sheet resistance to 8Ω / □.

Before forming an electrode on the substrate surface, a portion of the SiO ₂ insulating layer formed on the entire surface is partly connected to the p ^{+ in} order to establish conduction with the n ⁺ type emitter layer, p ⁺ type base layer, and n ⁺ collector layer. It was removed in the same manner as when the mold base layer was formed.
After removing the photoresist, a metal film was laminated on the entire surface of the substrate in the order of Al, Ti, and Ag. The substrate temperature was 150 ° C., the degree of vacuum was 2 × 10 ⁻⁵ torr, and the purity of the metal used was 99.9% or more. This time, the thickness of each layer was adjusted to be Al 5000 mm, Ti 1000 mm, and Ag 5000 mm. The electrode pattern is formed in the same manner as when forming the p ⁺ type base layer, and an etchant having a mixture ratio of H ₃ PO ₄ : CH ₃ COOH: HNO ₃ : H ₂ O = 750 cc: 150 cc: 30 cc: 20 cc In 60 seconds, the Ag film was removed, and then Ti / Al was removed at 150 ° C. for 3 seconds using an etchant of H ₃ PO ₄ Conc. Overflow rinsing with ultrapure water was performed for 10 minutes, and then the photoresist was removed.

Sintering was performed for the purpose of conduction between Al and n-type Si. The conditions were 490 ° C. and 10 minutes under N ₂ gas flow.
In this state, the back surface of the Si substrate was lapped with # 1200 to reduce the substrate thickness to 150 μm.
Thereafter, a metal film was formed on the entire back surface in the order of Cr and Au. The substrate temperature was 250 ° C., the degree of vacuum was 2 × 10 ⁻⁵ torr, and the purity of the metal used was 99.9% or more. This time, the thicknesses of the respective layers were adjusted to be Cr 500 mm and Au 1000 mm.
The characteristics of the substrate having the reverse voltage protection circuit function manufactured as described above were evaluated. For two electrode pads formed on the substrate surface, Iz = 5 mA, Vz is 5.3 V to 6.5 V, Iz = 0.25 mA, Zzk is 2.9 kΩ to 3.6 kΩ, Iz = 5 mA, and Zz is 40Ω. Ir at ˜50Ω, Vz = 3V was 3.6 μA to 4.0 μA, and Vf at If = 10 mA was 0.8V to 1.0V.

Next, a flip chip type blue LED made of a group III nitride semiconductor was mounted on the substrate using gold bumps. When the applied current is applied in the region of -30mA to + 30mA with the forward direction of the LED being positive with respect to the back surface of the substrate and the electrode pad for 1 wire, the current-voltage curve on the forward side becomes the same curve as the single LED, and the reverse direction Then, asymptotically approaching the current-voltage curve of the protection circuit was observed, and it was confirmed that the substrate functions as a protection element against the reverse voltage of the LED.
Furthermore, when a blue LED mounted on the substrate with the protective function was mounted in the center of the side view package, the luminance was 1400 mcd when a forward current of 20 mA was applied. When a conventional Zener diode is provided, the power is 850 mcd, which shows the effect of the present invention.

  By using a bipolar transistor as the reverse voltage protection circuit for the LED, it is possible to make one wire in the wiring. Also, the reverse voltage protection circuit space can be made compact. And symmetrization of light distribution characteristics, and can be used for indicators, large outdoor displays, backlight light sources for mobile phones, headlights, illumination light sources, etc.

It is a top view which shows an example of the electrode pattern formed in the board | substrate surface in this invention. It is a top view which shows the electrode formed in the board | substrate back surface in this invention. It is sectional drawing of the light-emitting device of this invention. It is a top view which shows an example of arrangement | positioning of the side view package using the submount with a bipolar transistor type protective element function in this invention. It is a top view which shows one example of the electrode pattern formed in the board | substrate surface which mounts several LED in this invention. In this example, three LEDs are connected in a horizontal row. It is a top view which shows one example of arrangement | positioning of the side view package using the submount with a bipolar transistor type protective element function which mounts several LED in this invention. In this example, three chips are arranged in a horizontal row. It is sectional drawing which shows an example of the power package using the board | substrate with a bipolar transistor type protection element function in this invention. It is a top view which shows another example of the electrode pattern formed in the board | substrate surface in this invention. It is a top view which shows arrangement | positioning of the side view package containing a Zener diode in a prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Insulation film | membrane 12 Front side electrode pad 13 Bump formation marker 14 Connection hole position to emitter layer 15 Connection hole position to base layer 16 Connection hole position to collector layer 17 Semiconductor light emitting element arrangement position 18 Back side electrode pad 19 Transistor 20 n ⁺ collector layer 21 n-type epitaxial layer 22 n ⁺ substrate 23 n ⁺ emitter layer 24 p ⁺ base layer 25 short-circuited portion
26 Light Emitting Element 27 Au Bump 28 Inner Lead 29 Zener Diode 30 Au Wire 31 Submount Without Overvoltage Protection Function 33 Outer Lead 34 Submount with Transistor Type Protection Element 35 Insulating Adhesive 36 Wiring Pattern
37 Heat dissipation board 38 Reflector

Claims (9)

  A semiconductor light-emitting device comprising a bipolar transistor as a protection circuit against a reverse voltage of the semiconductor light-emitting element.   The protection circuit is short-circuited between the base and collector of the bipolar transistor, and is connected in parallel with the semiconductor element circuit so that the polarity between the emitter and the base is opposite to the polarity of the semiconductor light emitting element. The semiconductor light emitting device according to claim 1.   In the substrate on which the semiconductor light emitting element is mounted, a bipolar transistor in which a base collector is short-circuited is formed in the vicinity of the substrate surface, and an electrode pad to which the anode and cathode of the semiconductor light emitting element can be connected to the emitter and collector of the bipolar transistor A substrate for a semiconductor light-emitting element, comprising an electrode pad for external connection on the front surface and the back surface of the substrate.   The substrate for a semiconductor light emitting element according to claim 3, wherein the substrate is Si.   5. The substrate for a semiconductor light emitting element according to claim 3, wherein a plurality of semiconductor light emitting elements can be mounted on the substrate.   A semiconductor light-emitting device comprising a semiconductor light-emitting element mounted on the semiconductor light-emitting element substrate according to claim 3, wherein the bipolar transistor and the semiconductor light-emitting element have opposite polarities in parallel. A semiconductor light emitting device, wherein an anode and a cathode of the semiconductor light emitting element are connected to an emitter and a collector of a bipolar transistor.   The semiconductor light-emitting device according to claim 1, wherein the semiconductor light-emitting element is a III-V group compound semiconductor.   The semiconductor light-emitting device according to claim 1, wherein the semiconductor light-emitting element and the phosphor are combined. A semiconductor light-emitting element package or a semiconductor light-emitting element module on which the semiconductor light-emitting device according to any one of claims 1, 2, 6, 7, and 8 is mounted.

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