JP2007019648A - Data transfer controller and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data transfer controller suitable for half-duplex data transfer, and electronic equipment. <P>SOLUTION: The data transfer controller 30 includes a transceiver 40 which receives data from an opposite-side data transfer controller 10 through a serial bus during reception of half-duplex transfer and transmits data to the opposite-side data transfer controller 10 through the serial bus during transmission of half-duplex transfer, and a link controller 100 which controls the transceiver 40. The transceiver 40 outputs an information signal indicating a transfer direction to the link controller 100. The link controller 100 outputs a forcible switching signal SWRX for forcibly switching the transfer direction of the transceiver from the transmission direction to the reception direction to the transceiver 40 when the transfer direction that the information signal DIR indicates is the transmission direction although the transfer direction of the transceiver 40 should not be switched to the transmission direction. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a data transfer control device and an electronic device.

  In recent years, high-speed serial transfer interfaces such as LVDS (Low Voltage Differential Signaling) have attracted attention as interfaces for the purpose of reducing EMI noise. In this high-speed serial transfer, the transmitter circuit transmits serialized data using differential signals, and the receiver circuit differentially amplifies the differential signal to realize data transfer.

  A general mobile phone includes a first device portion provided with buttons for inputting a telephone number and characters, a second device portion provided with a main LCD (Liquid Crystal Display), a sub LCD and a camera, and a second device portion. 1. It is comprised by connection parts, such as a hinge which connects the 2nd apparatus part. Therefore, if the data transfer between the first board provided in the first device portion and the second board provided in the second device portion is performed by serial transfer using a differential signal, the connection portion It is possible to reduce the number of wires passing through the terminal. Therefore, the appearance of a high-speed serial interface capable of realizing efficient serial transfer at such a connection portion is desired.

By the way, the host device mounted on the first substrate described above transfers display data to the main LCD and the sub LCD. On the other hand, the main LCD and the sub LCD sometimes transfer the status information and the like to the host device. However, in this case, most of the transfer data is occupied by display data transferred from the host device to the main LCD or sub LCD. Therefore, the transfer method for such an application need not be a full-duplex transfer method in which data can be received simultaneously while transmitting data, and transfer in either direction is possible, but data transmission and data reception are simultaneous. A half-duplex transfer method that does not suffice is sufficient. If the half-duplex transfer method is adopted, the number of wires passing through the first and second device parts can be further reduced as compared with the full-duplex transfer method, and the design of the connection portion is facilitated. Can be planned.
JP 2001-222249 A

  The present invention has been made in view of the technical problems as described above, and an object of the present invention is to provide a data transfer control device and electronic apparatus suitable for half-duplex data transfer. is there.

  The present invention relates to a data transfer control device for transferring data to and from a counterpart data transfer control device via a serial bus. When receiving half-duplex transfer, the counterpart side via the serial bus A transceiver that receives data from the data transfer control device and transmits data to the counterpart data transfer control device via the serial bus at the time of half-duplex transfer, and a link controller that controls the transceiver And the transceiver outputs a notification signal notifying the transfer direction of the transceiver to the link controller, the link controller notifying the notification when the transfer direction of the transceiver is not to be switched to the transmission direction. When the transfer direction notified by the signal is the transmission direction, the transfer direction of the transceiver is changed. A forced switching signal forcibly switched to the receive direction from Shin direction, related to the data transfer control device for outputting to the transceiver.

  In the present invention, when the transfer direction of the transceiver is not to be switched to the transmission direction but the notification signal from the transceiver indicates the transmission direction, the transfer direction of the transceiver is forcibly switched to the reception direction. Therefore, even if the transfer direction of both the own data transfer control device and the partner data transfer control device becomes the transmission direction, it is possible to return to the normal state, and the serial transfer of the half-duplex transfer method A data transfer control device suitable for the above can be provided.

  In the present invention, the link controller may be configured such that the transfer direction notified by the notification signal does not exceed a given time after receiving the packet from the counterpart data transfer control device via the serial bus. In the case of the transmission direction, the forcible switching signal may be output to the transceiver.

  In this way, even if a given time elapses after receiving the packet, if the transfer direction of the transceiver is the transmission direction, it is forcibly switched to the reception direction and can be returned to the normal state. It becomes like this.

  In the present invention, the link controller analyzes the packet received from the counterpart data transfer control device via the serial bus, and if the transfer direction of the transceiver does not need to be switched to the transmission direction, the packet analysis result is obtained. However, if the transfer direction notified by the notification signal is the transmission direction, the forcible switching signal may be output to the transceiver.

  In this way, according to the packet analysis result, there is no need to switch to the transmission direction, but when the transceiver transfer direction is the transmission direction, it is forcibly switched to the reception direction, and the normal state Will be able to return.

  In the present invention, the link controller determines a transfer direction indicated by the notification signal after the processing for the packet received from the counterpart data transfer control device via the serial bus is completed, and the transfer direction is transmitted. In the case of the direction, the forcible switching signal may be output to the transceiver.

  In this way, after the processing on the received packet is completed, if the transfer direction of the transceiver is the transmission direction, it is forcibly switched to the reception direction and can be returned to the normal state.

  In the present invention, the transceiver includes a transmitter circuit that transmits data via the serial bus, a receiver circuit that receives data via the serial bus, and a transfer direction switching circuit that switches a transfer direction of the transceiver. A transfer direction switching instruction circuit that instructs the transfer direction switching circuit to switch the transfer direction, a code detection circuit that detects a transfer direction switching request code received from the counterpart data transfer control device, and the notification signal. A notification signal generation circuit that generates and outputs to the link controller, and when the transfer direction switching request code is detected by the code detection circuit, the transfer direction switching instruction circuit Instructs the transfer direction switching circuit to switch the transfer direction, and Notification signal generating circuit may be output to the link controller generates the notification signal.

  In this way, when the transfer direction switching request code is detected, the transfer direction is switched from the reception direction to the transmission direction, and the link controller is notified that a transfer direction switching request has been received. Therefore, for example, it is possible to prevent a situation where two transmitter circuits are connected to the serial bus at the transfer direction switching timing.

  Also, in the present invention, the transceiver receives a serial / parallel conversion circuit that converts serial data received from the receiver circuit into parallel data, and parallel data from the serial / parallel conversion circuit. A decoding circuit that performs a decoding process of the data encoded by the code and the special code, wherein the code detection circuit is a special code assigned to the transfer direction switching request code among the special codes defined by the encoding method By detecting this, the transfer direction switching request code may be detected.

  In this way, it is possible to detect the transfer direction switching request code by effectively utilizing the special code defined by the encoding method, and the circuit and processing can be simplified.

  In the present invention, when a reception error is detected during or before the detection of the transfer direction switching request code by the code detection circuit, the transfer direction switching instruction circuit transfers the transfer from the reception direction to the transmission direction. The direction switching instruction may be canceled.

  In this way, it is possible to prevent a situation in which two transmitter circuits are connected to the serial bus at the time of a reception error.

  In the present invention, when a CRC error is detected in a packet received from the counterpart data transfer control device, the link controller is a packet for notifying the counterpart data transfer control device of a CRC error. After the packet transmission is completed, a transfer direction switching request for returning the transfer direction from the transmission direction to the reception direction may be performed.

  In this way, even when a CRC error occurs, it can be appropriately dealt with.

  The present invention also relates to an electronic apparatus including any one of the data transfer control apparatuses described above and at least one of a communication device, a processor, an imaging device, and a display device.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. System Configuration FIG. 1 shows a data transfer control device (data transfer control circuit) of this embodiment and a system configuration example thereof. In the present embodiment, a so-called bridge function between a system bus and an interface bus is realized by using the host-side and target-side data transfer control devices 10 and 30 in FIG.

  The data transfer control devices 10 and 30 are not limited to the configuration shown in FIG. 1, and some of the circuit blocks shown in FIG. 1 may be omitted, the connection form between the circuit blocks may be changed, May be added. For example, the interface circuit 92 of the host-side data transfer control device 10 may be omitted, or the interface circuit 110 of the target-side data transfer control device 30 may be omitted. The data transfer control device 30 and the display driver 6 may be configured with two chips (semiconductor chips), but may be configured with one chip. For example, when the data transfer control device 30 is used as an IP (Intellectual Property) core, the data transfer control device 30 can be built in the semiconductor chip of the display driver 6 as a high-speed interface circuit. Similarly, the host device 5 (system device) and the data transfer control device 10 can be configured by one chip.

  The host-side data transfer control device 10 and the target-side data transfer control device 30 perform data transfer (packet transfer) via a serial bus (DATA +, DATA−) of differential signals (differntial signals), for example. More specifically, data (packets) are transmitted / received by current driving or voltage driving differential signal lines of the serial bus.

  The host-side data transfer control device 10 includes an interface circuit 92 that performs interface processing with the host device 5 (CPU, baseband engine, display controller, etc.). The interface circuit 92 is connected to the host device 5 via a system bus (host bus). The system bus can be used as an RGB interface bus or an MPU (Micro Processor Unit) interface bus. When used as an RGB interface bus, the system bus can include signal lines such as a horizontal synchronization signal, a vertical synchronization signal, a clock signal, and a data signal. When used as an MPU interface bus, the system bus can include signal lines such as a data signal, a read signal, a write signal, an address 0 signal (command / parameter identification signal), and a chip select signal.

  The host-side data transfer control device 10 includes a link controller 90 (link layer circuit) that performs link layer processing. The link controller 90 generates a packet (request packet, stream packet, etc.) that is transferred to the target-side data transfer control device 30 via the serial bus (LVDS), and performs processing for transmitting the generated packet. Specifically, a transmission transaction is activated to instruct the transceiver 20 to transmit the generated packet.

  The host-side data transfer control device 10 includes a transceiver 20 (PHY) that performs physical layer processing and the like. The transceiver 20 transmits the packet instructed by the link controller 90 to the target-side data transfer control device 30 via the serial bus. The transceiver 20 also receives a packet from the target-side data transfer control device 30. In this case, the link controller 90 analyzes the received packet and performs a link layer (transaction layer) process.

  The target-side data transfer control device 30 includes a transceiver 40 (PHY) that performs physical layer processing and the like. The transceiver 40 receives a packet from the host-side data transfer control device 10 via the serial bus. The transceiver 40 also transmits a packet to the host-side data transfer control device 10. In this case, the link controller 100 generates a packet to be transmitted and instructs transmission of the generated packet.

  The target-side data transfer control device 30 includes a link controller 100 (link layer circuit). The link controller 100 receives a packet from the host-side data transfer control device 10 and performs a link layer (transaction layer) process for analyzing the received packet.

  The target-side data transfer control device 30 includes an interface circuit 110 that performs interface processing with the display driver 6 (display driver circuit) that drives the display panel 7 (LCD or the like). The interface circuit 110 generates various interface signals and outputs them to the interface bus. The interface circuit 110 can include an RGB interface circuit, an MPU interface circuit, or a serial interface circuit (first to Nth interface circuits in a broad sense). Note that the interface circuit 110 may perform an interface process with the camera device or the sub LCD.

  In the following, for simplification of description, the configuration and operation of the present embodiment when the host-side data transfer control device 10 transmits a request packet to the target-side data transfer control device 30 will be described. The same configuration and operation are performed when the data transfer control device 30 transmits a request packet to the data transfer control device 10 on the host side.

2. Packet Format FIGS. 2A to 3B show a format example of a packet transferred via the serial bus. The write request packet in FIG. 2A is a packet for requesting data (command) write. The read request packet in FIG. 2B is a packet for requesting data read. This read request packet has a read data request size field instead of the data / parameter field of the write request packet in FIG. 2A, and is otherwise the same as the write request packet. The response packet in FIG. 3A is a packet for returning the response to the read request packet in FIG. In this response packet, the data / parameter returned as a response is set (inserted) in the data / parameter field. The acknowledgment packet (handshake packet) in FIG. 3B is a packet for transmitting an acknowledgment (ACK) or a negative acknowledgment (NACK). This acknowledge packet is not provided with a data / parameter field.

  The response request field included in the request packet (write request packet, read request packet) is a field for notifying whether or not to perform handshake transfer using an acknowledge packet (ACK, NACK). For example, when the response request value (response request flag) in the response request field is “0”, it indicates that an acknowledge packet is not required, and when it is “1”, it indicates that an acknowledge packet is required.

  The packet type field is a field for notifying the packet type. In this embodiment, a write request packet, a read request packet, a response packet, an acknowledge packet, and the like are prepared as packet types.

  The data / parameter field of the response packet is a field for setting (inserting) the read data requested by the read request packet. For example, when a read request packet is transmitted to the counterpart device, the counterpart device sets the read data corresponding to the read request packet in the data / parameter field of the response packet and transmits it.

  The response code field of the acknowledge packet is a field for notifying the reception status of the received packet. For example, when the response code value is “F”, it indicates that the reception has been successful, and when the response code value is “0”, it indicates that the reception has failed.

  In the present embodiment, as shown in FIGS. 2A and 2B, the request packet has a response request field. Then, when the host side (or the target side) transmits a request packet in which the response request field is set in the response request field to the target side (or the host side), the target side sends an acknowledge packet (ACK, NACK) is transmitted to the host side. On the other hand, when the host transmits a request packet in which no response request is set in the response request field to the target, the target does not transmit an acknowledge packet to the host. Thereby, efficient data transfer such as stream transfer can be realized.

3. Half-duplex transfer In the present embodiment, each of the host-side data transfer control device 10 and the target-side data transfer control device 30 performs data transfer via the serial bus while switching to the transmission side or the reception side by the half-duplex transfer method. I do. The data transfer control device on the transmission side of the data transfer control devices 10 and 30 drives the differential signal line of the serial bus (current drive, voltage drive).

  In an initial state after initialization processing performed immediately after power-on, the host-side data transfer control device 10 operates as a transmission side, and the target side operates as a reception side. That is, the basic state of the host-side data transfer control device 10 is a transmission state, and the basic state of the target-side data transfer control device 30 is a reception state.

  When receiving the half-duplex transfer, the target-side transceiver 40 receives data from the host-side data transfer control device 10 (in a broad sense, the partner-side data transfer control device) via the serial bus. On the other hand, at the time of transmission of half-duplex transfer, data is transmitted to the host-side data transfer control device 10 via the serial bus.

  Specifically, the host-side transceiver 20 includes a transmitter circuit HTX that transmits data to the target side via a serial bus, and a receiver circuit HRX that receives data from the target side via the serial bus. The target-side transceiver 40 includes a receiver circuit TRX that receives data from the host side via a serial bus, and a transmitter circuit TTX that transmits data to the host side via the serial bus. When data is transmitted from the host side to the target side, the host-side transmitter circuit HTX drives the serial bus to transmit data, and the target-side receiver circuit TRX receives the data. On the other hand, when data is transmitted from the target side to the host side, the transmitter circuit TTX on the target side drives the serial bus to transmit data, and the receiver circuit HRX on the host side receives the data. Each of the transceivers 20 and 40 has a transfer direction switching circuit (not shown), and switching from the transmission direction to the reception direction or from the reception direction to the transmission direction is performed by the transfer direction switching circuit.

  The host-side link controller 90 controls the transceiver 20. The transceiver 20 then outputs a signal DIR (transfer direction signal) for notifying the transfer direction of the transceiver 20 to the link controller 90. The target side link controller 100 controls the transceiver 40. The transceiver 40 then outputs a signal DIR notifying the transfer direction of the transceiver 40 to the link controller 100.

  FIG. 4A is a signal waveform diagram showing how the transfer direction is switched in the normal state. First, as shown at A1, the transceiver 20 on the host side transmits a packet to the target side via the serial bus. Specifically, following the preamble code PRE, DATA is transmitted, and finally a Direction code that is a transfer direction switching request code is transmitted. After the Direction code is transmitted in this way, the transfer direction of the host-side transceiver 20 is switched from the transmission direction (TX) to the reception direction (RX) as indicated by A2. Further, as shown in A3, a notification signal DIR notifying that the transfer direction of the transceiver 20 on the host side is the reception direction is output to the link controller 90 on the host side.

  When the target-side transceiver 40 receives the direction code, the transfer direction of the target-side transceiver 40 is switched from the reception direction to the transmission direction as indicated by A4. Further, as indicated by A5, the target-side transceiver 40 outputs the notification signal DIR to the target-side link controller 100. When the target side transmits a Direction code to the host side as indicated by A6, similarly, the transfer direction on the target side is switched to the reception direction, and the transfer direction on the host side is switched to the transmission direction.

  For example, in current-driven serial transfer, when the host side and the target side are in the transmission direction, and the host-side transmitter circuit HTX and the target-side transmitter circuit TTX are connected to the same serial bus, the potential of the serial bus becomes 0V. It will fall and it will take a long time to return to the normal state, or it will not be possible to return to the normal state.

  In this regard, in this embodiment, the host side (transmission side) switches its own transfer direction from the transmission direction to the reception direction after transmitting a Direction code that is a transfer direction switching request code. Further, the target side (reception side) switches its own transfer direction from the reception direction to the transmission direction after receiving the Direction code. Therefore, as indicated by A7 in FIG. 4A, both the transfer direction on the host side and the target side at the transfer direction switching timing is the reception direction. Therefore, the potential of the serial bus is maintained at a DC bias voltage of about 1V, for example. As a result, it is possible to return to a normal state in a short time.

  However, it has been found that a packet transmitted via the serial bus may be erroneously recognized on the receiving side. This is because the higher the speed of the signal transmitted via the serial bus, the more affected by noise and the like, the higher the possibility that the signal on the serial bus will be erroneously detected and the packet will be erroneously recognized on the receiving side. is there.

  For example, in A8 of FIG. 4B, the STOP code transmitted from the target side is erroneously recognized as a Direction code by the host side due to noise. As a result, as shown in A9, a TX-TX state in which the transfer directions on the host side and the target side are both in the transmission direction has occurred. In A10 of FIG. 4C, the STOP code transmitted from the host side is erroneously recognized as a Direction code by the target side due to noise. As a result, the TX-TX state is generated as indicated by A11. When such a TX-TX state occurs, there is a possibility that it cannot be restored to a normal state.

4). Avoidance of TX-TX State In this embodiment, the following method is adopted to avoid the TX-TX state as described above. That is, the target-side transceiver 40 outputs a notification signal DIR notifying the transfer direction to the link controller 100. The basic state on the target side is the reception state. Therefore, the link controller 100 outputs a signal SWRX forcibly switching the transfer direction of the transceiver 40 to the reception direction when the transfer direction notified by the notification signal DIR is the transmission direction. To do. That is, when the transfer direction of the transceiver 40 does not need to be switched to the transmission direction but the notification signal DIR indicates the transmission direction, the forcible switching signal SWRX is asserted and output to the transceiver 40. There are first, second, and third methods for outputting such a forced switching signal SWRX. 5, 6, and 7 show flowcharts of the first, second, and third methods.

4.1 First Method In the first method shown in FIG. 5, the link controller 100 receives a packet from the host side (the other party data transfer control device) via the serial bus, and then a given time elapses. However, when the transfer direction notified by the notification signal DIR is the transmission direction, the forced switching signal SWRX is output to the transceiver 40.

  That is, when the link controller 100 receives a packet from the host side (step S1), the link controller 100 starts a timer (step S2). Specifically, the count value is set in a counter circuit (not shown), and the count operation is started. When a given time (fixed time) elapses (step S3), it is determined whether or not the notification signal DIR from the transceiver 40 indicates the transmission direction (transmission state) (step S4), and indicates the transmission direction. If it is, the forced switching signal SWRX is asserted and output to the transceiver 40 (step S5).

  That is, in this embodiment, the basic state on the target side is the reception state. Accordingly, if the notification signal DIR indicates the transmission direction even after a certain time has elapsed, it is considered that the transceiver 40 erroneously detects switching of the transfer direction due to noise. Therefore, in this case, the transfer direction of the transceiver 40 is forcibly switched to the reception direction by the forcible switching signal SWRX.

  FIG. 8A is a signal waveform diagram of the first technique of FIG. In B1 of FIG. 8A, the STOP code transmitted from the host side is erroneously recognized as a direction code by the target side due to noise or the like. As a result, the serial bus is in the TX-TX state as indicated by B2. In this case, in the first method, the link controller 100 asserts the forcible switching signal SWRX as indicated by B3 because the notification signal DIR indicates the transmission direction after the predetermined time T has elapsed. Thereby, as shown in B4, the transfer direction on the target side is forcibly changed to the reception direction, and the TX-TX state is avoided.

4.2 Second Method In the second method of FIG. 6, the link controller 100 analyzes a packet received from the host side via the serial bus. If the transfer direction of the transceiver 40 does not need to be switched to the transmission direction, the forced switching signal SWRX is sent to the transceiver 40 when the notification signal DIR is in the transmission direction despite the determination based on the packet analysis result. Output.

  That is, when the link controller 100 receives a packet from the host side (step S11), the link controller 100 analyzes the received packet by a packet analysis circuit (not shown). If the received packet is a write request packet (step S12), it is determined whether the received packet is set to have a response request (step S13). Specifically, the response request field in FIG. 2A is analyzed to determine whether the response request value (response request flag) is “0” or “1”.

  If the response request value in the response request field is “1” and the response request is set to be present, an ACK (acknowledge) packet is transmitted (transmission transaction) in FIG. 3B (step S14). . Then, the transfer direction switching request code Direction is transmitted to the host side (step S15).

  On the other hand, if the response request value in the response request field is “0” and set to no response request in step S13, it is determined whether or not the notification signal DIR indicates the transmission direction (step S16). ). If the transmission direction is indicated, the forced switching signal SWRX is asserted and output to the transceiver 40 (step S17). That is, in the case of a write request packet with a response request, the transfer direction of the target transceiver 40 is switched to the transmission direction for ACK packet transmission. However, when there is no response request in the write request packet, the transfer direction of the target transceiver 40 does not need to be switched from the reception direction, which is the basic state, to the transmission direction. Accordingly, if the notification signal DIR indicates the transmission direction at this time, it is considered that the transceiver 40 has erroneously detected switching of the transfer direction due to noise or the like, and therefore the transfer direction of the transceiver 40 is forcibly determined by the forced switching signal SWRX. Switch to receiving direction.

  If it is determined in step S12 of FIG. 6 that the received packet is not a write request packet, it is determined whether or not it is a read request packet (step S18). If it is a read request packet, the response packet shown in FIG. 3A is sent (transmission transaction) (step S19). Then, the transfer direction switching request code Direction is transmitted to the host side (step S20).

  On the other hand, if it is determined in step S18 that the received packet is not a read request packet, it is determined whether or not the notification signal DIR indicates the transmission direction (step S21). If the transmission direction is indicated, the forcible switching signal SWRX is asserted and output to the transceiver 40 (step S22).

  That is, if the received packet is neither a write request packet nor a read request packet, it is considered an illegal packet. Therefore, when the notification signal DIR indicates the transmission direction at this time, it is considered that the transceiver 40 erroneously detects switching of the transfer direction due to noise. Therefore, in this case, the transfer direction of the transceiver 40 is forcibly switched to the reception direction by the forcible switching signal SWRX.

  FIG. 8B is a signal waveform diagram of the second technique of FIG. In B5 of FIG. 8B, the STOP code transmitted from the host side is erroneously recognized as the direction code by the target side. As a result, as shown in B6, the serial bus is in the TX-TX state. In this case, in the second method, the received packet is analyzed as indicated by B7. The link controller 100 determines that the transceiver 40 does not need to switch in the transmission direction based on the analysis result of the packet, but the notification signal DIR indicates the transmission direction, so that the forcible switching signal SWRX is displayed as shown in B8. Assert. Thereby, as shown in B9, the transfer direction on the target side is forcibly changed to the reception direction, and the TX-TX state is avoided.

4.3 Third Method In the third method of FIG. 7, the link controller 100 determines the transfer direction indicated by the communication signal DIR after the processing on the packet received from the host side via the serial bus is completed. . When the transfer direction is the transmission direction, the forced switching signal SWRX is output to the transceiver 40.

  That is, when receiving a packet from the host side (step S31), the link controller 100 determines whether the received packet is a write request packet (step S32). If the received packet is a write request packet, it is determined whether the received packet is set to have a response request (step S33). If the response request is set, an ACK packet is transmitted (step S34). Then, the transfer direction switching request code Direction is transmitted to the host side (step S35).

  On the other hand, if it is determined in step S32 of FIG. 7 that the received packet is not a write request packet, it is determined whether or not it is a read request packet (step S36). If it is a read request packet, a response packet is transmitted (step S37). Then, the transfer direction switching request code Direction is transmitted to the host side (step S38).

  In the third method, when the packet processing (transaction) in steps S32 to S38, which is processing for the received packet, is completed, it is determined whether or not the notification signal DIR indicates the transmission direction (step S39). If the transmission direction is indicated, the forced switching signal SWRX is asserted and output to the transceiver 40 (step S40).

  That is, in this embodiment, the basic state on the target side is the reception state. Therefore, even if all the processing on the received packet is completed, if the notification signal DIR indicates the transmission direction, it is considered that the transceiver 40 erroneously detects the switching of the transfer direction due to noise or the like. Therefore, in this case, the transfer direction of the transceiver 40 is forcibly switched to the reception direction by the forcible switching signal SWRX.

  FIG. 8C is a signal waveform diagram of the third technique of FIG. In B10 of FIG. 8C, the STOP code transmitted from the host side is erroneously recognized as the Direction code by the target side. As a result, as shown in B11, the serial bus is in the TX-TX state. In this case, in the third method, after the packet processing is completed as indicated by B12, the notification signal DIR is confirmed as indicated by B13. Since the notification signal DIR indicates the transmission direction even after the packet processing ends, the forcible switching signal SWRX is asserted as shown in B14. Thereby, as shown in B15, the transfer direction on the target side is forcibly changed to the reception direction, and the TX-TX state is avoided.

  As described above, in the present embodiment, when the TX-TX state occurs due to a malfunction caused by noise or the like, the transfer direction of the transceiver 40 is forcibly set to the reception direction, so the TX-TX state can be avoided. It is possible to return to the normal state.

5. Detailed Example 5.1 Detailed Configuration Example FIGS. 9 to 11 show a detailed configuration example of the present embodiment. In the figure, the host-side data transfer control device 10 is a side that supplies a clock, and the target-side data transfer control device 30 is a side that operates using the supplied clock as a system clock.

  In FIG. 9, DTO + and DTO- are OUT data output from the host side to the target side. CLK + and CLK− are clocks supplied from the host side to the target side. The host side outputs DTO +/− in synchronization with the CLK +/− edge (rising edge or falling edge). Therefore, the target side can sample and capture DTO +/− using CLK +/−. Further, in FIG. 9, the target side operates based on the clock CLK +/− supplied from the host side. That is, CLK +/− becomes the system clock on the target side. Therefore, the PLL (Phase Locked Loop) circuit 12 (clock generation circuit in a broad sense) is provided on the host side, and is not provided on the target side.

  DTI + and DTI- are IN data output from the target side to the host side. STB + and STB- are strobes (clocks in a broad sense) supplied from the target side to the host side. The target side generates and outputs STB +/− based on CLK +/− supplied from the host side. The target side outputs DTI +/− in synchronization with the STB +/− edge (rising edge or falling edge). Therefore, the host side can sample and capture DTI +/− using STB +/−.

  The transceiver 20 on the host side includes transmitter circuits 22 and 24 for OUT transfer (data transfer in a broad sense) and clock transfer, IN transfer (data transfer in a broad sense), and strobe transfer (clock in a broad sense). (Receiver) receiver circuits 26 and 28 are included. The target-side transceiver 40 includes receiver circuits 42 and 44 for OUT transfer and clock transfer, and transmitter circuits 46 and 48 for IN transfer and strobe transfer. Note that a configuration in which some of these circuit blocks are not included may be employed. For example, when full-duplex transfer is unnecessary, the receiver circuits 26 and 28 on the host side and the transmitter circuits 46 and 48 on the target side may be omitted.

  10 and 11 show more detailed configuration examples of the present embodiment. In the following description, the transmitter circuits 22 and 24 and the receiver circuits 26 and 28 on the host side are respectively expressed as OUTTX, CLKTX, INRX, and STBRX as appropriate. Further, the receiver circuits 42 and 44 and the transmitter circuits 46 and 48 on the target side are represented as OUTRX, CLKRX, INTX, and STBTX, respectively.

  FIG. 10 shows a configuration example of the transceiver 20 and the link controller 90 on the host side. The transaction controller 50 performs data transfer transaction control. Specifically, a packet transfer instruction such as a request packet, an acknowledge packet, or a stream packet is instructed. The packet generation & transfer abort circuit 52 performs a process for generating a packet (packet header) instructed by the transaction controller 50 and a process for aborting the data transfer.

  The 8B / 10B encoding circuit 54 (encoding circuit in a broad sense) encodes an 8B / 10B encoding method (in a broad sense, N bits are expanded to M bits (N <M, where N and M are integers of 2 or more)). Data is encoded by the method. The code generation circuit 55 generates a 10-bit (M bits in a broad sense) special code defined by 8B / 10B encoding. Specifically, a generation process and an additional process of a preamble code, a stop code, an abort code, a direction code (transfer direction switching request code) assigned to a special code of the 8B / 10B encoding method are performed. The encoding method performed by the encoding circuit 54 is not limited to the 8B / 10B encoding method.

  The parallel / serial conversion circuit 56 converts the parallel data received from the 8B / 10B encoding circuit 54 into serial data. The OUTTX receives serial data from the parallel / serial conversion circuit 56, drives a DTO +/− serial bus (serial signal line), and transmits data. CLKTX receives the clock generated by the PLL circuit 12, drives the CLK +/− serial bus, and transmits the clock. These OUTTX and CLKTX can be configured by analog circuits that drive the serial bus with current (or voltage drive). The clock generated by the PLL circuit 12 is frequency-divided by the frequency dividing circuit 14 and supplied to circuit blocks (blocks for processing parallel data) in the transceiver 20 and the link controller 90.

  The INRX receives data transferred via the DTI +/− serial bus and outputs the received serial data to the serial / parallel conversion circuit 60. The STBRX receives the strobe (clock) transferred via the STB +/− serial bus, and outputs the received strobe to the serial / parallel conversion circuit 60. These INRX and STBRX can be configured by an analog circuit that detects the drive current (or drive voltage) of the serial bus.

  The serial / parallel conversion circuit 60 converts serial data transferred via the DTI +/− serial bus into parallel data. Specifically, the serial / parallel conversion circuit 60 samples serial data transferred via the DTI +/− serial bus based on a strobe (clock) transferred via the STB +/− serial bus. To do. The sampled serial data is converted into parallel data.

  The idle detection circuit 59 is a circuit that detects, for example, an idle signal of “0” as a differential signal (an idle signal whose logic level is fixed to the first logic level). The preamble error detection circuit 61 performs a detection process of a preamble code that is one of special codes of the 8B / 10B encoding method. When a preamble error, which is an error state in which no preamble code is detected, is detected, the link controller 90 is notified.

  The 8B / 10B decoding circuit 62 (decoding circuit in a broad sense) performs a decoding process of data encoded by the 8B / 10B encoding method and a special code. The code detection circuit 63 included in the 8B / 10B decoding circuit 62 performs a special code detection process defined by 8B / 10B encoding. Specifically, a detection process such as a stop code, an abort code, a direction code (transfer direction switching request code) assigned to a special code of the 8B / 10B encoding method is performed.

  The error signal generation circuit 64 generates an error signal and outputs it to the transaction controller 50 when a preamble error is detected, or when a disparity error or a decoding error is detected.

  The interface circuit 65 is a circuit that performs interface processing between PHY and LINK (between the transceiver and the link controller). The interface circuit 65 includes a notification signal generation circuit 66 that generates a notification signal and outputs the notification signal to the link controller 90. The notification signal generation circuit 66 generates, for example, a signal notifying that a transfer direction switching request has been received from the target-side data transfer control device 30 and outputs the signal to the link controller 90.

  The packet analysis & header / data separation circuit 68 performs processing for analyzing a received packet and processing for separating the header and data of the received packet. The interface circuit 67 is a circuit that performs interface processing between PHY and LINK.

  In this embodiment, half-duplex transfer using DTO + and DTO- is possible, and for this purpose, a receiver circuit HRX connected to the DTO + and DTO- serial buses is provided. The HRX receives data transferred via the DTO + and DTO- serial buses when the transfer direction is switched in half-duplex transfer. The transfer direction switching circuit 58 switches between a transmission direction that is a transfer direction in which data is transmitted by OUTTX and a reception direction that is a transfer direction in which data is received by HRX. The transfer direction switching instruction circuit 57 instructs the transfer direction switching circuit 58 to switch the transfer direction.

  FIG. 11 shows a configuration example of the transceiver 40 and the link controller 100 on the target side. The configuration and operation of the circuits 70, 72, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88 of FIG. 11 are the same as those of the circuit 50 of FIG. , 52, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, the description thereof will be omitted. The strobe control circuit 16 (frequency divider circuit) receives the clock received at CLKRX, performs strobe control such as clock frequency division, and outputs a strobe signal to STBTX. The frequency dividing circuit 18 receives the clock received by CLKRX and supplies the frequency-divided clock to the circuit block in the transceiver 40 and the link controller 100. The transmitter circuit TTX is used when performing half-duplex transfer using DTO + and DTO-. Specifically, TTX drives DTO + and DTO- serial buses to transmit data when the transfer direction is switched in half-duplex transfer. At this time, the transfer direction is switched by the transfer direction switching circuit 78, and the transfer direction switching instruction is performed by the transfer direction switching instruction circuit 77.

  5 is realized by the counter circuit 94 (timer) included in the interface circuit 87 in FIG.

  5 is performed by the notification signal determination circuit 95 included in the interface circuit 87. The notification signal DIR determination processing in steps S16 and S21 in FIG. 6 and step S39 in FIG. That is, the notification signal DIR generated by the notification signal generation circuit 86 is output from the interface circuit 85 and input to the interface circuit 87. The notification signal determination circuit 95 determines whether or not the input notification signal DIR indicates the transmission direction.

  Further, the forced switching signal generation circuit 96 included in the interface circuit 87 performs the process of generating the forced switching signal SWRX in steps S5 and S17 and S22 in FIG. That is, the forced switching signal generation circuit 96 generates the forced switching signal SWRX when it is determined that the notification signal DIR indicates the transmission direction even though the transfer direction is not to be switched to the transmission direction. The generated forced switching signal SWRX is output from the interface circuit 87 and input to the interface circuit 85.

  7 is performed by the packet processing end determination circuit 97 included in the transaction controller 70. When the packet processing ends, the packet processing end signal is asserted and input to the notification signal determination circuit 95. The notification signal determination circuit 95 determines whether or not the notification signal DIR indicates the transmission direction. If the notification signal DIR indicates the transmission direction, the forcible switching signal generation circuit 96 asserts the forcible switching signal SWRX.

5.2 8B / 10B Code In 8B / 10B encoding, 256 types of 8-bit data are encoded into 256 types of 10-bit data. By this encoding, the ratio of “1” and “0” of 10-bit data can be set to 4: 6, 5: 5, 6: 4, and the balance of DC components can be adjusted. Specifically, in 8B / 10B encoding, 8-bit data is defined as A, B, C, D, E, F, G, and H from lsb to msb. In the encoding process, an ABCDE (5-bit) data block x (decimal notation) and an FGH (3-bit) data block y (decimal notation) are separated. This separated data block is considered by replacing it with a character code called Dxy called D code. The ABCDE block is encoded with 5B / 6B and converted to abcdei (6 bits). The FGH block is encoded with 3B / 4B and converted to fghj (4 bits). Then, 10-bit encoded data is obtained by combining abcdei and fghj.

  According to the 8B / 10B encoding, even if data having “0” or “1” continues, the bit change of the signal increases after the encoding, and the occurrence of a transfer error due to noise or the like can be reduced. . Further, according to 8B / 10B encoding, the bit width is expanded from 8 bits to 10 bits, so that it is possible to generate a special code (control code) as shown in FIG. 12 in addition to data.

  In this embodiment, a preamble code, a stop code, a direction code (transfer direction switching request code) or the like is assigned to a special code obtained by 8B / 10B encoding (encoding for extending the bit width) to transfer data. Data is transferred via a serial bus (DTO). For example, in FIG. 12, the codes K28.1, K28.2, K28.3, K28.4, K28.5, K28.6, K28.7 are respectively a preamble code, a stop code, an abort code, and a division code ( Multi-channel division transfer code), data power down code, direction code (transfer direction switching request code), and all power down code are allotted to the serial bus for data transfer. Then, the receiver side performs a decoding process in the 8B / 10B encoding system and detects the codes K28.1 to K28.7, thereby detecting the direction code and the like.

  As shown in FIG. 12, each code includes a plus code (positive symbol code) and a minus code (negative symbol code). The minus code is a code obtained by inverting each bit of the plus code.

  In 8B / 10B encoding, 8-bit data is converted into 10-bit plus code data and minus code data and transmitted alternately. As a result, since the receiving side can predict the disparity of the next data every 10 bits, an error in the transmission path can be detected.

5.3 Details of Half Duplex Transfer Next, details of the half duplex transfer of this embodiment will be described. If half-duplex transfer can be realized, it is not necessary to perform full-duplex transfer. Therefore, the receiver circuits INRX and STBRX for full-duplex transfer in FIG. 10 and the transmitter for full-duplex transfer in FIG. The configurations of the circuits INTX and STBTX can be omitted.

  FIG. 13A is a diagram for explaining the half-duplex transfer method of the present embodiment at the normal time. First, as shown in (1) of FIG. 13A, the host switches the transfer direction from the transmission direction to the reception direction. Specifically, the transfer direction switching instruction circuit 57 in FIG. 10 instructs the transfer direction switching circuit 58 to switch the transfer direction. Then, the transfer direction switching circuit 58 switches from the transmitter circuit OUTTX to the half-duplex transfer receiver circuit HRX. That is, in the forward direction (transmission direction), the transfer direction switching circuit 58 sets OUTTX to an enabled state and HRX to a disabled state. On the other hand, when the transfer direction is switched to the reverse direction (reception direction), the transfer direction switching circuit 58 sets OUTTX to a disabled state and HRX to an enabled state.

  After the host switches the transfer direction from the transmission direction to the reception direction in this way, the target switches the transfer direction from the reception direction to the transmission direction as shown in (2) of FIG. Specifically, the transfer direction switching instruction circuit 77 in FIG. 11 instructs the transfer direction switching circuit 78 to switch the transfer direction. Then, the transfer direction switching circuit 78 switches from the receiver circuit OUTRX to the half-duplex transfer transmitter circuit TTX. That is, in the forward direction (reception direction), the transfer direction switching circuit 78 sets OUTRX to an enabled state and sets TTX to a disabled state. On the other hand, when the transfer direction is switched to the reverse direction (transmission direction), the transfer direction switching circuit 78 sets OUTRX to a disabled state and sets TTX to an enabled state.

  Next, as shown in (3) of FIG. 13A, the target starts transfer in the reverse direction. That is, the target transmitter circuit TTX drives the serial bus (serial signal line) with current, and transmits data to the host. Then, as shown in (4) of FIG. 13A, the host also performs reception in the reverse direction. That is, the host receiver circuit HRX detects the current flowing through the serial bus (converts the current into a voltage) and receives data transferred from the TTX.

  FIG. 13B is a diagram showing an outline of the half-duplex transfer method of this embodiment when reception fails. First, as shown in (1) of FIG. 13B, the host switches the transfer direction from the transmission direction to the reception direction. In this embodiment, when a reception error occurs, the target does not switch the transfer direction from the reception direction to the transmission direction. That is, the target cancels the switching of the transfer direction from the reception direction to the transmission direction, which should have been performed in response to a transfer direction switch request from the host, and does not switch from the receiver circuit OUTRX to the transmitter circuit TTX. More specifically, when a reception error occurs when a transfer direction switching request from the host to the target is detected or before detection (when a transfer direction switching request code is detected or before detection), the target transmits from the reception direction. Cancel the transfer direction switch to the direction. Examples of such reception errors include a preamble error and a decoding error.

  Then, as shown in (2) of FIG. 13B, after the transmission is completed, the host does not receive a response (response packet) from the target even if a predetermined time elapses. Return the transfer direction to the send direction and send again. Then, the transfer direction is switched from the transmission direction to the reception direction.

  Next, as shown in (3) of FIG. 13B, when the target succeeds in reception by the receiver circuit OUTRX, the target switches the transfer direction from the reception direction to the transmission direction.

  In the case of a CRC error or the like detected after detection of the transfer direction switching request, the target switches the transfer direction from the reception direction to the transmission direction in accordance with the transfer direction switching request from the host as usual. Then, the target transmits a packet for notifying the CRC error to the host, and after the packet transmission is completed, returns the transfer direction from the transmission direction to the reception direction. On the other hand, when the host (link controller 90) receives a packet reporting a CRC error from the target, the host (link controller 90) returns the transfer direction from the reception direction to the transmission direction.

  In serial transfer such as current drive, it is desirable to avoid a situation where the host transmitter circuit and the target transmitter circuit are connected to the same serial bus. When such a situation occurs, the two transmitter circuits perform current driving in which current flows to the VSS side, so the potential of the serial bus drops to 0 V, and it takes a long time to return to the normal state. It is. On the other hand, even if the host receiver circuit and the target receiver circuit are connected to the same serial bus, the voltage of the serial bus is set to a DC bias voltage of about 1 V, for example, by the DC bias circuit included in these receiver circuits. Maintained. Therefore, the analog circuit can be restored to a normal state in a short time.

  In this regard, in the half-duplex transfer system of this embodiment shown in FIG. 13A, the host first switches from the transmitter circuit OUTTX to the receiver circuit HRX, and then the target switches from the receiver circuit OUTRX to the transmitter circuit TTX. Accordingly, it is possible to avoid a situation in which the transmitter circuits OUTTX and TTX are simultaneously connected to the DTO +/− serial bus at the transfer direction switching timing. At such transfer direction switching timing, the receiver circuits HRX and OUTRX are connected to DTO +/−. Therefore, the voltage of the serial bus is maintained at a DC bias voltage of, for example, about 1 V by the DC bias circuit included in the receiver circuits HRX and OUTRX, so that the analog circuit can be restored to a normal state in a short time.

  Furthermore, as shown in FIG. 13B, in this embodiment, the target is not switched from the receiver circuit OUTRX to the transmitter circuit TTX in the event of a reception error. Therefore, even when the host times out and returns from the receiver circuit HRX to the transmitter circuit OUTTX, it is possible to avoid a situation where the host transmitter circuit OUTTX and the target transmitter circuit TTX are simultaneously connected to the DTO +/− serial bus. . Therefore, even in the case of a reception error, it is guaranteed that the host receiver circuit HRX and the target receiver circuit OUTRX are connected to the serial bus, so that the analog circuit can be restored to a normal state in a short time.

  Next, the half-duplex transfer method of this embodiment will be described in more detail with reference to FIGS. First, as shown in FIG. 14A, a transfer direction switching request is received from the link controller 90 of the host. Then, the code generation circuit 55 of the 8B / 10B encoding circuit 54 generates a transfer direction switching request code.

  Specifically, the encoding circuit 54 encodes the data by the 8B / 10B encoding method. The code generation circuit 55 generates a special code assigned to the transfer direction switching request code among the special codes defined by the 8B / 10B encoding method. That is, in FIG. 12, the direction code that is the transfer direction switching request code is assigned to the special code K28.6 of 8B / 10B. As will be described later, the code generation circuit 55 receives a special code generation instruction signal (TxCode) from the link controller 90, and when the generation of the transfer direction switching request code is instructed by the special code generation instruction signal, Generate. In this way, the transfer direction switching request of the link controller 90 is accepted.

  Next, the parallel / serial conversion circuit 56 monitors a transfer direction switching request while executing serial transfer (parallel / serial conversion). Then, when all the 10-bit transfer direction switching request codes have been passed to the analog circuit, the transfer direction switching instruction circuit 57 instructs the transfer direction switching circuit 58 to switch the transfer direction. That is, the transmitter circuit OUTTX of the analog circuit instructs the switching of the transfer direction after transmitting the transfer direction switching request code to the target via the serial bus. When the transfer direction is instructed in this way, the transfer direction switching circuit 58 switches the transfer direction from the transmission direction to the reception direction. That is, the transmitter circuit OUTTX is switched to the receiver circuit HRX.

  As described above, in this embodiment, when a transfer direction switching request is received from the link controller 90, the transmitter circuit OUTTX transmits the transfer direction switching request code generated by the code generation circuit 55 to the host via the serial bus. To do. Then, after transmitting the transfer direction switching request code, the transfer direction switching instruction circuit 57 instructs the transfer direction switching circuit 58 to switch the transfer direction from the transmission direction to the reception direction.

  Next, as shown in FIG. 14B, the target serial / parallel conversion circuit 80 monitors the transfer direction switching request from the host while performing serial reception (serial / parallel conversion). When the code detection circuit 83 detects the transfer direction switching request code, the transfer direction switching instruction circuit 77 instructs the transfer direction switching circuit 78 to switch the transfer direction. When the switching of the transfer direction is instructed in this way, the transfer direction switching circuit 78 switches the transfer direction from the reception direction to the transmission direction. That is, the receiver circuit OUTRX is switched to the transmitter circuit TTX.

  When the code detection circuit 83 detects the transfer direction switching request code, the notification signal generation circuit 86 generates a signal (DIR) notifying that a transfer direction switching request has been received and outputs the signal (DIR) to the link controller 100.

  Specifically, the 8B / 10B decoding circuit 82 receives parallel data from the serial / parallel conversion circuit 80 and decodes the data encoded by the 8B / 10B encoding method and the special code. Then, the code detection circuit 83 detects the special code (K28.6 in FIG. 12) assigned to the transfer direction switching request code among the special codes defined in the 8B / 10B encoding method, thereby requesting the transfer direction switching. Detect code. As described above, when a reception error is detected at the time of code detection by the code detection circuit 83 or before code detection, the transfer direction switching instruction circuit 77 issues an instruction to switch the transfer direction from the reception direction to the transmission direction. Cancel.

  As described above, in this embodiment, when the transfer direction switching request code is detected by the code detection circuit 83, the transfer direction switching instruction circuit 77 switches the transfer direction from the reception direction to the transmission direction. Instruct the circuit 78. In addition, the notification signal generation circuit 86 generates a signal notifying that a transfer direction switching request has been received from the host (partner data transfer control device), and outputs the signal to the link controller 100. As a result, the link controller 100 can know that a transfer direction switching request has been received from the host, and can proceed with the subsequent processing.

  As described with reference to FIGS. 14A and 14B, in this embodiment, a transfer direction switching request from the host is transmitted to the target by transmitting a transfer direction switching request code from the host to the target. Then, after transmitting the transfer direction switching request code, the host switches from the transmitter circuit OUTTX to the receiver circuit HRX. Further, after detecting the transfer direction switching request code, the target switches from the receiver circuit OUTRX to the transmitter circuit TTX. In this case, it takes a certain time to transfer the transfer direction switching request code via the serial bus. Therefore, for a certain time when the transfer direction is switched, the host receiver circuit HRX and the target receiver circuit OUTRX are connected to the serial bus, and the voltage of the serial bus is maintained at a voltage of, for example, 1V. Therefore, the analog circuit can be restored to a normal state in a short time.

5.4 Data Transfer Format FIG. 15 shows a data transfer format in the normal transfer method. In FIG. 15, the state where no data is transferred via the serial bus is the idle state. In the present embodiment, a state (signal) in which the logic level of the serial bus (serial signal line) is fixed to the first logic level (for example, “0”) continuously for a given number of bits (M bits) or more. , Defined as an idle state (idle signal). More specifically, a state (signal) in which “0” of the differential signal is continuously output for 10 bits (M bits) or more is defined as an idle state (idle signal). Here, “0” of the differential signal means, for example, that the current flowing in the negative signal line (DTO−, DTI−) of the differential signal is more than the current flowing in the positive signal line (DTO +, DTI +). There are many states. Further, “1” of the differential signal means, for example, a state where the current flowing through the plus signal line of the differential signal is larger than the current flowing through the minus signal line.

  As shown in FIG. 15, in this embodiment, when packet transfer is performed, IDLE and two preamble codes are inserted between packets. Specifically, the transmitting side outputs an idle signal IDLE of “0” as a differential signal to the serial bus, and then transmits a plus code (first polarity in a broad sense) preamble code PRE + and a minus code (first in a broad sense). 2) of the preamble code PRE- is transmitted via the serial bus. As a result, the receiving side can detect the preamble code and synchronize the packets. After that, the transmission side transmits a plus code DATA + and a minus code DATA− encoded by 8B / 10B, and finally transmits a stop code STOP +/−. Thereafter, the idle signal IDLE is output again.

  As described above, in this embodiment, an idle code of “0” (or “1”) may be output as a differential signal instead of outputting an idle code during an idle period. Therefore, the operation of the encoding circuit (code generation circuit), parallel / serial conversion circuit, serial / parallel conversion circuit, and decoding circuit (code detection circuit) can be stopped during the idle period. Therefore, it is possible to effectively prevent a wasteful current from flowing in the logic circuit during the idle period, thereby saving power. Thereby, the electric current etc. which flow at the time of standby of portable information equipment, such as a cellular phone, can be reduced.

  Further, in the present embodiment, only the minus code (second polarity) preamble code PRE- is detected without ignoring the plus code (first polarity) preamble code PRE +. Then, on the condition that the preamble code PRE- has not been detected (provided that PRE- has not been detected one or more times), the preamble error notification signal is activated to notify the preamble error.

  If only the preamble code PRE− is detected in this way, PRE + is ignored even if a change in data from “0” to “1” in the first bit of PRE + cannot be detected. No preamble error is detected. Accordingly, it is possible to prevent a situation where a preamble error is erroneously notified.

  FIG. 16 shows an example of signal waveforms when the host side transmits data to the target side in the normal transfer method. On the other hand, FIG. 17 shows an example of a signal waveform when the host side transmits data to the target side in the half-duplex transfer method of this embodiment, and FIG. 18 shows the data from the target side to the host side in the half-duplex transfer method. An example of a signal waveform when transmitting is shown.

  As shown in FIG. 16, in the normal transfer method, the host (OUTTX) transmits a stop code (STOP) in addition to data of a packet to be transmitted via the serial bus. On the other hand, in the half-duplex transfer method of FIG. 17, the host (OUTTX) adds to the packet data to be transmitted via the serial bus (after transmission of the packet data) and transfers the transfer direction switching request code (Direction). ). In this way, after the data is transmitted, the host can receive the data by switching the transfer direction from the transmission direction to the reception direction, for example, in the next transaction.

  The host (OUTTX) outputs an idle signal of “0” as a differential signal after transmitting a transfer direction switching request code (Direction) via the serial bus. That is, an idle signal whose logic level is fixed to the first logic level (“0”) continuously for 10 bits (M bits) or more is output to the serial bus.

  When the host outputs such 10-bit IDLE, the host switches the transfer direction from the transmission direction to the reception direction. This enables reverse transfer. On the other hand, after detecting the transfer direction switching request code (Direction), the target switches the transfer direction from the reception direction to the transmission direction when one (10 bits) IDLE is detected. This avoids the situation where OUTTX and TTX are simultaneously connected to the serial bus at the transfer direction switching timing.

  If a reception error occurs on the target side after the host transmits a transfer direction switching request code (Direction), switching of the transfer direction is prohibited on the target side as described above. For this reason, the host does not need to transmit a transfer direction switching request code to return the transfer direction, and the processing can be simplified.

  As can be seen from a comparison between FIG. 17 and FIG. 18, in the half-duplex transfer of this embodiment, the transfer rate is, for example, 200 Mbps in the forward data transfer from the host to the target, which is high speed. . On the other hand, in the data transfer from the target to the host in the reverse direction, the transfer rate is, for example, 50 Mbps, which is a low speed.

5.5 Configuration of Transmitter Circuit, Receiver Circuit, and Transfer Direction Switching Circuit FIG. 19 shows a detailed configuration example of the transmitter circuit, the receiver circuit, and the transfer direction switching circuit. Note that these circuits of the present embodiment are not limited to the configuration shown in FIG.

  As shown in FIG. 19, the host-side transmitter circuit OUTTX includes N-type (first conductivity type in a broad sense; the same applies to other descriptions) transistors TR1, TR2, TR3, TR4, and current sources IH1, IL1, IH2, IL2. including. Note that IH1 and IH2 are current sources that can pass a larger amount of current than IL1 and IL2.

  The transistor TR1 has a DTO + signal line connected to its drain, an input signal DIN + input to the gate via the transistor TR11, and a current source IH1 connected to the source. The transistor TR2 has a DTO + signal line connected to its drain, an input signal DIN- input to the gate via the transistor TR12, and a current source IL1 connected to its source. The transistor TR3 has a DTO- signal line connected to the drain, an input signal DIN- input to the gate via the transistor TR12, and a current source IH2 connected to the source. The transistor TR4 has a DTO- signal line connected to its drain, an input signal DIN + input to the gate via the transistor TR11, and a current source IL2 connected to the source.

  For example, assume that the transistors TR11 and TR12 are turned on. Then, when DIN + is at the H level (“1”) and DIN− is at the L level (“0”), the transistors TR1 and TR4 are turned on and the transistors TR2 and TR3 are turned off. Therefore, a large current flows through the DTO + signal line by the current source IH1, and a small current flows through the DTO- signal line by the current source IL2. On the other hand, when DIN + is L level and DIN- is H level, the transistors TR2 and TR3 are turned on and the transistors TR1 and TR4 are turned off. Therefore, the current source IL1 causes a small current to flow through the DTO + signal line, and the current source IH2 causes a large current to flow through the DTO− signal line. By doing so, it is possible to drive the current of the serial bus.

  The target-side receiver circuit OUTRX includes DC bias circuits 400 and 402, IV conversion circuits 410 and 412, and a comparator 414. The DC bias circuits 400 and 402 generate a DC bias voltage of about 1 V, for example, at the differential signal input nodes N1 and N2. The IV conversion circuits 410 and 412 convert currents flowing through the DTO + and DTO− signal lines into voltages, respectively. In this case, current-voltage conversion in the IV conversion circuits 410 and 412 can be speeded up by generating a DC bias voltage by the DC bias circuits 400 and 402. The comparator 414 compares the first and second voltages generated by the current-voltage conversion of the IV conversion circuits 410 and 412 and outputs the result as DOUT.

  The configuration of the target-side transmitter circuit TTX is substantially the same as that of the host-side transmitter circuit OUTTX, and the configuration of the host-side receiver circuit HRX is also substantially the same as that of the target-side receiver circuit OUTRX.

  The host-side transfer direction switching circuit 58 of FIG. 10 includes N-type (first conductivity type) transistors TR11, TR12, TR13, TR14 as shown in FIG. The target-side transfer direction switching circuit 78 in FIG. 11 includes N-type transistors TR21, TR22, TR23, and TR24.

  When the host-side transfer direction switching instruction signal SDIR becomes L level, the transistors TR11 and TR12 are turned on, and the input signals DIN + and DIN− are input to the transistors TR1, TR2, TR3, and TR4. That is, the transmitter circuit OUTTX is set to an enable state. Further, when the instruction signal SDIR becomes L level, the transistors TR13 and TR14 are turned off, and the DC bias circuits 420 and 422 are set to a disabled state. The IV conversion circuits 430 and 432 are also set to a disabled state. For this reason, the receiver circuit HRX is set to a disabled state. Thereby, the transfer direction is set to the transmission direction.

  On the other hand, when the host side instruction signal SDIR becomes H level, the transmitter circuit OUTTX is set to the disabled state and the receive circuit HRX is set to the enabled state, and the transfer direction is the receiving direction, contrary to the L level. Set to

  Similarly, when the transfer direction switching instruction signal SDIR on the target side becomes L level, the receiver circuit OUTRX is set to the enabled state and the transmitter circuit TTX is set to the disabled state, so that the transfer direction is set to the reception direction. . On the other hand, when the instruction signal SDIR becomes H level, the receiver circuit OUTRX is set to the disabled state and the transmitter circuit TTX is set to the enabled state, so that the transfer direction is set to the transmission direction. As described above, the transfer direction can be switched to an arbitrary direction by using the instruction signal SDIR output from the transfer direction switching instruction circuits 57 and 77.

6). Electronic Device FIG. 20 shows a configuration example of the electronic device of this embodiment. This electronic device includes the data transfer control devices 502, 512, 514, 520, and 530 described in the present embodiment. Further, it includes a baseband engine 500 (a communication device in a broad sense), an application engine 510 (a processor in a broad sense), a camera 540 (an imaging device in a broad sense), or an LCD 550 (a display device in a broad sense). Note that some of these may be omitted. According to this configuration, a mobile phone having a camera function and an LCD (Liquid Crystal Display) display function can be realized. However, the electronic device of the present embodiment is not limited to a mobile phone, and can be applied to various electronic devices such as a digital camera, a PDA, an electronic notebook, an electronic dictionary, a projector, a rear projection television, or a portable information terminal.

  As shown in FIG. 20, this embodiment is implemented between a host-side data transfer control device 502 provided in the baseband engine 500 and a target-side data transfer control device 512 provided in the application engine 510 (graphic engine). The serial transfer described in the embodiment is performed. The present embodiment also includes a host-side data transfer control device 514 provided in the application engine 510, a data transfer control device 520 including a camera interface circuit 522, and a data transfer control device 530 including an LCD interface circuit 532. The serial transfer described in (1) is performed. Note that the baseband engine 500 and the application engine 510 may be realized by the same hardware (CPU or the like).

  According to the configuration of FIG. 20, EMI noise can be reduced as compared with a conventional electronic device. Further, by realizing a reduction in the size and power consumption of the data transfer control device, it is possible to further reduce the power consumption of the electronic device. When the electronic device is a mobile phone, the signal line passing through the connection portion (hinge portion) of the mobile phone can be a serial signal line, and the mounting can be facilitated.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, a term (host-side data transfer control device, etc.) described with a broader or synonymous different term (other party data transfer control device, etc.) at least once in the specification or drawing is not Can also be replaced by the different terms.

  Further, the configuration and operation of the data transfer control device and the electronic device are not limited to those described in the present embodiment, and various modifications can be made. For example, the forced switching signal generation method and the half-duplex transfer method are not limited to those described in the present embodiment.

1 is a configuration example of a data transfer control device according to the present embodiment. 2A and 2B show packet format examples. 3A and 3B show packet format examples. 4A, 4B, and 4C are explanatory diagrams of the problem of half-duplex transfer. The flowchart of the 1st method of this embodiment. The flowchart of the 2nd method of this embodiment. The flowchart of the 3rd method of this embodiment. FIGS. 8A, 8B, and 8C are signal waveform diagrams of the first to third methods of the present embodiment. 2 is a detailed configuration example of a data transfer control device according to the present embodiment. Configuration example of host side transceiver and link controller. Configuration example of target side transceiver and link controller. Explanatory drawing of the method of assigning various codes to a special code. 13A and 13B are detailed explanatory diagrams of half-duplex transfer according to the present embodiment. FIGS. 14A and 14B are detailed explanatory diagrams of half-duplex transfer according to this embodiment. Example of data transfer format for normal transfer. Signal waveform example when the host sends data to the target in normal transfer. Signal waveform example when the host sends data to the target in half-duplex transfer. Signal waveform example when the target sends data to the host in half-duplex transfer. Configuration example of a transmitter circuit, a receiver circuit, and a transfer method switching circuit. Configuration example of an electronic device.

Explanation of symbols

HTX, TTX transmitter circuit, HRX, TRX receiver circuit,
5 Host device, 6 Display driver, 7 Display panel,
10 Host side data transfer control device, 20 Transceiver,
30 target side data transfer control device, 40 transceiver,
90, 100 link controller, 92, 110 interface circuit,

Claims (9)

A data transfer control device for performing data transfer with a counterpart data transfer control device via a serial bus,
When receiving a half-duplex transfer, data is received from the counterpart data transfer control device via the serial bus, and when sending a half-duplex transfer, the data is sent to the counterpart data transfer control device via the serial bus. A transceiver that transmits data,
A link controller for controlling the transceiver,
The transceiver is
A notification signal for notifying the transfer direction of the transceiver is output to the link controller;
The link controller
The transfer direction of the transceiver is forcibly switched from the transmission direction to the reception direction when the transfer direction notified by the notification signal is the transmission direction even though the transfer direction of the transceiver is not to be switched to the transmission direction. A data transfer control device for outputting a forcible switching signal to the transceiver. In claim 1,
The link controller
After the packet is received from the counterpart data transfer control device via the serial bus, the forced direction is determined when the transfer direction notified by the notification signal is the transmission direction even if a given time has elapsed. A data transfer control device for outputting a switching signal to the transceiver. In claim 1,
The link controller
The packet received from the counterpart data transfer control device via the serial bus is analyzed, and it is determined that the transfer direction of the transceiver does not need to be switched to the transmission direction based on the packet analysis result. A data transfer control device that outputs the forced switching signal to the transceiver when the transferred direction is a transmission direction. In claim 1,
The link controller
After the processing on the packet received from the counterpart data transfer control device via the serial bus is completed, the transfer direction indicated by the notification signal is determined, and the forced switching is performed when the transfer direction is the transmission direction. A data transfer control device for outputting a signal to the transceiver. In any one of Claims 1 thru | or 4,
The transceiver is
A transmitter circuit for transmitting data via the serial bus;
A receiver circuit for receiving data via the serial bus;
A transfer direction switching circuit for switching the transfer direction of the transceiver;
A transfer direction switching instruction circuit that instructs the transfer direction switching circuit to switch the transfer direction;
A code detection circuit for detecting a transfer direction switching request code received from the counterpart data transfer control device;
A notification signal generation circuit that generates the notification signal and outputs the notification signal to the link controller;
When the transfer direction switching request code is detected by the code detection circuit, the transfer direction switching instruction circuit instructs the transfer direction switching circuit to switch the transfer direction from the reception direction to the transmission direction, and the notification The data transfer control device, wherein the signal generation circuit generates the notification signal and outputs the notification signal to the link controller. In claim 5,
The transceiver is
A serial / parallel conversion circuit for converting serial data received from the receiver circuit into parallel data;
A decoding circuit that receives parallel data from the serial / parallel conversion circuit and performs a decoding process of data encoded by a predetermined encoding method and a special code;
The code detection circuit includes:
The data transfer control device, wherein the transfer direction switching request code is detected by detecting a special code assigned to the transfer direction switching request code among the special codes defined by the encoding method. In claim 5 or 6,
When a reception error is detected during or before the detection of the transfer direction switching request code by the code detection circuit, the transfer direction switching instruction circuit issues an instruction to switch the transfer direction from the reception direction to the transmission direction. A data transfer control device for canceling. In any of claims 5 to 7,
The link controller
When a CRC error is detected in the packet received from the counterpart data transfer control device, a packet for notifying the CRC error is sent to the counterpart data transfer control device, and the packet transmission is completed. A data transfer control device that performs a transfer direction switching request to return the transfer direction from the transmission direction to the reception direction later. A data transfer control device according to any one of claims 1 to 8,
An electronic apparatus comprising: at least one of a communication device, a processor, an imaging device, and a display device.

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