JP2007005452A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent break of substrate wire extended from land in a semiconductor package generated by thermal stress resulting from difference in thermal expansion coefficients of semiconductor package and a mounted substrate. <P>SOLUTION: An angled land 8c is formed in an SMD structure where the land surface 8a is in contact with an internal circumferential end 14a of an aperture of an insulating film at an external joining terminal where an external joining terminal 9 is joined with the land 8. A center 8d at the external edge of land held by the angled lands 8c is formed in an NSMD structure where a gap 16 is formed between a land external edge 8b and the internal circumferential end 14a of the aperture of the insulating film. A land lead wire is formed to the angled land covered with the insulating film 7, and the SMD structure and the NSMD structure are alternately provided in three or more locations. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device (semiconductor package), and more particularly to a semiconductor device in which a semiconductor element is mounted on a printed wiring board and packaged and mounted on a mounting board (motherboard) with solder bumps or the like.

  A semiconductor package (semiconductor device) that packages semiconductor devices (semiconductor chips) with various functions that are mounted on portable devices that require multiple functions and miniaturization, and various electronic control devices mounted on automobiles. However, BGA (Ball Grid Array) type, which is suitable for multi-terminals due to downsizing and multi-functionality, is increasing. A BGA type package is packaged by mounting a semiconductor element on a printed wiring board also called an interposer and applying resin sealing or the like.

  On the surface (back surface) opposite to the semiconductor element mounting surface (main surface) of the printed wiring board, external joint terminals made of a ball or paste solder material for mounting a semiconductor package on the mounting substrate of various devices Is bonded to a land provided on the surface on the back side of the printed wiring board.

  An insulating film (solder resist) is provided on the surface on the back side of the printed wiring board, and an opening for exposing the land surface (connection opening) for bonding an external junction terminal to the land. Is formed. In addition, wiring for electrically connecting the semiconductor element and the external junction terminal is formed on the printed wiring board, and this wiring is a package of the front wiring (main surface and back wiring) of the printed wiring board and the internal wiring. The structure is appropriately combined depending on the size and the number of terminals.

  In the joint portion of the external joint terminal, the land diameter for joining the external joint terminal is conventionally smaller than the opening diameter of the insulating film (solder resist) covering the surface on the back side of the printed wiring board. An NSMD (called Non-Solder Mask Defined or non-over resist) structure in which a gap exists between the outer peripheral end and the inner peripheral end of the insulating film opening is used. In the NSMD structure, not only the land surface but also the solder which is an external connection terminal is bonded to the land side surface. Further, the wiring drawn out from the land is exposed from the insulating film at the outer peripheral end of the land and the inner peripheral end of the insulating film opening, and after the solder bonding, the solder is also bonded to the exposed portion of the wiring.

  When the environmental temperature changes with the semiconductor package in which the semiconductor element is packaged mounted on the mounting board, the difference in linear expansion coefficient between the semiconductor package and the housing of the electronic device on which the mounting board is mounted The resulting thermal stress acts on the external joint terminal portion. This thermal stress may cause damage such as cracks or breaks in the external joint terminals, resulting in poor conduction, and the reliability of the semiconductor package may be reduced. The continuity failure that occurs in the external joint terminal portion may be caused by damage to the solder that is the external joint terminal or the lead wiring from the land.

  In recent semiconductor packages, lead-free materials that do not contain lead (such as Sn-Ag-Cu-based materials) are increasingly used from the viewpoint of environmental problems, and the size of the package is reduced by increasing the size and increasing the number of terminals. The land interval is narrowed, and the lead-out wiring from the land is miniaturized. Since lead-free solder has higher yield stress than lead solder, plastic deformation of the solder material is less likely to occur, and the stress generated in the land lead wiring is increased. Further, miniaturization of the lead-out wiring further increases the wiring stress, and the reliability deterioration due to the wiring damage is remarkable.

  In order to solve the lowering of reliability due to damage to the lead wiring from the land, for example, there are the following known examples.

  In Japanese Patent Laid-Open No. 2000-315843, the width of a signal pattern extending from a plurality of connecting portions including an outer connecting portion and an inner connecting portion for connecting to a component is determined between the outer connecting portion and the inner connecting portion. A configuration is disclosed in which the width of the signal pattern extending from the outer connection portion is made wider than that of the inner connection portion. As a result, it is intended to prevent disconnection of the signal pattern extending from the outer connection portion that is susceptible to deformation due to thermal expansion during reflow or mechanical load during incorporation into equipment.

  In Japanese Patent Application Laid-Open No. 2003-23243, the wiring extending from the circular connection electrode portion provided on the wiring board protects the connection electrode end and the conductor so as not to be wetted by the solder material. The form covered with the protective film within the fixed space | interval of the film | membrane edge is disclosed. As a result, the area where the wiring is exposed from the protective film is reduced, the thermal stress applied to the wiring portion caused by the solder getting wet with the wiring is reduced, and the reliability is improved.

  In Japanese Patent Application Laid-Open No. 2004-128290, for example, the wiring of the external terminal of the outer edge corner of the semiconductor element and the wiring of the outermost inner terminal are drawn inward, and the wiring of the external terminal positioned outside the outer edge of the semiconductor element is outward. A withdrawal form is disclosed. The disconnection of the wiring due to thermal stress is suppressed by setting the wiring lead-out direction of the external terminal to the inner side or the outer side in the positional relationship with the outer edge portion of the semiconductor element.

  In Japanese Patent Laid-Open No. 2001-230513, an over resist structure in which a part of the outer peripheral edge of the land is covered with a resist film, and the remaining part is an outer peripheral edge of the land and an inner peripheral edge of the opening of the resist film. A form of a non-over resist structure in which a gap is formed between the two is disclosed. In particular, the above-described embodiment is applied to the outermost land among a plurality of lands arranged in an aligned state. In this land, the portion located outside the surface mount component is a non-over resist structure and the inner side. A form in which the portion located is an over resist structure is shown. As a result, of the lands arranged in a large number, the bonding strength is high for the outermost land to which the stress due to the impact such as a drop impact and the stress due to warping and bending acts most strongly.

JP 2000-315843 A JP 2003-23243 A JP 2004-128290 A JP 2001-230513 A

  The BGA type semiconductor package targeted by the present invention is mainly composed of a semiconductor element, a printed wiring board also called an interposer, and a sealing resin. Generally, silicon (Si) is generally used for a semiconductor element mounted in the central portion of a semiconductor package, its linear expansion coefficient is about 3 ppm / ° C., and the apparent linear expansion coefficient of the package outer edge is printed wiring. When the substrate is a glass epoxy material and the sealing resin is an epoxy resin for transfer molding, it is about 10 ppm / ° C. The linear expansion coefficient of the mounting substrate is about 15 to 20 ppm for the glass epoxy material. The stress generated in the external joint terminal due to the difference in coefficient of linear expansion between the semiconductor package and the mounting substrate increases as the distance from the center of the semiconductor package (a point where diagonal lines intersect in a rectangular plane) increases, but the semiconductor element portion Since the difference in linear expansion coefficient from the mounting substrate is larger than the outer edge portion of the semiconductor package, a large stress is also generated in the outer edge portion of the semiconductor element and the external junction terminal located inside the outer edge of the semiconductor element. Therefore, in the form described in Japanese Patent Application Laid-Open No. 2000-315843, an effect is obtained for disconnection of the lead-out wiring of the land to which the external joint terminal in the outer part of the semiconductor package is joined. It is difficult to suppress disconnection at the external junction terminal of the semiconductor element portion.

  Moreover, although the form of Unexamined-Japanese-Patent No. 2003-23243 forms a protective film so that the lead wiring of a land may also be covered, since a protective film and solder do not join (or adhere | attach), it changes with temperature changes. The contact interface between the protective film edge and the solder crosses the width direction of the wiring, and the contact interface opens and closes, concentrating on the wiring directly under the protective film edge and generating stress, suppressing wiring disconnection There are cases where it is not possible.

  Japanese Patent Application Laid-Open No. 2004-128290 forms the lead-out wiring from the land in the optimum direction for each part in the positional relationship between the outer edge of the semiconductor element and the external junction terminal. However, in order to direct a plurality of adjacent land lead wires in the same direction, the substrate internal wiring (through hole) for conducting the semiconductor element mounting surface side and the external junction terminal side is located away from the land to be connected. In some cases, the wiring length of the printed wiring board becomes long, which hinders the speeding up of the semiconductor package. In addition, the number of external junction terminals increases, the distance between terminals decreases, the number of printed circuit board surface wiring between terminals increases, the number of internal wiring (through holes) increases, and it is placed near the land. In some cases, the wiring cannot be formed in the optimum direction.

  Furthermore, the form described in Japanese Patent Application Laid-Open No. 2001-230513 can improve the reliability against impacts such as drop impacts, warping and bending, but is generated at the external joint terminals due to the difference in the linear expansion coefficient between the semiconductor package and the mounting substrate. As for the damage to the external joint terminal portion due to the stress to be applied, the effect of suppressing the damage cannot be obtained because the direction in which the high stress acts is different from the case of the drop impact.

  According to the present invention, the reliability of the semiconductor package is deteriorated due to the damage of the lead-out wiring from the land due to the stress generated in the external joint terminal due to the difference in the linear expansion coefficient between the semiconductor package and the mounting substrate, which could not be sufficiently solved by the above prior art It aims at solving the subject which suppresses. In addition, a sufficient bonding area between the land surface and the solder is ensured, stress concentration at the solder joint is suppressed, and reduction of reliability of the semiconductor package due to solder damage is also suppressed.

Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
The present invention solves the above problems and suppresses the disconnection of the land lead-out wiring due to the thermal stress caused by the difference in thermal expansion coefficient between the semiconductor package and the mounting substrate.

(1) Regarding the junction structure between the land and the external junction terminal, the NSMD structure part and the SMD (Solder Mask Defined, or over resist) structure part are provided at three or more locations, respectively, and the lead wiring surface is covered with an insulating film. About. Specifically, a semiconductor element, a printed circuit board on which the semiconductor element is mounted, a land provided on the surface layer opposite to the semiconductor element mounting surface of the printed circuit board, and the same surface layer as the land extending from the land An insulating film covering the surface of the printed circuit board formed with a substantially circular opening for joining the external junction terminal to the land, and an external junction terminal joined to the land. The part where the inner peripheral edge of the film opening and the land surface are in contact, that is, the part where the land surface is covered with an insulating film, and the part where a gap is formed between the outer edge of the land and the inner peripheral edge of the opening of the insulating film That is, the semiconductor package is characterized in that three or more NSMD structure portions are provided, and the surface of the wiring extending from the land is covered with an insulating film.

(2) A gap between the portion (SMD structure portion) where the inner peripheral edge of the opening of the insulating film and the land surface are in contact with each other, and the outer edge of the land and the inner peripheral edge of the opening of the insulating film described in (1) The semiconductor package is characterized in that the portions where NS is formed (NSMD structure portion) are alternately formed along the outer edge of the land.

(3) About the junction structure of the land and the external junction terminal, the NSMD structure portion and the SMD structure portion are provided at three or more locations, and at least one of the NSMD structure portions is connected to the center of the semiconductor element and the center of the opening of the insulating film. The present invention relates to a configuration in which the lead wiring surface is covered with an insulating film provided at a position intersecting with the line. Specifically, a semiconductor element, a printed circuit board on which the semiconductor element is mounted, a land provided on the surface layer opposite to the semiconductor element mounting surface of the printed circuit board, and the same surface layer as the land extending from the land An insulating film covering the surface of the printed circuit board formed with a substantially circular opening for joining the external junction terminal to the land, and an external junction terminal joined to the land. Three or more portions where a gap is formed between the inner peripheral edge of the opening of the film and the land surface, that is, the NSMD portion, and the outer edge of the land and the inner peripheral edge of the opening of the insulating film, that is, three or more. And at least one portion of the NSMD structure portion where a gap is formed between the outer edge of the land and the inner peripheral edge of the opening of the insulating film is at a position intersecting with a line connecting the center of the semiconductor element and the center of the opening of the insulating film. Ah Thus, the semiconductor package is characterized in that the surface of the wiring extending from the land is covered with an insulating film.

(4) At least one of the NSMD structure portions described in (3) is provided at a position intersecting with a line connecting the center of the semiconductor element and the center of the opening of the insulating film at a position intersecting with the outer edge of the semiconductor element. The land, the land on the inner side of the outer edge and the group of lands adjacent to the semiconductor element on the outer side of the outer edge are in the direction opposite to the center of the semiconductor element.

(5) The position at least one of the NSMD structure portion described in (3) is provided at a position intersecting with a line connecting the center of the semiconductor element and the center of the opening of the insulating film at a position farthest from the outer edge of the semiconductor element. The land group is a semiconductor package characterized by being on the center direction side of the semiconductor element.

  In the present invention, the NSD structure portion and the SMD structure portion are provided at three or more locations for the junction structure of the land and the external junction terminal, the lead wiring extending from the land is led out from the SMD structure portion, and the surface of the wiring is an insulating film (solder resist) Cover with. As a result, the contact interface between the wiring insulating film and the solder does not cross in the width direction of the wiring, so that thermal stress generated in the wiring can be suppressed. In addition, by providing three or more NSMD structure portions and SMD structure portions, it is possible to secure a sufficient bonding area between the land surface and the solder that is the external bonding terminal.

  When the semiconductor element is mounted at the center of the semiconductor package, the stress generated in the external junction terminal due to temperature change is caused by thermal deformation that occurs in the direction along the line connecting the center of the semiconductor element and the center of the external junction terminal. It occurs as a result. Therefore, high stress is generated in the external deformation terminal portion in the thermal deformation direction. When at least one location where the line connecting the center of the semiconductor element and the center of the external junction terminal intersects the outer edge of the land is the NSMD structure portion, the solder is bonded not only to the land surface but also to the land side surface. As a result, stress is dispersed over a wide range, and solder damage can be suppressed.

  There are two positions where the line connecting the center of the semiconductor element and the center of the external junction terminal and the outer edge of the land intersect each external junction terminal portion. The NSMD structure portion provided at at least one of the intersecting portions is preferably formed on the side where the stress increases among the two intersecting portions, and is appropriately selected depending on the position of the external junction terminal in the semiconductor package.

  For the land intersecting the outer edge of the semiconductor element, the land inside the outer edge of the semiconductor element, and the land group closest to the semiconductor element outside the outer edge of the semiconductor element, the NSMD structure portion is the center of the semiconductor element. Provide in the opposite direction. In the land in the vicinity of the outer edge of the semiconductor element or on the inner side, high stress is generated in the direction opposite to the center of the semiconductor element. By making this portion have an NSMD structure, the stress generated at the external joint terminal portion is dispersed and suppressed, and damage to the solder can be prevented.

  For the land group located farthest from the outer edge of the semiconductor element, the NSMD structure portion is provided in the direction of the center of the semiconductor element. In this land group, a high stress is generated on the center direction side of the semiconductor element. Therefore, by forming this portion with the NSMD structure, the stress generated in the external joint terminal portion can be dispersed and suppressed.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

1 to 4 are diagrams related to a semiconductor package (semiconductor device) according to a first embodiment of the present invention.
FIG. 1 is a diagram showing a schematic configuration of a semiconductor package ((a) is a schematic sectional view, (b) is a schematic bottom view),
2A and 2B are diagrams showing a state before the external junction terminal is joined to the land of the semiconductor package (FIG. 2A is a schematic plan view, and FIG. 2B is a schematic cross-sectional view taken along line AA in FIG. (C) is a schematic sectional view taken along line BB in (a)),
FIG. 3 is a schematic cross-sectional view enlarging a part of FIG.

  As shown in FIGS. 1 (a) and 1 (b), a semiconductor package according to a first embodiment of the present invention includes a semiconductor element (semiconductor chip) 1, a printed wiring board 5 called an interposer, an external junction terminal 9, and a semiconductor. A conductive member 3 such as a metal wire that electrically connects the element 1 and the printed wiring board 5, a sealing resin 4, an adhesive member 2, and the like are provided.

  As shown in FIG. 1A, the semiconductor element 1 is mounted on the main surface 5 a which is a semiconductor element mounting surface of the printed wiring board 5 by an adhesive member 2. A sealing resin 4 is provided on the main surface 5 a of the printed wiring board 5 so as to cover the semiconductor element 1 and the conductive member 3, and the main surface 5 a of the semiconductor element 1, the conductive member 3 and the printed wiring board 5. Is protecting. A plurality of bump-like external joint terminals 9 are provided on the surface (back surface) 5b opposite to the semiconductor element mounting surface (main surface 5a) of the printed wiring board 5, and the plurality of external joint terminals 9 are shown in FIG. As shown in (b), they are arranged in a lattice pattern. In FIG. 1B, a total of 272 external junction terminals 9 are arranged, with 16 in the center of the printed wiring board 5 and 256 in 4 rows on the outer peripheral portion.

  As shown in FIG. 3, the printed wiring board 5 is mainly provided with a core layer 6, an electrode 12 provided on the main surface of the core layer 6 and joined with a thin metal wire, and opposite to the main surface of the core layer 6. A land 8 provided on the rear surface and to which the external connection terminal 9 is bonded, a lead-out wiring 10 extending from the land 8 and formed on the same plane as the land 8, and a plane extending from the electrode 12 and the same plane as the electrode 12. The wiring 13 formed above, the internal wiring (through-hole wiring) 11 that electrically connects the wiring 13 and the lead-out wiring 10, and the insulating film (solder resist film) that covers the main surface and the back surface of the core layer 6 respectively. 7. The electrode 12 is constituted by a part of the wiring 13 formed on the main surface 5 a side of the printed wiring board 5, and the land 8 is formed by a part of the lead wiring 10 formed on the back surface 5 b side of the printed wiring board 5. Has been.

  The semiconductor element 1 and the printed wiring board 5 are electrically connected by electrically connecting the electrode on the surface of the semiconductor element (not shown) and the electrode 12 of the printed wiring board 5 with a conductive member 3 such as a thin metal wire. The The land 8 and the electrode 12 are respectively provided with openings 14 and 15 of the insulating film 7 so that the conductive member 3 can be joined to the electrode 12 and the external joint terminal 9 can be joined to the land 8. An external joint terminal 9 is joined to the land 8 on the back surface 5 b side of the printed wiring board 5, and the external joint terminal 9 is electrically connected to the semiconductor element 1 via the wiring of the conductive member 3 and the printed wiring board 5. Continuity is made.

  The printed wiring board 5 includes a core layer 6 in which epoxy resin, BT resin, and the like are combined with glass cloth, a multilayer printed wiring board provided with wiring 13 and internal wiring 11, and a tape board made of polyimide resin. A wiring board or the like on which wiring is formed is used. For the conductive member 3, a fine metal wire such as gold or aluminum is used. Further, as the sealing resin, a material in which an epoxy resin is filled with silica particles or the like is used. The external joint terminal 9 is made of solder mainly composed of tin (Sn), lead (Pb), silver (Ag), copper (Cu), or the like.

  The planar shape of the land 8 is rectangular as shown in FIG. The planar shape of the opening 14 of the insulating film 7 is circular, and overlaps with the land 8 and the central portion of the land surface 8 a is exposed from the insulating film 7, but the corner 8 c of the land 8 is covered with the insulating film 7. . The lead wiring 10 from the land 8 extends from the land corner portion 8 c, and the lead wiring 10 is covered with the insulating film 7. In the land corner portion 8c, the land surface 8a and the opening inner peripheral edge 14a of the insulating film are in contact with each other, and this portion has an SMD (over resist) structure (FIG. 2B).

  A gap 16 is formed between the land outer edge end 8b and the opening inner peripheral edge 14a of the insulating film 7 in the center portion 8d of the land outer edge sandwiched between the land corner portions 8c at the land outer edge end 8b. In the portion where the gap 16 is formed, the solder is bonded to the land side surface 8e as well as the land surface 8a, and this portion has an NSMD (non-over resist) structure (FIG. 2C).

  There is a gap 16 between the SMD structure portion (land corner portion 8c) where the land surface 8a contacts the inner peripheral edge 14a of the opening of the insulating film 7, and the outer edge 8b of the land and the inner peripheral edge 14a of the opening of the insulating film 7. The NSMD structure portions (land outer edge central portion 8d) to be formed are provided at four locations on one land, and these are alternately formed along the land outer edge.

  According to the first embodiment, the lead-out wiring 10 from the land 8 is covered with the insulating film 7, and the contact interface between the insulating film 7 and the external joint terminal 9 made of a solder crosses in the width direction of the lead-out wiring 10. There is no such a position. As a result, it is possible to suppress the thermal stress generated in the lead-out wiring 10 by the opening / closing opening of the contact interface when the temperature changes. Further, by providing four NSMD structure portions and four SMD structure portions, the gap 16 can be reduced between the land outer edge 8b of the NSMD structure portion and the opening inner peripheral end 14a of the insulating film 7, and the land surface The joint area between 8a and the external joint terminal 9 can be increased. In the NSMD structure portion, since the external joining terminal material is joined not only to the land surface 8a but also to the side surface, the stress generated in the external joining terminal 9 is dispersed to the land surface 8a and the side surface. The effect of dispersing the generated stress can also be obtained by increasing the bonding area between the land surface 8a and the external bonding terminal material. As a result, it is possible to suppress an increase in the stress generated in the solder itself serving as the external joint terminal 9, and not only damage of the land lead-out wiring 10 but also of the semiconductor package (semiconductor device) due to damage of the external joint terminal itself. Reliability degradation can be prevented.

  In the first embodiment, the planar shape of the land 8 is a rectangle (rectangle), but it may be a polygonal shape such as a pentagon or a hexagon more than a rectangle. Also in this case, the opening shape of the insulating film 7 is circular, and the inner peripheral edge 14a of the opening portion of the insulating film 7 is in contact with the land surface 8a at the polygonal corners.

  In the direction in which the extraction wiring 10 extending from the land 8 is extracted, the entire extraction wiring 10 is covered with the insulating film 7, so that a stress suppressing effect can be obtained regardless of the direction. However, when the semiconductor element 1 is mounted on the central part of the semiconductor package (the part where the diagonal lines intersect in the rectangular plane) due to the temperature change, the stress generated in the external joint terminal part is the center of the semiconductor element 1 ( This occurs due to thermal deformation in the direction along the line connecting the diagonal lines on the rectangular plane) and the center of the external connection terminal 9. Therefore, in the external junction terminal portion, as shown in FIG. 4, high stress is generated in a portion 17 where the line C connecting the center of the semiconductor element 1 and the center of the external junction terminal portion intersects the land outer edge 8b. Therefore, as shown in FIG. 4, the effect of suppressing the wiring stress can be further enhanced by forming the lead-out wiring 10 in the portion 18 excluding the intersecting portion.

  Especially in semiconductor packages mounted on electronic devices such as engine control units and car navigation systems mounted on automobiles, the temperature change range of the environment used is wide, and the mounting board may be bonded to a metal casing. Further, the difference in coefficient of linear expansion from the semiconductor package is further enlarged. In such a state, even if the lead-out wiring 10 from the land 8 is covered with the insulating film 7, if the wiring is formed in a direction in which the stress increases, a relatively high stress may be generated in the wiring. Therefore, it is necessary to form the wiring direction in a direction where the stress is low.

  If the gap 16 of the NSMD structure portion where the gap 16 is formed between the land outer edge 8b and the opening inner peripheral edge 14a of the insulating film 7 becomes too large, the land surface 8a and an external joint terminal such as solder are formed. Therefore, the stress generated at the solder itself or at the interface between the solder and the land surface 8a increases. For this reason, the gap 16 is desirably set to a minimum interval for the molten solder to wet the land side surface 8e. Actually, since it is necessary to consider the alignment accuracy between the land 8 and the opening 14 of the insulating film, the land size and the insulation are set so that the widest part of the gap 16 (D in FIG. 4) is about 50 μm. Adjust the opening diameter of the membrane.

5 and 6 are diagrams related to a semiconductor package that is Embodiment 2 of the present invention.
FIG. 5 is a schematic bottom view of a semiconductor package,
FIG. 6 is a schematic plan view showing a state before the external junction terminal is joined to the land of the semiconductor package.
The second embodiment of the present invention will be described below with reference to FIGS.

  When the semiconductor element (1) is mounted on the central portion of the semiconductor package, the stress generated in the external joint terminal 9 due to the temperature change is the direction along the line C connecting the center of the semiconductor element and the center of the external joint terminal 9 This is caused by thermal deformation.

  Therefore, high stress is generated in the external deformation terminal portion in the heat deformation direction (direction of line C). A gap 16 is formed between the land outer edge portion 8b and the opening inner peripheral edge 14a of the insulating film 7 at least at one position 19 where the line C connecting the center of the semiconductor element and the center of the external junction terminal 9 and the land outer edge 8b intersect. In this portion (NSMD structure portion), since the solder is bonded not only to the land surface 8a but also to the land side surface 8e, the stress is distributed over a wide area between the land surface and the side surface. Damages such as cracks and cracks at the joint interface can be suppressed.

  As shown in FIG. 6, there are two positions 19 where the line C connecting the center of the semiconductor element and the center of the external junction terminal 9 and the land outer edge 8b intersect as shown in FIG. The NSMD structure portion provided at at least one of the intersection positions 19 is preferably formed at a position where the stress is increased at the external terminal joint, and the NSMD structure portion is formed by the positional relationship between the semiconductor element and the external joint terminal 9. To decide. As shown in FIG. 5, with respect to the plurality of external junction terminals 20 closest to the semiconductor element at the position intersecting with the outer edge 1a of the semiconductor element, inside the outer edge 1a of the semiconductor element, and outside the outer edge 1a of the semiconductor element, The NSMD structure portion is provided at a position opposite to the center of the semiconductor element. The external junction terminal group 21 located farthest from the outer edge portion of the semiconductor element has an NSMD structure portion at a position in the center direction of the semiconductor element. Note that the positions where the NSMD structure portions are formed relate to the joint portions of the external joint terminals on the semiconductor package side.

Example 3 of the present invention will be described with reference to the drawings.
In the above-described first and second embodiments of the present invention, the land shape is rectangular (quadrangle), and the SMD structure portion (land corner portion 8c) where the land surface 8a and the opening inner peripheral edge 14a of the insulating film 7 are in contact with the land outer edge. The NSMD structure portion (land outer edge central portion 8d) in which the gap 16 is formed between the end 8b and the opening inner peripheral end 14a of the insulating film 7 is provided at four locations on one external joint terminal portion. 7A and 7B are schematic plan views of the external junction terminal portion structure in which three SMD portions and three NSMD portions are provided. FIG. 7 ((a), (b)) is a planar structure before an external junction terminal is joined to a land.

  There are three land corners 8c, which are covered with the insulating film 7 and are SMD structure portions where the land surface and the inner peripheral edge 14a of the opening of the insulating film 7 are in contact with each other. The lead wiring 10 extending from the land 8 is formed at the corner 8c, and the lead wiring 10 is covered with an insulating film. At locations 22a and 22b sandwiched between the corners 8c of the land outer edge 8b, a gap 16 is formed between the land outer edge end 8b and the opening inner peripheral edge 14a of the insulating film 7, and this is an NSMD structure portion. Yes. One portion 22a of the portions 22 sandwiched between the corner portions 8c of the land outer edge 8b has an arc shape along the shape of the opening 14 of the circular insulating film 7, and the gap 16 is spaced apart from each other. Is not widened. The remaining two portions 22b surrounded by the corners 8c are formed into a straight line or a curved shape having a large curvature radius so that the gap 16 does not extend more than necessary.

  A gap 16 is formed between the SMD structure portion (land corner portion 8c) where the land surface 8a contacts the inner peripheral edge 14a of the opening of the insulating film 7, the land outer edge 8b, and the inner peripheral edge 14a of the opening of the insulating film 7. NSMD structure portions (land outer edge central portion 8d) are provided at three locations on one land, and these are alternately formed along the outer edge of the land.

  According to the third embodiment, the lead-out wiring 10 from the land 8 is covered with the insulating film 7 so that the contact interface between the insulating film 7 and the external joint terminal 9 made of a solder material crosses in the width direction of the wiring 10. It wo n’t be in the right position. As a result, the thermal stress generated in the lead wiring when the temperature changes can be suppressed. In addition, three NSMD structure portions and three SMD structure portions are provided, and the shape of the outer edge of the land is set so that the gap between the inner peripheral edge of the opening of the insulating film is not widened, and the bonding area between the land surface and the external bonding terminal is increased. it can. As a result, it is possible to suppress an increase in the stress generated in the solder itself used for the external joint terminal, and to prevent deterioration of the reliability of the semiconductor package due to damage to the external joint terminal itself as well as damage to the land lead wiring itself. Can do.

  As in the present embodiment, in the external joint terminal portion in which three NSMD structure portions and three SMD structure portions are formed, the range of the NSMD structure portion having a high effect of reducing stress generated in the solder itself can be widened. As a result, the effect of suppressing solder damage can be further obtained.

The stress generated in the external junction terminal due to the temperature change is caused by thermal deformation in a direction along the line C connecting the center of the semiconductor element and the center of the external junction terminal when the semiconductor element is mounted in the central portion of the semiconductor package. It occurs as a result.
The position 19 where the line C connecting the center of the semiconductor element and the center of the external joint terminal and the land outer edge 8b intersect is present at two locations in each external joint terminal portion, and high stress is generated in either one of them. The NSMD structure portion is desirably formed at a position where stress is increased at the external terminal joint portion, and the formation position of the NSMD structure portion at the external joint terminal portion is determined by the positional relationship between the semiconductor element and the external joint terminal. In the land shape shown in FIG. 7 ((a), (b)), the NSMD structure portion is formed in a wide range (long in the direction along the outer edge of the land). Since it is larger than the portion 22b, it is effective to form the 22a portion at a position where the stress becomes high.

  When the external junction terminal is located closest to the semiconductor element at a position intersecting with the outer edge 1a of the semiconductor element, inside the outer edge 1a of the semiconductor element, and outside of the outer edge 1a of the semiconductor element (20 in FIG. 5). 7), as shown in FIG. 7A, the NSMD structure portion is provided at a position opposite to the center direction of the semiconductor element (the direction of the arrow in the figure). Further, the external junction terminal group 21 located farthest from the outer edge of the semiconductor element has the NSMD structure portion at a position on the center direction (arrow direction in the figure) side of the semiconductor element as shown in FIG. 7B. Provide.

  FIG. 8 is a diagram showing another embodiment of the third embodiment shown in FIG. 7 ((a), (b)), and is a schematic plan view before joining an external junction terminal to a land.

  7 ((a), (b)) is that the formation range (length in the direction along the outer edge of the land) of the three NSMD structure portions 23 is substantially the same. The shape is an arc shape that follows the shape of the opening 14 of the circular insulating film 7. Also in the present embodiment, at least one portion of the NSMD structure portion 23 is formed on the side where the high stress is generated at the position where the line C connecting the center of the semiconductor element and the center of the external junction terminal and the land outer edge 8b intersect.

  The above-described semiconductor package according to the present invention is mounted on the mounting substrate 24 of various electronic control devices for portable devices and automobiles as shown in FIG.

  In the case of a temperature change, particularly a temperature drop, when the semiconductor package is mounted on the mounting substrate, the stress relaxation effect of the solder that is the external joint terminal is reduced, so that a large stress is generated in the external joint terminal portion. Usually, the linear expansion coefficient of the mounting board is larger than the apparent linear expansion coefficient of the semiconductor package. Therefore, the deformation of the mounting board causes a large tensile force in the direction opposite to the center of the semiconductor package at the junction of the external bonding terminal on the semiconductor package side. Stress (or plastic strain) is generated. The tensile stress generated in the external joint terminal portion is particularly large in the external joint terminal in the semiconductor element portion having a small linear expansion coefficient in the semiconductor package.

  In the semiconductor package in which the printed wiring board shown in the embodiments of the present invention is sealed with a sealing resin as an interposer, the linear expansion coefficient of the interposer is usually larger than that of the sealing resin. Accordingly, the semiconductor package itself is warped upward and convex due to a temperature drop. Although the central portion of the semiconductor package does not generate a large warp due to the restraint of the semiconductor element, the warp at the outer portion of the outer edge of the semiconductor element, particularly the outer edge portion of the semiconductor package, becomes large. In the external joint terminal portion on the package side of the outer edge portion of the semiconductor package, tensile stress is generated on the center direction side of the semiconductor package due to warpage deformation of the package.

BRIEF DESCRIPTION OF THE DRAWINGS It is a figure ((a) is typical sectional drawing, (b) is typical bottom view) which shows schematic structure of the semiconductor package (semiconductor device) which is Example 1 of this invention. The figure which shows the state before joining an external junction terminal to the land of the semiconductor package which is Example 1 of this invention ((a) is a typical top view, (b) is the model which follows the AA line of (a). (C) is typical sectional drawing which follows the BB line of (a). It is the typical sectional view which expanded a part of Drawing 1 (a). It is a typical top view which shows the state before joining an external junction terminal to the land of the semiconductor package which is a modification of Example 1 of this invention. It is a typical bottom view of the semiconductor package which is Example 2 of this invention. It is a typical top view which shows the state before joining an external junction terminal to the land of the semiconductor package which is Example 2 of this invention. It is a figure ((a) and (b) is a typical top view) which shows the state before joining an external junction terminal to the land of the semiconductor package which is Example 3 of this invention. It is a figure which shows the other aspect of Example 3, and is a schematic plan view which shows the state before joining an external junction terminal to a land. It is typical sectional drawing which shows the state which mounted the semiconductor package to which this invention was applied to the mounting board | substrate.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor element 2 ... Adhesive member 3 ... Conductive member 4 ... Sealing resin 5 ... Printed wiring board (interposer)
DESCRIPTION OF SYMBOLS 7 ... Insulating film 8 ... Land 9 ... External junction terminal 10 ... Lead wire 12 ... Electrode 13 ... Surface wiring 14 ... Insulating film opening 16 ... Gap 17, 19 ... Line which connects the center of a semiconductor element, and the center of an external junction terminal 24 where the outer edge of the land intersects the mounting board

Claims (5)

A semiconductor element;
A wiring board having a first surface and a second surface opposite to the first surface, wherein the semiconductor element is mounted on the first surface side;
A land provided on the second surface side of the wiring board;
A wiring extending from the land and provided on the second surface side of the wiring board;
An external junction terminal joined to the land;
An insulating film provided on the second surface side of the wiring board, the insulating film having an opening for joining the external junction terminal to the land;
Providing at least three portions where the inner peripheral edge of the opening of the insulating film and the land surface are in contact with each other and a portion where a gap is formed between the outer edge of the land and the inner peripheral edge of the opening of the insulating film;
The surface of the wiring extended from the said land is covered with the said insulating film, The semiconductor device characterized by the above-mentioned. The semiconductor device according to claim 1,
A portion where the inner peripheral edge of the opening of the insulating film is in contact with the land surface and a portion where a gap is formed between the outer edge of the land and the inner peripheral edge of the opening of the insulating film are along the outer edge of the land. A semiconductor device characterized by being formed alternately. A semiconductor element;
A wiring board having a first surface and a second surface opposite to the first surface, wherein the semiconductor element is mounted on the first surface side;
A land provided on the second surface side of the wiring board;
A wiring extending from the land and provided on the second surface side of the wiring board;
An external junction terminal joined to the land;
An insulating film provided on the second surface side of the wiring board, the insulating film having an opening for joining the external junction terminal to the land;
Providing at least three portions where the inner peripheral edge of the opening of the insulating film and the land surface are in contact with each other and a portion where a gap is formed between the outer edge of the land and the inner peripheral edge of the opening of the insulating film;
At least one of the locations where a gap is formed between the outer edge of the land and the inner peripheral edge of the opening of the insulating film is at a position that intersects a line connecting the center of the semiconductor element and the center of the opening of the insulating film. ,
A surface of a wiring extending from the land is covered with the insulating film. The semiconductor device according to claim 3.
A plurality of the lands are provided,
The plurality of lands include a first land at a position intersecting with an outer edge portion of the semiconductor element, a second land located inside the outer edge portion of the semiconductor element, and the semiconductor device outside the outer edge portion of the semiconductor element. A third land adjacent to the element;
In the land group including the first to third lands, a portion where a gap is formed between the outer edge of the land and the inner peripheral edge of the opening of the insulating film is in a direction opposite to the center of the semiconductor element. A semiconductor device, wherein the semiconductor device is located at a position that intersects a line connecting the center of the semiconductor element and the center of the opening of the insulating film. The semiconductor device according to claim 3.
The land group located farthest from the outer edge portion of the semiconductor element has a portion where a gap is formed between the outer edge portion of the land and the inner peripheral edge of the opening of the insulating film in the center side direction of the semiconductor element. A semiconductor device, wherein the semiconductor device is located at a position that intersects a line connecting the center of the semiconductor element and the center of the opening of the insulating film.

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