JP2007096036A - Set-up circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a step-up circuit which can be mounted in an LSI according to the standard CMOS process realizing the reduction of the layout area. <P>SOLUTION: The step-up circuit has several stages each composed of MOS transistors (M04, M14, M24, M34) and capacitors (C14, C24a, C24b, C34a, C34b, C34c), each connected at one end to either the drain or source of the MOS transistor; the MOS transistors are cascade-connected to connect the stages one to another. The gate and either the drain or source of the MOS transistor in each stage are electrically connected to each other, and the substrate of at least one set of adjacent MOS transistors is electrically connected to either drain or source of one of both. This restrains the back bias effect and reduces the layout area. The step-up capacitors in the latter stage may be composed of a plurality of series capacitors to restrain the voltage-withstanding level deterioration of each capacitor. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a booster circuit formed on a silicon substrate, and more particularly to a booster circuit that can be embedded in a standard CMOS process LSI.

  A Cockcroft-Walton type booster circuit that can be formed on a silicon substrate was published in a 1976 paper. This is because a driving MOS transistor having a drain and a gate connected to each other and a capacitor constitute a boosting cell at each stage, and the voltage at the previous stage is sequentially superimposed on the boosting cell at the next stage according to a two-phase clock signal. A desired voltage is obtained in the final booster cell (see Non-Patent Document 1).

  The Cockcroft-Walton type booster circuit has a problem that as the boosted potential increases, the influence of the back bias effect increases, the threshold voltage of the drive transistor increases, and therefore the boosting efficiency decreases.

  Therefore, according to a certain prior art, in order to reduce the influence of the back bias effect, the N-type well region for forming each driving PMOS transistor on the P-type silicon substrate is electrically separated from each other, and the substrate is formed at each stage. The potential is fixed to the source potential of each driving PMOS transistor (see Patent Document 1).

According to another conventional technique, a triple well structure is adopted on a P-type silicon substrate, and in order to reduce the influence of the back bias effect, the P-type well regions forming the driving NMOS transistors are electrically separated from each other, At each stage, the substrate potential is fixed to the drain potential of each driving NMOS transistor. A four-phase clock signal type booster circuit has also been introduced (see Patent Document 2).
JF Dickson, “On-Chip High-Voltage Generation in MNOS Integrated Circuits Using an Improved Voltage Multiplier Technique,” IEEE J. Solid-State Circuits, Vol. SC-11, No. 3, pp. 374-378, June 1976. JP 7-298607 A Japanese Patent Laid-Open No. 11-283392

  Now, in a nonvolatile semiconductor memory device such as a flash memory or an EEPROM, a voltage higher than the power supply voltage is required at the time of signal writing or erasing. In the case of a flash memory, a high withstand voltage transistor for high bias can be used in a dedicated process for the booster circuit. However, when a step-up circuit is mounted on an advanced standard CMOS process LSI, a dedicated high-voltage transistor cannot be used. Therefore, when the capacitor of the booster circuit is composed of one MOS transistor, a high voltage is applied between the gate and the substrate, and the breakdown voltage of the capacitor cannot be guaranteed due to time-dependent dielectric breakdown (TDDB). As a result, it is difficult to mount a step-up circuit on an advanced standard CMOS process LSI.

  Further, as described above, if the well regions forming the respective driving MOS transistors are electrically isolated from each other as a countermeasure against the back bias effect, an isolation layer is required between the respective stages, so that the layout area of the booster circuit is reduced. Problems such as an increase occur.

  According to the present invention, each stage includes a MOS transistor and a capacitor having one end connected to one of the drain or source of the MOS transistor, and the stages are connected by cascade connection of the MOS transistors. The gates of the MOS transistors in each stage and one of the drains or the sources are electrically connected to each other, and at least one set of adjacent MOS transistor substrates is electrically connected to the one of the drains or the sources. A booster circuit is provided.

  According to the booster circuit having the above-described configuration, the substrate of at least one pair of adjacent drive MOS transistors is electrically connected to one of the drain or the source thereof, so that the back bias effect is suppressed and the boosting efficiency is reduced. Can be suppressed. In addition, since the substrate of at least one pair of adjacent MOS transistors is common, the substrate isolation region can be reduced and the layout area can be reduced.

  Further, according to the present invention, the capacitors connected in series at each stage of the booster circuit can divide the voltage applied to both ends of each capacitor and suppress the deterioration of the breakdown voltage of the capacitor. A booster circuit can be mounted on a CMOS process LSI.

  According to the first and second aspects of the present invention, each stage includes a MOS transistor and a capacitor having one end connected to one of a drain or a source of the MOS transistor, and the MOS transistors are connected in cascade. Are connected to each other, and the gate of the MOS transistor and one of the drain or the source in each stage are electrically connected to each other, and at least one pair of adjacent MOS transistors is connected to one of the drain or the source. Boosting circuit characterized in that the back bias effect of the MOS transistor is mitigated, deterioration of the boosting efficiency is suppressed, and the layout area can be reduced. .

  The invention according to claim 3 is the booster circuit according to claim 1, wherein the MOS transistor is a PMOS transistor formed in an N-type well region, and the invention according to claim 4 is the MOS transistor 2. The boosting circuit according to claim 1, wherein the transistor is an NMOS transistor formed in a P-type well region, wherein the driving MOS transistor is formed on the well so that the substrate of the driving MOS transistor is adjacent. Therefore, the back bias effect of the MOS transistor can be relaxed, deterioration of the boosting efficiency can be suppressed, and the layout area can be reduced.

  The invention according to claim 5 is the booster circuit according to claim 1, wherein the capacitor of at least one stage is composed of a plurality of capacitors connected in series, and is applied to both ends of each capacitor. This has the effect of dividing the voltage and suppressing the deterioration of the breakdown voltage of the capacitor.

  According to a sixth aspect of the present invention, each stage includes a MOS transistor and a capacitor having one end connected to one of a drain or a source of the MOS transistor, and the capacitor of at least one stage is a plurality of capacitors connected in series. The voltage booster circuit is characterized in that the voltage applied to both ends of each capacitor is divided to suppress the deterioration of the breakdown voltage of the capacitor.

  The invention according to claim 7 is the booster circuit according to claim 6, wherein the capacitor is formed of an N-type depletion MOS transistor, and the invention according to claim 8 is the capacitor according to claim 8. 7. The booster circuit according to claim 6, wherein the booster circuit is constituted by a PMOS transistor, and since well separation is possible, a plurality of capacitors can be connected in series, and the breakdown voltage degradation of the capacitor can be suppressed. Have

  The invention according to claim 9 is characterized in that each stage is constituted by a MOS transistor manufactured by the same process as the MOS transistor forming the input / output circuit of the LSI. In addition, there is an effect of realizing a booster circuit that can be mixedly mounted on an LSI of an advanced standard CMOS process.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a circuit diagram showing a configuration of a booster circuit according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view showing the element structure of the booster circuit according to the first embodiment of the present invention. 1 to 4 are gates, 5 and 6 are N-type well regions, and 7 is a P-type silicon substrate. As shown in FIG. 2, a booster circuit is configured using a PMOS transistor formed on an N-type well region. This is a two-phase clock signal type booster circuit, which is composed of a capacitor Cp (C11, C21, C31) and a drive transistor M (M01, M11, M21, M31), and a clock signal CLKA for driving it and its CLKA The inverted clock signal CLKB obtained by inverting is applied to one end of the capacitor. Here, four drive transistors are shown as PMOS transistors (M01, M11, M21, M31) and capacitors (C11, C21, C31) are in three stages. Driving transistors M01, M11, M21, and M31 are connected in series, one end of a boosting capacitor Cp is connected to the diffusion layer between the transistors, and a clock signal is applied to the other end. The clock signal is applied in a combination of two phases CLKA and CLKB shown in FIG. The driving transistors (M01, M11, M21, M31) have a MOS configuration in which the drain and the gate are connected. In this booster circuit, in accordance with the clock signals CLKA and CLKB, the voltage of the previous stage is sequentially superimposed on the booster cell of the next stage and the desired voltage can be obtained in the booster cell of the final stage.

Next, the boosted voltage will be described. In FIG. 1, the threshold voltages of the drive transistors (M01, M11, M21, M31) are Vt0, Vt1, Vt2, and Vt3, respectively. The power supply voltage is VDD, and the voltage amplitude of the clock signal applied to the capacitor is VDD. When the step-up operation is started, the potential of (VDD−Vt0 + VDD) is at node V11, the potential of (VDD−Vt0 + VDD−Vt1 + VDD) is at node V21, and the potential of (VDD−Vt0 + VDD−Vt1 + VDD−Vt2 + VDD) is at node V31. Given, the boosted voltage VPP1 which is the drain potential of the final drive transistor M31 is:
VPP1 = (VDD−Vt0) + VDD × 3− (Vt1 + Vt2 + Vt3)
It is boosted to the potential of.

When the driving transistor has n stages, the boosted voltage VPP1, which is the drain potential of the n-th driving transistor, is
VPP1 = (VDD−Vt0) + VDD × n
− (Vt1 + Vt2 + Vt3 +... + Vtn)
It is boosted to the potential of.

  FIG. 6x shows a layout diagram of the booster circuit (when the capacitor is configured by an N-type depletion MOS (DMOS)) according to the conventional technique 2.

  FIG. 4 is a layout diagram in the case where the capacitor is formed of an N-type depletion MOS (DMOS) in the booster circuit of FIG. 1 according to the first embodiment of the present invention. Here, 11 is a well contact region for providing a well potential of a driving PMOS transistor, 12 is an N-type DMOS capacitor, and 13 is a driving PMOS transistor. In the booster circuit of the present invention, since the well contact regions of the driving PMOS transistors M01 and M11, M21 and M31 can be shared, the layout area can be reduced.

  As described above, in the booster circuit according to the first embodiment of the present invention, each stage includes a PMOS transistor and a capacitor having one end connected to one of the drain and the source of the PMOS transistor, and the PMOS transistors are connected in cascade. Each stage is connected to each other, and the gate and drain or source of the MOS transistor in each stage are electrically connected to each other, and at least one pair of adjacent PMOS transistor substrates is connected to the one drain. Alternatively, since it is electrically connected to one of the sources, the influence of the back bias effect can be reduced even when the boosted potential is increased, and an increase in the threshold voltage of the driving transistor can be suppressed. Accordingly, the boosting efficiency of the booster circuit of the present invention shown in FIG. 1 does not deteriorate. In addition, since the booster circuit can reduce the substrate isolation region (well isolation) by sharing the substrate of at least one pair of adjacent PMOS transistors, the layout area can be reduced.

  FIG. 5 is a circuit diagram showing a configuration of a booster circuit according to the second embodiment of the present invention. FIG. 6 is a sectional view showing the element structure of the booster circuit according to the second embodiment of the present invention. Here, 14, 15, 16, 17 are gates, 18, 20 are P-type well regions, 19, 21 are N-type well regions, and 22 is a P-type silicon substrate. As shown in FIG. 6, a booster circuit is configured using an NMOS transistor formed on a triple well (P-type well on an N-type well). In the booster circuit of the present invention, when an NMOS is used for the driving MOS transistors (M02, M12, M22, M32), a triple well process is required. This is a two-phase clock signal type booster circuit, which is composed of a capacitor Cp (C12, C22, C32) and a driving transistor M (M02, M12, M22, M32), and a clock signal CLKA and its CLKA for driving it. The inverted clock signal CLKB obtained by inverting is applied to one end of the capacitor. Here, a case is shown in which there are four drive transistors M02, M12, M22, and M32 and three stages of capacitors. Driving transistors (M02, M12, M22, M32) are connected in series, one end of a boosting capacitor Cp is connected to a diffusion layer between the transistors, and a clock signal is applied to the other end. As shown in FIG. 3, the clock signal is applied in a combination of two phases CLKA and CLKB. The drive transistors (M02, M12, M22, M32) have a MOS configuration in which the drain and the gate are connected.

  In this booster circuit, in accordance with the clock signals CLKA and CLKB, the voltage of the previous stage is sequentially superimposed on the booster cell of the next stage, and a desired voltage can be obtained in the nth booster cell.

  1 has the same configuration as the booster circuit according to the first embodiment, and each stage includes an NMOS transistor and a capacitor having one end connected to the source of the NMOS transistor, and the NMOS transistors (M02, M12, M22, Each stage is connected by cascading M32), and the gate of the NMOS transistor (M02, M12, M22, M32) and one of the drain or the source in each stage are electrically connected to each other. Since the substrate of at least one pair of adjacent NMOS transistors is electrically connected to one of the drain or source, the influence of the back bias effect is reduced even when the boosted potential is increased, and the driving NMOS transistor ( M02, M12, M22, M32) are prevented from increasing in threshold voltage. Can. Therefore, the boosting efficiency in the booster circuit according to the second embodiment of the present invention shown in FIG. 5 does not deteriorate. In addition, since this booster circuit can reduce the substrate isolation region by sharing the substrate of at least one pair of adjacent NMOS transistors (M02, M12, M22, M32), the layout area can be reduced. .

  FIG. 7 is a circuit diagram showing a configuration of the booster circuit according to the third embodiment of the present invention. Each stage comprises a PMOS transistor (M03, M13, M23, M33) and a capacitor having one end connected to one of the drain or source of the PMOS transistor (M03, M13, M23, M33). C13 is a booster circuit characterized in that one capacitor is connected in series with two capacitors C23a and C23b, and a capacitor in the third stage is connected in series with three capacitors C33a, C33b and C33c. is there.

  As described above, when the step-up operation is started, the potential of (VDD−Vt0 + VDD) is applied to the node V13, and the potential of (VDD−Vt0 + VDD−Vt1 + VDD) is applied to the node V23. A potential of (VDD−Vt0 + VDD−Vt1 + VDD−Vt2 + VDD) is applied to the node V33. Since the voltage at the subsequent node becomes higher, the first capacitor C13 is one here, the second capacitor is a series connection of two capacitors C23a and C23b, and the third capacitor is three capacitors C33a and C33b. , C33c connected in series can divide the voltage applied to both ends of each capacitor and suppress the withstand voltage of the capacitor. The number of capacitors connected in series at each stage is determined in consideration of the maximum voltage applied to the node of each stage, the TDDB characteristics of the capacitor, and the like. With the capacitor configuration as described above, it is possible to suppress the deterioration of the breakdown voltage of the capacitor and mount a booster circuit without an additional mask in the advanced CMOS standard process.

  FIG. 8 is a circuit diagram showing a configuration of the booster circuit according to the fourth embodiment of the present invention. The capacitors (C14, C24a, C24b, C34a, C34b, C34c) of this booster circuit are constituted by N-type DMOS capacitors, the first stage is an N-type DMOS capacitor C14, the second stage is N-type DMOS capacitors C24a and C24b, The third stage consists of N-type DMOS capacitors C34a, C34b and C34c. When an N-type DMOS capacitor is used as the capacitor, as shown in FIG. 8, the gate of the N-type DMOS capacitor is connected to V14, V24, V34 on the high voltage side, and the N-type well is connected to the low voltage side (CLKA, CLKB). By doing so, a stable channel inversion capacitance can be obtained.

  FIG. 9 is a cross-sectional view of an N-type DMOS capacitor used in the booster circuit according to Embodiment 4 of the present invention. 23 is a gate terminal of the N-type DMOS capacitor, 24 is an N-type well (diffusion layer) terminal of the N-type DMOS capacitor, 25 is an N-type well region, and 26 is a P-type silicon substrate.

  FIG. 10 is a layout diagram of the booster circuit according to the fourth embodiment of the present invention using an N-type DMOS capacitor. Here, 30 is a well contact region, 31 is a capacitor, and 32 is a driving MOS transistor. The value of the boost capacitor is 1 pF. In FIG. 8, C14 is 1 pF, C24a and C24b are 2 pF, and C34a, C34b, and C34c are 3 pF. In the booster circuit of the present invention shown in FIG. 8, since the wells of the driving PMOS transistors (M04, M14, M24, M34) are connected in common, the well isolation region can be reduced, so the layout area of the booster circuit Can be reduced.

  FIG. 11 is a circuit diagram showing a configuration of a booster circuit according to the fifth embodiment of the present invention. The capacitor of this booster circuit is composed of PMOS capacitors (C15, C25a, C25b, C35a, C35b, C35c). The first stage is the PMOS capacitor C15, the second stage is the PMOS capacitors C25a and C25b, and the third stage is the PMOS capacitor C35a. , C35b and C35c. When a PMOS capacitor is used as a boost capacitor, the PMOS capacitor gate is connected to the low voltage side (CLKA, CLKB) and the N-type well is connected to the high voltage side (V15, V25, V35) as shown in FIG. A stable channel inversion capacity can be obtained.

  In each of the above-described embodiments, if each stage is constituted by a MOS transistor manufactured by the same process as the MOS transistor forming the input / output circuit of the LSI, a booster circuit that can be embedded in the LSI of the advanced standard CMOS process can be realized. .

  The booster circuit according to the present invention is useful as a built-in booster circuit for a non-volatile memory in a standard CMOS process LSI.

It is a circuit diagram which shows the structure of the booster circuit in Embodiment 1 of this invention. It is sectional drawing which shows the element structure of the booster circuit in Embodiment 1 of this invention. It is a figure which shows the clock signal timing of the booster circuit in Embodiment 1 of this invention. 1 is a layout diagram of a booster circuit (N-type DMOS capacitor) in Embodiment 1 of the present invention. It is a circuit diagram which shows the structure of the booster circuit in Embodiment 2 of this invention. It is sectional drawing which shows the element structure of the booster circuit in Embodiment 2 of this invention. It is a circuit diagram which shows the structure of the booster circuit in Embodiment 3 of this invention. It is a circuit diagram which shows the structure of the booster circuit in Embodiment 4 of this invention. It is sectional drawing of the N type DMOS capacitor of the booster circuit in Embodiment 4 of this invention. FIG. 10 is a layout diagram of a booster circuit (N-type DMOS capacitor) in Embodiment 4 of the present invention. It is a circuit diagram which shows the structure of the booster circuit in Embodiment 5 of this invention.

Explanation of symbols

1, 2, 3, 4, 14, 15, 16, 17 Gate 5, 6, 19, 21, 25 N-type well region 7, 22, 26 P-type silicon substrate 11, 30 Well contact region 12, 31 Capacitor region 13 , 32 MOS transistors 18, 20 P-type well region 23 N-type DMOS capacitor gate terminal 24 N-type DMOS capacitor N-type well (diffusion layer) terminals C11, C21, C31 Capacitors C12, C22, C32 Capacitors C13, C23a, C23b C33a, C33b, C33c Capacitor C14, C24a, C24b, C34a, C34b, C34c Capacitor C15, C25a, C25b, C35a, C35b, C35c Capacitor CLKA, CLKB Clock signal M01, M11, M21, M31 Driving PMOS transistor M 02, M12, M22, M32 Drive NMOS transistors M03, M13, M23, M33 Drive PMOS transistors M04, M14, M24, M34 Drive PMOS transistors M05, M15, M25, M35 Drive PMOS transistors V11, V21, V31 Nodes V12, V22, V32 nodes V13, V23, V33 nodes V14, V24, V34 nodes V15, V25, V35 node VDD power supply voltage VPP1-VPP5 output voltage of the booster circuit

Claims (9)

Each stage consists of a MOS transistor and a capacitor having one end connected to one of the drain or source of the MOS transistor, and each stage is connected by cascading the MOS transistors,
In each stage, the gate of the MOS transistor and one of the drain or the source are electrically connected to each other, and the substrate of at least one pair of adjacent MOS transistors is electrically connected to one of the one drain or source. A booster circuit characterized by comprising: The booster circuit according to claim 1,
A booster circuit, wherein a pair of clock signals having opposite phases are input to the other end of the two successive capacitors. The booster circuit according to claim 1,
A booster circuit, wherein the MOS transistor is a PMOS transistor formed in an N-type well region. The booster circuit according to claim 1,
A booster circuit, wherein the MOS transistor is an NMOS transistor formed in a P-type well region. The booster circuit according to claim 1,
The booster circuit according to claim 1, wherein the capacitor of at least one stage includes a plurality of capacitors connected in series.   A step-up circuit characterized in that each stage includes a MOS transistor and a capacitor having one end connected to one of the drain and source of the MOS transistor, and at least one stage capacitor includes a plurality of capacitors connected in series. . The booster circuit according to claim 6, wherein
A booster circuit, wherein the capacitor is formed of an N-type depletion MOS transistor. The booster circuit according to claim 6, wherein
A booster circuit, wherein the capacitor comprises a PMOS transistor. The booster circuit according to claim 1 or 6,
A booster circuit characterized in that each stage is constituted by a MOS transistor manufactured by the same process as a MOS transistor forming an input / output circuit of an LSI.

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