JP2007066979A - Transistor and control method of depletion layer in transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a transistor capable of enhancement operation. <P>SOLUTION: The transistor comprises a channel layer formed above a predetermined substrate, a drain electrode layer formed above the channel layer, a source electrode layer, and a gate electrode layer. The gate electrode layer is so structured that it may include a p-type GaN semiconductor layer and a metal electrode layer formed on the semiconductor layer. By controlling the hole carrier concentration and the thickness of the p-type GaN semiconductor layer, a region of the depletion layer is controlled. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a GaN-based semiconductor (AlN, InN and mixed crystal thereof) transistor that is expected to be applied in the field of power electronics.

  In recent years, there has been a growing demand for semiconductor devices that can be used in harsh environments such as low loss, high speed, and high temperatures of power semiconductor devices in many fields, and Si-based semiconductor materials, SiC-based semiconductor materials, and GaAs-based semiconductor materials. In addition, research for device development has been actively conducted focusing on InP-based semiconductor materials and GaN-based semiconductor materials (AlN, InN and mixed crystals thereof). In Si-based semiconductor materials, efficiency of 90% or more is achieved at a frequency of 100 kHz band, and it is put into practical use. However, Si semiconductor materials are approaching their limits for further energy saving and higher speed in the future.

 On the other hand, it has been theoretically shown that the use of wide band gap semiconductors such as SiC-based semiconductor materials and GaN-based semiconductor materials instead of Si is effective in improving device performance in order to realize energy-saving devices. . For SiC-based semiconductor materials, transistors have already been realized by several research institutions. For example, in a transistor using a typical SiC-based semiconductor material, a buffer layer is epitaxially grown on a semi-insulating SiC substrate, and subsequently an n-type layer for a p-type conductive layer, a source electrode, and a drain electrode is grown. Thereafter, the portion where the gate electrode is formed is etched to the p-type conductive layer, the surface is oxidized to form a gate oxide film, and the source electrode, drain electrode, and gate electrode are formed. If the interface state between the oxide film and the p-type conductive layer is small, when a positive potential is applied to the gate electrode, an inversion layer in which electrons are accumulated is generated in the vicinity of the interface and operates as a semiconductor transistor (for example, FED Journal Vol. 11 (2000) p.85).

 However, the SiC-based semiconductor material has a problem that it is not easy to form an oxide film having a low interface state. In addition, there is a problem of crystal defects such as micropipes in the SiC substrate, and there are many problems to be solved for practical use in the future. In addition, SiC-based semiconductor materials also have a material problem that it is difficult to increase the speed in principle because a heterojunction is not used.

  In the development of a semiconductor transistor capable of operating at high speed, GaAs-based semiconductor materials, InP-based semiconductor materials, SiGe semiconductor materials, and GaN-based semiconductor materials are mainly studied. High-speed transistors have already been developed centering on GaAs-based semiconductor materials, InP-based semiconductor materials, and SiGe-based semiconductor materials, and GaAs-based transistors have already been put into practical use in communication fields such as mobile phones. However, GaAs-based semiconductor materials, InP-based semiconductor materials, and SiGe-based semiconductor materials have a problem that efficiency is lowered when the output is increased because the band gap is narrow. In addition, in a high temperature environment, electrons existing in the valence band are excited to the conduction band by heat, so that there is a problem that the transistor does not operate.

  In the future, as electronics technology advances, transistors that can be used in harsh conditions such as high output, high speed, and high temperature are desired. The most suitable semiconductor material is a wide band gap semiconductor, which has mobility. There are GaN-based semiconductors that are relatively expensive and can use heterojunctions. Research on this semiconductor has been extensively conducted on short-wavelength light-emitting elements typified by blue light-emitting elements, but in recent years, the characteristics of the wide-bandgap semiconductors and high-concentration 2 due to piezoelectric fields etc. Due to the availability of two-dimensional electron gas, it has been actively researched for application to mobile phone base stations, and a high-performance transistor with a transconductance of 525 mS / mm has also been reported (for example, applied physics). Vol.73 (2004) p.358).

FED Journal Vol.11 (2000) p.85 Applied Physics, Vol.73 (2004) p.358

  Although a transistor using a GaN-based semiconductor material has been reported to operate in a high-speed, high-power and high-temperature region, there still exists a serious problem. As a feature of the GaN-based semiconductor material, the group III nitride semiconductor is c-axis oriented. Therefore, when a heterojunction is used, a high density sheet carrier density can be obtained by a piezoelectric field. This high density sheet carrier density is believed to be advantageous for high power transistors.

A structure of a typical transistor using a GaN-based semiconductor is shown in FIG. A crystal growth of a low-temperature AlN buffer layer 102 at about 500 ° C. and an undoped semi-insulating GaN layer 103 at about 1000 ° C. are grown on the sapphire substrate 101 by an organic metal compound vapor deposition method or the like. Thereafter, an n-type AlGaN layer 105 having a free electron density of 1 × 10 ¹⁸ cm ⁻³ obtained by adding 2 nm of Si to the undoped AlGaN spacer layer 104 is grown to 8 nm, and a gate electrode 106, a drain electrode 107, and A source electrode 108 is formed.

  Next, typical characteristics of the GaN-based semiconductor transistor shown in FIG. 1 are shown in FIG. As shown in FIG. 2, the transistor operates as a depletion type in which a drain current flows when the gate voltage is set to 0 V and no drain current flows when a certain voltage is applied to the gate voltage.

  Next, FIG. 3 shows a band diagram immediately below the gate electrode 106 in the GaN-based semiconductor transistor shown in FIG. In the conduction band 301 in FIG. 3, a portion lower than the quasi-Fermi level 302 of electrons exists at the interface between the undoped semi-insulating GaN layer 304 and the AlGaN spacer layer 305, and this layer operates as a channel layer. Accordingly, when a voltage is applied between the drain electrode and the source electrode, a drain current flows even when the gate voltage is 0 V, and as described above, the GaN-based semiconductor transistor functions as a depletion type.

  On the other hand, a transistor using a GaN-based material can theoretically be operated as a high-power amplifier exceeding several hundred W at about 100 GHz, and is aimed at application to a mobile phone base station or the like. However, when used for power electronics, the fact that the drain current flows when no gate voltage is applied indicates that there is always a power loss, which increases the power loss. In the field of power electronics, in particular, enhancement type transistors are required. However, as described above, since the GaN-based semiconductor transistor functions as a depletion type, it has been considered unsuitable from the viewpoint of the power loss when used for power electronics.

  From this point of view, in recent years, by using a Schottky electrode with a high barrier height and by thinning the channel layer of carriers, it is possible to expand the depletion layer into the channel layer and thereby operate in an enhancement type. (For example, Japanese Jour [nA] l of Applied Physics, Vol. 43 (2004) p.2255), and the possibility of application to power electronics is also shown. However, the stability of Schottky electrodes made of GaN-based semiconductor materials, few electrode materials with high Schottky barriers, and the enhancement of thinning of the channel layer and enhancement of operation unless the channel layer is precisely controlled in units of several nanometers, etc. There are a number of problems such as difficulty in processing and difficulty in high-current operation because the channel layer cannot be structurally thickened.

  The present invention has been made in view of the above-described problems, and solves problems such as instability of the Schottky electrode, fluctuation of the barrier height, large current operation and high output, and a transistor capable of enhancement operation. It is for realizing.

In order to achieve the above object, the present invention provides:
A channel forming layer formed above a predetermined substrate; a drain electrode layer formed above the channel layer; a source electrode layer; and a gate electrode layer,
The gate electrode layer includes a p-type GaN-based semiconductor layer and a metal electrode layer formed on the semiconductor layer, and relates to a transistor.

The present invention also provides:
A depletion layer in the channel formation layer in a transistor comprising a channel formation layer formed above a predetermined substrate, a drain electrode layer formed above the channel layer, a source electrode layer, and a gate electrode layer Control method,
The gate electrode layer is configured to include a p-type GaN-based semiconductor layer and a metal electrode layer formed on the semiconductor layer, and the hole carrier density and thickness of the p-type GaN-based semiconductor layer are controlled. The present invention relates to a method for controlling a depletion layer in a transistor, wherein the region of the depletion layer is controlled.

  In the present invention, unlike the conventional GaN-based semiconductor transistor shown in FIG. 1, the gate electrode layer has a two-layer structure of a p-type GaN-based semiconductor layer and a metal electrode layer. Therefore, the p-type GaN-based semiconductor layer can form a depletion layer in the channel formation layer of the transistor, and the size of the depletion layer can be freely controlled by controlling its hole carrier density, thickness, etc. Will be able to control.

 Accordingly, by appropriately controlling the hole carrier density and thickness in the p-type GaN-based semiconductor layer, when the gate voltage in the gate electrode layer is 0 V, a voltage is generated between the drain electrode layer and the source electrode layer. Even if is applied, current can be prevented from flowing due to the presence of the depletion layer. As a result, it is possible to provide an enhancement type transistor that has been impossible with conventional GaN-based semiconductor transistors.

  Further, in the present invention, the conventional Schottky electrode described above is not used, and a complicated operation such as thinning the channel layer is not performed, and a p-type semiconductor layer is simply included in the gate electrode layer. The enhancement type transistor can be provided by operation.

  The “GaN-based semiconductor” in the present invention means that AlN and / or InN may be included in addition to GaN. As a general formula, GaxAlyInzN (x + y + z = 1, x, y, z ≧ 0) It means something that can be written. However, basically, GaN is mainly (main component).

  Hereinafter, other features and advantages of the present invention will be described in detail based on the best mode for carrying out the invention.

(Embodiment 1)
FIG. 4 is a cross-sectional view showing an example of a GaN-based semiconductor transistor of the present invention. A GaN-based semiconductor transistor 10 shown in FIG. 4 includes an AlN buffer layer 2, an undoped semi-insulating GaN layer 3, an undoped AlGaN spacer layer 4, and an n-type AlGaN layer 5 that are sequentially formed on a sapphire substrate 1. .

The AlN buffer layer 2 to the n-type AlGaN layer 5 can be formed by a metal organic compound vapor deposition method (MOCVD method). In this example, the AlN buffer layer 2 was formed at a low temperature of about 500 ° C., and the undoped semi-insulating GaN layer 3 to the n-type AlGaN layer 5 were formed at a temperature of about 1000 ° C. In this example, the thickness of the AlN buffer layer 2 is 0.02 μm, the thickness of the undoped semi-insulating GaN layer 3 is 2 μm, the thickness of the undoped AlGaN spacer layer 4 is 2 nm, and the n-type AlGaN layer 5 The thickness was 8 nm. The n-type AlGaN layer contains Si as a dopant at a concentration of 2 × 10 ¹⁸ / cm ³ .

  As described in detail below, in this example, the undoped semi-insulating GaN layer 3 and the undoped AlGaN spacer layer 4 function as channel forming layers.

Next, the GaN-based semiconductor transistor 10 has a gate electrode layer 7, a drain electrode layer 8, and a source electrode layer 9 on the n-type AlGaN layer 5. The gate electrode layer 7 is composed of a p-type GaN layer 7A and a Ni / Au electrode layer 7B according to the present invention. The drain electrode layer 8 and the source electrode layer 9 are composed of Ti / Al electrode layers. The thickness and hole carrier concentration in the p-type GaN layer 7A can be appropriately set according to the purpose. In this example, Mg is contained at a concentration of 3 × 10 ¹⁹ / cm ³ , The hole carrier density is 1 × 10 ¹⁸ / cm ³ and the thickness is 20 nm.

  From the gate electrode layer 7 to the source electrode layer 9, the multilayer structure in which the AlN buffer layer 2 to the p-type GaN layer 7A are formed on the sapphire substrate 1 is 5 at a temperature of about 700 ° C. in a nitrogen atmosphere. After performing heat treatment for a minute, a metal electrode layer 7B made of Ni / Au is formed using a photolithography technique, and a Ni mask is deposited thereon. Thereafter, the p-type GaN layer 7A is completely etched in the thickness direction by using, for example, a reactive ion etching apparatus using chlorine plasma, and the n-type AlGaN layer 5 is exposed. Thereafter, a drain electrode 8 and a source electrode 9 made of Ti / Al are formed on the exposed surface using a photolithography technique.

  FIG. 5 shows a band diagram immediately below the gate electrode layer 7 in a state where the gate voltage is not applied to the gate electrode layer 7 (gate voltage 0 V) of the GaN-based semiconductor transistor 10 shown in FIG. When attention is paid to the conduction band 11 in FIG. 5, there is no portion lower in energy than the quasi-Fermi level 12 of electrons. Therefore, even if a voltage is applied between the drain electrode layer 8 and the source electrode layer 9 in this state, no current flows.

  6 shows a band diagram immediately below the gate electrode layer 7 when a gate voltage of 2 V is applied to the gate electrode layer 7 of the GaN-based semiconductor transistor 10 shown in FIG. In this way, by applying a gate voltage of 2 V to the gate electrode layer 7, an electron pseudo-Fermi level 22 is formed at the interface between the undoped semi-insulating GaN layer 3 and the undoped AlGaN spacer layer 4 having different band gaps. The place where energy is lower than this is made, and this becomes a channel. Therefore, by applying a predetermined voltage between the drain electrode 8 and the source electrode 9, carriers can flow through the channel and current can flow.

  Thus, in the GaN-based semiconductor transistor 10 shown in this example, no current flows when a gate voltage is not applied to the gate electrode layer 7, and a current flows only when a gate voltage is applied to the gate electrode layer 7. Therefore, it can be made to function as an enhancement type instead of the conventional depletion type. This is because the gate electrode layer 7 includes the p-type GaN layer, so that a depletion layer having a sufficient extension is formed in the channel formation layer composed of the undoped semi-insulating GaN layer 3 and the undoped AlGaN spacer layer 4. This is because the band structure is bent as shown in FIGS.

  FIG. 7 is a characteristic diagram of the GaN-based semiconductor transistor 10 shown in FIG. At this time, the gate voltage to be applied to the gate electrode layer 7 is changed in the range of 0 to 2.4V. As can be seen from FIG. 7, when the gate voltage is 0V, the drain current hardly flows even when a voltage is applied between the drain electrode 8 and the source electrode 9, but the gate voltage is reduced from 0.6V to 2.4V. It can be seen that by sequentially increasing the voltage, a drain current corresponding to the magnitude of the gate voltage flows by applying a voltage between the drain electrode 8 and the source electrode 9. Therefore, it can be seen from the characteristic diagram shown in FIG. 7 that the GaN-based semiconductor transistor 10 shown in FIG. 4 functions as an enhancement type.

  Specifically, the leakage current when the gate voltage is 0 V can be reduced to 100 nA or less.

As described above, in order to make the GaN-based semiconductor transistor 10 shown in FIG. 4 function as an enhancement type, an optimum depletion layer is formed in the above-described channel formation layer by the p-type GaN layer 7A constituting the gate electrode layer 7. It needs to be possible. In the above specific example, the thickness of the p-type GaN layer 7A is 20 nm and the hole carrier density is 1 × 10 ¹⁸ / cm ³ , but the thickness and hole carrier density are specific to the GaN-based semiconductor transistor. It is necessary to set appropriately according to the material component and configuration.

In the GaN-based semiconductor transistor having the material components and configuration shown in FIG. 4, the thickness of the p-type GaN layer 7A is 1 nm to 500 nm, and the hole carrier density is 1 × 10 ¹⁶ pieces / cm ³ to 1 × 10. ^By setting the number to ¹⁹ / cm ³ , an enhancement type transistor can be realized.

  The n-type AlGaN layer 5 is not necessarily required and can be omitted as long as the object of the present invention is achieved. Similarly, the undoped AlGaN spacer layer need not be provided, but in the case where it is provided, the thickness is 200 nm or less.

Further, since the presence of the n-type AlGaN layer 5 also affects the formation of the depletion layer by the p-type GaN layer 7A described above, the thickness, the electron carrier density, etc. are GaN-based semiconductors including the p-type GaN layer 7A. It is necessary to determine the entire transistor 10 in consideration. Specifically, when the GaN-based semiconductor transistor 10 functions as an enhancement type, the electron carrier density is set to 1 × 10 ¹⁴ pieces / cm ³ to 1 by considering the above-described conditions regarding the p-type GaN layer 7A, for example. × 10 ¹⁹ pieces / cm ³ , and the thickness can be 1 nm to 200 nm.

  In the GaN-based semiconductor transistor 10 of this example, it is not necessary to use a Schottky electrode or make the channel layer thin, unlike a conventional transistor. Therefore, it is possible to increase the thickness of the undoped AlGaN spacer layer 4 and the n-type AlGaN layer 5 which are channel forming layers, and therefore, a large current operation can be easily performed.

(Embodiment 2)
FIG. 8 is a cross-sectional view showing another example of the GaN-based semiconductor transistor of the present invention. A GaN-based semiconductor transistor 30 shown in FIG. 8 includes an AlN buffer layer 32 and a first n-type GaN layer 33 that are sequentially formed on a sapphire substrate 31. The AlN buffer layer 32 and the n-type GaN layer 33 can be formed by a metal organic compound vapor deposition method (MOCVD method). In this example, the AlN buffer layer 32 was formed at a low temperature of about 500 ° C., and the n-type GaN layer 33 was formed at a temperature of about 1000 ° C. The thickness of the AlN buffer layer 2 was 0.02 μm, and the thickness of the n-type GaN layer 33 was 3 μm. The n-type GaN layer 33 contains Si as a dopant at a concentration of 5 × 10 ¹⁸ / cm ³ . SiH ₄ diluted with H ₂ was used as a raw material for the Si dopant.

The GaN-based semiconductor transistor 30 includes a ridge-type undoped GaN layer 34 and a second n-type GaN layer 35 on the n-type GaN layer 33. These layers can also be formed in the same manner as the n-type GaN layer 33. In this example, the second n-type GaN layer 35 is also made to contain Si so that its concentration becomes 5 × 10 ¹⁸ / cm ³ , as in the first n-type GaN layer 33. The undoped GaN layer 34 has a thickness of 0.5 μm, and the second n-type GaN layer 35 has a thickness of 1 μm. The undoped GaN layer 34 functions as a channel formation layer.

  Further, the GaN-based semiconductor transistor 30 has a first gate electrode layer 38-1 and a second gate electrode layer 38-2 so as to sandwich the undoped GaN layer 34 from both sides, and a second n-type GaN layer. 35 has a drain electrode layer 37 and a source electrode layer 39 on the right side of the second gate electrode layer 38-2. According to the present invention, the first gate electrode layer 38-1 and the second gate electrode layer 38-2 are respectively formed of p-type GaN layers 38-1A and 38-2A and Ni / Au electrode layers 38-1B and 38-. 2B. The drain electrode layer 37 and the source electrode layer 39 are composed of a Ti / Al electrode layer.

The thickness and the hole carrier concentration of the p-type GaN layers 38-1A and 38-2A can be appropriately set according to the purpose, but in this example, Mg has a concentration of 3 × 10 ¹⁹ / cm ³ . The hole carrier density is 1 × 10 ¹⁸ / cm ³ and the thickness is 1.2 μm.

The undoped GaN layer 34, the second n-type GaN layer 35, the gate electrode layers 38-1 and 38-2, the drain electrode layer 37, and the source electrode layer 39 are formed as follows. First, a stripe-shaped mask (for example, 2 μm in width) is formed using SiO ₂ or the like by photolithography, and the first n-type GaN layer is formed except for the lower portion of the mask using a reactive ion etching apparatus using Cl ₂ gas. Etch to 33. Thereafter, after performing an appropriate semiconductor substrate processing such as aqua regia, sulfuric acid, and organic cleaning, the p-type GaN layers 38-1A and 38-2A are formed again by an organic metal compound vapor phase growth method. Next, the mask is removed by etching with hydrofluoric acid and the like, and after heat treatment in a nitrogen atmosphere at a temperature of 700 ° C. for 5 minutes, the p-type GaN layers 38-1A and 38− are formed by photolithography and a reactive ion etching apparatus. A part of 2A is removed by etching, and the first n-type GaN layer 33 is exposed. Then, the metal electrode layers 38-1B and 38-2B in the gate electrode layers 38-1 and 38-2 are formed, and the drain electrode layer 38 and the source electrode layer 39 are formed.

  FIG. 9 is a characteristic diagram of the GaN-based semiconductor transistor 30 shown in FIG. In the GaN-based semiconductor transistor 30 shown in this example, the p-type GaN layers 38-1A and 38-2A in the first gate electrode layer 38-1 and the second gate electrode layer 38-2 are used as channel forming layers. A depletion layer is formed in an undoped GaN layer 34.

  Therefore, when the gate voltage applied to the first gate electrode layer 38-1 and the second gate electrode layer 38-2 is 0 V, even if a voltage is applied between the drain electrode layer 37 and the source electrode layer 39, In the undoped GaN layer 34, no drain current flows as shown in FIG. However, when a predetermined gate voltage is applied to the first gate electrode layer 38-1 and the second gate electrode layer 38-2, the region of the depletion layer changes, so that the region between the drain electrode layer 37 and the source electrode layer 39 is changed. When a voltage is applied to the drain, a drain current corresponding to the magnitude of the gate voltage flows in the undoped GaN layer 34. As a result, the GaN-based semiconductor transistor 30 in this example functions as an enhancement type.

  Specifically, the leakage current when the gate voltage is 0 V can be reduced to 100 nA or less.

As described above, in order for the GaN-based semiconductor transistor 30 shown in FIG. 8 to function as an enhancement type, the p-type GaN layers 38-1A and 38-2A constituting the gate electrode layers 38-1 and 38-2 are used as described above. It is necessary to be able to form an optimum depletion layer in the undoped GaN layer 34 which is the channel forming layer. In the above specific example, the p-type GaN layers 38-1A and 38-2A have a thickness of 1.2 μm and a hole carrier density of 1 × 10 ¹⁸ / cm ^3. It is necessary to set appropriately according to the specific material components and configuration of the GaN-based semiconductor transistor.

In the GaN-based semiconductor transistor having the material components and the configuration as shown in FIG. 8, the thicknesses of the p-type GaN layers 38-1A and 38-2A are 10 nm to 5 μm, and the hole carrier density is 1 × 10 ¹⁶ / By setting cm ³ to 1 × 10 ¹⁹ / cm ³ , an enhancement type transistor can be realized. Furthermore, it is realizable by making the width into 0.1 micrometer-20 micrometers.

  The second n-type GaN layer 35 is not necessarily required and can be omitted as long as the object of the present invention is achieved.

The presence of the n-type GaN layer 35 also affects the formation of the depletion layer by the p-type GaN layers 38-1A and 38-2A described above. It is necessary to determine in consideration of the entire GaN-based semiconductor transistor 30 including -1A and 38-2A. Specifically, when the GaN-based semiconductor transistor 30 is made to function as an enhancement type, for example, by considering the above-described conditions regarding the p-type GaN layer and the p-type GaN layers 38-1A and 38-2A, the electron carrier density is increased. The thickness can be 1 × 10 ¹⁴ pieces / cm ³ to 1 × 10 ¹⁹ pieces / cm ³ , and the thickness can be 1 nm to 200 nm.

  While the present invention has been described in detail based on the best mode for carrying out the invention with specific examples, various modifications and changes can be made without departing from the scope of the present invention.

For example, in the first and second embodiments, a sapphire substrate is used as the substrate, but other substrates such as a SiC substrate, a Si substrate, an AlN substrate, a GaN substrate, and a ZrB ₂ substrate can also be used.

  In the first and second embodiments, AlN and InN can be included in all layers made of only GaN. Further, Mg is used as the dopant for the p-type semiconductor and Si is used as the dopant for the n-type semiconductor, but naturally other dopants may be used.

  Further, in the first and second embodiments, the depletion type can be obtained by appropriately controlling the width and thickness of the p-type GaN layer.

  In the first embodiment, the n-type AlGaN layer 5 can be undoped, or can be formed by ion implantation instead of an actual layer form.

  Furthermore, in the second embodiment, after the sapphire substrate 31 is peeled off by the substrate peeling technique, the source electrode layer 39 is formed on the peeled surface, so that the growth direction of each layer constituting the transistor, that is, It is also possible to cause a current to flow in the thickness direction.

It is sectional drawing which shows an example of the conventional GaN-type semiconductor transistor. FIG. 2 is a characteristic diagram of the GaN-based semiconductor transistor shown in FIG. 1. It is a figure which shows the band structure of the GaN-type semiconductor transistor shown in FIG. It is sectional drawing which shows an example of the GaN-type semiconductor transistor of this invention. FIG. 5 is a diagram showing a band structure of the GaN-based semiconductor transistor shown in FIG. 4 in a state where a gate voltage is not applied to the gate electrode layer (gate voltage 0 V). FIG. 5 is a diagram showing a band structure of the GaN-based semiconductor transistor shown in FIG. 4 when a gate voltage of 2 V is applied to the gate electrode layer. FIG. 5 is a characteristic diagram of the GaN-based semiconductor transistor 10 shown in FIG. 4. It is sectional drawing which shows the other example of the GaN-type semiconductor transistor of this invention. FIG. 9 is a characteristic diagram of the GaN-based semiconductor transistor shown in FIG. 8.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Sapphire substrate 2 AlN buffer layer 3 Undoped semi-insulating GaN layer 4 Undoped AlGaN spacer layer 5 n-type AlGaN layer 7 gate electrode layer 7A p-type GaN layer 7B metal electrode layer 8 drain electrode layer 9 source electrode layer 10 GaN-based semiconductor transistor 11 Conduction band 12 Electron pseudo-Fermi level 13 Valence band 14 Hole pseudo-Fermi level 15 Undoped semi-insulating GaN layer 16 Undoped AlGaN spacer layer 17 n-type AlGaN layer 18 p-type GaN layer 21 conduction band 22 pseudo-electron Fermi level 23 Valence band 24 Hole pseudo-Fermi level 25 Undoped semi-insulating GaN layer 26 Undoped AlGaN spacer layer 27 n-type AlGaN layer 28 p-type GaN layer 30 GaN-based semiconductor transistor 31 Sapphire substrate 32 AlN buffer layer 33 First n GaN layer 34 Undoped GaN layer 35 Second n-type GaN layer 37 Drain electrode layer 38-1 First gate electrode layer 38-2 Second gate electrode layer 38-1A, 38-2A p-type GaN layer 38-1B , 38-2B Metal electrode layer 39 Source electrode layer 101 Sapphire substrate 102 AlN buffer layer 103 Undoped semi-insulating GaN layer 104 Undoped AlGaN spacer layer 105 N-type AlGaN layer 106 Gate electrode 107 Drain electrode 108 Source electrode 301 Conduction band 302 Electron band Pseudo Fermi level 303 Valence band 304 Undoped semi-insulating GaN layer 305 Undoped AlGaN spacer layer 306 n-type AlGaN layer

Claims (25)

A channel forming layer formed above a predetermined substrate; a drain electrode layer formed above the channel layer; a source electrode layer; and a gate electrode layer,
The transistor, wherein the gate electrode layer includes a p-type GaN-based semiconductor layer and a metal electrode layer formed on the semiconductor layer.   The transistor according to claim 1, wherein a depletion layer is formed in the channel formation layer by the gate electrode layer.   3. The transistor according to claim 2, wherein a region of the depletion layer is controlled by controlling a hole carrier density and a thickness of the p-type GaN-based semiconductor layer in the gate electrode layer. .   The channel forming layer is characterized in that at least two GaN-based semiconductor layers having different band gaps are adjacent to each other, and a channel is formed at an interface between the at least two GaN-based semiconductor layers. The transistor according to any one of the above.   The n-type GaN-based semiconductor layer is provided between the channel formation layer and the drain electrode layer, the source electrode layer, and the gate electrode layer, according to any one of claims 1 to 4. The transistor described.   The transistor according to claim 1, wherein the transistor functions as an enhancement type transistor.   The transistor according to claim 5, wherein the transistor functions as an enhancement type transistor. The hole carrier density in the p-type GaN-based semiconductor layer in the gate electrode layer is 1 × 10 ¹⁶ pieces / cm ³ to 1 × 10 ¹⁹ pieces / cm ³ , and the thickness is 1 nm to 500 nm. The transistor according to claim 6, characterized in that: The hole carrier density in the p-type GaN-based semiconductor layer in the gate electrode layer is 1 × 10 ¹⁶ pieces / cm ³ to 1 × 10 ¹⁹ pieces / cm ³ , and the thickness is 1 nm to 500 nm. 8. A transistor according to claim 7, characterized in that The electron carrier density in the n-type GaN-based semiconductor layer is 1 × 10 ¹⁴ / cm ³ to 1 × 10 ¹⁹ / cm ³ , and the thickness is 1 nm to 200 nm. Item 10. The transistor according to Item 7 or 9.   The leakage current when a voltage of 20 V is applied between the drain electrode layer and the source electrode layer in a state where the gate voltage in the gate electrode layer is 0 V is 100 nA or less. The transistor according to any one of the above. Wherein the substrate is a sapphire substrate, SiC substrate, Si substrate, AlN substrate, GaN substrate is selected from the group consisting of ZrB ₂ substrate, characterized in that it comprises at least one substrate, any one of claims 4 to 11 The transistor according to 1.   The gate electrode layer is composed of a first gate electrode layer and a second gate electrode layer, and the channel forming layer is located between the first gate electrode layer and the second gate electrode layer. The transistor according to claim 1, characterized in that:   The transistor according to claim 13, further comprising an n-type GaN-based semiconductor layer adjacent to the channel formation layer.   The transistor according to claim 13, wherein the transistor functions as an enhancement type transistor.   The transistor according to claim 14, wherein the transistor functions as an enhancement type transistor. The hole carrier density in the p-type GaN-based semiconductor layer in the gate electrode layer is 1 × 10 ¹⁶ / cm ³ to 1 × 10 ¹⁹ / cm ³ , and the thickness is 10 nm to 5 μm, The transistor according to claim 15, wherein the width is 0.1 μm to 20 μm. The hole carrier density in the p-type GaN-based semiconductor layer in the gate electrode layer is 1 × 10 ¹⁶ / cm ³ to 1 × 10 ¹⁹ / cm ³ , and the thickness is 10 nm to 5 μm, The transistor according to claim 16, wherein the width is 0.1 μm to 20 μm. The electron carrier density of the n-type GaN-based semiconductor layer is 1 × 10 ¹⁴ / cm ³ to 1 × 10 ¹⁹ / cm ³ , and the thickness thereof is 1 nm to 200 nm. The transistor according to 16 or 18.   20. The leakage current when a voltage of 20 V is applied between the drain electrode layer and the source electrode layer in a state where the gate voltage in the gate electrode layer is 0 V is 100 nA or less. The transistor according to any one of the above. Wherein the substrate is a sapphire substrate, SiC substrate, Si substrate, AlN substrate, GaN substrate is selected from the group consisting of ZrB ₂ substrate, characterized in that it comprises at least one substrate, any one of claims 15 to 20 The transistor according to 1. A depletion layer in the channel formation layer in a transistor comprising a channel formation layer formed above a predetermined substrate, a drain electrode layer formed above the channel layer, a source electrode layer, and a gate electrode layer Control method,
The gate electrode layer is configured to include a p-type GaN-based semiconductor layer and a metal electrode layer formed on the semiconductor layer, and the hole carrier density and thickness of the p-type GaN-based semiconductor layer are controlled. A method for controlling a depletion layer in a transistor, characterized in that a region of the depletion layer is controlled.   An n-type GaN-based semiconductor layer is provided between the channel formation layer, the drain electrode layer, the source electrode layer, and the gate electrode layer, and the electron carrier density and thickness in the n-type GaN-based semiconductor layer are set. 23. The method of controlling a depletion layer in a transistor according to claim 22, wherein the region of the depletion layer is controlled by controlling.   The gate electrode layer includes a first gate electrode layer and a second gate electrode layer, and the channel formation layer is located between the first gate electrode layer and the second gate electrode layer. The n-type GaN-based semiconductor layer is provided adjacent to the channel forming layer, and the electron carrier density and thickness in the n-type GaN-based semiconductor layer are controlled to control the region of the depletion layer. The method for controlling a depletion layer in a transistor according to claim 22.   The method for controlling a depletion layer in a transistor according to any one of claims 22 to 24, wherein the transistor functions as an enhancement type transistor.

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