JP2007059447A - Solid-state imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging apparatus capable of driving at high speed and acquiring a good image with brightness unevenness inhibited even with fine pixels, and its manufacturing method. <P>SOLUTION: A sidewall injection layer 40 which is an impurity ion injection region with a conductivity type reverse to a case where a PD9, an FD13, source-drain regions or the like of respective transistors are formed, a channel-stop layer 41 and a well 42 are formed inside a semiconductor substrate 2. The sidewall injection layer 40 is formed by injecting impurity ions inside from a surface of a groove 60 made in forming an element isolation part 44. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a solid-state image pickup device used in a device equipped with a MOS type or CCD type image sensor such as a digital camera or a digital video camera.

  FIG. 5 shows a configuration of a pixel area (light receiving area) 3 and a signal processing area 4 included in the solid-state imaging device 1. In the pixel region 3, pixel cells 5 including photodiodes are arranged in the row direction and the column direction. The signal processing area 4 is provided with a processing circuit for a signal read from the pixel cell 5 through the vertical signal line 7 and includes a noise canceling circuit 6. The image signal processed in the signal processing area 4 is output to the outside through the horizontal signal line 8.

  FIG. 6 shows an example of a specific circuit diagram of the pixel cell 5 and the noise cancellation circuit 6 shown in FIG. FIG. 7 shows an example of the layout of the pixel region 3. In brief, the pixel cell 5 includes a PD 9, a transfer gate 10, a floating diffusion (FD) 13, a reset transistor 14 having a reset gate 28, an amplification transistor 15 having an amplification gate 27, and a capacitor 12. ing. The noise cancellation circuit 6 includes an NCSH transistor 19, an NCCL transistor 21, a capacitor 20, a capacitor 22, and an HSROUT transistor 23.

  This solid-state imaging device is driven as shown in the timing chart of FIG. That is, before the image data reading operation, the reset transistor 14, the NCSH transistor 19, and the NCCL transistor 21 are controlled to be in an ON state (timing a). As a result, the potential of the FD 13 changes, and the potential when the reset transistor 14 is turned off (timing b) is ideally Ereset. Next, the NCCL transistor 21 is also turned off (timing c). When a voltage is applied to the transfer gate 10 in this state (timing de), photoelectrons obtained by photoelectric conversion at the PD 9 are transferred to the FD 13. At this time, the potential of the FD 13 drops to a magnitude corresponding to the amount of charge accumulated in the PD 9 and ideally becomes Esignal at the timing e. The potential of the FD 13 becomes the potential of the amplification gate 27. A voltage signal having a magnitude obtained by transforming the power supply voltage VDD in accordance with the magnitude of the gate voltage of the amplification transistor 15 appears on the vertical signal line 7.

  Here, the capacitor 12 is grounded via the semiconductor substrate 2, and the FD 13, the capacitor 12, and the semiconductor substrate 2 constitute an RC circuit. Therefore, under the influence of fluctuations in the gate voltages of the transfer gate 10 and the reset transistor 14, at the timings b and e, the potential of the FD 13 also decreases as indicated by the arrows until the potential of the FD 13 reaches a steady state. A certain time (RC circuit time constant τ) is required.

  The noise cancellation circuit 6 calculates and outputs a difference ΔV between Ereset and Esignal. After the reset transistor is turned off at the timing b, the difference ΔV is smaller than the ideal state if the potential of the FD 13 does not become the steady state Ereset even at the timing c. Therefore, the output image becomes darker than the case where it is not affected by switching the gate voltage of the reset transistor 14.

  Further, if Esignal becomes low at timing e, the difference ΔV becomes larger than the ideal state. Therefore, the output image becomes brighter than the case where it is not affected by switching the voltage applied to the transfer gate 10.

  Here, the time constant τ is proportional to the capacitance of the capacitor 12 and the resistance of the semiconductor substrate 2. Since the semiconductor substrate 2 is grounded outside the pixel region 3, when the capacitance of the capacitor 12 and the resistivity of the semiconductor substrate 2 are uniform, the resistance value at each position in the pixel region is the pixel region 3. It is proportional to the distance to the outside. Accordingly, when the image becomes darker, the image becomes darker toward the center of the pixel region 3, and when the image becomes brighter, the image becomes brighter toward the center of the pixel region 3. In such a case, concentric luminance unevenness (shading) occurs in the image (see Patent Document 1).

In order to suppress shading, it is sufficient to shorten the time constant. For that purpose, it is effective to lower the substrate resistance. 9 shows a cross-sectional view taken along the line ABC in the layout shown in FIG. Inside the p-type semiconductor substrate 2, a well 36 and a channel stop layer 35 formed by implanting p-type impurities are provided below an element isolation portion 33 of STI (Shallow trench isolation). If the impurity buried layer (well 36 and channel stop layer 35) is thus provided, the resistance of the semiconductor substrate 2 can be reduced. Note that if an impurity buried layer is provided in the region where the PD 9 and the FD 13 are formed, the basic characteristics of the solid-state imaging device such as the saturation charge amount that can be accumulated by one pixel are adversely affected. Cannot form an impurity buried layer.
Japanese Patent Application Laid-Open No. 2004-320592

  Recently, in order to improve the moving image shooting function, there is an increasing demand for a solid-state imaging device that can be driven at a higher speed. However, if the drive frequency is increased and the interval between the timings shown in FIG. 8 is shortened, unless the time constant τ is made smaller, the above-described luminance unevenness becomes remarkable and the image quality deteriorates. .

  In order to reduce the time constant τ, the resistance of the semiconductor substrate 2 should be further reduced. However, since the region in which the impurity buried layer can be formed is limited as the pixels are miniaturized, the resistance according to the above method is reduced. There was also a limit to the reduction of. More specifically, the resist pattern for forming the well 36 and the channel stop layer 35 is generally 1.2 μm or more so that impurity ions do not penetrate the resist and reach the semiconductor substrate 2. Thickness is said to be necessary. However, when the opening is formed by etching, the difference in the size of the opening between the resist surface and the bottom surface (the surface of the semiconductor substrate 2) becomes more noticeable as the resist thickness increases. It becomes difficult to form the opening. Therefore, when the pixel is miniaturized, a region where the impurity buried layer cannot be formed is generated.

  Therefore, an object of the present invention is to provide a solid-state imaging device that can be driven at high speed and can acquire a good image with reduced luminance unevenness even when the pixel is fine, and a method for manufacturing the same. .

  A solid-state image pickup device according to a first aspect of the present invention is a solid-state image pickup device in which pixels provided with photodiodes are arranged in a row direction and a column direction in an image region of a semiconductor substrate, on the surface of the semiconductor substrate. An active region including a photodiode formed by implanting first conductivity type impurity ions, an element isolation portion made of an insulating material filling a groove formed between adjacent active regions, and a second in the groove One or more layers formed by selectively implanting the second conductivity type impurity ions below the trench in the sidewall implantation layer formed by implanting the conductivity type impurity ions and the region between the adjacent active regions And a buried layer.

  The buried layer may be formed below the wider one of the region between the active regions adjacent in the row direction and the region between the active regions adjacent in the column direction.

  The buried layer is preferably formed in a region where the interval between adjacent active regions is 0.80 μm or more.

  A solid-state imaging device according to a second aspect of the present invention is a solid-state imaging device in which pixels provided with photodiodes are arranged in a row direction and a column direction in an image region of a semiconductor substrate, on a surface of the semiconductor substrate. Between the active region including the photodiode formed by implanting impurity ions of the first conductivity type and an adjacent active region, an element isolation portion formed by a LOCOS method and a second conductive layer below the element isolation portion. One or more impurity buried layers formed by implanting impurity ions of the type, and having a narrower distance between a region between active regions adjacent in the row direction and a region between active regions adjacent in the column direction The number of buried layers in is smaller than the number of buried layers in the wider interval.

  In the method for manufacturing a solid-state imaging device according to the first aspect of the present invention, pixels including photodiodes formed by implanting impurity ions of the first conductivity type in an image region of a semiconductor substrate are arranged in a row direction and a column direction. A method of manufacturing a solid-state imaging device, comprising: a step of forming a groove in a region of a surface of a semiconductor substrate other than a region where an active region including a photodiode is formed; and a second conductivity type in the groove The step of implanting impurity ions, the step of filling the trench with an insulating material to form an element isolation portion, and selecting the second conductivity type impurity ions below the trench in the region between adjacent active regions And forming a buried layer of one or more layers.

  In the method for manufacturing a solid-state imaging device according to the second aspect of the present invention, pixels including photodiodes formed by implanting impurity ions of the first conductivity type in an image region of a semiconductor substrate are arranged in a row direction and a column direction. A method for manufacturing a solid-state imaging device, comprising: a step of forming an element isolation portion by a LOCOS method in a region other than a region for forming an active region including a photodiode on a surface of a semiconductor substrate; A region between the active regions adjacent to each other in the row direction, by implanting impurity ions of the second conductivity type below the element isolation portion in a region between the regions and forming one or more buried layers And the number of impurity buried layers in the narrower one of the regions between the active regions adjacent in the column direction is smaller than the number of impurity buried layers in the wider one That.

  According to the solid-state imaging device according to the first aspect of the present invention, when forming the STI element isolation region, impurity ions are implanted into the trench to form the sidewall injection layer. Therefore, the resistance of the semiconductor substrate can be reduced even when the region where the impurity buried layer can be formed is limited with the miniaturization of the pixel. If the resistance of the semiconductor substrate can be reduced, the time (time constant τ) required to shift to a steady state when the potential of the FD changes from the ideal potential due to the influence of the gate voltage switching in the pixel is shortened. be able to. If the time constant τ is small, luminance unevenness of the image is suppressed even when the solid-state imaging device is driven at high speed, so that a good image can be obtained.

  Further, according to the solid-state imaging device according to the second aspect of the present invention, when the element isolation portion is formed by the LOCOS method, it is adjacent to the region between the active regions adjacent in the row direction and in the column direction. Of the regions between the active regions, the number of impurity buried layers in the narrower space is smaller than the number of impurity buried layers in the wider space. Thus, even when the total number of impurity buried layers is partially reduced, the resistance of the semiconductor substrate can be reduced as compared with the case where it is not formed at all.

(First embodiment)
FIG. 1 is a partial cross-sectional view of a pixel region of the solid-state imaging device according to the first embodiment of the present invention, and is a cross-sectional view taken along a line corresponding to a cross section taken along line ABC in FIG. This solid-state imaging device includes a side wall injection layer 40 that is not provided in a conventional solid-state imaging device. The side wall injection layer 40 contains impurities having a conductivity type opposite to that in the case where active regions such as the PD9, the FD13 and the source / drain regions of the transistor are formed from the surface of the groove 60 formed when the element isolation portion 44 is formed. It is formed by injecting. The sidewall injection layer 40 makes the resistance of the semiconductor substrate 2 smaller.

  A method for manufacturing the solid-state imaging device shown in FIG. 1 will be described with reference to FIGS. First, as shown in FIG. 2A, the surface of the silicon semiconductor substrate 2 is oxidized to form a silicon oxide film 30, and a silicon nitride film 31 is formed thereon. Then, a resist pattern 32 is formed on the silicon nitride film 31 using a photolithography technique. This resist pattern is a pattern having openings in regions other than PD9 and FD13 and the source-drain regions of other transistors included in the pixel.

  Next, dry etching is performed to remove portions of the silicon nitride film 31, the silicon oxide film 30, and the semiconductor substrate 2 exposed from the opening of the resist pattern 32. Then, the resist pattern 32 is removed. As a result, a groove (shallow trench) 60 is formed in a region other than the region to be the active region on the surface of the semiconductor substrate 2 (FIG. 2B). Here, the groove 60 is formed in a planar mesh shape.

Next, using the silicon nitride film 31 as a mask, p-type impurity ions such as B ⁺ ions are implanted into the exposed portion of the semiconductor substrate 2 with an implantation amount of 1 × 10 ¹³ cm ⁻² or more, and in the groove 60 of the semiconductor substrate 2. Then, a sidewall injection layer 40 having a thickness of 100 nm or more is formed (FIG. 2C). At this time, B ⁺ ions can be efficiently implanted into the trench 60 by implanting impurities from a direction inclined about 25 degrees from the axis (z-axis) perpendicular to the semiconductor substrate 2. Further, in order to uniformly inject B ⁺ ions into any wall surface, the semiconductor substrate 2 is rotated around the z axis by 90 degrees, for example, and the total implantation amount is divided into four at each position. An amount of B ⁺ ions should be implanted. Hereinafter, this method is referred to as a rotational injection method. The peak concentration of the sidewall injection layer 40 is preferably 1 × 10 ¹⁸ cm ⁻³ or more.

  Next, a silicon oxide film 43 is deposited by CVD or the like, and silicon dioxide is embedded in the trench 60 (FIG. 2D). Thereafter, a portion of the silicon oxide film 43 formed on the silicon nitride film 31 is removed and planarized to form the element isolation portion 44. Thereafter, the silicon nitride film 31 is also removed (FIG. 2E). The element isolation portion 44 may be made of a material other than the above as long as it is an insulating material.

Next, the PD 9, the FD 13, and the first element isolation region IR 1 are covered with a resist pattern 45. Here, a region sandwiched in a column direction by a rectangular region surrounding PD9 and FD13 is referred to as a first element isolation region IR1, and a region sandwiched in a row direction is referred to as a second element isolation region IR2. It is assumed that the width of the first element isolation region IR1 is as narrow as about 0.45 μm and the width of the second element isolation region IR2 is 0.80 μm or more. In this case, since a resist pattern having a desired opening cannot be formed in the first element isolation region IR1, the resist pattern 45 having an opening only in the second element isolation region IR2 is used. Then, under the conditions of an acceleration voltage of 300 keV and an implantation amount of 1 × 10 ¹³ cm ⁻² , p-type impurity ions such as B ⁺ ions are implanted using a rotational implantation method or the like, and a well 42 is formed in the second element isolation region IR2. Form. Subsequently, B ⁺ ions are implanted using a rotational implantation method or the like under the conditions of an acceleration voltage of 160 keV and an implantation amount of 6 × 10 ¹² cm ⁻² to form a channel stopper layer 41 above the well 42 (FIG. 2 ( f)). Thereafter, the resist pattern 45 is removed. The peak concentrations of the well 42 and the channel stopper layer 41 are both preferably 1 × 10 ¹⁷ cm ⁻³ or more.

  Thereafter, n-type impurity ions such as phosphorus are implanted to form PD9, FD13, source / drain regions of the reset transistor 14 and the amplification transistor 15, and further, a gate insulating film, a gate electrode, a wiring, and the like are formed.

  According to the method for manufacturing the solid-state imaging device according to the present embodiment, when forming the STI element isolation portion 44, impurity ions are implanted into the trench 60 to form the sidewall injection layer 40. Therefore, the resistance of the semiconductor substrate 2 can be reduced even when the region where the impurity ion buried layer (well 42 and channel stop layer 41) can be formed is limited as the pixel is miniaturized. If the resistance of the semiconductor substrate 2 can be reduced, when the potential of the FD 13 is changed by switching the voltage applied to the reset gate and the transfer gate, the time (time constant τ) until the transition to the steady state is shortened. Can do. If the time constant τ is small, luminance unevenness of the image is suppressed even when the solid-state imaging device is driven at high speed, so that a good image can be obtained.

(Second Embodiment)
FIG. 3 is a partial cross-sectional view of the pixel region of the solid-state imaging device according to the second embodiment of the present invention, and is a cross-sectional view taken along a line corresponding to the cross section taken along the line ABC in FIG. In this solid-state imaging device, the element separation unit 51 is formed of LOCOS. Only the channel stopper layer 52 is formed below the first element isolation region IR1, and the channel stopper layer 52 and the well 53 are formed below the second element isolation region IR2. That is, the number of impurity buried layers in the narrower one of the region between the adjacent regions in the row direction and the region adjacent in the column direction that surrounds the PD 9 and the FD 12 is the distance between It is smaller than the number of impurity buried layers in the wider one. Thus, even when the number of impurity buried layers is partially reduced, the resistance of the semiconductor substrate 2 can be reduced as compared with a case where the number of impurity buried layers is not formed at all.

  Below, the manufacturing method of the solid-state imaging device concerning this embodiment is explained. First, as shown in FIG. 4, the surface of the semiconductor substrate 2 is oxidized to form a silicon oxide film 30, and a silicon nitride film 31 is formed thereon. Then, a resist pattern 55 having an opening is formed in a region where the element isolation portion 51 is to be formed, and the silicon nitride film 31 exposed from the resist pattern 55 is removed by dry etching (FIG. 4A). Thereafter, the resist pattern 55 is also removed. Next, the semiconductor substrate 2 is thermally oxidized to form the element isolation portion 51 with the silicon oxide film 30, and then the silicon nitride film 31 is removed (FIG. 4B).

Next, the region for forming PD 9 and FD 13 and the first element isolation region IR 1 are covered with a resist pattern 56. Subsequently, B ⁺ ions are implanted under the conditions of an acceleration voltage of 300 keV and an implantation amount of 1 × 10 ¹³ cm ⁻² to form a well 53 (FIG. 4C). Thereafter, the resist pattern 56 is removed.

Next, a region for forming PD 9 and FD 13 is covered with a resist pattern 57. Subsequently, B ⁺ ions are implanted under the conditions of an acceleration voltage of 160 keV and an implantation amount of 6 × 10 ¹² cm ⁻² to form a channel stopper layer 52 (FIG. 4D). Thereafter, the resist pattern 57 is removed. Then, n-type impurity ions such as phosphorus are implanted to form active layers such as PD9, FD13, and source-drain regions of the transistor, and further, a gate insulating film, a gate electrode, a wiring, and the like are formed.

  The solid-state imaging device according to the present invention can be used as an imaging device including a MOS type or CCD type image sensor such as a digital camera for a mobile phone or a digital still camera.

Sectional drawing of the solid-state imaging device concerning the 1st Embodiment of this invention Manufacturing process diagram of the solid-state imaging device of FIG. Sectional drawing of the solid-state imaging device which concerns on the 2nd Embodiment of this invention. Manufacturing process diagram of the solid-state imaging device of FIG. Diagram showing the configuration of the solid-state imaging device Circuit diagram of pixel cell and noise cancellation circuit Control timing chart of each transistor Pixel area layout Sectional view of a conventional solid-state imaging device

Explanation of symbols

2 Semiconductor substrate 3 Pixel area 4 Signal processing area 5 Pixel cell 6 Noise cancel circuit 7 Vertical signal line 8 Horizontal signal line 9 PD
10 Transfer gate 12 Capacitor 13 FD
14 reset transistor 15 amplification transistor 16 RSCELL signal line 17 TRANS signal line 18 VDD signal line 19 NCSH transistor 20 capacitor 21 NCCL transistor 22 capacitor 23 HSROUT transistor 27 amplification gate 28 reset gate 30 silicon oxide film 31 silicon nitride film 32 resist pattern 33 element Separating part 34 Resist pattern 35 Channel stop layer 36 Well 51 Element separating part 52 Channel stopper layer 53 Well 55 Resist pattern 56 Resist pattern 57 Resist pattern 60 Groove

Claims (6)

A solid-state imaging device in which pixels having photodiodes are arranged in a row direction and a column direction in an image region of a semiconductor substrate,
An active region including the photodiode, formed by implanting first conductivity type impurity ions on the surface of the semiconductor substrate;
An element isolation portion of an insulating material filling a groove formed between the adjacent active regions;
A sidewall implantation layer formed by implanting impurity ions of the second conductivity type into the groove;
A solid-state imaging device comprising: one or more buried layers formed by selectively implanting impurity ions of the second conductivity type below the trench in a region between adjacent active regions.   The buried layer is formed below a wider one of a region between the active regions adjacent in the row direction and a region between the active regions adjacent in the column direction. Item 2. The solid-state imaging device according to Item 1.   The solid-state imaging device according to claim 2, wherein the buried layer is formed in a region in which an interval between adjacent active regions is 0.80 μm or more. A solid-state imaging device in which pixels having photodiodes are arranged in a row direction and a column direction in an image region of a semiconductor substrate,
An active region including the photodiode, formed by implanting first conductivity type impurity ions on the surface of the semiconductor substrate;
An element isolation portion formed by a LOCOS method between the adjacent active regions,
And one or more impurity buried layers formed by implanting impurity ions of the second conductivity type below the element isolation part,
Of the regions between the active regions adjacent in the row direction and the regions between the active regions adjacent in the column direction, the number of the buried layers in the narrower interval is the embedded layer in the wider interval A solid-state imaging device, wherein the number of layers is less than the number of layers. A method of manufacturing a solid-state imaging device in which pixels having photodiodes formed by implanting first conductivity type impurity ions are arranged in an image region of a semiconductor substrate in a row direction and a column direction,
Forming a groove in a region of the surface of the semiconductor substrate other than a region for forming an active region including the photodiode;
Implanting second conductivity type impurity ions into the trench;
Filling the groove with an insulating material to form an element isolation portion;
A step of selectively injecting impurity ions of the second conductivity type below the trench in a region between the adjacent active regions to form one or more buried layers. Manufacturing method. A method of manufacturing a solid-state imaging device in which pixels having photodiodes formed by implanting first conductivity type impurity ions are arranged in an image region of a semiconductor substrate in a row direction and a column direction,
Forming a device isolation portion by a LOCOS method in a region other than a region for forming an active region including the photodiode, on a surface of a semiconductor substrate;
A step of implanting impurity ions of the second conductivity type below the element isolation part in a region between the adjacent active regions to form one or more buried layers,
Of the regions between the active regions adjacent to each other in the row direction and the regions between the active regions adjacent to each other in the column direction, the number of the impurity buried layers in the narrower space is the impurity in the wider space. A method for manufacturing a solid-state imaging device, wherein the number is less than the number of buried layers.

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