JP2007049126A - Test method for detecting locality fault on semiconductor wafer and test system using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To disclose a test method for a wafer having a semiconductor chip, and its test system. <P>SOLUTION: The test method is used as a method for determining whether a wafer is a defective wafer or a non-defective wafer. The determination is based on filtered defective chips of spatially-related groups. The spatially-related groups correspond to the fault of locality on the wafer and are used for calculating a defect index value. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method and a system for testing a semiconductor chip on a wafer, and more particularly, a test method for identifying a local defect of a semiconductor chip on a wafer and a test system using the same. wafer and test system used therain).

  The main element of all semiconductor devices is an integrated circuit formed on a die of semiconductor material. The die is commonly referred to as a semiconductor “chip”. Many semiconductor chips are manufactured on a wafer. The wafer is made of a polished thin silicon material. On the other hand, the wafer can be made of other materials than silicon.

  The commerciality of semiconductor chip manufacturing is the most competitive, and the yield (ie, the percentage of semiconductor chips that actually operate out of the total number of semiconductor chips manufactured on the wafer) is important when considering commerciality. Become an element. An increase or decrease in yield is considered as the difference between profitability and failure. Thus, all aspects of semiconductor chip design, manufacturing and testing are focused on significantly increasing manufacturing yield.

  Furthermore, it is not easy to improve the yield of complicated semiconductor chips. Current semiconductor chips are manufactured on a wafer with different processes performed in a very complicated procedure. The processes performed by such a complicated procedure include various techniques such as a photographic process, an etching process, a diffusion process, an ion implantation process, and a thin film deposition process. In this way, very small components and regions are formed on the wafer using many processes. These components and areas have extremely narrow manufacturing process tolerances. In fact, as the degree of integration of semiconductor chips continues to increase over the last few decades, the manufacturing process and process margins are increasingly decreasing.

  Due to the complexity of the manufacturing process and the potential for errors in the corresponding processes, semiconductor chips must be tested precisely at many stages of the manufacturing process. Many such tests are performed on the semiconductor chip immediately after the semiconductor chip is fabricated on the wafer (ie, before the semiconductor chips are separated from the wafer). Such a test is generally called a “wafer level test”.

  When the semiconductor chip is packaged to separate from the wafer and form a completed semiconductor device, further testing proceeds. The package of the semiconductor device and the corresponding “package level test” are executed by a specific object, that is, a third company. That is, the semiconductor chip manufacturer may not directly participate in the semiconductor chip packaging process and its associated package level test. Ideally, all semiconductor chips delivered from the semiconductor manufacturer can be good chips. Therefore, the wafer level test can be said to be an important part in a series of manufacturing processes for producing extremely completed semiconductor devices.

  In addition, semiconductor chip manufacturers must understand wafer yield measurement and yield trends through the manufacturing process. It is common for first generation semiconductor chips to show yields lower than 70% -80%. Through precise testing, detailed analysis, and minute process changes, semiconductor chip vendors can expect a yield of 99% or more.

  An important analysis tool used by manufacturers to improve yield is the so-called “wafer map”. The wafer map allows a good chip (GC) to be identified from a defective chip (FC) by at least one type of electrical test performed on the semiconductor chip. 5, 11 and 12 are exemplary wafer maps discussed next.

  Manufacturing efficiency concerns are concentrated on systems where multiple wafers are processed in batch or lot units. Typically, wafer level testing is performed on a lot basis to sense and evaluate manufacturing process deviations that result in increased or decreased yields. If it is determined that each wafer in one lot has a defect (that is, it indicates a low yield that cannot be accommodated), a specific failure analysis is performed. Such specific failure analysis increases costs and consumes time, but is essential for improving yield. Thus, manufacturers try to apply limited quality control resources in an efficient manner for the most useful failure analysis.

  It is very important to determine defect criteria for wafers in a lot. In general, it is determined whether the wafer is a defective wafer by using the yield as a criterion. That is, according to the prior art, a semiconductor wafer showing a yield lower than the target yield can be regarded as a defective wafer. Accordingly, even when the first wafer among the wafers has a yield higher than a specific yield, the first wafer may have a localized failure chip. On the other hand, the second wafer among the measured wafers has a yield lower than the specific yield, but may have defective chips uniformly distributed over the entire wafer. In this case, it may be necessary to consider the first wafer as a defective wafer rather than the second wafer in order to improve the yield. This is because defects in the process related to the poor locality chip can directly affect the yield reduction.

  Meanwhile, the position of the defective chip can be provided by a wafer map. However, it is difficult to accurately determine whether or not the locally defective chip exists in the wafer using only the wafer map. This is because it is difficult to determine a criterion for determining the poor locality chip using only the wafer map.

  As a result, it can be said that there is a limit to efficient defect analysis in order to improve the yield in the above-described conventional technology.

  Further, in the prior art, the wafer map and yield data are provided after continuously measuring every chip on a series of wafers (eg, a plurality of wafers constituting one lot) using a wafer tester. This makes it impossible to perform defect analysis on each of the wafers in real time.

An apparatus and method for detecting a process defect in real time using an optical tool is disclosed in US Pat. No. 6,057,096 by Sommeh et al. Under the name “realtime defect source identification”. Has been. However, according to Sommek et al., It is difficult to determine defects in local processes that exist locally in the wafer.
US Pat. No. 6,763,130B1

  The technical problem to be solved by the present invention is to provide a test method capable of detecting a defective wafer having a local failure mode for efficient failure analysis.

  Another technical problem to be solved by the present invention is to provide a test system for detecting a defective wafer having a local failure mode for efficient failure analysis.

  Embodiments of the present invention provide improved defect analysis for classifying defective wafers from a large number of wafers within a lot where the manufacturing process has been completed. The failure analysis standard according to the embodiment of the present invention is not limited only to the target yield. Rather, embodiments of the invention can identify poor locality on the wafer. Furthermore, embodiments of the present invention provide defect information for each wafer rather than for each lot. As a result, it is possible to perform defect analysis on each wafer in one lot in real time.

  According to one embodiment of the present invention, a method for testing a wafer including semiconductor chips is provided. The wafer test method includes generating a wafer map indicating defective semiconductor chips on the wafer. A filtered wafer map indicating the defective semiconductor chips filtered from the wafer map is generated. A wafer defect index is calculated from the filtered wafer map. The wafer defect index is compared with an upper limit line.

  In one embodiment of the present invention, it is possible to determine whether the wafer is defective or non-defective based on a comparison result between the wafer defect index and the upper limit line. If is defective, the wafer can be analyzed for defects.

  In another embodiment, generating the wafer map includes generating test data by performing an electrical test on the semiconductor chip, and whether each of the semiconductor chips is a defective semiconductor chip based on the test data. Determining whether or not. Further, generating the wafer map can further include forming a data file from the test data. In this case, the wafer map can be formed from the data file. Further, generating the wafer map can further include generating a graphic file showing data identifiable by a monitor.

  In yet another embodiment, the filtered wafer map can be generated by applying a spatial filter having a predetermined size to the wafer map. The spatial filter may include “n × m” matrix cells, and each of the cells may have a weighting factor. The wafer map defines a layout matrix related to the arrangement of the semiconductor chips on the wafer. In this case, generating the filtered wafer map includes applying the spatial filter to each semiconductor chip using test data values associated with the semiconductor chips corresponding to the cells of the layout matrix, respectively. Can do. Applying the spatial filter to one semiconductor chip includes calculating a filtered value for the one semiconductor chip, and using the filtered value by the calculation as a reference filter value. And determining whether the one semiconductor chip is a filtered defective chip based on the comparison result. The filtered value is calculated by multiplying the weighting factor of the cell of the spatial filter by a test data value of the semiconductor chip corresponding to the cell, respectively, and a weighted multiplied value corresponding to the semiconductor chip. calculating product values), adding the weighted multiplication values to obtain a sum thereof, and dividing the weighted multiplication value sum by the size of the spatial filter. Each of the weighting factors may have a unit value, and each of the test data values may have a single bit binary data value. The reference filter value may be 0.5. Generating the filtered wafer map can further include generating a graphic file showing data that can be identified by a monitor.

  In yet another embodiment, calculating the wafer defect index value from the filtered wafer map defines at least one group comprised of the filtered defective semiconductor chips and having a unique value; The method may include calculating the wafer defect index value using the at least one group value. Calculating the wafer defect index value using the at least one group value includes calculating a square value of the group value and obtaining a square root of a sum of the square values; Dividing the square root by the total number of the semiconductor chips on the wafer may be included.

  In still another embodiment, the upper limit line can be determined using actual test data obtained by testing a semiconductor chip similar to the semiconductor chip on the wafer. The upper limit line may be determined using a statistical model or mathematical representation of the actual tester data.

  According to another aspect of the invention, a method for determining whether a wafer is defective includes defining at least one spatial group composed of filtered defective semiconductor chips on the wafer. A wafer defect index value is calculated for the at least one spatial group, and the defect index value of the wafer is compared with an upper limit line.

  In one embodiment of the present invention, defining the at least one spatial group includes generating a wafer map from test data for displaying defective semiconductor chips on the wafer, and applying a spatial filter to the wafer map. Generating a filtered wafer map and grouping the filtered defective semiconductor chips on the filtered wafer map into at least one group. The wafer test method can be sequentially applied to each wafer in a lot, and the wafer test method further includes generating a graphic file from the wafer map and the filtered wafer map. it can. Each graphic file can display the test data of each wafer in real time on a monitor while testing the wafers in the one lot. Generating the wafer map includes generating an electrical test on the semiconductor chip to generate the test data, generating a data file from the test data, and generating the wafer map from the data file. And determining whether each of the semiconductor chips is a defective semiconductor chip based on the test data.

  In another embodiment, the wafer is analyzed as defective when it is determined that the wafer is defective based on a comparison result between the wafer defect index value and the upper limit line.

  In still another embodiment, the spatial filter may include cells constituting a matrix of “n × m” type, and each of the cells may have a weighting coefficient. The wafer map defines a layout matrix relating to the arrangement of the semiconductor chips on the wafer, and generating the filtered wafer map relates to the semiconductor chips corresponding to the cells of the layout matrix, respectively. Applying the spatial filter to each semiconductor chip using a test data value may be included.

  In yet another embodiment, applying the spatial filter to one semiconductor chip includes calculating a filtered value for the one semiconductor chip and comparing the filtered value of the calculation to a reference filter value. And determining whether the one semiconductor chip is a filtered defective chip based on the comparison result. The filtering value is calculated by multiplying the weighting factor of the cell of the spatial filter by the test data value of the semiconductor chip corresponding to the cell, and multiplying the weighted multiplication value corresponding to the semiconductor chip, respectively. Calculating, adding the weighted multiplication values to obtain a sum of these, and dividing the weighted multiplication value sum by the size of the spatial filter. Each of the weighting factors may have a unit value, and each of the test data values may have a single bit binary data value. The reference filter value may be 0.5.

  In still another embodiment, the upper limit line can be determined using actual test data obtained by testing a semiconductor chip similar to the semiconductor chip on the wafer. The upper limit line may be determined using a statistical model or mathematical representation of the actual tester data.

  According to yet another aspect of the invention, a test system for testing a wafer is provided. The test system includes a wafer tester that performs an electrical test on a semiconductor chip formed on the wafer and generates test data corresponding to the electrical test, and a controller that stores the test data in a database as a data file. . The controller causes at least one software module to execute with the database. The at least one software module generates a wafer map that displays defective semiconductor chips among the semiconductor chips from the test data, and generates a filtered wafer map that displays defective semiconductor chips filtered from the wafer map. Generating, limiting at least one spatial group comprised of the filtered defective semiconductor chips, calculating a wafer defect index value for the at least one spatial group, and the wafer defect At least one of comparing the exponent value with the upper limit line is performed.

  In one embodiment of the present invention, a monitor operated by the controller may be further included. The monitor can display the wafer map and the filtered wafer map in real time and in the form of a graph. The monitor may further include a function of displaying whether the wafer is defective based on a comparison result between the wafer defect index value and the upper limit line.

  In another embodiment, the wafer tester may include a plurality of wafer testers. Each of the plurality of wafer testers can measure different electrical test items for the wafer.

  In yet another embodiment, the at least one software module can be stored in the database. The at least one software module may be operated by an operating system executed by the controller.

  In yet another embodiment, the controller can execute automated test instructions to run the at least one software without intervention of an operator of the test system.

  According to the present invention, the defect index of a wafer is calculated using a spatial filter without depending on the yield of the wafer. Therefore, the locality failure mode in the wafer can be detected efficiently. In addition, the wafer defect index is calculated every time the electrical measurement of each wafer is completed by the wafer tester. Therefore, failure analysis can be performed on all wafers in real time.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein, and may be embodied in other forms. Rather, the embodiments introduced herein are provided to demonstrate that the disclosed invention has been completed and to fully convey the spirit of the invention to those skilled in the art.

  The first embodiment of the present invention will be described in connection with the process flowchart shown in FIGS. 1A and 1B. The process flow chart illustrates an exemplary method for testing wafers in a lot that overcomes the disadvantages associated with conventional test methods. In particular, the method provides for detecting locality defects on individual wafers and performing defect analysis on each of the wafers in real time.

  Referring to FIG. 1A, the method according to the present embodiment begins by selecting a product type to be tested (step 31). The product type corresponds to at least one specific semiconductor chip design. Many other types and / or versions of semiconductor chips can be manufactured using common manufacturing equipment. The step (31) of selecting the product type can retrieve from the memory a series of test items related to the selected product type using an automated test apparatus. The automated test controller can then turn on and / or configure the test equipment according to the series of test items. On the other hand, the step (31) of selecting the product type can provide a series of commands to an operator who has to perform a test on a specific wafer on the wafer test apparatus. Here, the “specific wafer” is a term used to distinguish a wafer from which test data is obtained or a wafer to be tested from other wafers in a single lot.

  After selecting the product type to be tested, a spatial filter is defined (step 33). The spatial filter may provide a geometric pattern or a mathematical relationship that links semiconductor chips according to their relative positions on the specific wafer. The spatial filter can have many other forms. However, the example shown in FIG. 2 presents a two-dimensional (eg, row and column) matrix-like spatial filter. Choosing a two-dimensional matrix is convenient because individual semiconductor chips are manufactured so that they can be two-dimensionally arranged on the wafer according to rows and columns.

  If a two-dimensional matrix is provided as a spatial filter, the spatial filter can be shown to include “n” rows and “m” columns. Thus, the size of the spatial filter can be expressed as a multiplication of the row and column. For example, the predictive spatial filter (SF) shown in FIG. 2 includes three rows and three columns, and has a size corresponding to “9”. Further, each cell in the matrix (i.e., each row and column intersection, or C1-C9 in FIG. 2) can be assigned a weighting coefficient. The weighting factor limits the weighting value of the spatial filter.

  In one embodiment, limiting the spatial filter 33 includes limiting the size and weight of the spatial filter. As will be described later, the spatial filter appropriately limited by the size and the weighting value serves as a weighting filter (that is, a low-pass spatial filter). However, the size and weight of the spatial filter can vary depending on the type of product being tested and the failure mode distinguished with respect to the wafer. In particular, the magnitude (minimum and / or maximum) of locality defects distinguished by the test method can be determined by the definition of the spatial filter.

  When considering the type of product and the failure mode to be identified, a spatial filter with the appropriate size and weight is associated with empirical data obtained from past test results run on similar semiconductor chips. Can be defined. The weighting factor of each cell constituting the spatial filter and the size of the spatial filter can affect the clarity of the test method in relation to potential locality defects.

  Once the spatial filter is defined, the test method according to the present invention determines an upper limit line UCL for the target defect index value DI. The defect index value is a value calculated from test data obtained from an electrical / functional test of the wafer (see step 47). The upper limit line UCL is a reference for determining whether the specific wafer is a defective wafer or a non-defective wafer. When the defect index value DI calculated for the specific wafer is larger than the set upper limit line UCL, the specific wafer corresponds to a wafer to be analyzed for defects. In general, the upper limit line UCL for a wafer increases with continuous production of semiconductor elements formed on the wafer. That is, to predict a higher yield, the upper limit line UCL must be increased.

  A specific wafer is selected and tested with the defined spatial filter and the set upper limit line (step 35). The selection of the specific wafer can be automatically performed from one wafer lot using a bin number or an identification label associated with the specific wafer. After such wafer selection, the specific wafer is tested (step 37).

  The specific wafer can be measured using at least one electrical and / or functional test program. For example, a direct current test (DC test) such as an open / short test of a circuit is performed. In addition or separately, an AC test (AC test) is performed. The AC test may include a specific function, a multi test, and / or a checker board test. Each semiconductor chip is a good chip that exhibits an acceptable value within the range determined for one test item during a series of electrical tests, while it is determined for the other test item. It can correspond to a defective chip that goes out of range. The results for each electrical test performed on a wafer can be stored in memory (ie, a database) for each semiconductor chip on the wafer. Such storage of test results is important because many wafers in a lot are best measured on one wafer tester before being moved to another test station and measured by another wafer tester. That is, the test data includes a wafer identification number and a test bin number (bin number) for each wafer among a large number of wafers in one lot, and for each test item among a series of test items performed on a specific wafer. ) Must be sorted out.

  Test data can be recorded in at least one data file associated with a particular wafer (step 39). The test data is used to classify each semiconductor chip as a good chip or a defective chip for each test item or an accumulated test item in relation to a test determination criterion. Once the test data is stored in the data file, a wafer map is generated (step 41).

  “Wafer map” is a term that refers to a spatial graph that represents not only the quality (ie, good or defective) of semiconductor chips on a specific wafer, but also the data associated therewith. Therefore, the wafer map can be a graph data file that can be confirmed by the operator with the naked eye. On the other hand, a wafer map can mean data stored in a data file that simply sets the quality for a semiconductor chip on a specific wafer. In addition, the expression “applying a spatial filter to a wafer map” includes at least one step in which a weighting factor included in the spatial filter is mathematically applied to data on which the wafer map is based.

  A portion of an exemplary wafer map WM is shown in FIG. The wafer map is expressed as a square shape, that is, as a two-dimensional planar matrix 60 composed of first to sixth rows and first to fifth columns. Individual semiconductor chips are formed in each of the cells C11 to C65 defined by the planar matrix 60. The planar matrix 60 also defines virtual chips (virtual chips; for example, non-operating chip regions formed in the edge of the wafer occupying the cells C11, C12, C21, C31). The reason why the virtual chip is described is that the planar matrix is a square while the corresponding wafer is a circle. Referring to FIG. 3, in the matrix 60, a good chip is displayed as a test data value “1”, and a defective chip (a chip indicated by hatching) is displayed as a test data value “0”.

  As described above, the wafer map can be generated based on a macro-test or one specific test item (step 41). In a wafer map generated based on a macro test, a good chip means a semiconductor chip that satisfies all acceptance criteria for a series of test items, and a failed chip indicates a series of test items. Of these, it means a semiconductor chip that deviates from the acceptance criteria for at least one test item. However, the notation for good and bad chips can be displayed on a wafer map for one specific test item or a wafer map for a series of test items.

  The above-described wafer map is converted into a filtered wafer map FWM (step 43). For example, the wafer map WM shown in FIG. 3 can be converted into the filtered wafer map FWM of FIG. 4 using the spatial filter SF described with reference to FIG.

  The filtered wafer map is generated by applying a spatial filter defined on the wafer map. In one embodiment, applying a spatial filter to the wafer map can be accomplished by multiplying a weighting factor in the spatial filter matrix by one-to-one with test data values associated with semiconductor chips in the layout matrix. That is, in one embodiment of the present invention, the semiconductor chips are arranged on the wafer by the layout matrix 60. The layout matrix 60 may have appropriate limitations (e.g., geometrical form or mathematical relevance) that spatially correspond to the semiconductor chips on the wafer. A spatial filter having a predetermined size and weight can be defined on the side of the layout matrix 60 so that it can be applied on the layout matrix 60 in units of chips.

  As an example, a 3 × 3 spatial filter having nine cells and having a weighting factor “1.0” assigned to each cell is assumed. Subsequently, the spatial filter is sequentially applied to each cell of the layout matrix including the first cell (ie, cell C11) of the layout matrix 60. During application of the spatial filter, a number of cells adjacent to a particular cell are placed on the wafer map by the spatial filter. The weight value of the cell and the test data value of the semiconductor chip corresponding to the cell are applied to a mathematical formula for determining the filtered value P for the specific cell. The test data value for each of the semiconductor chips is obtained from the test result of the semiconductor chip. As an example, “1” and “0” are used as exemplary test data values to display good and bad chips.

  An exemplary spatial matrix for cell C43 in the layout matrix of FIG. 3 may include cells C32, C33, C34, C42, C43, C44, C52, C53, and C54. The test data value associated with the semiconductor chip identified on the wafer by the layout matrix is multiplied by the weighting factor of the cell of the spatial filter corresponding to the semiconductor chip, and the result of such multiplication is filtered for the cell C43. The value (filtered value) P is calculated.

  The filtered value P for each cell in the layout matrix can be calculated using various mathematical formulas. For example, in calculating the filtered value P, the following Equation 1 is used.

  Here, “j” is the position of each cell in the layout matrix defined by the spatial filter matrix, and “S” is a test data value (for example, “1” associated with the semiconductor chip corresponding to the cell in the layout matrix). "W" is a weighting factor assigned to the cell of the spatial filter matrix corresponding to the semiconductor chip. “M” and “n” are the number of rows and columns of the spatial filter matrix, respectively.

  Assuming that the spatial filter applied to the cell C43 in the layout matrix shown in FIG. 3 has a 3 × 3 configuration and the weighting factor W of the spatial filter has a unit value of “1.0”, The filtered value P of cell C43 is 0.33. When a reference filtered value Pref for determining whether a filtered chip is defective or not is determined as 0.5, the cell C43 has a defective chip filtered in the filtered wafer map of FIG. classified as filtered failed chip). The above-described procedure is an example of a calculation method employed for determining whether or not a defect is present for any actual semiconductor chip related to the partial layout matrix shown in FIG.

  Employing 0.5 as the reference filter value Pref is an example, and the reference filter value Pref may have a value other than 0.5 when the desired filtering effect is different.

  In the above example, if the spatial filter is applied to cell C22, the spatial filter may be placed on several virtual chips (ie, C11, C12, C21 and C31). In this regard, these virtual chips can be assumed by having data values corresponding to good chips to calculate the filtered values for cell C22.

  FIGS. 5A and 5B show a comparison of a filtered wafer map 71 generated from the wafer map 70 using a test method similar to the above example. A large number of defective chips FC distributed in the wafer map 70 are filtered through a spatial filter having an appropriate weight value, so that the wafer map 70 on a specific wafer is very different from the distribution of the defective chips FC. It is converted into a filtered wafer map 71 consisting of filtered defective chips FFC in various crowd forms showing different distributions. These filtered clusters of defective chips FFC can exhibit at least one locality defect in connection with the process applied to the specific wafer.

  Referring again to the flow chart of FIG. 1A, after the filtered wafer map 71 is generated in step 45, grouping of the filtered defective chips FFC in the filtered wafer map 71 proceeds (see FIG. 1A). Step 45). The grouping may correspond to a calculation related to visual mapping and / or a calculation related to data processing performed with or without a test system worker.

  FIG. 6 further illustrates the filtered defective chip of FIG. 5B, showing four different groups of the filtered defective chips. Each of the groups has a size. That is, the first and fourth groups G1 and G4 each have one isolated single chip, and the second and third groups G2 and G3 have 133 chips and 5 chips, respectively. Accordingly, each of the first and fourth groups G1 and G4 has a size of “1”, and each of the second and third groups G2 and G3 has a size of “133” and “5”, respectively. The group size is regarded as a unique value given to the group.

  Referring now to FIG. 1B, after grouping the defective chips filtered in step 45, a defect index value DI is calculated for the specific wafer (step 47). A suitable group weighting equation can be used to calculate the defect index value. Since locality defects may be considered more important than many other failure modes in the management aspect of the manufacturing process, the wafer defect index value (ie, the discrimination between defective and non-defective wafers) The mathematical formula used to calculate the value used to make it appropriate must emphasize the importance of the size of the group consisting of filtered defective chips on the wafer. Therefore, when defective chips filtered over the entire wafer are uniformly distributed, the corresponding defect index value is relatively low. However, when the filtered defective chips are locally clustered and distributed, the defect index value is relatively high.

  For example, the following Equation 2 can be used to calculate the defect index value DI.

  Here, “T” is the total number of semiconductor chips on the specific wafer, “A1” is the size of the first group (ie, G1 = 1), and “A2” is the size of the second group ( That is, G2 = 133), and “Ak” is the size of the last group (ie, G4 = 1). Applying Equation 2 to the filtered defective chip grouping shown in FIG. 6 yields a defect index value of 20.6 for the specific wafer.

  Referring again to FIG. 1B, the calculated defect index value DI is compared with a predetermined upper limit line value UCL (step 49). If the calculated defect index value DI for the specific wafer is larger than the upper limit line UCL, the specific wafer is sent to the defect analysis stage (step 51). Otherwise, the test system that executes the test method according to the flowcharts of FIGS. 1A and 1B determines whether the specific wafer is the last wafer in one lot (step 53). If the specific wafer is the last wafer, the test method ends. However, if the specific wafer is not the last wafer, the next wafer is selected (step 55), and a series of tests starting at step 37 of FIG. 1A are applied to the next wafer.

  The step of determining the upper limit UCL is very important in distinguishing defective wafers having unacceptable locality from the entire measured wafer. 7 and 8 are one exemplary graph used to select an appropriate upper limit line UCL. It is very important in the practice of the present invention that experimental data available in the semiconductor industry is used.

  The experimental data can be in agreement with a frequency distribution chart (histogram) as shown in FIG. Individual defect index values DI can be shown on the frequency distribution diagram in relation to the frequency F of occurrence. FIG. 8 is a general beta probability distribution diagram showing the beta probability PB based on the wafer defect index value DI. The beta probability distribution diagram shows beta (β) and alpha (α) calculated from the frequency distribution diagram of FIG. Created using. The beta (β) and alpha (α) are obtained by using the following Equation 3 and Equation 4, respectively.

  Here, “X” is a standard mean calculated from the frequency distribution chart of FIG. 7, and “σ” is a standard deviation calculated from the frequency distribution chart of FIG.

  The beta probability distribution chart of FIG. 8 can be statistically evaluated in relation to manufacturing process conditions, expected mass production yields, quality control items, and the like in order to determine an appropriate upper limit line UCL.

  The above method for testing a wafer in a lot can be carried out on a commonly used test equipment such as a test station automatically controlled by a microprocessor or a test system developed at the request of the user. it can. FIG. 9 is a schematic block diagram illustrating an example of a test system employed to proceed with a test method according to an embodiment of the present invention.

  Referring to FIG. 9, the test system 20 operates in connection with at least one wafer tester 19 or wafer test station. Wafer tester 19 can be an apparatus or system employed to perform electrical tests on a specific wafer. A number of different wafer testers are often used to measure a series of electrical test items for a particular wafer. For example, a first wafer tester of the wafer testers may be used to measure a first test item of a series of test items for the specific wafer, and a second wafer tester of the wafer testers may be used for a series of tests for the specific wafer. It can be used to measure the second test item among the items. A general control bus line 21 can be installed for wired / wireless communication or network communication between the test system controller 3 and the wafer tester 19.

  Test data measured from the wafer tester 19 for each semiconductor chip of a specific wafer can be stored in the corresponding database 1 by the controller 3. The database 1 can take other forms, but can typically comprise hardware including non-volatile memory. Conventional database software can be used to record data in the database 1 or to access stored data in the database 1. Furthermore, the database 1 can also store test device control programs, test system operation instructions, and / or test data and associated data structures.

  The controller 3 can be a normal microprocessor or microcontroller that is connected to a normal register 5 and executes an operating system program such as Windows or Linux. In one embodiment, the test system 20 can be run on a regular personal computer. The controller 3 also connects to a normal peripheral device such as a monitor (ie, a liquid crystal display (LCD) or cathode ray tube (CRT)) 17 and / or a mouse or keyboard (not shown) within the test system 20. be able to. The test system operator can execute communication with the test system 20 via the peripheral device and / or the monitor 17.

  The test system 20 shown in FIG. 9 can operate with five exemplary software modules operated by the controller 3. These software modules can include a wafer map generator 7, a filtered map generator 9, a grouped map generator 11, a defect index value DI generator 13 and a defect index comparator 15. Data communication 22 is performed between the controller 3 and each software module. The data communication 22 can be performed using hardware (ie, data / address / control signal lines connecting the controller 3 to a memory such as the database 1) and / or software. The exemplary modules will be described by taking the execution of the test method shown in FIGS. 1A and 1B as an example.

  Referring to FIGS. 1A, 1B, and 9, to begin operation of the test system 20, a test system operator selects a product to be tested (step 31). Such selection can be performed using a menu displayed on the monitor 17. Also, the test system operator can determine an appropriate spatial filter and a corresponding upper limit line using a peripheral device such as a mouse provided as part of the test system 20 (step 33). Subsequently, a specific wafer to be tested is selected (step 35). The controller 3 is used to control the operation of the wafer tester 19 and / or automated wafer transfer system. Subsequently, the wafer tester 19 measures at least one test item for the specific wafer (step 37), and sends test data to the controller 3. The test data generates a corresponding data file in the database 1 (step 39).

  The controller 3 controls the wafer map generator 7 to generate a wafer map using the data file in the database 1 (step 41). In one embodiment, the wafer map may be generated with a graphic file showing identifiable data on the monitor 17. Therefore, the wafer map is displayed via the monitor 17 so that the test system operator can confirm with the naked eye.

  Once the wafer map is generated, the controller 3 uses the filtered map generator 9 to filter the map using at least one data file associated with the wafer map (ie, the filtered wafer map). (Step 43). The filtered wafer map can also be generated with a graphic file showing identifiable data on the monitor 17. Therefore, the filtered wafer map is also displayed via the monitor 17 so that the test system operator can confirm with the naked eye. Once the filtered wafer map is generated, the controller 3 causes the grouped map generator 11 to use the filtered file map with at least one data file associated with the filtered wafer map. In step 45, the filtered defective chips in the wafer map are grouped into one crowd or two or more crowds.

  When the filtered defective chips are grouped, the controller 3 calculates the data calculated by the defect index value generator 13 from the grouped filtered defective chips. Is used to calculate the defect index value DI for the specific wafer (step 47). When the defect index value DI is calculated, the controller 13 controls the defect index comparator 15 to compare the calculated defect index value DI with a preset upper limit line (step 49). Specifically, the controller 3 determines whether the specific wafer is a defective wafer that requires defect analysis (step 51) based on the comparison result or a non-defective wafer that does not require defect analysis (step 51). Is determined (step 49). In one example, the necessity or disuse of the defect analysis for the specific wafer can be displayed through the monitor 17 so that the test system operator can recognize it.

  After the test method for the specific wafer is completed, the controller 3 determines whether the specific wafer is the last wafer in one test lot (step 53). If the specific wafer is the last wafer in one lot, the test method ends. However, if the specific wafer is not the last wafer in one lot, the next wafer is selected (step 55), and the above-described series of test steps are sequentially performed on the selected wafer.

  The wafer test method and / or test system according to the above-described embodiment does not necessarily require an operator. That is, the controller can execute automated test instructions for operating at least one of the software modules without the intervention of a test system operator. As a result, at least one stage of the wafer test method according to the present invention can be performed automatically without operator assistance. Similarly, the test system according to the present invention can operate automatically without operator assistance.

  10 and 11 are actual wafer maps employed for applying the embodiment of the present invention. In FIG. 10 and FIG. 11, the embedded squares indicate the defective chip FC, and the empty squares indicate the good chip GC. The first wafer of the wafer map of FIG. 10 shows a yield of 95.57%, and the second wafer of the wafer map of FIG. 11 shows a yield of 94.79%. In this case, according to the conventional defective wafer detection method employing the yield of 95% as the target yield, the first wafer is classified as a non-defective wafer, and the second wafer is classified as a defective wafer. However, when the embodiment of the present invention is applied to the wafer maps of FIGS. 10 and 11, the wafer maps of FIGS. 10 and 11 can be converted to the filtered wafer maps of FIGS. 12 and 13, respectively. In this case, the spatial filter used in the embodiment of the present invention is set to have a size of “3 × 3”, a weight value of “1”, and a reference filter value of “0.5”. In FIG. 12 and FIG. 13, the embedded square represents the filtered defective chip FFC.

  Also, the wafer defect index value calculated from the filtered wafer map of FIG. 12 is “0.51”, and the wafer defect index value calculated from the filtered wafer map of FIG. 13 is “0.08”. Met. Thus, when a target defect index of 0.5 (ie, an upper limit line) is employed, the first wafer is classified as a defective wafer and the second wafer is classified as a non-defective wafer.

6 is a flowchart illustrating one exemplary test method according to an embodiment of the present invention. 6 is a flowchart illustrating one exemplary test method according to an embodiment of the present invention. It is a figure which shows the two-dimensional nxm matrix-like spatial filter. It is a figure which shows a part of wafer map (WM) which identifies a favorable chip | tip from the defective chip | tip in a layout matrix. FIG. 4 illustrates a portion of a filtered wafer map (FWM) as obtained from the wafer map of FIG. 3. 3 is an exemplary wafer map. 5B is a filtered wafer map obtained from the wafer map of FIG. 5A. 6 is a map illustrating a method of defining a filtered defective chip group from a filtered wafer map. 6 is a histogram used to determine an upper limit line of defect indices useful in embodiments of the present invention. FIG. 8 is a beta probability distribution diagram obtained from the histogram data of FIG. 7. 1 is a schematic diagram illustrating hardware and software components of a test system employed to perform a test method according to an embodiment of the present invention. It is a figure which shows the wafer map which has a similar semiconductor chip, showing a mutually different yield. It is a figure which shows the wafer map which has a similar semiconductor chip, showing a mutually different yield. FIG. 11 is a filtered wafer map obtained from the wafer map of FIG. 12 is a filtered wafer map obtained from the wafer map of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Database 2 Data communication 3 Test system controller 5 Register 7 Wafer map generator 9 Filtered map generator 11 Grouped map generator 13 Defect index value generator 15 Defect index comparator 17 Monitor 19 Wafer tester 20 Test system 21 Control bus line

Claims (34)

In a method for testing a wafer having semiconductor chips, the method comprises:
Generating a wafer map indicating defective semiconductor chips of the wafer;
Generating a filtered wafer map showing defective semiconductor chips filtered from the wafer map;
Calculating a wafer defect index value from the filtered wafer map;
Comparing the wafer defect index value with an upper limit line;
A wafer test method comprising: Determining whether the wafer is defective or non-defective based on a comparison between the wafer defect index value and the upper limit line;
Analyzing the wafer for defects when the wafer is defective;
The wafer test method according to claim 1, further comprising: Generating the wafer map comprises:
Performing an electrical test on the semiconductor chip to generate test data;
Determining whether each of the semiconductor chips is a defective semiconductor chip based on the test data; and
The wafer test method according to claim 1, further comprising:   4. The wafer test method according to claim 3, wherein generating the wafer map further comprises forming a data file from the test data, and the wafer map is formed from the data file.   5. The wafer test method according to claim 4, wherein the step of generating the wafer map further includes the step of generating a graphic file indicating data identifiable by a monitor.   The wafer test method according to claim 1, wherein the filtered wafer map is generated by applying a spatial filter having a predetermined size to the wafer map.   The wafer test method according to claim 6, wherein the spatial filter includes “n × m” matrix cells, and each of the cells has a weighting factor. The wafer map defining a layout matrix related to the arrangement of the semiconductor chips on the wafer; and
Generating the filtered wafer map includes applying the spatial filter to each semiconductor chip using test data values associated with the semiconductor chip corresponding to the cells of the layout matrix, respectively.
The wafer test method according to claim 7, further comprising: Applying the spatial filter to one semiconductor chip comprises calculating a filtered value for the one semiconductor chip;
Comparing the calculated filtered value with a reference filter value;
Determining whether the one semiconductor chip is a filtered defective chip based on the comparison result; and
The wafer test method according to claim 8, further comprising: Calculating the filtered value comprises:
Multiplying the weighting coefficient of the cell of the spatial filter by the test data value of the semiconductor chip corresponding to the cell, respectively, to calculate a weighted multiplication value corresponding to the semiconductor chip,
Adding the weighted multiplication value to obtain a sum of these values;
Dividing the sum of the weighted multiplication values by the size of the spatial filter;
10. The wafer test method according to claim 9, further comprising:   11. Each of the weighting factors has a unit value, each of the test data values has a single bit binary data value, and the reference filter value is 0.5. Wafer test method.   The method of claim 6, wherein generating the filtered wafer map further comprises generating a graphic file indicating data identifiable by a monitor. Calculating the wafer defect index value from the filtered wafer map comprises:
Defining at least one group comprised of the filtered defective semiconductor chips, the at least one group having a unique value;
Calculating the wafer defect index value using the at least one group value;
The wafer test method according to claim 1, further comprising: Calculating the wafer defect index value using the at least one group value;
Calculating a square value of the group value;
Obtaining a square root of the sum of the squared values;
Dividing the square root by the total number of the semiconductor chips on the wafer;
The wafer test method according to claim 13, comprising:   2. The wafer test method according to claim 1, wherein the upper limit line is determined using actual test data obtained by testing a semiconductor chip similar to the semiconductor chip on the wafer.   16. The wafer test method according to claim 15, wherein the upper limit line is determined using a statistical model or a mathematical expression of the actual tester data. In a method for determining whether a wafer is defective, said method comprises:
Defining at least one spatial group comprised of filtered defective semiconductor chips on the wafer;
Calculating a wafer defect index value in relation to the at least one spatial group;
Comparing the wafer defect index value with an upper limit line;
A wafer test method comprising: Defining the at least one spatial group comprises:
Generating a wafer map from test data for displaying defective semiconductor chips on the wafer;
Applying a spatial filter to the wafer map to generate a filtered wafer map;
Grouping the filtered defective semiconductor chips on the filtered wafer map into at least one group;
The wafer test method according to claim 17, further comprising: The wafer test method is sequentially applied to each of the wafers in one lot,
The wafer test method further includes generating a graphic file from the wafer map and the filtered wafer map, and the graphic file stores test data of each wafer while testing the wafers in the lot. 19. The wafer test method according to claim 18, wherein the wafer test method is displayed in real time on a monitor.   18. The wafer according to claim 17, further comprising a step of analyzing the wafer for defects when it is determined that the wafer is defective based on a comparison result between the wafer defect index value and the upper limit line. Test method. Generating the wafer map comprises:
Performing an electrical test on the semiconductor chip to generate the test data;
Generating a data file from the test data;
Generating the wafer map from the data file;
Determining whether each of the semiconductor chips is a defective semiconductor chip based on the test data; and
The wafer test method according to claim 18, further comprising:   19. The wafer test method according to claim 18, wherein the spatial filter includes cells constituting an “n × m” matrix, and each of the cells has a weighting factor. The wafer map defines a layout matrix related to the arrangement of the semiconductor chips on the wafer,
Generating the filtered wafer map includes applying the spatial filter to each semiconductor chip using test data values associated with the semiconductor chips corresponding to the cells of the layout matrix, respectively. The wafer test method according to claim 22. Applying the spatial filter to one semiconductor chip comprises:
Calculating a filtered value for the one semiconductor chip;
Comparing the calculated filtered value to a reference filter value;
Determining whether the one semiconductor chip is a filtered defective chip based on the comparison result; and
24. The wafer test method according to claim 23, comprising: Calculating the filtered value comprises:
Multiplying the weighting coefficient of the cell of the spatial filter by the test data value of the semiconductor chip corresponding to the cell, respectively, to calculate a weighted multiplication value corresponding to the semiconductor chip,
Adding the weighted multiplication value to obtain a sum of these values;
Dividing the sum of the weighted multiplication values by the size of the spatial filter;
25. The wafer test method according to claim 24, comprising:   26. Each of the weighting factors has a unit value, each of the test data values has a single bit binary data value, and the reference filter value is 0.5. Wafer test method.   18. The wafer test method according to claim 17, wherein the upper limit line is determined using actual test data obtained by testing a semiconductor chip similar to the semiconductor chip on the wafer.   28. The wafer test method according to claim 27, wherein the upper limit line is determined using a statistical model or mathematical expression of the actual tester data. A wafer tester for performing an electrical test on a semiconductor chip formed on the wafer and generating test data corresponding to the electrical test;
A controller for storing the test data as a data file in a database;
The controller generates a wafer map that displays defective semiconductor chips among the semiconductor chips from the test data together with the database, and generates a filtered wafer map that displays the filtered defective semiconductor chips from the wafer map. , Limiting at least one spatial group composed of the filtered defective semiconductor chips, calculating a wafer defect index value for the at least one spatial group, and comparing the wafer defect index value with an upper limit line A test system for executing at least one software module.   30. The test system of claim 29, further comprising a monitor operated by the controller, the monitor showing the wafer map and the filtered wafer map in real time and graphically.   31. The test system according to claim 30, wherein the monitor further includes a function of indicating whether or not the wafer is defective based on a comparison result between the wafer defect index value and the upper limit line.   30. The test system according to claim 29, wherein the wafer tester includes a plurality of wafer testers, and each of the plurality of wafer testers measures different electrical test items for the wafer.   30. The test system of claim 29, wherein the at least one software module is operated by an operating system stored in the database and executed by the controller.   30. The test system of claim 29, wherein the controller executes automated test instructions for operating the at least one software without intervention of an operator of the test system.