JP2006506940A - Two-stage power conversion circuit - Google Patents

Abstract

A power conversion circuit is provided. The circuit includes a stand-alone board mounted power module operable to convert the nominal input voltage to an intermediate bus voltage, such board mounted power module being unregulated and controlled in an open loop. The circuit also includes a plurality of strictly regulated load point converters operable to convert the intermediate bus voltage into respective load point voltages and power each load number.

Description

  The present invention relates to a power conversion circuit, for example, a two-stage power conversion circuit used in network and communication applications.

  In today's information era, information bandwidth is increasingly required for network and communication applications. As demand for bandwidth increases, there is an increasing demand to better guarantee data integrity in quality of service (QoS) and maximize system uptime. For this purpose, intelligent routing management is often employed. For example, in packet distribution routing, the data flow is reorganized into small packets of data, each sent to its final destination via a separate data path, where the packet is ultimately the original data flow. Reconfigured. Such routing can only be done through complex deep packet processing, but such processing requires faster and more powerful NPUs and ASICs.

  The growing demand for data processing has not surprisingly affected internal hardware design, especially in the field of built-in power distribution. Since the standard size of communication boards remains relatively constant, power distribution systems must be installed in even smaller spaces as future designs require more and more processors to be added to the board. At the same time, power consumption always increases as the number of components increases. To install the power supply in a smaller space to satisfy the increasing demand for power, the power distribution design should be optimized to ensure efficiency. If a more efficient power supply is designed, the heat dissipation can be reduced because the dissipation is reduced.

  Many of today's networking and communication systems employ power structures that receive 48V nominal input from bulky bulk AC / DC rectifier modules. The 48V input is a nominal input, but various systems are receiving a power input on either side within the nominal range. For example, the voltage range of general-purpose telecommunications is 36Vin to 75Vin, and the voltage range of ETSI (European telecommunications standard input) is 36V to 60V. Other systems operate at +/- 10% from a regulated 48V bus. Regardless of which distribution method is employed, the input voltage should be distributed to the load point in the most electrically efficient and cost effective manner possible.

  In order to meet these more demanding requirements, two-stage power conversion is becoming the new standard for board-mounted power distribution. Traditionally, as shown in FIG. 1, a plurality of independent power converters 105a,..., 105n-1, 105n called “Brix” are used to power various low voltage loads on a board such as a computer motherboard. Was. The output to the low current periphery will transfer the intermediate power generated by one of these “bricks” to POLs 110a. . . It was supplied by converting through 110n.

And in an attempt to increase the simplicity and flexibility of onboard power distribution design, a fully regulated converter is used to generate the intermediate bus voltage, which is then generated by the load point power converters (POLs). It was converted to the load point voltage. For example, in one aspect (not shown) , the -48 Vin nominal input is converted to a 3.3 volt intermediate bus voltage using a single independent converter. This intermediate bus voltage is supplied directly to the load with the least power on the board, but the load with less power receives the power through the respective POL converter . Throughput efficiency was maximized in order to minimize any costs of the two-stage configuration, it must be carefully optimized each power conversion stage. However, throughput efficiency of these configurations have low.

  No. 60 / 425,422, filed on Nov. 11, 2002, Dec. 23, 2002, Feb. 14, 2003, and Jun. 9, 2003, respectively. 60 / 436,316, 60 / 447,635, and 60 / 477,311 (IR-2412 PROV, IR-2412 PROV II, IR-2412 PROV III, and IR-2412 PROV IV, respectively) It is based on and claims this. The disclosures of these provisional applications are incorporated herein by reference in their entirety.

The object of the present invention is to provide a cost- and space-efficient power distribution design that meets the increasing power requirements for many today's applications while employing fewer components, and thus the conventional two-stage power distribution configuration. Overcoming the drawbacks. To this end, the exemplary embodiment of the present invention takes advantage of the fact that a stand-alone converter does not need to precisely control the intermediate bus voltage when using a strictly regulated POL converter. ing. Conversely, it is possible to realize effective performance by driving any transmitter without restriction in an open loop.

  By driving an independent DC bus converter in an open loop with an unregulated regulation method with a 50% duty cycle, the control and circuit design required to control such power conversion becomes very simple, And high efficiency. This is because open loop design does not require the complex closed loop control and overvoltage protection circuitry of traditional strictly regulated power conversion designs. Therefore, such a control circuit system can be realized by a single integrated circuit in a small space. Power conversion performance is achieved using minimal voltage and current stress. This allows for more efficient power MOSFETS with a lower effectiveness measure (FOM). Furthermore, a fixed 50% duty cycle improves reliability by allowing the use of a simple and highly efficient self-driven secondary synchronous rectifier circuit while minimizing the need for input and output filtering.

  To control a simple and novel open loop control configuration here, there are two exemplary integrated circuit controllers. One is a half-bridge converter and one is a full-bridge converter. While an exemplary half-bridge converter according to the present invention can be used to convert to a nominal input power supply in a specific range, for example in the range of 60-160W, a full-bridge converter in accordance with the present invention can have a nominal power in the range of, for example, 120-160W. Can be converted to input. With a fixed 50% duty cycle, the output voltage is proportional to the nominal input voltage by a factor K. For the half-bridge converter according to the invention, the factor K is divided by the transformer tuning ratio, for example equal to one half. For a full bridge converter according to the invention, the factor K is divided by the tuning ratio of the transformer, for example equal to 1. Thus, the full bridge topology provides additional flexibility with respect to output voltage selection.

In a basic scheme, according to one embodiment according to the present invention, as shown in FIG. 2, nominally −48V is converted to a 12V intermediate bus voltage 205 via a single independent converter 210. . The intermediate bus voltage 205 is converted into various load point voltages via the respective POLs 215a, 215b, 215c,.

  Referring now to FIG. 3, it can be seen a first exemplary half-bridge two-stage power conversion configuration 300 according to the present invention. The power conversion configuration 300 includes a single stand-alone unregulated board mounted power module (BMP) 305 that operates in an open loop. The BMP 305 can be operated to convert the nominal input voltage 320 to the intermediate bus voltage 325. The intermediate bus voltage 325 is then supplied to various load point (POL) converters 310a, 310b,..., 310n, where the intermediate bus voltage 325 is used to power various loads (not shown) on the board. Are converted into respective load point voltages 330a, 330b,..., 330n.

  Referring now to FIG. 4, an exemplary half-bridge converter circuit 405 for use with the BMP power module 305 of FIG. 3 can be seen. The half-bridge converter circuit 405 includes a primary open loop inverting circuit 410, a primary bias circuit 430, a secondary rectification and filtering circuit 425, and a secondary bias circuit 420.

  The primary open loop inverting circuit 410 includes a primary half-bridge controller IC 415 having terminals (CS), (CT), (G), (LO), (Vb), (HO), (Vs) and (Vcc). Yes. The diode D1 is connected between Vdd and the terminal (Vb) of the controller IC 415, the resistor R1 is connected between Vdd and the terminal (CT) of the controller IC 415, and the capacitor C1 is connected to Vdd and the controller IC 415. The capacitor C2 is connected between the terminal (CT) of the controller IC 415 and the ground, and the terminal (CS), (G) of the controller IC 415 is connected to the terminal (CS), (G). ), The capacitor C3 is connected between the terminals (Vb) and (Vs) of the controller IC 415, and the terminal (Vcc) is connected to Vdd. Primary open loop inverter 410 also includes power MOSFETS M1, M2 connected together at node N1 in a half-bridge configuration between a 48 volt nominal input 320 and ground (eg, a bias such that the gate drive voltage is 7.5 volts). There are also two IRF6603 30V n-channel direct FET power MOSFETS) clamped to voltage. The node N1 is also connected to the terminal (Vs) of the controller IC 415. The gates of MOSFETS M1 and M2 are connected to terminals (HO) and (LO), respectively. Series-connected capacitors C5 and C6 and capacitor C4 are connected in parallel to half-bridge MOSFETS M1, M2 between 48 volt nominal input 320 and ground. The primary winding I1 is connected between the node N2 and a terminal (Vs) of the controller IC 415.

  The choice of MOSFET is important in meeting the requirements of electrical and thermal efficiency to maintain a minimal number of components while keeping the mounting location small. The power MOSFETS M1, M2 may comprise next generation MOSFET technology and may be configured in a half-bridge configuration to operate with the half-bridge controller IC 415. Direct FET packaging may also be employed to virtually eliminate packaging resistance, which allows for low overall on-state resistance. In addition, because direct FET technology employs plastic packaging, direct FET MOSFETS are very efficient when employing top surface cooling. Primary bias circuit 430 includes dual FET package 435 (eg, IRF7380 n-channel FETs) including primary bias MOSFETS M3, M4, resistors R2, R3 connected in parallel between 48 volt nominal input 320 and MOSFET M3. A resistor R4 connected between the 48 volt nominal input 320 and the MOSFET M4, a series-connected Zener diodes D4 and D5 connected between the resistor R4 and ground, and between the nodes N3 and Vdd , A diode D2 connected to MOSFET M4, and a primary bias winding I2 connected between diode D2 and ground. In this way, the primary side bias is obtained at startup via the linear regulator and from the transformer in steady state.

  The secondary rectification and filtering circuit 425 includes a secondary winding I3 that is magnetically coupled to the primary winding I1 of the primary open-loop inverting circuit 410. The secondary winding I3 is connected between MOSFETS M5 and M6 connected in parallel with each other at the node N4. The resistor R5 and the capacitor C7 are connected to each other in parallel with the diode d6 connected in parallel with the source and drain terminals of the MOSFET M5. Similarly, the resistor R6 and the capacitor C8 are connected to each other in parallel with the diode D7 connected in parallel with the source and drain terminals of the MOSFET M6. The gate nodes of M5 and M6 are each connected to a node N4 via respective resistors R7 and R8. The inductor coil I4 is connected to the center tap node N5, and the capacitors C9, C10, C11 are connected in parallel to each other between the inductor coil I4 and the node N4. The secondary rectification and filtering circuit 425 is also provided with two secondary MOSFETS M7, M8. The gate nodes of MOSFETS M7 and M8 are connected to each other. The source nodes of MOSFETS M7 and M8 are connected to the gate nodes of MOSFETS M5 and M6, respectively, and the drain nodes of MOSFETS M7 and M8 are connected to the drain nodes of MOSFETS M6 and M5, respectively. The secondary side MOSFETS M7, M8 may be realized using, for example, an IRF6603 direct FET MOSFETS configured in a self-driven synchronous rectification topology.

  Secondary bias circuit 420 includes a secondary bias wiring I5 that is magnetically coupled to primary bias wiring I2 of primary bias circuit 430. The diodes D8 and D9 are connected to each other in series between the node N4 and the node N6. Capacitor C12 is connected to node N7. The bias wiring I5 is connected between the capacitor C12 and the node N4. The resistor R8 is connected in series with the Zener diode D10 between the nodes N6 and N4. Capacitor C13 and resistor R9 are connected in parallel between node N4 and the gates of MOSFETS M7 and M8. In this way, the secondary bias circuit 420 is designed such that the outputs of two bus converters operating at different nominal input voltages can be connected in parallel. Thus, the secondary bias circuit 420 allows the half-bridge converter circuit 405 to continue to operate even if one of the two bus converters fails.

  Referring now to FIG. 7, the front and back of an exemplary power distribution board 705 according to the present invention can be seen. The power distribution board can deliver 150W with 8V output voltage to the 1/8 converter BMP output line with efficiency exceeding 96%. This is completely regulated and is 3 to 5% more efficient and 50% smaller in size than a board-mounted power converter. In order to minimize printed circuit board (PCB) power loss, the power distribution board 705 may have a multi-layer PCB board configuration, such as an 8-layer PCB board configuration. The top and bottom layers may be made of, for example, 2 ounce copper, and the inner six layers may be made of, for example, 4 ounce copper. Distribution board 705 may also include a transformer with a flat PQ core that performs voltage conversion and isolation between primary open-loop inverting circuit 410 and secondary rectification and filtering circuit 425. The magnetic core for the transformer may be selected according to the maximum input voltage and frequency. The FR3 material may be a high frequency and low loss material. A very small air gap may be provided in the transformer to shorten the turn-off time of the primary side MOSFETs M1 and M2 at a light load. A small 160 nH output inductor with 1 mm air spacing may be used to limit the output and input current ripple to less than 4 amps.

  The half-bridge controller IC 415 can be operated to provide high side and low side drive signals for the primary driver MOSFETS M1, M2 with a 50% duty cycle and a minimum number of external components. The gate drive capability of the half-bridge controller IC 415 is optimized to directly drive the new generation power MOSFETS M1, M2 without any additional drivers or buffers. The high side nominal input voltage 320 may be as high as 100V, for example, even if the 48V nominal input voltage is used to implement the example circuit of FIG. This configuration thus allows a wide nominal input voltage range, for example between 24V and 48V, for telecommunications, networking and computing. Further, the circuit performance can be further optimized by setting the primary side bias voltage in the range of, for example, 10 to 15V.

In order to prevent flux imbalance, the difference in pulse width between the high side drive signal and the low side drive signal should be less than a predetermined threshold, for example less than 25 ns. This can be important in certain applications. The switching frequency and dead time between the high side and low side drive signals can be varied for different applications by adjusting the values of resistor R1 and capacitor C2. The switching frequency is determined by the following formula.
f _s = 1 / (2R ₁ C ₂ )

External resistor R1 and capacitor C2 also determine the dead time between the high side and low side drive signals. Referring now to FIG. 5, a chart showing the relationship between the value of the resistor R1 and the dead time when the capacitor C2 has a specific capacitance value can be seen. The dead time should be longer than the turn-off time of the primary side MOSFETS M1, M2 to prevent short circuit current. The turn-off time of the primary power MOSFETS can be estimated by the following formula.
t _off = (Q _gd + Q _gs2 ) / I _g
Where Qgd is the MOSFET gate-to-drain charge (ie, “mirror” charge), Qgs2 is the post-threshold gate charge, and Ig is the drive current.

  During the dead time, the body diodes of the secondary MOSFETS M7 and M8 are conducted. Therefore, the dead time should be set as short as possible to maximize efficiency while still providing sufficient time for the primary side MOSFETS M1, M2 to turn off under worst case operating conditions. is there.

  Referring now to FIG. 6, further details of the exemplary half-bridge controller IC 415 of FIG. 4 can be seen. The entire controller IC 415 operates with a bias voltage (eg, 10 to 15 volts) generated by the bias block 610. Half-bridge controller IC 415 includes undervoltage lockout (UVLO) blocks 605, 650 assigned to Vcc and Vb, respectively. Undervoltage monitoring ensures that all timing signals are kept within specification. The oscillator block 615 provides a 555 type oscillation waveform signal S1 having a duty cycle of 50%. Internal soft start block 630 ensures that the duty cycle of signals S2, S3, S4 gradually increases from zero to 50%, thereby facilitating inrush current during start-up. High-side and low-side drivers 655, 660 can provide, for example, 1 ampere of current with high-side and low-side driver signals (HO), (LO) through MOSFETS 665, 670, 675, 680. . The half-bridge controller IC 415 also has a current limiting function via current sources 640, 645 and MOSFETS 690, 695.

  As described above, the half-bridge controller IC 415 may be used to control an unregulated independent DC bus converter operated in an open loop, such as a 48V, two-board onboard distribution system. The half-bridge controller IC 415 is optimized for performance, simplicity, and cost, and the entire controller IC 415 can be integrated into a single package, such as a single S08 package.

  Referring now to FIG. 9, an exemplary full bridge converter circuit 900 for the BMP power module 305 of FIG. 3 can be seen. The full bridge converter circuit 900 includes a primary open loop inverting circuit 910, a primary bias circuit 915, and a secondary rectification and filtering circuit 425.

  The primary open loop inversion circuit 910 includes terminals (CS), (D), (CT), (G1), (LO1), (Vcc), (VB1), (HO1), (VS1), (G2), (G A primary full bridge controller IC 905 having LO2), (VS2), (HO2), and (VB2) is provided. The diode D11 is connected between Vcc and the terminal (VB1) of the controller IC 905. The diode D12 is connected between Vcc and the terminal (VB2) of the controller IC 905. The resistor R1 is connected between Vcc and a terminal (CT) of the controller IC 905. The capacitor C1 is connected between Vcc and the terminal (G1) of the controller IC 905. The capacitor C2 is connected between the terminal (CT) of the controller IC 905 and the ground. The capacitor C15 is connected between the terminals (Vb1) and (VS1) of the controller IC 905. The terminal (Vcc) is connected to Vcc. Capacitors C17 and C18 are connected in parallel with each other between a 48 volt nominal input 320 and ground. The capacitor C16 is connected between the terminals (VS2) and (VB2) of the controller IC 905. Primary open loop inverter 905 also includes power MOSFETS M9, M10, M11, M12 (eg, four IRF6603 30V n-channel direct FET power MOSFETS). MOSFETs M9, M10, and M11, M12 are connected together at nodes N9, N10, respectively, between the 48 volt nominal input 320 and ground in a full bridge configuration. The node N9 is also connected to the terminal (VS1) of the controller IC 905, and the node N10 is also connected to the terminal (VS2) of the controller IC 905. The gates of MOSFETS M9, M10, M11, and M12 are connected to terminals (HO1), (LO1), (HO2), and (LO2), respectively. Primary winding I7 is connected between nodes N9 and N10.

  Primary bias circuit 915 includes primary bias MOSFETS M15, M16, resistors R16, R17 connected in parallel between 48 volt nominal input 320 and MOSFET M15, and between 48 volt nominal input 320 and MOSFET M4. The connected resistor R18, the Zener diodes D13 and D14 connected in series connected between the resistor R18 and the ground, the diode D15 connected to the MOSFET M16, and the diode D15 connected between the ground A primary bias winding I9, a resistor R14 and a capacitor C22 connected in parallel between the terminal (CS) of the controller IC 905 and the ground, and a node between the terminal (CS) of the controller IC 905 and the ground. Resistors R15, R13 connected in series at N11; The resistor R19 connected between the terminals (CS) and (rm) of the controller IC 905, the diodes D16 and D17 connected in series connected between the node N11 and the ground, and the node N11 and the ground And diodes D18 and D19 connected in series, and diodes D16 and D17 connected in series, and a coil I10 connected between D18 and D19.

  The secondary rectification and filtering circuit 920 includes a secondary winding I11 that is magnetically coupled to the primary winding I7 of the primary open-loop inverting circuit 910. The secondary winding I11 is connected between MOSFETS M17 and M18 connected to each other at the node N12. The gate nodes of MOSFETS M17 and M18 are connected to node N12 via respective resistors R11 and R10. The inductor coil I8 is connected to the center tap node N13, and the capacitors C19, C20, C21 are connected to each other in parallel between the inductor coil I8 and the node N12. The secondary rectification and filtering circuit 425 is also provided with two secondary MOSFETS M13, M14. The gate nodes of MOSFETS M13 and M14 are connected to each other. Zener diode D20 and capacitor C23 are connected in parallel with each other between the gate nodes of MOSFETS M13 and M14 and node N12. The resistor R12 is connected between the gate nodes of the MOSFETS M13 and M14 and the inductor coil I8. The source nodes of MOSFETS M13 and M14 are connected to the gate nodes of MOSFETS M17 and M18, respectively, and the drain nodes of MOSFETS M13 and M14 are connected to the drain nodes of MOSFETS M18 and M17, respectively. The secondary side MOSFETS M13 and M14 may be realized by using, for example, an IRF6603 direct FET MOSFETS configured in a self-driven synchronous rectification topology.

  The full bridge controller and driver IC 905 is similar to the half bridge controller 415 of FIG. 4, but has an improved current limit function mode and flexible soft-start capability. The current limiting function has a temporary interruption mode, which may be externally controlled by a capacitor during the temporary interruption period. The primary current is sensed by a current transformer. For example, it has a high turn ratio of 150 to 1. The sensed AC current information is rectified and, after RC filtering, provided as an input to the current sense pin (CS) of driver IC 905.

  Since this controller IC 905 is designed for all bridge circuits, it provides four gate drive signals for MOSFETS M9, M10, M11, M12, respectively. The controller turns on each branch alternately with a 50% duty cycle. The difference in turn-on period between the two branches should be less than 25 ns, for example, to prevent flux imbalance. The turn-on and turn-off timing difference between the two MOSFETS should also be less than 25 ns.

  Referring now to FIG. 10, a graph can be seen showing the output voltage waveform during the temporary break mode with a current limit setting of 21A, a current load setting of 22A, and a nominal input voltage of 48V. As shown in FIG. 10, the controller IC 905 attempts to turn on the converter once during a predetermined period. For example, the predetermined period may be set to, for example, 500 ms by adjusting the value of the capacitor C14.

  Both the half-bridge controller IC 415 and the full-bridge controller IC 905 are designed to be easily synchronized with the outside within the overlapping frequency range. For this purpose, it is necessary to remove the timing resistor R1, and it is necessary to connect the timing capacitor C2 between the ICs 415 and 905 and the external synchronization source as shown in FIG. In the self oscillation mode, the current passing through the external timing resistor R1 is charged in the timing capacitor C2. Whenever the voltage at either (CT) terminal of the ICs 415, 905 is higher than a predetermined threshold, for example, half of the IC supply voltage Vcc or Vdd, the internal driver of the controller ICs 415, 905 causes the timing capacitor C2 Start to discharge. After the voltage at the terminal (CT) reaches a predetermined threshold value, for example, after it becomes one fifth of the supply voltage Vcc or Vdd, the controller ICs 405 and 915 disable the internal driver and the timing capacitor C2 Discharging is stopped and the current through resistor R1 begins to charge capacitor C2 again.

  In the synchronous mode of operation, the external capacitor C2 is connected to the (CT) terminal at the rising edge of the external synchronization source. Whenever the voltage at the terminal (CT) is higher than a predetermined threshold, for example when it is half the IC supply voltage, the internal driver in the controller ICs 415, 905 begins to discharge the voltage at the terminal (CT). When the voltage at the terminal (CT) is less than a predetermined threshold value, for example, when the voltage of IC415, 905 is one fifth of the supply voltage, IC415, 905 disables the driver and stops the discharge of timing capacitor C2. Let When a negative edge is applied, the internal diode resets the voltage at the terminal (CT) and maintains the voltage across the external timing capacitor C2 at zero volts. When the voltage across the external timing capacitor C2 reaches zero, the capacitor C2 is ready for the next external positive pulse. In the synchronous mode, the dead time is determined only by the internal impedance at the terminal (CT) and the capacitance of the external timing capacitor C2.

  In the self-oscillation mode, the timing resistor R1 cannot be too low, thereby limiting the maximum operating frequency. Normally, the timing resistor R1 should be higher than a predetermined value such as 2 kΩ. The lower the resistance value of the resistor R1, the higher the sink current for the internal discharge drivers of the ICs 415 and 905. In the synchronous mode, the timing resistor R1 is removed, so that a higher operating frequency can be realized. The maximum operating frequency in the synchronous mode is determined by the power loss derived from driving the external primary MOSFETS.

It is a block diagram which shows the conventional 2 step | paragraph power conversion structure. 1 is a block diagram showing a basic two-stage power conversion configuration according to the present invention . FIG. 1 is a block diagram illustrating a first exemplary power conversion configuration according to the present invention. FIG. 3 is an exemplary power conversion circuit for a board mounted power module according to the present invention. 4 is a graph showing dead time of a half-bridge driver IC according to the present invention. FIG. 5 is a block diagram of the half-bridge driver of FIG. 4. 2 is a front and back view of an exemplary power conversion board according to the present invention. FIG. It is a graph which shows power conversion efficiency versus output load current. 6 is another exemplary power conversion circuit for a board mounted power module according to the present invention. It is a graph which shows a temporary interruption waveform. 5 illustrates two methods for configuring the half-bridge driver IC of FIG. 4 to drive in either a self-oscillating mode or a synchronous mode.

Claims (20)

An unregulated independent board mounted power module operable to convert a nominal input voltage to an intermediate bus voltage, the independent board mounted power module being controlled in an open loop;
A plurality of strictly regulated load point converters operable to convert the intermediate bus voltage into respective load point voltages and power each load;
A power conversion circuit comprising:   The board-mounted power module includes a primary open loop inversion circuit, a primary bias circuit, a secondary synchronous rectification and filtering circuit, and a secondary bias circuit that are magnetically coupled to each other, and the synchronous rectification and filtering circuit The power conversion circuit according to claim 1, wherein the power generation circuit generates an intermediate bus voltage.   The primary open loop inverting circuit comprises a half-bridge controller IC and a pair of MOSFETS connected in a half-bridge configuration, the controller IC being operable to alternately control the pair of MOSFETS at a 50% duty cycle. The power conversion circuit according to claim 2, wherein:   4. The primary open loop inversion circuit includes a timing resistor and a timing capacitor, and a dead time and a switching frequency of a controller IC are adjusted according to values of the timing resistor and the timing capacitor. Power conversion circuit. The switching frequency is the following formula:
f _s = 1 / (2R ₁ C ₂ )
The power conversion circuit according to claim 4, wherein fs is a switching frequency, R1 is a value of a timing resistor, and C2 is a value of a timing capacitor.   The power conversion circuit according to claim 3, wherein the pair of MOSFETS includes direct FETs.   The power conversion of claim 3, wherein the half-bridge controller IC can be driven in at least two modes, one of the modes being a self-oscillating mode and the other being a synchronous mode. circuit.   The primary open-loop inverting circuit comprises a full-bridge controller IC and two pairs of MOSFETS connected in a full-bridge configuration so that the controller IC alternately controls the two pairs of MOSFETS with a 50% duty cycle. The power conversion circuit according to claim 2, wherein the power conversion circuit is controllable.   9. The primary open loop inversion circuit includes a timing resistor and a timing capacitor, and a dead time and a switching frequency of all bridge controller ICs can be adjusted according to values of the timing resistor and the timing capacitor. The power conversion circuit described in 1. The switching frequency is the following formula:
f _s = 1 / (2R ₁ C ₂ )
10. The power conversion circuit according to claim 9, wherein fs is a switching frequency, R1 is a value of the timing resistor, and C2 is a value of the timing capacitor.   The power conversion circuit according to claim 8, wherein the two pairs of MOSFETS include direct FETs.   The said bridge controller IC can be driven in at least two modes, one of the modes is a self-oscillation mode and the other of the modes is a synchronous mode. Half-bridge power conversion circuit. An independent unregulated board mounted power module operable to convert a nominal input voltage to an intermediate bus voltage, said board mounted power module being controlled in an open loop, and an intermediate bus voltage respectively A half-bridge controller IC for use with a power converter circuit comprising a plurality of strictly regulated load point converters operable to convert to a plurality of load point voltages and power each load number, The half bridge controller IC
A bias circuit for generating a bias voltage for operating the half-bridge controller IC;
An undervoltage lockout circuit operable to monitor the voltage at the power supply pin of the half-bridge controller IC;
An oscillator circuit that provides a timing signal having a 50% duty cycle;
A soft-start circuit that facilitates inrush current during start-up, ensuring that the duty cycle of the timing signal gradually increases from zero to 50% duty cycle,
The half-bridge controller IC alternately controls MOSFETS with a 50% duty cycle and provides a MOSFET drive signal to control a pair of MOSFETS connected to each other in a half-bridge configuration. When,
A half-bridge controller IC comprising:   The half-bridge controller IC of claim 13, wherein the MOSFETS comprises a pair of direct FETs. An unregulated independent board mounted power module operable to convert a nominal input voltage to an intermediate bus voltage, wherein the independent board mounted power module is controlled in an open loop and the unregulated independent The on-board power module includes a half-bridge controller IC, the half-bridge controller IC generating a bias voltage to operate the half-bridge controller IC, and a power supply pin of the half-bridge controller IC. Undervoltage lockout circuit operable to monitor voltage, oscillator circuit providing timing signal with 50% duty cycle, ensuring that duty cycle of timing signal gradually increases from zero to 50% duty cycle The running in A soft start circuit for facilitating a shush current, a high side and a low side driver for providing a MOSFET drive signal and controlling a pair of MOSFETS connected to each other in a half bridge configuration, Unregulated independent board-mounted power module that alternately controls MOSFETS with% duty cycle, and can operate to convert intermediate bus voltage to respective load point voltage to power each load Multiple strictly regulated load point transducers,
A power conversion circuit comprising:   The board-mounted power module includes a primary open loop inverting circuit, a primary bias circuit, a secondary rectification and filtering circuit, and a secondary bias circuit, and the primary open loop inverting circuit is magnetically coupled to the secondary rectification and filtering circuit. 16. The circuit of claim 15, wherein the primary bias circuit is magnetically coupled to the secondary bias circuit, and the secondary rectification and filtering circuit generates the intermediate bus voltage. The power conversion circuit described in 1.   The primary open loop inversion circuit includes a timing resistor and a timing capacitor, and a dead time and a switching frequency of a controller IC are adjusted according to values of the timing resistor and the timing capacitor. Power conversion circuit. The switching frequency is the following formula:
f _s = 1 / (2R ₁ C ₂ )
18. The power conversion circuit according to claim 17, wherein fs is a switching frequency, R1 is a value of a timing resistor, and C2 is a value of a timing capacitor.   The power conversion circuit according to claim 16, wherein the pair of MOSFETS includes direct FETs.   The power of claim 16, wherein the half-bridge controller IC can be driven in at least two modes, one of the modes is a self-oscillating mode and the other of the modes is a synchronous mode. Conversion circuit.

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