JP2006339479A - Multi-layered wiring and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To simultaneously prevent an adhesive layer coverage defect in groove wiring formation and generation of a void after liner etching. <P>SOLUTION: The disclosed method includes the steps of forming, on a substrate 100, a second insulating film 107 so that film thickness on a first wiring layer 106a becomes thinner than film thickness on a first insulating film 101; forming a third insulating film 108 on the second insulating film; forming a connecting hole 109 through the third insulating film to the second insulating film, at a position at least partially overlapping with the first wiring layer in a planar view; and exposing the first wiring layer in an area overlapping with the first wiring layer, on a bottom surface of the connecting hole, and de-etching the second insulating film exposed on the bottom surface of the connecting hole so that the second insulating film becomes residual in an area not overlapping with the first wiring layer on the bottom surface of the connecting hole. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a multilayer wiring and a multilayer wiring, and more particularly to a method for manufacturing a multilayer wiring including a lower layer wiring and an upper layer wiring and a connection hole for connecting them, and the multilayer wiring.

  In recent years, Cu has been used as a wiring material having a small specific resistance in order to reduce wiring delay due to high integration of semiconductor integrated circuits. Damascene technology is used as a general method for forming Cu wiring. In this technique, after forming concave portions such as via holes and wiring grooves in the wiring interlayer insulating film, a conductive film is embedded using a sputtering method, a plating method, and the like, and then a conductive film formed in a region other than the concave portions is formed. Wiring is formed by removing using chemical mechanical polishing (CMP).

  A conventional multilayer wiring manufacturing method will be described below with reference to FIGS. 8 and 9 (for example, Patent Document 1).

As shown in FIG. 8A, after depositing a first insulating film 101 made of SiO ₂ on a semiconductor substrate 100, a resist pattern formed through a lithography process on the insulating film 101 is used as a mask ( The insulating film 101 is dry-etched. By this dry etching, a wiring trench 102 having a width of 200 nm is formed in the insulating film 101 as shown in FIG.

  Next, as shown in FIG. 8B, a conductive film 103 made of a tantalum nitride film having a thickness of 20 nm and a tantalum having a thickness of 20 nm are formed in the wiring groove 102 by sputtering over the entire surface of the insulating film 101. A conductive film 104 made of a film is sequentially deposited. Subsequently, a conductive film 105 made of copper having a thickness of 100 nm is deposited on the conductive film 104 by a sputtering method.

  Next, as shown in FIG. 8C, the conductive film 105 is used as a seed layer, and a copper film 106 is formed by electrolytic plating so that the wiring groove 102 is completely embedded on the entire surface of the conductive film 105. Form. Thereafter, the conductive film 103, 104, 105, 106 in the region other than the wiring groove 102 is removed by using the CMP method so that the formed conductive film remains only in the wiring groove 102.

Next, as shown in FIG. 8D, the second insulating film 107 made of Si ₃ N ₄ having a thickness of 150 nm is formed on the entire upper surface flattened by the CMP method, and then the second insulating film 107 is formed. Then, a third insulating film 108 made of SiO ₂ having a thickness of 900 nm and a fourth insulating film 112 made of a silicon oxynitride film as an antireflection film are sequentially deposited. Thereafter, the third insulating film 108 and the fourth insulating film 112 are dried using the resist pattern formed through the lithography process on the third insulating film 108 and the fourth insulating film 112 as a mask (not shown). Etching is performed to form a connection hole 109 so that the bottom reaches the second insulating film 107. Hereinafter, this process is referred to as via etching in this specification.

  Next, as illustrated in FIG. 9A, a resist 110 is applied by a lithography process to form a wiring groove forming opening pattern around the connection hole 109, and the resist 110 is embedded in the connection hole 109. Then, patterning is performed so as to remain.

  Subsequently, as shown in FIG. 9B, the wiring groove forming opening of the third insulating film 108 including the connection hole 109 in which the resist 110 remains is dry-etched.

  Thereafter, as shown in FIG. 9C, the resist 110 is removed through an ashing and cleaning process, thereby forming a wiring trench 111 having a width of 200 nm and a depth of 400 nm in the insulating film. Hereinafter, this process is referred to as trench etching in this specification.

Subsequently, as shown in FIG. 9D, the entire surface of the third insulating film 108 and the fourth insulating film 112 is dry-etched, and the second insulating film at the bottom of the exposed connection hole 109 is etched. The connection hole 109 that is removed and connected to the wiring is opened. Hereinafter, this process is referred to as liner etching in this specification.
JP 2000-188329 A JP-A-11-163127

  However, in the conventional multilayer wiring manufacturing method, when the wiring and the connection hole have the same size (so-called borderless contact), as shown in FIG. Thus, the bottom of the connection hole sometimes protrudes from the groove wiring, and a gap having a narrow shape is formed at this time.

  If the cleaning is further performed after the liner etching in the state where the gap is formed in this manner, a void may be generated. This is because, as shown in FIG. 10 (b), the cleaning chemical after liner etching is mainly composed of dilute hydrofluoric acid, and the cleaning liquid entering the gap cannot be completely removed in the cleaning process. This is because the oxide film adjacent to the wiring elutes due to the formation of high concentration hydrofluoric acid.

  When this void occurs, defects such as step breakage occur when a conductive film such as an adhesion layer or a seed layer is deposited later by a sputtering method. In addition, a short circuit failure between adjacent wirings and a defective filling of Cu wiring may occur, which may reduce the reliability of the wiring.

  As a method for solving the problems of the conventional method for forming a multilayer wiring, a method for forming an etching suppression layer on the wiring upper layer is disclosed in JP-A-11-163127 (Patent Document 2). This document discloses a wiring formation method in which the wiring structure is changed without changing the wiring dry etching conditions.

  Here, as shown in FIG. 11A, a silicon nitride film 12 is deposited on a semiconductor substrate 11, and a first insulating layer 13 is deposited thereon. Subsequently, an etching suppression layer 14 is deposited. Thereafter, a patterning process is performed using a normal lithography method, and the first insulating layer 13 and the etching suppression layer 14 are simultaneously etched to form the trench wiring 15. Thereafter, after performing a cleaning process by a sputter etching method, an adhesion layer 22 made of Ti and TiN is formed in the wiring groove 15 and the etching suppression layer 14 by using a long distance sputtering method. Thereafter, the metal wiring 23 is embedded in the wiring groove 15.

  Next, as shown in FIG. 11B, a second insulating layer 31 is formed, and an opening 32 is formed by performing a normal lithography method and etching. At this time, since the etching suppression layer 14 is formed of a material that is harder to etch than the second insulating layer 31, the etching is performed even if the opening 32 is formed to be shifted from the wiring groove 15 due to misalignment. Since it stops at the suppression layer 14, void formation by etching can be prevented.

  However, in this multilayer wiring forming method, the etching suppression layer 14 and the first insulating film are simultaneously etched to form a wiring groove, so that the first etching rate higher than that of the etching suppression layer 14 is obtained. The insulating layer is also etched in the lateral direction, and the opening extends in the lateral direction as compared with the etching suppression layer. As a result, the etching suppression layer remains in the shape of a ridge, and an adhesion layer and a barrier metal that are later formed in this portion are not deposited below the etching suppression layer 14, resulting in poor coverage. As a result, disconnection or the like occurs when the Cu film is embedded, resulting in poor plating.

  Therefore, in view of the above, an object of the present invention is to provide a multilayer wiring structure and a method for manufacturing the same, which simultaneously prevent adhesion layer coverage failure during groove wiring formation and void generation after liner etching.

  In order to solve the above-mentioned problem, a manufacturing method of a multilayer wiring according to claim 1 of the present invention includes a first step of forming a first insulating film on a substrate, and a first step in the first insulating film. A second step of forming a wiring trench; a third step of forming a first wiring layer by embedding a conductive film in the first wiring trench; and on the substrate on the first wiring layer. A fourth step of forming the second insulating film so that the film thickness is thinner than the film thickness on the first insulating film; and a second step of forming the third insulating film on the second insulating film. 5 and a connection hole that penetrates the third insulating film and reaches the second insulating film is formed at a position at least partially overlapping the first wiring layer as viewed in a plan view. In the sixth step, the first wiring layer is exposed in a region overlapping the first wiring layer on the bottom surface of the connection hole. The second insulating film exposed on the bottom surface of the connection hole is removed by etching so that the second insulating film remains in a region that does not overlap the first wiring layer on the bottom surface of the connection hole. 7 steps.

  According to the multilayer wiring manufacturing method, the fourth step of forming the second insulating film is performed so that the film thickness on the first wiring layer is thinner than the film thickness on the first insulating film. Therefore, the thickness of the second insulating film on the wiring is made thinner than the thickness other than on the wiring. For this reason, when the connection hole is opened by performing liner etching, the connection hole portion on the wiring is opened first, so that the second insulating film in the other region does not penetrate, so that no void is generated. Therefore, it is possible to form a multilayer wiring having high reliability.

  The multilayer wiring manufacturing method according to claim 2 is the multilayer wiring manufacturing method according to claim 1, wherein the fourth step includes a surface of the first wiring layer by plasma treatment using a gas containing at least hydrogen. And a step of depositing the second insulating film on the first wiring layer having the surface deactivated and the first insulating film.

  According to the multilayer wiring manufacturing method, the fourth step performs the step of inactivating the surface of the first wiring layer by plasma processing using a gas containing at least hydrogen. The growth of the second insulating film on the wiring layer can be suppressed.

  The method of manufacturing a multilayer wiring according to claim 3, wherein a first step of forming a first insulating film on a substrate, a second step of forming a first wiring groove in the first insulating film, A third step of embedding a conductive film in the first wiring trench to form a first wiring layer; and a fourth step of setting the surface height of the first insulating film lower than the surface height of the first wiring layer. Forming a second insulating film on the first wiring layer and the first insulating film, and planarizing a surface of the second insulating film; and A sixth step of forming a third insulating film on the insulating film, and the first wiring as viewed in plan view of a connection hole that reaches the second insulating film through the third insulating film A seventh step of forming at a position at least partially overlapping the layer, and the first wiring layer overlapping the bottom surface of the connection hole In the region where the first wiring layer is exposed and in the region where the first wiring layer does not overlap the bottom surface of the connection hole, the second insulating film remains on the bottom surface of the connection hole. And an eighth step of etching away the exposed second insulating film.

  According to the multilayer wiring manufacturing method, the fourth step of lowering the surface height of the first insulating film below the surface height of the first wiring layer, and on the first wiring layer and the first insulating film In addition to forming the second insulating film and performing the fifth step of flattening the surface of the second insulating film, the thickness of the second insulating film on the wiring is set to the second region in the other region. It is thinner than the insulating film. For this reason, when the liner etching is performed to open the connection hole, the second insulating film in the region other than the groove wiring is not penetrated, so that no void is generated, and a highly reliable multilayer wiring is formed. Can be formed. In the fourth step, since the thickness of the second insulating film in the region outside the trench wiring can be arbitrarily adjusted, the second insulating film in the region other than on the trench wiring accompanying the over-etching amount of the process It is excellent in that it is easy to cope with the amount of shaving.

  According to a fourth aspect of the present invention, in the multilayer wiring manufacturing method according to the third aspect, the fourth step is performed using a chemical mechanical polishing method or a dry etching method.

  According to the multilayer wiring manufacturing method, since the fourth step is performed using a chemical mechanical polishing method or a dry etching method, the surface height of the first insulating film is made lower than the surface height of the first wiring layer. can do.

  The multilayer wiring manufacturing method according to claim 5 is the multilayer wiring manufacturing method according to claim 3 or 4, wherein, in the fourth step, the surface height of the first insulating film is set to be equal to that of the first wiring layer. At least 10 nm lower than the surface height.

  The method of manufacturing a multilayer wiring according to claim 6, wherein a first step of forming a first insulating film on a substrate, a second step of forming a first wiring groove in the first insulating film, A third step of embedding a conductive film in the first wiring trench to form a first wiring layer; a fourth step of modifying the surface layer of the first insulating film; and A fifth step of forming a second insulating film on the first insulating film whose surface layer has been modified; a sixth step of forming a third insulating film on the second insulating film; A seventh step of forming a connection hole penetrating through the insulating film 3 and reaching the second insulating film at a position at least partially overlapping with the first wiring layer in plan view; In the region overlapping the first wiring layer on the bottom surface of the connection hole, the first wiring layer is exposed and the bottom of the connection hole The second insulating film exposed on the bottom surface of the connection hole is removed by etching so that at least the surface layer of the modified first insulating film remains in a region that does not overlap the first wiring layer in FIG. Including an eighth step, and in the fourth step, the etching rate of the surface layer of the modified first insulating film is equal to or lower than the etching rate of the second insulating film.

  According to the multilayer wiring manufacturing method, the fourth step of modifying the surface layer of the first insulating film, and the second insulation on the first wiring layer and the first insulating film whose surface layer has been modified. The fifth step of forming the film is performed, and in the fourth step, the etching rate of the surface layer of the modified first insulating film is equal to or lower than the etching rate of the second insulating film. The surface layer of the first insulating film is modified to a film having an etching rate equal to or lower than that of the second insulating film. As a result, the thickness of the second insulating film on the trench wiring is effectively thinner than the second insulating film in other regions. For this reason, when the liner etching is performed to open the connection hole, the first insulating film in the region other than on the trench wiring is not etched, so that no void is generated, and a highly reliable multilayer wiring is formed. can do. In addition, a layer having a lower etching rate than the first insulating film can be formed in a region other than on the trench wiring by plasma treatment or the like, which is excellent in that the process is simple and easy.

  The multilayer wiring manufacturing method according to claim 7 is the multilayer wiring manufacturing method according to claim 6, wherein the fourth step includes a surface of the first insulating film by plasma treatment using a gas containing at least nitrogen. Nitriding treatment.

  According to the multilayer wiring manufacturing method, the fourth step includes a step of nitriding the surface of the first insulating film by plasma processing using a gas containing at least nitrogen. A nitride layer is formed from the upper layer of the first insulating film.

  The multilayer wiring manufacturing method according to claim 8 is the multilayer wiring manufacturing method according to claim 6 or 7, wherein, in the fourth step, the surface layer of the first insulating film is modified to a depth of at least 10 nm or more. .

  The multilayer wiring manufacturing method according to claim 9, wherein a first step of forming a first insulating film on a substrate, a second step of forming a first wiring groove in the first insulating film, A third step of embedding a conductive film in the first wiring trench to form a first wiring layer; and a fourth step of setting the surface height of the first wiring layer to be lower than the surface height of the first insulating film. A step, a fifth step of modifying the surface layer of the first insulating film, and forming a second insulating film on the first wiring layer and on the first insulating film whose surface layer has been modified. A sixth step; a seventh step of forming a third insulating film on the second insulating film; and a connecting hole that penetrates the third insulating film and reaches the second insulating film. 8th step of forming the first wiring layer at a position at least partially overlapping with the first wiring layer, and the first wiring layer on the bottom surface of the connection hole The first wiring layer is exposed in the overlapping region, and at least the surface layer of the modified first insulating film remains in the region that does not overlap the first wiring layer on the bottom surface of the connection hole. And the ninth step of etching away the second insulating film exposed on the bottom surface of the connection hole. In the fifth step, the etching rate of the surface layer of the modified first insulating film is It is equal to or smaller than the etching rate of the second insulating film.

  According to the multilayer wiring manufacturing method, the fourth step of making the surface height of the first wiring layer lower than the surface height of the first insulating film, and the fifth step of modifying the surface layer of the first insulating film. And a sixth step of forming a second insulating film on the first wiring layer and the first insulating film whose surface layer has been modified. In the fifth step, the modified first insulation is performed. Since the etching rate of the surface layer of the film is equal to or lower than the etching rate of the second insulating film, the upper surface of the wiring is made lower than the upper surface of the first insulating film, and the surface layer of the first insulating film is set to the second layer. A film having an etching rate equal to or lower than that of the first insulating film is modified, and a second insulating film is deposited thereon. For this reason, the thickness of the second insulating film on the trench wiring can be made thinner than the second insulating film in other regions. As a result, when the liner etching is performed to open the connection hole, the first insulating film in the region other than on the trench wiring is not etched, so that no void is generated, and a highly reliable multilayer wiring is formed. Can be formed.

  A multilayer wiring manufacturing method according to a tenth aspect of the present invention is the multilayer wiring manufacturing method according to the ninth aspect, wherein the fourth step is performed using a chemical mechanical polishing method.

  According to the multilayer wiring manufacturing method, since the fourth step is performed using a chemical mechanical polishing method, the surface height of one wiring layer can be made lower than the surface height of the first insulating film.

  The multilayer wiring manufacturing method according to claim 11 is the multilayer wiring manufacturing method according to claim 9 or 10, wherein in the fourth step, the surface layer of the first insulating film is modified to a depth of at least 10 nm or more. .

  13. The multilayer wiring according to claim 12, wherein a first insulating film formed on a substrate, a first wiring layer formed in a wiring groove in the first insulating film, and the first wiring layer A second insulating film formed on and on the first insulating film; a third insulating film formed on the second insulating film; the third insulating film and the second insulating film; A connection hole that penetrates the film and reaches the first wiring layer, and the connection hole is formed at a position at least partially overlapping with the first wiring layer in plan view, The second insulating film remains in a region that does not overlap the first wiring layer on the bottom surface of the connection hole.

  According to the multilayer wiring, the multilayer wiring can be manufactured by the multilayer wiring manufacturing method according to the first or third aspect, and the same effect can be obtained.

  The multilayer wiring according to claim 13 is the multilayer wiring according to claim 12, wherein the film thickness of the second insulating film is the same as the film thickness on the first wiring layer. It is formed to be thinner than the film thickness.

  The multilayer wiring according to claim 14 is formed on a substrate, a first insulating film whose surface layer is modified, a first wiring layer formed in a wiring groove in the first insulating film, A second insulating film formed on the first wiring layer and the first insulating film; a third insulating film formed on the second insulating film; and the third insulating film. And a connection hole that penetrates the second insulating film and reaches the first wiring layer, and the connection hole at least partially overlaps the first wiring layer in plan view. In the region that is formed at the position and does not overlap the first wiring layer on the bottom surface of the connection hole, at least the modified surface layer of the first insulating film remains.

  According to the multilayer wiring, the multilayer wiring can be manufactured by the multilayer wiring manufacturing method according to the sixth or ninth aspect, and similar effects can be obtained.

  The multilayer wiring according to claim 15 is the multilayer wiring according to claim 14, wherein the modified surface layer of the first insulating film contains Si, O, and includes any one of N and C. .

  The multilayer wiring according to claim 16 is the multilayer wiring according to claim 14 or 15, wherein the etching rate of the modified surface layer of the first insulating film is equal to the etching rate of the second insulating film, or Smaller than that.

  The multilayer wiring according to claim 17 is the multilayer wiring according to claim 12, 13, 14, 15 or 16, wherein the second insulating film is less likely to be etched than the first and third insulating films, The selectivity of the etching rate of the first or third insulating film with respect to the second insulating film is at least 2 or more.

  The multilayer wiring according to claim 18 is the multilayer wiring according to claim 12, 13, 14, 15, 16 or 17, wherein the first and third insulating films are made of fluorine-containing silicon oxide film or organic-inorganic hybrid film. Become.

  The multilayer wiring according to claim 19 is the multilayer wiring according to claim 12, 13, 14, 15, 16, 17 or 18, wherein the second insulating film is a silicon nitride film, a silicon oxynitride film, or a carbon-containing silicon. It consists of any one of an oxide film and a silicon carbide film, or a laminated film of two or more of them.

  According to the present invention, even when the connection hole is displaced from the wiring, the bottom of the connection hole is always in the second insulating film in the upper layer or the modified first in the liner etching for opening the connection hole. It is formed in the surface layer of the insulating film. In other words, since the first insulating film in the lower layer is not etched by the liner etching, a portion sandwiched by the first insulating film does not occur. Therefore, it is possible to prevent a defect such as loss of an oxide film due to a cleaning process or a defect that a conductive film is not embedded.

(First embodiment)
Hereinafter, a method for manufacturing a multilayer wiring according to a first embodiment of the present invention will be described with reference to FIGS.

  First, as shown in FIG. 1A, a first insulating film 101 made of a silicon oxide film having a thickness of 1000 nm is deposited on a semiconductor substrate 100 by, for example, a CVD method, and then a lithography process is performed on the insulating film 101. A predetermined region of the insulating film 101 is dry-etched using the resist pattern (not shown) formed through this as a mask to form a wiring groove 102 having a groove width of 200 nm and a groove depth of 400 nm.

  Next, as shown in FIG. 1B, a conductive film 103 made of a tantalum nitride film having a thickness of 20 nm and a tantalum film having a thickness of 20 nm are formed on the entire surface of the insulating film 101 including the inside of the wiring trench 102 by sputtering. A conductive film 104 is deposited. Subsequently, a conductive film 105 made of a copper film having a thickness of 100 nm is deposited on the conductive film 104 by a sputtering method.

  Next, as shown in FIG. 1C, a conductive film 106 made of a copper film is grown on the seed layer by electrolytic plating using the conductive film 105 as a seed layer so that the trench for wiring is completely filled. . At this time, a growth inhibitor is added so that the growth rate of the copper film other than the wiring groove region is suppressed so that the wiring groove 102 is completely filled.

  Next, as shown in FIG. 1 (d), the copper film is removed by using a CMP method so that the polishing rate of the tantalum film or the tantalum nitride film with respect to each copper film is 1:40. To do. Thereafter, the tantalum film and the nitrogen tantalum film are polished by CMP using polishing conditions such that the polishing rate of the tantalum film or the tantalum nitride film with respect to each silicon oxide film is 40: 1. The conductive film is completely removed. In this way, the embedded wiring is completed.

  Next, as shown in FIG. 1E, after the upper portion of the copper wiring 106a is inactivated using hydrogen plasma treatment, a second insulating film 107 made of a silicon nitride film having a thickness of 150 nm is formed by, for example, plasma CVD. Deposit by the method. Here, the reason why the upper part of the copper wiring 106a is inactivated using hydrogen plasma treatment is to suppress the growth of the silicon nitride film on the copper wiring 106a by this treatment. Details will be described later.

As an example of the growth conditions of the plasma nitride film, SiH ₄ : 500 sccm and N ₂ : 1400 sccm were used as process gases, the pressure during film growth was set to 2 Torr, and the RF power of the apparatus was set to 600 W.

As an example of the hydrogen plasma treatment conditions, H ₂ : 200 sccm and Ar: 800 sccm were used as the plasma introduction gas, the pressure in the chamber atmosphere was set at 2 Torr, and the substrate temperature was set at 400 ° C.

  In this way, by reducing the growth rate of the second insulating film 107 on the trench wiring 106a, the thickness of the second insulating film 107 on the trench wiring 106a becomes about 110 nm, and the second insulating film 107 on the trench wiring 106a has a thickness of about 110 nm. The thickness of the second insulating film 107 can be made thinner than the thickness of 150 nm of the second insulating film 107 in a region other than on the trench wiring.

  Next, as shown in FIG. 1F, a 900 nm-thickness third insulating film 108 made of a silicon oxide film is deposited by, for example, a CVD method, and subsequently a film thickness made of a silicon oxynitride film as an antireflection film. A 60 nm fourth insulating film 112 is deposited by using, for example, a plasma CVD method. Subsequently, using the resist pattern (not shown) formed through the lithography process as a mask, the insulating films 108 and 112 are dry-etched to form connection holes with an opening diameter of 200 nm. At this time, dry etching conditions in which the etching selectivity of the third insulating film 108 to the second insulating film 107 is 10 or more are applied. As a result, the second insulating film 107 is hardly shaved, and the bottom of the connection hole is formed in the second insulating film 107.

As an example of the dry etching conditions, C ₅ F ₈ : 20 sccm, Ar: 600 sccm, and O ₂ : 20 sccm are used as the etching gas, the pressure of the etching atmosphere is 15 Pa, a two-frequency RIE type etching apparatus is used, and RF power is used. The upper electrode 1600W, the lower electrode 800W, and the substrate temperature was set to 20 ° C.

  Next, as shown in FIG. 2A, a resist 110 is applied by a lithography process to form a wiring groove forming opening pattern around the connection hole 109 and the resist 110 is embedded in the connection hole 109. Then, patterning is performed so as to remain.

  In this resist patterning, a wiring groove pattern can be formed in the periphery of the connection hole 109 in order to focus on a portion where the wiring groove is to be formed, and the exposure focus is not focused in the connection hole. The resist 110 can remain on the side closer to the bottom than the center.

  Next, as shown in FIG. 2B, the insulating films 108 and 112 are dry-etched using the wiring groove forming opening pattern as a mask to form a wiring groove 111 having a width of 200 nm and a depth of 400 nm.

As an example of the dry etching conditions, a two-frequency RIE type etching apparatus is used, the etching gas is C ₅ F ₈ : 25 sccm, Ar: 600 sccm, O ₂ : 20 sccm, the etching atmosphere pressure is 10 Pa, and RF power is used. The upper electrode 1500W, the lower electrode 800W, and the substrate temperature were set to 50 ° C.

  Next, as shown in FIG. 2C, the resist 110 is removed through ashing and cleaning steps. Thereby, the resist remaining in the connection hole is removed. Thereafter, the connection hole is opened by dry etching the insulating film 107 exposed in the connection hole.

As an example of the dry etching conditions, a two-frequency RIE etching apparatus is used, the etching gas is CHF ₃ : 10 sccm, Ar: 600 sccm, O ₂ : 10 sccm, the etching atmosphere pressure is 15 Pa, and the etching apparatus RF The power was set to the upper electrode 1100W, the lower electrode 800W, and the substrate temperature was set to 20 ° C.

  Thereafter, the groove wiring can be formed by forming the copper wiring using a technique similar to the technique for forming the groove wiring 106a, and the connection hole and the upper layer wiring can be formed.

  According to the first embodiment, the thickness immediately after deposition of the second insulating film 107 is 110 nm on the first groove wiring 106 a of the lower layer wiring and 150 nm on the outside of the groove wiring.

  This can be explained as follows from the relationship between the hydrogen plasma processing time and the SiN film growth rate shown in FIG. It can be seen that when the plasma treatment is performed on the trench wiring, the deposition rate of the initial SiN film on the trench wiring is lower than that of the sample not subjected to the treatment. This is because the hydrogen treatment terminates the dangling bonds on the metal surface in the same manner as the hydrogen termination effect on the Si substrate, resulting in an inactive state. This suppresses the growth rate of the silicon nitride film deposited initially on the copper wiring. As a result, the silicon nitride film on the copper wiring is formed thinner than the silicon nitride film other than on the copper wiring.

  In order to prevent foreign matters from adhering to the surface, it is desirable that the hydrogen plasma treatment and the nitride film deposition be performed in the same chamber. As a result, the thickness immediately after deposition of the second insulating film 107 is 110 nm for the thickness of the lower layer wiring on the first groove wiring 106 a and 150 nm for the thickness outside the groove wiring 106 a.

  Even if the second insulating film 107 is shaved by about 10 nm by over-etching of the via etching, the second insulating film 107 has a film thickness of 100 nm on the groove wiring 106a as shown in FIG. Otherwise, the film thickness is 140 nm. Further, when performing liner etching for opening the trench wiring 106a and the connection hole 109 of the lower layer wiring, even if 20% over-etching is applied to eliminate the opening defect, the amount of abrasion of the second insulating film 107 is 120 nm. In addition, the thickness of the second insulating film 107 outside the trench wiring 106a is 20 nm, and the second insulating film 107 remains on the first insulating film 101, and generation of voids and the like can be completely prevented. .

  In the present embodiment, the case where the wiring is formed above the connection hole has been described. However, the same effect can be obtained even if the connection hole is used alone.

  As the first insulating film 101 and the third insulating film 108, for example, a low dielectric constant film such as SiOF (fluorine-containing silicon oxide film) or SiOC (carbon-containing silicon oxide film), an organic-inorganic hybrid film, or the like is used. A layer or a laminated film can be used. In particular, the use of a low dielectric constant film is preferable because the capacitance between wirings can be reduced.

Further, as the second insulating film 107, for example, SiON (silicon oxynitride film), SiOC (carbon-containing silicon oxide film), or SiC (silicon carbide film) having a low dielectric constant can be used instead of the silicon nitride film. .
(Second Embodiment)
Hereinafter, a method of manufacturing a multilayer wiring according to the second embodiment of the present invention will be described with reference to FIG.

  First, according to the same method as in the first embodiment, as shown in FIG.

  Next, as shown in FIG. 4B, the first insulating film 101 is polished using a CMP method under such polishing conditions that the polishing rate of the silicon oxide film with respect to the copper film is 40: 1. A process of exposing the upper surface of the trench wiring 106 a to an upper surface of about 50 nm from the first insulating film 101 is performed.

  In the conventional example, the conductive film is simply deposited in the wiring groove and polished so as to leave the conductive film, and the upper surface of the groove wiring is formed on the lower surface than the first insulating film. The point is greatly different from the present invention.

  Next, as shown in FIG. 4C, a 200 nm-thick second insulating film 107 made of a silicon nitride film is deposited by, for example, plasma CVD. After that, the second insulating film 107 is polished by about 100 nm using a CMP method, and a planarization process is performed. As a result, the silicon nitride film is deposited on the trench wiring 106a by about 50 nm, and the silicon nitride film is deposited on the first insulating layer 101 by about 100 nm.

  Next, as shown in FIG. 4D, a third insulating layer 108 made of a silicon oxide film having a thickness of 900 nm is deposited by, for example, a CVD method, and subsequently a film thickness made of a silicon oxynitride film as an antireflection film. A 60 nm fourth insulating film 112 is deposited by using, for example, a plasma CVD method. Subsequently, the insulating films 108 and 112 are dry-etched using a resist pattern (not shown) formed on the insulating films 108 and 112 through a lithography process as a mask to form a connection hole 109 having an opening diameter of 200 nm. At this time, dry etching conditions in which the etching selectivity of the third insulating film 108 with respect to the second insulating film 107 is 10 or more are applied. Thereby, the second insulating film 107 is hardly etched.

As an example of the dry etching conditions, a two-frequency RIE type etching apparatus is used, the etching gas is C ₅ F ₈ : 20 sccm, Ar: 600 sccm, O ₂ : 20 sccm, the etching atmosphere pressure is 15 Pa, and the upper electrode The RF power was set to 1500 W, the lower electrode RF power was set to 800 W, and the substrate temperature was set to 20 ° C.

  The subsequent steps are processed using the same method as in the first embodiment to form the multilayer wiring shown in FIG.

  According to the second embodiment, the thickness immediately after depositing and polishing the second insulating film 107 is 50 nm on the trench wiring 106 a of the lower layer wiring and 100 nm on the thickness other than the trench wiring. .

  Even if the SiN film thickness is reduced by about 10 nm by over-etching of the via etching, as shown in FIG. 4D, the second insulating film 107 has a film thickness of 40 nm on the groove wiring 106a and is not formed on the groove wiring. The thickness is 90 nm. Further, when performing liner etching for opening the trench wiring 106a and the connection hole 109 of the lower layer wiring, even if 20% over-etching is applied to eliminate the opening defect, the scraping amount of the second insulating film 107 is 48 nm. In addition, in a region other than on the trench wiring 106a, only about 8 nm can be scraped from the upper surface of the trench wiring, so that the occurrence of void defects can be completely prevented.

  In the present embodiment, in the step of polishing the first insulating film 101 and exposing the upper surface of the groove wiring 106a to the upper surface of the first insulating film 101, the thickness of the second insulating film 107 in the region outside the groove wiring is set. It can be adjusted arbitrarily. For this reason, it is excellent in that it is easy to cope with the amount of abrasion of the second insulating film 107 in the region other than on the trench wiring due to the over-etching amount of the process.

  As the first insulating film 101 and the third insulating film 108, for example, a low dielectric constant film such as SiOF (fluorine-containing silicon oxide film) or SiOC (carbon-containing silicon oxide film), an organic-inorganic hybrid film, or the like is used. A layer or a laminated film can be used. In particular, the use of a low dielectric constant film is preferable because the capacitance between wirings can be reduced.

Further, as the second insulating film 107, for example, SiON (silicon oxynitride film), SiOC (carbon-containing silicon oxide film), or SiC (silicon carbide film) having a low dielectric constant can be used instead of the silicon nitride film. .
(Third embodiment)
A multilayer wiring manufacturing method according to the third embodiment of the present invention will be described below with reference to FIGS.

  First, according to the same method as in the first embodiment, as shown in FIG.

  Next, as shown in FIG. 5B, the upper portion of the first insulating film 101 is nitrided using nitrogen plasma processing. By performing this nitriding treatment, a nitride layer 107A of about 40 nm is formed from the upper layer of the first insulating film 101.

As an example of the nitrogen plasma treatment conditions, N ₂ : 1400 sccm and Ar: 800 sccm were used as the plasma introduction gas, the chamber atmosphere pressure was set to 2 Pa, and the substrate temperature was set to 400 ° C.

  Next, as shown in FIG. 5C, a second insulating film 107 having a thickness of 150 nm made of a silicon nitride film is deposited by, for example, plasma CVD. By doing so, the thickness of the second insulating film 107 on the wiring groove 102 is 150 nm, and in a region other than on the wiring groove 102, the nitride layer 107A of about 40 nm and the second insulating film 107 of 150 nm are formed. A combined 190 nm film is formed. Subsequently, a 900 nm-thick third insulating film 108 made of a silicon oxide film is deposited by, for example, a CVD method, and then a 60 nm-thickness fourth insulating film 112 made of a silicon oxynitride film is used as an antireflection film, for example. Deposition using a plasma CVD method.

  Subsequently, using the resist pattern (not shown) formed through the lithography process as a mask, the third insulating film 108 and the fourth insulating film 112 are dry-etched to form a connection hole 109 having an opening diameter of 200 nm. At this time, dry etching conditions are applied in which the etching selectivity of the third insulating film 108 to the second insulating film 107 is 10 or more. Thereby, the second insulating film 107 is hardly etched.

As an example of the dry etching conditions, a two-frequency RIE type etching apparatus is used, C ₅ F ₈ : 20 sccm, Ar: 600 sccm, and O ₂ : 20 sccm are used as etching gases, and RF power is set to the upper electrode 1500 W and the lower electrode. The pressure in the etching atmosphere was set to 15 Pa, and the substrate temperature was set to 20 ° C.

  The subsequent steps are processed using the same method as in the first embodiment to form the multilayer wiring shown in FIG.

  According to the third embodiment, the nitride layer 107 </ b> A can be formed on the surface layer of the first insulating film 101. FIG. 6 shows the relationship between the depth of the nitride layer 107A and the nitrogen plasma treatment time.

  It can be seen from FIG. 6 that the nitriding proceeds in the depth direction of the first insulating film as the plasma processing time becomes longer, but the nitriding stops as the processing proceeds for 30 seconds or longer. This is considered to be because the nitridation of the surface layer of the first insulating film 101 is completed and a dense film is formed. By this nitrogen plasma treatment, a nitride layer 107A of about 40 nm is formed from the upper layer of the first insulating film 101.

  Further, the surface of the first wiring 106a is nitrided by the nitrogen plasma treatment, but since the nitride layer on the surface of the wiring is removed in the liner etching process that opens the connection hole 109, conduction between the wiring layers is secured, which is a problem. There is no.

  Although the film thickness of the second insulating film 107 immediately after deposition is 150 nm, the SiN film thickness is reduced by about 10 nm by overetching of the via etching, so that the second insulating film 107 has a thickness as shown in FIG. The thickness is 140 nm. Subsequently, when liner etching for opening the first trench wiring 106a and the connection hole 109 of the lower layer wiring is performed, if 20% over-etching is applied to eliminate the opening defect, the amount of the second insulating film 107 is removed. Is 168 nm. However, since the nitride layer 107A exists after etching the second insulating film 107 in a region other than on the trench wiring 106a, the etching rate of the nitride layer 107A is almost equal to that of the second insulating film 107. As a result, the nitride layer 107A remains 12 nm, and the bottom of the connection hole 109 does not reach the first insulating film 101, so that the occurrence of void defects can be completely prevented.

  If the nitride layer 107A is not present, a void is generated. As a result, a step failure occurs when the conductive films 103, 104, and 105 are deposited, resulting in a void failure.

  In the third embodiment, a layer having a lower etching rate than that of the first insulating film 101 can be formed by plasma treatment in a region other than on the trench wiring 106a. Therefore, the process is simpler than that of the second embodiment. It is excellent in that it is easy.

  In the present embodiment, the case where the wiring is formed above the connection hole 109 has been described. However, the same effect can be obtained even if the connection hole alone is used.

  As the first insulating film 101 and the third insulating film 108, for example, a low dielectric constant film such as SiOF (fluorine-containing silicon oxide film) or SiOC (carbon-containing silicon oxide film), an organic-inorganic hybrid film, or the like is used. A layer or a laminated film can be used. In particular, the use of a low dielectric constant film is preferable because the capacitance between wirings can be reduced.

Further, as the second insulating film 107, for example, SiON (silicon oxynitride film), SiOC (carbon-containing silicon oxide film), or SiC (silicon carbide film) having a low dielectric constant can be used instead of the silicon nitride film. .
(Fourth embodiment)
A method for manufacturing a multilayer wiring according to the fourth embodiment of the present invention will be described below with reference to FIG.

  First, according to the same method as in the first embodiment, as shown in FIG.

  Next, as shown in FIG. 7 (b), the groove wiring 106a is polished by using the CMP method and polishing conditions such that the polishing rate of the copper film to the silicon oxide film is 40: 1. A process of polishing the upper surface of the first insulating film 101 to a lower surface of about 40 nm than the first insulating film 101 is performed.

  Next, as in the third embodiment, as shown in FIG. 7C, the upper portion of the first insulating film 101 is nitrided using nitrogen plasma processing. By this nitrogen plasma treatment, a nitride layer 107A having a thickness of about 40 nm is formed from the upper surface of the first insulating film 101.

  Next, as shown in FIG. 7D, a second insulating film 107 made of a silicon nitride film and having a thickness of 150 nm is deposited by, for example, plasma CVD. By doing so, the thickness of the second insulating film 107 on the wiring groove 102 is 150 nm, and in a region other than on the wiring groove 102, the nitride layer 107A of about 40 nm and the second insulating film 107 of 150 nm are formed. A combined 190 nm film is formed.

  Subsequently, a 900 nm-thick third insulating film 108 made of a silicon oxide film is deposited by, for example, a CVD method, and then a 60 nm-thickness fourth insulating film 112 made of a silicon oxynitride film as an antireflection film (FIG. 5 (c) etc.) is deposited using, for example, plasma CVD.

  Subsequently, using the resist pattern (not shown) formed through the lithography process as a mask, the third insulating film 108 and the fourth insulating film 112 are dry-etched to form a connection hole with an opening diameter of 200 nm. At this time, dry etching conditions are applied in which the etching selectivity of the third insulating film 108 to the second insulating film 107 is 10 or more. Thereby, the second insulating film 107 is hardly etched.

As an example of the dry etching conditions, a two-frequency RIE type etching apparatus is used, C ₅ F ₈ : 20 sccm, Ar: 600 sccm, and O ₂ : 20 sccm are used as etching gases, and RF power is set to the upper electrode 1500 W and the lower electrode. The pressure in the etching atmosphere was set to 15 Pa, and the substrate temperature was set to 20 ° C.

  The subsequent steps are processed using the same method as in the first embodiment to form the multilayer wiring shown in FIG.

  According to the fourth embodiment, the thickness immediately after deposition of the second insulating film 107 is such that the thickness of the lower layer wiring on the first groove wiring 106a is 150 nm and the thickness outside the groove wiring is the second thickness. The insulating film 107 is 150 nm, the nitride layer 107A is 40 nm, and the total is 190 nm.

  Even if the second insulating film 107 is shaved by about 10 nm by over-etching of the via etching, as shown in FIG. 7D, the film thickness is 140 nm on the groove wiring 106 a and the film thickness is 180 nm on other than the groove wiring. Become. Further, when performing liner etching to open the trench wiring 106a of the lower layer wiring and the connection hole, even if 20% overetching is performed to eliminate the opening defect, the amount of abrasion of the second insulating film 107 and the nitride layer 107A is reduced. The total thickness is 168 nm, the film thickness on the portion other than the trench wiring is 12 nm, and the second insulating film 107 remains on the first insulating film 101. For this reason, generation | occurrence | production of a void etc. can be prevented completely. At this time, the etching rates of the second insulating film 107 and the nitride layer 107A are substantially equal. Even if the amount of over-etching increases and the second insulating film 107 does not remain other than on the trench wiring, the lower nitride layer 107A remains. For this reason, generation | occurrence | production of a void etc. can be prevented completely.

  In the fourth embodiment, the nitride layer 107A is formed into the first groove wiring by the height control of the groove wiring 106a by the CMP method in FIG. 7B and the film thickness control of the nitride layer 107A in FIG. 7C. It is possible to control so as to be formed only above the height of the surface of 106a. In this way, the nitride layer 107A is not formed on the lateral portion of the trench wiring 106a. For this reason, the effect that the interlayer capacity | capacitance with adjacent wiring is not raised is acquired.

  In the present embodiment, the case where the wiring is formed above the connection hole 109 has been described. However, the same effect can be obtained even if the connection hole alone is used.

  As the first insulating film 101 and the third insulating film 108, for example, a low dielectric constant film such as SiOF (fluorine-containing silicon oxide film) or SiOC (carbon-containing silicon oxide film), an organic-inorganic hybrid film, or the like is used. A layer or a laminated film can be used. In particular, the use of a low dielectric constant film is preferable because the capacitance between wirings can be reduced.

  Further, as the second insulating film 107, for example, SiON (silicon oxynitride film), SiOC (carbon-containing silicon oxide film), or SiC (silicon carbide film) having a low dielectric constant can be used instead of the silicon nitride film. .

  The multilayer wiring manufacturing method and multilayer wiring according to the present invention can simultaneously prevent the adhesion layer coverage defect at the time of trench wiring formation and the occurrence of voids after liner etching. This is useful in a method for manufacturing a multilayer wiring having a connection hole to be connected and in the multilayer wiring.

It is sectional drawing which shows each process of the manufacturing method of the multilayer wiring which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows each next process of FIG. The SIN deposition time and the SiN deposition thickness relationships as those conducted with H ₂ plasma treatment, shows a comparison of those not. It is sectional drawing which shows each process of the manufacturing method of the multilayer wiring which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows each process of the manufacturing method of the multilayer wiring which concerns on the 3rd Embodiment of this invention. It is the figure which showed the nitriding time and the amount of nitriding of the surface layer of the 1st insulating film. It is sectional drawing which shows each process of the manufacturing method of the multilayer wiring which concerns on the 4th Embodiment of this invention. It is sectional drawing which shows each process of the manufacturing method of the conventional multilayer wiring. FIG. 9 is a cross-sectional view showing each step subsequent to FIG. 8. (a), (b) is the cross-sectional schematic diagram of the defect which generate | occur | produced with the manufacturing method of the conventional multilayer wiring. (1), (2) is sectional drawing which shows the manufacturing method of a prior document.

Explanation of symbols

100 Semiconductor substrate 101 First insulating film 102 Trench for wiring First insulating film 103 Tantalum nitride film 104 Tantalum film 105 Copper film 106 Copper film 107 Second insulating film (Si ₃ N ₄ )
108 Third insulating film (SiO ₂ )
109 Connection hole 110 Resist 111 Wiring groove 112 Fourth insulating film (SiON)
107A Nitride layer

Claims (19)

A first step of forming a first insulating film on the substrate;
A second step of forming a first wiring trench in the first insulating film;
A third step of embedding a conductive film in the first wiring trench to form a first wiring layer;
A fourth step of forming a second insulating film on the substrate such that a film thickness on the first wiring layer is thinner than a film thickness on the first insulating film;
A fifth step of forming a third insulating film on the second insulating film;
A sixth step of forming a connection hole penetrating the third insulating film and reaching the second insulating film at a position at least partially overlapping with the first wiring layer as viewed in plan; ,
The first wiring layer is exposed in a region overlapping the first wiring layer on the bottom surface of the connection hole, and the second wiring is exposed in a region not overlapping with the first wiring layer on the bottom surface of the connection hole. And a seventh step of etching away the second insulating film exposed on the bottom surface of the connection hole so that the insulating film remains.   The fourth step includes a step of inactivating the surface of the first wiring layer by a plasma treatment using a gas containing at least hydrogen, the first wiring layer having the surface deactivated, and the step The method of manufacturing a multilayer wiring according to claim 1, further comprising: depositing the second insulating film on the first insulating film. A first step of forming a first insulating film on the substrate;
A second step of forming a first wiring trench in the first insulating film;
A third step of embedding a conductive film in the first wiring trench to form a first wiring layer;
A fourth step of making the surface height of the first insulating film lower than the surface height of the first wiring layer;
Forming a second insulating film on the first wiring layer and on the first insulating film, and planarizing a surface of the second insulating film;
A sixth step of forming a third insulating film on the second insulating film;
A seventh step of forming a connection hole penetrating the third insulating film and reaching the second insulating film at a position at least partially overlapping with the first wiring layer in plan view; ,
The first wiring layer is exposed in a region overlapping the first wiring layer on the bottom surface of the connection hole, and the second wiring is exposed in a region not overlapping with the first wiring layer on the bottom surface of the connection hole. And an eighth step of etching away the second insulating film exposed on the bottom surface of the connection hole so that the insulating film remains.   4. The method of manufacturing a multilayer wiring according to claim 3, wherein the fourth step is performed using a chemical mechanical polishing method or a dry etching method.   5. The method of manufacturing a multilayer wiring according to claim 3, wherein, in the fourth step, the surface height of the first insulating film is made at least 10 nm lower than the surface height of the first wiring layer. A first step of forming a first insulating film on the substrate;
A second step of forming a first wiring trench in the first insulating film;
A third step of embedding a conductive film in the first wiring trench to form a first wiring layer;
A fourth step of modifying the surface layer of the first insulating film;
A fifth step of forming a second insulating film on the first wiring layer and on the first insulating film whose surface layer has been modified;
A sixth step of forming a third insulating film on the second insulating film;
A seventh step of forming a connection hole penetrating the third insulating film and reaching the second insulating film at a position at least partially overlapping with the first wiring layer in plan view; ,
The first wiring layer is exposed in a region overlapping the first wiring layer on the bottom surface of the connection hole, and at least in the region not overlapping with the first wiring layer on the bottom surface of the connection hole. An eighth step of etching away the second insulating film exposed on the bottom surface of the connection hole so that the surface layer of the first insulating film thus formed remains.
In the fourth step, the etching rate of the surface layer of the modified first insulating film is equal to or lower than the etching rate of the second insulating film.   7. The method of manufacturing a multilayer wiring according to claim 6, wherein the fourth step includes a step of nitriding the surface of the first insulating film by plasma processing using a gas containing at least nitrogen.   8. The method of manufacturing a multilayer wiring according to claim 6, wherein in the fourth step, the surface layer of the first insulating film is modified to a depth of at least 10 nm or more. A first step of forming a first insulating film on the substrate;
A second step of forming a first wiring trench in the first insulating film;
A third step of embedding a conductive film in the first wiring trench to form a first wiring layer;
A fourth step of making the surface height of the first wiring layer lower than the surface height of the first insulating film;
A fifth step of modifying the surface layer of the first insulating film;
A sixth step of forming a second insulating film on the first wiring layer and on the first insulating film whose surface layer has been modified;
A seventh step of forming a third insulating film on the second insulating film;
An eighth step of forming a connection hole penetrating through the third insulating film and reaching the second insulating film at a position at least partially overlapping with the first wiring layer in plan view; ,
The first wiring layer is exposed in a region overlapping the first wiring layer on the bottom surface of the connection hole, and at least in the region not overlapping with the first wiring layer on the bottom surface of the connection hole. A ninth step of etching away the second insulating film exposed on the bottom surface of the connection hole so that the surface layer of the first insulating film thus formed remains,
In the fifth step, the multilayer wiring manufacturing method is characterized in that an etching rate of a surface layer of the modified first insulating film is equal to or lower than an etching rate of the second insulating film.   The method for manufacturing a multilayer wiring according to claim 9, wherein the fourth step is performed using a chemical mechanical polishing method.   11. The method of manufacturing a multilayer wiring according to claim 9, wherein in the fourth step, the surface layer of the first insulating film is modified to a depth of at least 10 nm or more. A first insulating film formed on the substrate;
A first wiring layer formed in a wiring trench in the first insulating film;
A second insulating film formed on the first wiring layer and on the first insulating film;
A third insulating film formed on the second insulating film;
A connection hole penetrating through the third insulating film and the second insulating film and reaching the first wiring layer,
The connection hole is formed at a position where at least part of the connection hole overlaps with the first wiring layer in plan view,
The multilayer wiring, wherein the second insulating film remains in a region of the bottom surface of the connection hole that does not overlap with the first wiring layer.   13. The multilayer according to claim 12, wherein the film thickness of the second insulating film is formed such that the film thickness on the first wiring layer is thinner than the film thickness on the first insulating film. wiring. A first insulating film formed on the substrate and having a modified surface layer;
A first wiring layer formed in a wiring trench in the first insulating film;
A second insulating film formed on the first wiring layer and on the first insulating film;
A third insulating film formed on the second insulating film;
A connection hole that penetrates through the third insulating film and the second insulating film and reaches the first wiring layer,
The connection hole is formed at a position where at least part of the connection hole overlaps with the first wiring layer in plan view,
The multilayer wiring according to claim 1, wherein at least a modified surface layer of the first insulating film remains in a region of the bottom surface of the connection hole that does not overlap with the first wiring layer.   The multilayer wiring according to claim 14, wherein the modified surface layer of the first insulating film contains Si and O, and includes any one of N and C.   The multilayer wiring according to claim 14 or 15, wherein an etching rate of the modified surface layer of the first insulating film is equal to or lower than an etching rate of the second insulating film.   The second insulating film is less likely to be etched than the first and third insulating films, and the selectivity of the etching rate of the first or third insulating film with respect to the second insulating film is at least 2 or more. The multilayer wiring according to claim 12, 13, 14, 15, or 16.   The multilayer wiring according to claim 12, 13, 14, 15, 16 or 17, wherein the first and third insulating films are made of a fluorine-containing silicon oxide film or an organic-inorganic hybrid film.   14. The second insulating film is formed of any one of a silicon nitride film, a silicon oxynitride film, a carbon-containing silicon oxide film, and a silicon carbide film, or a laminated film of two or more of them. , 14, 15, 16, 17 or 18.

Images