JP2006319096A - Schottky barrier diode - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a Schottky barrier diode for easy integration with MOSFET capable of flowing a current of wanted capacity at a low resistance, even if an SOI substrate is used. <P>SOLUTION: A plurality of low-concentration n-type SOI layers 12 and a plurality of high-concentration n-type SOI layers 13 are alternately formed, and arranged side by side. A silicide layer 7 is formed on the low-concentration n-type SOI layer 12. The silicide layer 7 and the low-concentration n-type SOI layer 12 form a Schottky junction. Since the distance is shortened between the silicide layer 7 and the high-concentration n-type SOI layer 13, a resistance can be reduced. By increasing the number of silicide layer 7, the current of wanted capacity can be allowed to flow. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a Schottky barrier diode applicable to high frequency products.

  A Schottky barrier diode (SBD) is used for a high-frequency switching regulator or the like by using the low forward voltage Vf.

  Also, thin-film SOI (Silicon On Insulator) -MOSFETs suitable for high-speed operation are about to be used for high-frequency applications, but SBDs are also formed on the same SOI substrate as MOSFETs, so that MOS circuits including SBDs can be integrated. Can be planned.

  However, when the SBD is formed on the SOI substrate, the silicon film (SOI film) of the SOI substrate is thin, so that a low resistance high-concentration N type buried diffusion layer cannot be provided on the SOI film.

  Therefore, the resistance between the anode electrode and the cathode electrode (on-resistance) is increased, and there is a problem that the operation speed is reduced and a desired current cannot flow.

  Therefore, the invention described in Patent Document 1 uses an SOI substrate having a buried oxide film layer inside, and extends from one main surface side of the substrate to the surface of the buried oxide film layer or through the buried oxide film layer. A plurality of trenches are formed by digging up to the surface of the substrate of the SOI substrate, and the convex blocks formed between adjacent trenches are diffused laterally into the N-layer having a low impurity concentration from the side surfaces of the trenches. Then, a high impurity concentration N + layer is formed, a barrier metal layer is formed at least in the trench on the anode electrode side, and then the anode is formed in the trench having the barrier metal layer and the trench facing the convex block. Each of the electrodes and the cathode electrode is formed, and the device current is formed so as to flow in the horizontal direction, not in the vertical direction, with respect to the main surface of the SOI substrate.

  Therefore, by disposing the anode electrode near the N + layer, the distance of the high resistance N− layer can be shortened and the resistance can be lowered.

JP 2004-55627 A

  However, in the invention described in Patent Document 1, it is necessary to add a process of forming a trench, and it cannot be formed in the same process as the MOSFET. For this reason, if the SBD and the MOSFET are formed on the same substrate, the manufacturing process becomes complicated.

  Moreover, since it is necessary to embed an electrode material in the trench, it is necessary to increase the shape of the trench. Therefore, it is difficult to reduce the element area.

  Furthermore, when the trench is formed, it is difficult to form a multilayer wiring on the upper portion.

  As described above, the SBD described in Patent Document 1 has low consistency with the MOSFET manufacturing process, and it is difficult to form the SBD on the same SOI substrate as the MOSFET.

  Accordingly, an object of the present invention is to provide a Schottky barrier diode that can be easily integrated with a MOSFET and can flow a current of a desired magnitude with a low resistance even when an SOI substrate is used. is there.

  The invention according to claim 1 is a Schottky barrier diode formed on an SOI substrate, the device isolation film formed so as to surround the active region of the SOI substrate, and the high concentration formed in the active region A diffusion layer; a low concentration diffusion layer formed adjacent to the high concentration diffusion layer; and a silicide layer formed on the low concentration diffusion layer and forming a Schottky junction with the low concentration diffusion layer. The high-concentration diffusion layer and the low-concentration diffusion layer are alternately arranged.

  According to the first aspect of the present invention, since the low-concentration diffusion layers and the high-concentration diffusion layers are alternately arranged adjacent to each other, the silicide layer forming the Schottky junction is located near the high-concentration diffusion layers on both sides. Can be arranged. For this reason, the distance through which the forward current flows through the low-concentration diffusion layer with high resistance is shortened, so that the on-resistance can be lowered.

  Further, by adjusting the number of Schottky junctions, it is possible to flow a desired current while reducing the resistance.

  Furthermore, since it can be formed by the same process as the MOSFET manufacturing process, the MOSFET and the Schottky barrier diode can be formed on the same substrate without increasing the manufacturing cost due to the complexity of the manufacturing process.

<Embodiment 1>
<A. Configuration>
FIG. 1 is a cross-sectional view showing the configuration of the Schottky barrier diode according to the present embodiment. FIG. 2 shows a top view of the Schottky barrier diode according to the present embodiment. Here, FIG. 1 corresponds to a cross-sectional view taken along line AA of FIG.

  A buried oxide film 11 is formed on the silicon substrate 1. A plurality (2 in the example of FIG. 1) of low concentration N-type SOI layers (N− layer: low concentration diffusion layer) 12 and a plurality of active regions (regions where Schottky barrier diodes are formed) on the buried oxide film 11 are formed. High-concentration N-type SOI layers (N + layer: high-concentration diffusion layer) 13 (3 in the example of FIG. 1) are alternately formed adjacent to each other.

  That is, the N + layer 13 is formed in the active region, the N− layer 12 is formed adjacent to the N + layer 13, and the N + layer 13 and the N− layer 12 are alternately arranged.

  As shown in FIG. 2, the N + layer 13 is formed so as to surround the N− layer 12 when viewed from above. An element isolation insulating film (hereinafter sometimes referred to as “element isolation film”) 4 is formed on the buried oxide film 11 so as to surround the active region of the SOI substrate.

  An anode-side silicide layer 7 (hereinafter sometimes simply referred to as “silicide layer 7”) is formed on the low-concentration N-type SOI layer 12, and a cathode-side silicide layer 8 is formed on the high-concentration N-type SOI layer 13. (Hereinafter may be simply referred to as “silicide layer 8”).

  The silicide layers 7 are connected to each other by wiring 9. Further, the silicide layers 8 are connected to each other by a wiring 10.

  Here, the silicide layer 7 forms a Schottky junction with the low-concentration N-type SOI layer 12.

  The silicide layer 7 corresponds to the anode electrode, and the silicide layer 8 corresponds to the cathode electrode.

  When a forward voltage is applied between the anode electrode and the cathode electrode, a forward current flows from the silicide layer 7 through the Schottky junction and the N− layer 12 to the N + layer 13 disposed on both sides thereof. When a reverse voltage is applied between the anode electrode and the cathode electrode, only a small reverse current flows due to the barrier due to the Schottky junction, and good Schottky diode characteristics can be obtained.

  The size and impurity concentration of each component of the Schottky barrier diode according to the present embodiment are formed as follows.

  The silicide layer 8 has a width of 0.5 to 3 μm and a length of 1 to 50 μm. The width of the silicide layer 7 is 0.2 to 2 μm. The thickness of the silicide layers 7 and 8 is 10 to 40 nm. The silicide layer 7 is formed 0.2 to 1 μm away from the N + layer 13.

  The buried oxide film layer 11 has a thickness of 0.1 to 0.5 μm, and the N + layer 13 and the N− layer 12 have a thickness of 0.05 to 0.5 μm.

The impurity concentration of the N− layer 12 is 10 ¹⁵ to 10 ¹⁸ cm ⁻³ , and the impurity concentration of the N + layer 13 is 10 ¹⁹ to 10 ²² cm ⁻³ .

<B. Manufacturing method>
Next, a method for manufacturing the Schottky barrier diode according to the present embodiment will be described with reference to FIGS.

  First, the element isolation film 4 is formed on the SOI substrate on which the silicon substrate 1, the buried oxide film 11, and the silicon film are stacked. The element isolation film 4 is formed so as to surround the active region of the silicon film 12 where the Schottky diode is formed. Subsequently, N-type impurities such as phosphorus are introduced into the silicon film to form the N− layer 12 (FIG. 3).

  Here, even if the element isolation film 4 is formed using an SOI substrate on which a silicon film having the same impurity concentration as that of the N− layer 12 is formed in advance, a similar structure can be obtained.

  Next, as shown in FIG. 4, a photoresist 51 is formed so as to cover a portion that is finally left as the N− layer 12. Then, an N-type impurity 52 such as As (arsenic) is introduced into the N− layer 12 by ion implantation or the like.

  Subsequently, the insulating film 5 is deposited on the SOI substrate, and the N-type impurity 52 is activated by heat treatment (annealing). By activating the N-type impurities 52, N− layers 12 and N + layers 13 are alternately formed in the active region.

  Thereafter, a photoresist 53 having an opening in a region where the silicide layers 7 and 8 are formed is formed on the insulating film 5. Then, using the photoresist 53, the insulating film 5 in the silicide layer 7 and 8 formation region is removed by etching (FIG. 5).

  Subsequently, after removing the photoresist 53, a metal film 14 such as cobalt or titanium having high reactivity with silicon is deposited on the SOI substrate (FIG. 6).

  Then, the metal film 14 reacts with the silicon of the N− layer 12 and the N + layer 13 by heat treatment at 400 ° C. to 600 ° C., and silicide layers 7 and 8 are formed on the N− layer 12 and the N + layer 13, respectively. (FIG. 7).

  Since the metal film 14 does not react with the insulating film 5, no silicide layer is formed on the insulating film 5.

  After the silicide layers 7 and 8 are formed, the unreacted metal film 14 is removed by wet etching or the like, and an insulating protective film (not shown) is formed on the SOI substrate surface. Thereafter, contacts for forming wiring on the anode electrode side and wiring on the cathode electrode side are opened in the insulating protective film, and metal wirings 9 and 10 (schematic diagrams in the figure) are applied to complete the SBD shown in FIG. .

<C. Effect>
In the Schottky barrier diode according to the present embodiment, since the N + layers 13 are alternately formed adjacent to the N− layer 12, the distance from the silicide layer 7 formed on the N− layer 12 to the N + layer 13. Can be arranged short.

  As a result, the distance through which the forward current flows through the N-layer 12 having a high resistance can be shortened, and the on-resistance can be lowered.

  Further, by alternately forming the N− layer 12 and the N + layer 13, the number of Schottky junctions can be increased without increasing the distance between the N− layer 12 and the N + layer 13. Therefore, a current having a desired magnitude can be passed without increasing the on-resistance.

  Specifically, the Schottky barrier diode according to the present embodiment is provided with a plurality of Schottky junction regions with a width of 0.5 to 3 μm, and low resistance high-concentration N-type diffusion layers on both sides. The structure is arranged close to 2 to 1 μm. Therefore, high-speed operation can be performed while supplying a desired current.

  Further, when the SBD is formed on the same substrate as the MOSFET, the low concentration layer 12 can be formed in the same process as the body portion of the PMOSFET and the high concentration layer in the same process as the source / drain layer of the NMOSFET.

  Therefore, the SBD can be created without adding a special process to the MOSFET manufacturing process.

  Furthermore, since it is not necessary to form a trench, the element area can be reduced and a multilayer wiring can be easily formed.

  As a result, the MOSFET and the SBD can be easily integrated.

  In this embodiment, as shown in FIG. 2, the N + layer 13 is formed so as to surround the N− layer 12, but the N− layer 12 may be formed up to the end of the active region. However, by forming the N + layer 13 so as to surround the N− layer 12, a forward current also flows to the N + layer 13 disposed above and below in FIG. 2, and a larger current can be passed.

<Embodiment 2>
<A. Configuration>
FIG. 8 is a top view showing the configuration of the Schottky barrier diode according to the present embodiment. 9 is a cross-sectional view taken along line YY of FIG.

  In the Schottky barrier diode according to the present embodiment, the silicide layers 7 and 8 are formed up to the end of the active region (see FIG. 8). The ends of the silicide layers 7 and 8 are in contact with the element isolation film 4. The N− layer 12 includes a P-type guard ring layer 15 at a position corresponding to a portion where the silicide layer 7 is in contact with the element isolation film 4.

  Other configurations are the same as those in the first embodiment, and the same components as those in the first embodiment are denoted by the same reference numerals, and redundant description is omitted.

  In the Schottky barrier diode according to the present embodiment, the silicide layer 7 is formed so as to reach the end of the active region. The end portion of the silicide layer 7 forms an ohmic junction with the P-type guard ring layer 15. Therefore, a portion of the silicide layer 7 formed on the N− layer 12 forms a Schottky junction with the N− layer 12.

  Further, since the P-type guard ring layer 15 is formed, the PN junction formed by the P-type guard ring layer 15 and the N + layer 13 is in parallel with the Schottky junction.

  However, the forward voltage Vf of the Schottky junction formed by the silicide layer 7 and the N− layer 12 is smaller than the forward voltage Vf of the PN junction. Therefore, the forward voltage Vf of the Schottky barrier diode is determined by the forward voltage Vf of the Schottky junction.

  As a result, even if the P-type guard ring layer 15 is formed, the operation of the Schottky barrier diode is not affected, and the same diode characteristics as in the first embodiment can be obtained.

<B. Manufacturing method>
Next, a method for manufacturing the Schottky diode according to the present embodiment will be described.

  In accordance with the process shown in the first embodiment, after implanting N-type impurity 52 (see FIG. 4), photoresist 51 is removed, and a portion of N− layer 12 where P-type guard ring layer 15 is formed is formed. Opened photoresist (not shown) is formed.

  Then, P-type impurities are introduced using the photoresist as a mask. Subsequently, a heat treatment for activating the implanted impurities is performed to form a P-type guard ring layer 15.

  Thereafter, the Schottky barrier diode shown in FIGS. 8 and 9 is completed according to the same steps as those in FIG.

  When the MOSFET is formed on the same substrate, a P-type impurity implantation for a guard ring is performed in a P-type impurity implantation step for the PMOS source drain following the high-concentration N-type impurity implantation step for forming the NMOS source drain. Can be done. As a result, the SBD and the MOSFET can be formed at the same time without increasing the manufacturing process.

<C. Effect>
When the silicide layer 7 is formed up to the active region end, that is, the element isolation film 4, a leak current is generated at the active region end due to stress generated between the element isolation film 4 and the active region. That is, a current that flows without passing through the Schottky junction is generated.

  In the Schottky barrier diode according to the present embodiment, a P-type guard ring layer 15 is formed in a portion of the N− layer 12 where the silicide layer 7 is in contact with the element isolation film 4.

  By forming the P-type guard ring layer 15, a depletion layer is formed between the P-type guard ring layer 15, the N− layer 12, and the N + layer 13, and leakage current is suppressed. Therefore, the silicide layer 7 can be formed up to the end of the active region without a problem of leakage current. As a result, the area of the SBD can be further reduced.

<Embodiment 3>
<A. Configuration>
FIG. 10 is a cross-sectional view showing the configuration of the Schottky barrier diode according to the third embodiment. FIG. 10 corresponds to a cross-sectional view taken along line YY in FIG.

  In the Schottky barrier diode according to the present embodiment, the element isolation film 4 is formed higher than the active region surface, and the sidewall 16 is formed on the side surface of the element isolation film 4 on the active region side.

  Then, the silicide layer 7 is formed on the inner side by the width of the side wall 16 from the end portion of the active region by the side wall 16. That is, the silicide layer 7 and the element isolation film 4 are separated under the sidewall 16.

  Here, the width of the sidewall 16 is approximately 0.05 to 0.1 μm.

<B. Manufacturing method>
Next, a method for manufacturing the Schottky barrier diode according to the present embodiment will be described.

  In the present embodiment, in the step of forming the element isolation film 4 of the first embodiment (FIG. 3), the element isolation film 4 is formed so as to be about 0.2 to 0.5 μm higher than the active region surface.

  Then, after forming the N− layer 12 and the N + layer 13 as in the first embodiment (FIG. 4), the sidewall 16 is formed on the active region side of the element isolation film 4.

  When the MOSFET is formed on the same substrate, the side wall 16 of the Schottky barrier diode is formed when the side wall of the gate side wall of the MOSFET is formed. By doing so, the Schottky barrier diode according to the present embodiment can be simultaneously formed without increasing the number of steps.

  After the sidewall 16 is formed, the Schottky barrier diode according to the present embodiment is completed according to the same process (FIGS. 5 to 7) as the first embodiment.

<C. Effect>
In the Schottky barrier diode according to the present embodiment, the sidewall 16 is formed with a constant width from the end of the active region. Therefore, the silicide layer 7 can be formed so as not to contact the element isolation film 4 by the sidewall 16. As a result, it is possible to increase the area of the silicide layer 7 while preventing the occurrence of leakage current at the end of the silicide layer 7.

  Since the distance from the end of the silicide layer 7 to the active region can be reduced to the sidewall width, the area of the entire Schottky barrier diode can be further reduced as compared with the third embodiment, and the area efficiency can be increased.

<Embodiment 4>
<A. Configuration>
FIG. 11 is a cross-sectional view showing the configuration of the Schottky barrier diode according to the present embodiment. FIG. 12 is a top view showing the configuration of the Schottky barrier diode according to the present embodiment. FIG. 11 corresponds to a cross-sectional view taken along line BB in FIG.

  In the Schottky barrier diode according to the present embodiment, an element isolation film 30 (partial element isolation film) is formed at the boundary between the N + layer (high concentration diffusion layer) 13 and the N− layer (low concentration diffusion layer) 12. Yes. The silicide layers 7 and 8 are separated by the element isolation film 30.

  The film thickness of the element isolation film 30 is set so that the SOI film remains under the element isolation film 30 that separates the silicide layers 7 and 8. Therefore, a current flows from the anode electrode to the cathode electrode through the remaining SOI film portion.

  In the N− layer 12, a P-type guard ring layer 15 is formed at a position corresponding to a portion where the end of the silicide layer 7 is in contact with the element isolation films 4 and 30.

  The P-type guard ring layer 15 is formed on one side surface of the element isolation film 30 on the low concentration layer 12 side and a part of the bottom surface.

<B. Manufacturing method>
Next, a method for manufacturing the Schottky barrier diode according to the present embodiment will be described with reference to FIGS.

  First, as shown in FIG. 13, an insulating film 54 of a type different from the element isolation films 4 and 30 is deposited on a substrate on which the silicon substrate 1, the buried oxide film 11, and the silicon film (SOI film) 32 are stacked. Thereafter, a photoresist 55 is formed so as to cover a region where the silicide layers 7 and 8 are to be formed. Subsequently, the insulating film 54 is etched using the photoresist 55 as a mask, and a trench is formed in the silicon film 32. Next, P-type impurities 56 such as boron (B +) are implanted into the side and bottom surfaces of the trench by oblique ion implantation (FIG. 13).

  Next, after removing the photoresist 55, as shown in FIG. 14, the active region is covered with the photoresist 57, and the exposed silicon film 32 is removed by etching. Subsequently, after the photoresist 57 is removed, an insulating film to be the element isolation films 4 and 30 is deposited thickly, and then is etched away so that the insulating film 54 is exposed by CMP or the like. An element isolation film 4 is formed so as to surround the active region, and an element isolation film 30 is formed between the silicide films 7 and 8. By heat treatment by depositing an insulating film or by adding an annealing process, the P-type impurity 56 is activated and the P-type guard ring layer 15 is formed (FIG. 15).

  Next, the N − layer 12 is formed by ion implantation using the element isolation films 4 and 30 as a mask.

  Specifically, after removing the insulating film 54, N-type impurities 52 such as phosphorus are implanted into the silicon film 32 in multiple steps while adjusting the implantation energy. Then, an N-type impurity 52 is implanted into the entire active region including the lower part of the element isolation film 30 (FIG. 16). Then, the N-type impurity 52 is activated by an annealing process to form the N− layer 12.

  Next, a photoresist (mask) 51 is formed so as to cover a region where the silicide layer 7 is to be formed.

  That is, the photoresist 51 is formed so as to cover the Schottky junction (region where the silicide layer 7 is formed).

  Next, an N + layer is formed by ion implantation using the element isolation film 30 and the photoresist 51.

  That is, an N-type impurity 52 such as As is implanted at a high concentration into the cathode contact formation region where the silicide layer 8 is formed (FIG. 17).

  At this time, since the element isolation film 30 also serves as a mask when the N-type impurity 52 is implanted, the Schottky junction and the N + layer 13 (cathode contact diffusion layer) are prevented from being slightly misaligned with the photoresist 51. The distance is not affected.

  After activating the N-type impurity by annealing to form the N + layer 13, a reactive metal film 14 is deposited, and silicide layers 7 and 8 are formed by reaction with silicon by heat treatment (FIG. 18).

  Subsequent steps are the same as those in the first embodiment, and the SBD shown in FIG. 11 is completed.

<C. Effect>
In the Schottky barrier diode according to the first embodiment, the silicide layer 7 and the N + layer 13 are separated by the insulating film 5.

  Then, the photoresist 53 for forming the insulating film 5 does not leave a mark when the photoresist 51 for forming the N + layer 13 is removed, so that it is necessary to overlap the element isolation film 4.

  Since the photoresist 51 and the photoresist 53 are indirectly overlapped via the element isolation film 4, the width of the photoresist 53 needs to be formed wide in consideration of the overlap margin. As a result, the width of the insulating film 5 is increased.

  On the other hand, in the Schottky barrier diode according to the present embodiment, the silicide layer 7 and the N + layer 13 are separated by the element isolation film 30.

  Since the photoresist 51 can be directly superimposed on the element isolation films 4 and 30, the overlay margin can be reduced. Therefore, the width of the element isolation film 30 can be narrowed. As a result, the formation area of the Schottky barrier diode can be further reduced.

  In addition, the formation of the P-type guard ring layer 15 for suppressing the leakage current at the edge of the active region also uses the mask for forming the element isolation film 30, so that mask alignment for forming the P-type guard ring layer 15 is unnecessary. become.

<Embodiment 5>
<A. Configuration>
FIG. 19 is a cross-sectional view showing the configuration of the Schottky barrier diode according to the present embodiment.

  In the Schottky barrier diode according to the present embodiment, the P-type guard ring layer 15 is formed only on one side surface of the element isolation film 30 and not on the bottom surface as compared with the fourth embodiment.

  That is, the guard ring layer 15 is formed so as not to contact the N + layer 13.

  Other configurations are the same as those in the fourth embodiment, and the same components are denoted by the same reference numerals, and redundant description is omitted.

<B. Manufacturing method>
Next, a method for manufacturing the Schottky barrier diode according to the present embodiment will be described with reference to FIGS.

  First, as shown in FIG. 20, an insulating film 54 of a type different from the element isolation film 4 is deposited on an SOI substrate on which the silicon substrate 1, the buried oxide film 11, and the silicon film 32 are stacked. Thereafter, a photoresist 55 is formed so as to cover a region where the silicide layers 7 and 8 are to be formed.

  The insulating film 54 is etched using the photoresist 55 as a mask, and a trench is formed shallowly in the silicon film 32.

Thereafter, a P-type impurity 56 such as boron (B ⁺ ) is implanted into the side and bottom surfaces of the trench by oblique ion implantation (FIG. 20).

  Next, as shown in FIG. 21, a second trench etching is performed using a photoresist 55, and the silicon film 32 including the P-type impurity 56 implanted into the bottom surface of the trench is removed.

  Thereafter, the same process as in the fourth embodiment is performed, and as shown in FIG. 22, the element isolation films 4 and 30 and the P-type guard ring layer 15 are formed. At this time, since the P-type impurity 56 on the bottom surface of the element isolation film 30 is removed, the P-type guard ring layer 15 is not formed on the bottom surface of the element isolation film 30 but only on the side surface.

  Thereafter, the SBD shown in FIG. 19 can be obtained through the same steps as in the fourth embodiment (see FIGS. 16 to 18).

<C. Effect>
In the Schottky barrier diode according to the fourth embodiment, the P-type guard ring layer 15 is in contact with the N + layer 13 having a high impurity concentration on the bottom surface of the element isolation film 30 to form a PN junction. The PN junction has a low reverse breakdown voltage because the impurity concentration of the N + layer 13 is high. For this reason, the Schottky barrier diode according to the fourth embodiment has a low reverse breakdown voltage.

  The Schottky barrier diode according to the present embodiment has a structure in which the P-type guard ring layer 15 and the N + layer 13 are not in contact with each other at the bottom surface of the element isolation film 30.

  As a result, the reverse breakdown voltage can be improved as compared with the Schottky barrier diode of the fourth embodiment.

<Embodiment 6>
<A. Configuration>
FIG. 23 is a cross-sectional view showing a configuration of the Schottky barrier diode according to the sixth embodiment. FIG. 24 is a top view showing the configuration of the Schottky barrier diode according to the sixth embodiment. FIG. 23 corresponds to the sectional view taken along the line CC of FIG.

  In the Schottky barrier diode according to the present embodiment, the silicide layers 7 and 8 are separated by the same structure 31 as the gate structure of the MOSFET (hereinafter, sometimes referred to as “gate structure” because of similarity to the MOSFET). is doing.

  As shown in FIG. 24, the gate structure 31 is formed so as to surround the Schottky junction formed by the silicide layer 7 and the N− layer 12.

  The gate structure 31 is formed of a gate insulating film 18, a gate electrode 19, a silicide layer 21, and a sidewall layer 20.

  A gate electrode 19 made of polysilicon is formed on the gate insulating film 18, and a silicide layer 21 is formed on the gate electrode 19. Sidewall layers 20 are formed on both sides of the gate electrode 19 and the silicide layer 21.

The gate length of the gate structure 31 is about 0.05 μm to 0.5 μm, and the gate electrode 19 made of polysilicon contains high-concentration (10 ¹⁹ to 10 ²² cm ⁻³ ) N-type impurities. It is.

<B. Manufacturing method>
Next, a method for manufacturing the Schottky barrier diode according to the present embodiment will be described with reference to FIGS.

  First, as shown in FIG. 25, an element isolation film 4 is formed on a silicon film (SOI film) formed on an SOI substrate so as to surround an active region.

  Here, the SOI substrate has a structure in which a buried oxide film 11 is formed on a silicon substrate 1 and a silicon film (SOI film) is laminated on the buried oxide film 11.

  Then, an N-type impurity such as phosphorus is introduced into the active region to form the N− layer 12 (FIG. 25).

  Here, the same structure can be obtained even if the element isolation film 4 is formed using an SOI substrate on which a silicon film having a desired N-type impurity concentration is formed in advance.

  Next, as in the MOSFET formation step, a thin oxide film 18 is formed on the N− layer 12. Then, a polysilicon film is deposited on the SOI substrate.

  Then, a photoresist 60 is formed so as to cover a portion where the gate electrode 19 is to be formed. Next, the polysilicon film is etched using the photoresist 60. As a result, the gate electrode 19 is formed so as to surround the region where the silicide layer 7 is formed (FIG. 26).

  Next, after removing the photoresist 60, an insulating film for forming the sidewall 20 is deposited and anisotropic etching is performed to form the sidewall 20 on the side surface of the gate electrode 19. At this time, the thin oxide film 18 is also etched, and the silicon surface of the N− layer 12 is exposed.

  Subsequently, a photoresist 51 is formed so as to cover a region where the silicide layer 7 is formed. Then, using the photoresist 51 and the gate structure 31 as a mask, an N-type impurity 52 such as As is implanted at a high concentration into the region where the N + layer 13 is to be formed (FIG. 27).

  At this time, as in the fourth and fifth embodiments, the gate structure 31 also serves as a mask at the time of implantation. Therefore, the distance between the silicide layer 7 and the N + layer 13 has an influence on the slight misalignment of the photoresist 51. Not receive.

  After activating the N-type impurity 52 by annealing to form the N + layer 13, a reactive metal film 14 is deposited. Then, the metal film 14 and the silicon film are reacted by heat treatment to form silicide layers 7 and 8 (FIG. 28).

  Thereafter, the same process as in the first embodiment is performed, and the SBD shown in FIG. 23 can be obtained.

<C. Effect>
The Schottky barrier diode according to the present embodiment forms the N + layer 13 because the distance between the silicide layer 7 and the N + layer 13 is determined by the width of the gate structure 31 as in the fourth and fifth embodiments. Therefore, it is not necessary to consider a mask misalignment margin for masking, and the element area can be reduced by that margin.

  Further, in the Schottky barrier diode according to the present embodiment, the gate structure 31 is formed on the silicon film. Therefore, the thickness of the silicon film 12 in the current path flowing from the anode electrode to the cathode electrode is increased, and the on-resistance can be further reduced as compared with the structure shown in the fourth or fifth embodiment.

  In the Schottky barrier diode according to the present embodiment, an inversion layer can be formed under the gate insulating film 18 at the time of reverse bias by connecting the gate electrode 19 to the anode electrode.

  When a reverse bias is applied, the electric field concentrates at the end of the silicide layer 7, and voltage breakdown of the Schottky junction is likely to occur at the end of the silicide layer 7.

  In the Schottky barrier diode according to the present embodiment, when the reverse bias voltage increases, the inversion layer extends to the end of the silicide layer 7. Then, the end portion of the silicide layer 7 is covered by the inversion layer, and the electric field at the end portion is weakened. As a result, the breakdown voltage of the Schottky barrier diode can be improved.

  In the case where it is not necessary to consider the breakdown voltage, a structure in which the gate electrode 19 is connected to the ground may be used.

<Embodiment 7>
<A. Configuration>
FIG. 29 is a cross-sectional view showing the configuration of the Schottky barrier diode according to the present embodiment.

  In the Schottky barrier diode according to the present embodiment, a MOSFET is formed on the same SOI substrate.

  On the buried oxide film 11, an active region made of a silicon film on which Schottky barrier diodes and MOSFETs are formed is formed.

  An element isolation film 4 is formed on the buried oxide film 11 so as to surround the active region.

  A gate structure 31 is formed on the silicon film in the MOSFET formation region. In the gate structure 31, a gate electrode 19 is formed on the gate oxide film 18, and a silicide layer 21 is formed on the gate electrode 19. Sidewalls 20 are formed on both sides of the gate electrode 19 and the silicide layer 21.

  An extension layer 23 is formed in the active region so as to sandwich the gate electrode 19. An N + layer 13 serving as a source / drain is formed in the active region so as to sandwich the gate structure 31.

  Of the active region, a region sandwiched between the extension layers 23 is a low-concentration P-type impurity layer (P-type body region) 22.

  A silicide layer 8 is formed on the N + layer 13. On the silicide layer 8 and the silicide layer 21, source / drain and gate wirings are respectively formed.

  In FIG. 29, a wiring 24 connected to the source, a wiring 26 connected to the drain, and a wiring 25 connected to the gate are schematically shown.

  Other configurations are the same as those in the sixth embodiment, and the same components as those in the sixth embodiment are denoted by the same reference numerals, and redundant description is omitted.

<B. Manufacturing method>
Next, a method for manufacturing the Schottky barrier diode according to the present embodiment will be described with reference to FIGS.

  First, as shown in FIG. 30, an element isolation film 4 is formed so as to surround an active region silicon film on an SOI substrate in which a silicon substrate 1, a buried oxide film 11, and a low-concentration P-type silicon film (SOI film) are stacked. Form.

  Then, a photoresist 61 is formed so as to cover the region to be the P-type body region 22 of the NMOSFET.

  Then, an N-type impurity 52 such as phosphorus is introduced into the SOI film by ion implantation or the like (FIG. 30).

  Next, heat treatment is performed to activate the N-type impurity 52 to form the N− layer 12. Subsequently, channel implantation for adjusting Vt of the NMOSFET is performed (not shown).

  Next, a gate insulating film 18 is formed on the active region, and a polysilicon film is deposited. Thereafter, a photoresist 60 is formed and the polysilicon film is etched to form the gate electrode 19 of the NMOSFET. Then, a gate electrode 19 is formed in the Schottky barrier formation region so as to surround the formation region of the silicide layer 7 (FIG. 31).

  After removing the photoresist 60, a new photoresist 63 having an opening in the NMOSFET formation region is formed.

  Then, N-type impurities are ion-implanted to form an extension layer of the NMOSFET (FIG. 32).

  After removing the photoresist 63, a sidewall insulating film is deposited and anisotropic etching is performed to form the sidewall 20 on the side surface of the polysilicon electrode 19. At the same time, the gate insulating film 18 is also etched to expose the silicon surface.

  Next, a photoresist pattern 51 is formed so as to cover a region where the silicide layer 7 is to be formed. Then, an N-type impurity 52 such as As is implanted at a high concentration into a region where the N + layer 13 of the Schottky barrier diode and the N + layer 13 which becomes the source / drain of the NMOSFET are formed (FIG. 33).

  By the annealing process, the extension layer 23 and the N + layer 13 serving as the source / drain are formed in the NMOSFET, and the N + layer 13 is formed in the Schottky barrier diode.

  Subsequently, a highly reactive metal film 14 is deposited on the SOI substrate, and heat treatment is performed to react the metal film 14 with silicon to form silicide layers 7, 8, and 21 (FIG. 34).

  Thereafter, the same process as in the first embodiment is performed, and the SBD integrated with the NMOSFET shown in FIG. 29 is completed.

<C. Effect>
This embodiment specifically shows that the SBD shown in Embodiment 6 is manufactured using a part of the MOSFET manufacturing process and can be integrated into a MOS-LSI.

  As shown in this embodiment mode, since the SBD shown in Embodiment Mode 6 can be formed in the MOSFET manufacturing process, integration is possible without an increase in the manufacturing process.

  Examples 1 to 5 are also formed by using a MOS manufacturing process and can be easily integrated.

1 is a cross-sectional view showing a configuration of a Schottky barrier diode according to a first embodiment. 1 is a top view showing a configuration of a Schottky barrier diode according to a first embodiment. 5 is a cross-sectional view showing a manufacturing process of the Schottky barrier diode according to the first embodiment. FIG. 5 is a cross-sectional view showing a manufacturing process of the Schottky barrier diode according to the first embodiment. FIG. 5 is a cross-sectional view showing a manufacturing process of the Schottky barrier diode according to the first embodiment. FIG. 5 is a cross-sectional view showing a manufacturing process of the Schottky barrier diode according to the first embodiment. FIG. 5 is a cross-sectional view showing a manufacturing process of the Schottky barrier diode according to the first embodiment. FIG. FIG. 5 is a top view showing a configuration of a Schottky barrier diode according to a second embodiment. FIG. 4 is a cross-sectional view showing a configuration of a Schottky barrier diode according to a second embodiment. FIG. 6 is a cross-sectional view illustrating a configuration of a Schottky barrier diode according to a third embodiment. FIG. 6 is a cross-sectional view showing a configuration of a Schottky barrier diode according to a fourth embodiment. 6 is a top view showing a configuration of a Schottky barrier diode according to a fourth embodiment. FIG. 12 is a cross-sectional view showing a manufacturing process of the Schottky barrier diode according to the fourth embodiment. FIG. 12 is a cross-sectional view showing a manufacturing process of the Schottky barrier diode according to the fourth embodiment. FIG. 12 is a cross-sectional view showing a manufacturing process of the Schottky barrier diode according to the fourth embodiment. FIG. 12 is a cross-sectional view showing a manufacturing process of the Schottky barrier diode according to the fourth embodiment. FIG. 12 is a cross-sectional view showing a manufacturing process of the Schottky barrier diode according to the fourth embodiment. FIG. 12 is a cross-sectional view showing a manufacturing process of the Schottky barrier diode according to the fourth embodiment. FIG. FIG. 9 is a cross-sectional view illustrating a configuration of a Schottky barrier diode according to a fifth embodiment. FIG. 10 is a cross-sectional view showing a manufacturing process of the Schottky barrier diode according to the fifth embodiment. FIG. 10 is a cross-sectional view showing a manufacturing process of the Schottky barrier diode according to the fifth embodiment. FIG. 10 is a cross-sectional view showing a manufacturing process of the Schottky barrier diode according to the fifth embodiment. FIG. 10 is a cross-sectional view illustrating a configuration of a Schottky barrier diode according to a sixth embodiment. FIG. 10 is a top view showing a configuration of a Schottky barrier diode according to a sixth embodiment. 14 is a cross-sectional view showing a manufacturing process of the Schottky barrier diode according to the sixth embodiment. FIG. 14 is a cross-sectional view showing a manufacturing process of the Schottky barrier diode according to the sixth embodiment. FIG. 14 is a cross-sectional view showing a manufacturing process of the Schottky barrier diode according to the sixth embodiment. FIG. 14 is a cross-sectional view showing a manufacturing process of the Schottky barrier diode according to the sixth embodiment. FIG. FIG. 10 is a cross-sectional view illustrating a configuration of a Schottky barrier diode according to a seventh embodiment. 12 is a cross-sectional view showing a manufacturing process of the Schottky barrier diode according to the seventh embodiment. FIG. 12 is a cross-sectional view showing a manufacturing process of the Schottky barrier diode according to the seventh embodiment. FIG. 12 is a cross-sectional view showing a manufacturing process of the Schottky barrier diode according to the seventh embodiment. FIG. 12 is a cross-sectional view showing a manufacturing process of the Schottky barrier diode according to the seventh embodiment. FIG. 12 is a cross-sectional view showing a manufacturing process of the Schottky barrier diode according to the seventh embodiment. FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Silicon substrate, 4,30 Element isolation insulating film, 7 Anode side silicide layer, 8 Cathode side silicide layer, 11 Embedded oxide film, 12 Low concentration N type SOI layer, 13 High concentration N type SOI layer, 14 Metal film, 15 P-type guard ring layer, 31 gate structure, 51, 53, 55, 57 photoresist, 54 insulating film, 56 P-type impurity.

Claims (7)

A Schottky barrier diode formed on an SOI substrate,
An element isolation film formed so as to surround the active region of the SOI substrate;
A high concentration diffusion layer formed in the active region;
A low concentration diffusion layer formed adjacent to the high concentration diffusion layer;
A silicide layer formed on the low concentration diffusion layer and forming a Schottky junction with the low concentration diffusion layer;
With
The Schottky barrier diode, wherein the high concentration diffusion layer and the low concentration diffusion layer are alternately arranged.   2. The device according to claim 1, further comprising a sidewall formed on a side surface of the element isolation film on the active region side, wherein the silicide layer and the element isolation film are separated under the sidewall. Schottky barrier diode.   3. The Schottky barrier diode according to claim 1, wherein the low-concentration diffusion layer includes a guard ring layer at a position corresponding to a portion where the silicide layer is in contact with the element isolation film. A partial element isolation film formed at a boundary portion between the high-concentration diffusion layer and the low-concentration diffusion layer;
3. The Schottky barrier according to claim 1, wherein the low-concentration diffusion layer includes a guard ring layer at a position corresponding to a portion where the silicide layer is in contact with the element isolation film and the partial element isolation film. diode.   The Schottky barrier diode according to claim 4, wherein the guard ring layer is formed so as not to contact the high concentration diffusion region.   The Schottky barrier diode according to claim 1, further comprising a gate structure formed on the SOI substrate so as to surround the silicide layer. 7. The Schottky barrier diode according to claim 1, wherein the Schottky barrier diode is formed on the same SOI substrate as the MOSFET.

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