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JP2006237104A - Semiconductor element for surge protection, and its manufacturing method - Google Patents

Semiconductor element for surge protection, and its manufacturing method Download PDF

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JP2006237104A
JP2006237104A JP2005046481A JP2005046481A JP2006237104A JP 2006237104 A JP2006237104 A JP 2006237104A JP 2005046481 A JP2005046481 A JP 2005046481A JP 2005046481 A JP2005046481 A JP 2005046481A JP 2006237104 A JP2006237104 A JP 2006237104A
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surge protection
conductivity type
type region
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semiconductor substrate
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Kazuhiro Onishi
一洋 大西
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • HELECTRICITY
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/4809Loop shape
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor element for a surge protection having a plurality of LEDs in the serial connection. <P>SOLUTION: In an n-type semiconductor substrate 2, p-type regions 3a and 3b and n-type regions 4a and 4b are formed. An LED is connected electrically between an anode electrode 6a and a cathode electrode 7a, and between an anode electrode 6b and a cathode electrode 7b. Zener diodes D34a and D34b configured by the n-type regions 4a and 4b and the p-type regions 3a and 3b have a breakdown voltage larger than the forward drop voltage in usual when each LED is used in usual, and it designs so that it may become under the withstand voltage of each LED. Isolation diodes D32a and D32b configured by the p-type regions 3a and 3b and the n-type semiconductor substrate 2 are designed so that the breakdown voltage may become higher than the sum of the forward drop voltages of all the LEDs. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明はサージ保護用半導体素子およびその製造方法に関する。   The present invention relates to a semiconductor device for surge protection and a method for manufacturing the same.

近年、発光ダイオード(LED:Light Emitting Diode)は多分野で使用されている。LEDは、GaAs(砒素化ガリウム)やGaN(窒化ガリウム)等の化合物半導体でなるために、静電気放電(ESD:Electro Static Discharge)などのサージに対して非常に弱い。よって、LEDには、サージ保護用回路が必ず必要になるために、予めサージ保護用半導体素子(ツェナーダイオード)を同封したLEDパッケージが提案されている(例えば、特許文献1参照)。   In recent years, light emitting diodes (LEDs) have been used in many fields. Since an LED is made of a compound semiconductor such as GaAs (gallium arsenide) or GaN (gallium nitride), it is very weak against surges such as electrostatic discharge (ESD). Therefore, since an LED needs a surge protection circuit, an LED package in which a surge protection semiconductor element (zener diode) is enclosed in advance has been proposed (see, for example, Patent Document 1).

図10(a)は、サージ保護用半導体素子100が同封されたLEDパッケージ111の一例を示している。図10(b)は、図10(a)の回路図である。このLEDパッケージ111は、LED112、サージ保護用半導体素子100、金属フレーム101a,101bおよび、光透過性樹脂でなる封止部113で構成されている。サージ保護用半導体素子100は、N型半導体基板102、P型領域103、絶縁膜105、カソード電極106、アノード電極107、および裏面電極108を備えた、フリップチップ型のツェナーダイオードである。LED112に並列接続されたサージ保護用半導体素子100によって、サージ電流の分岐回路が構成されている。
特開2002−185049号公報
FIG. 10A shows an example of the LED package 111 in which the surge protection semiconductor element 100 is enclosed. FIG. 10B is a circuit diagram of FIG. The LED package 111 includes an LED 112, a surge protection semiconductor element 100, metal frames 101a and 101b, and a sealing portion 113 made of a light transmissive resin. The surge protection semiconductor element 100 is a flip-chip type Zener diode including an N-type semiconductor substrate 102, a P-type region 103, an insulating film 105, a cathode electrode 106, an anode electrode 107, and a back electrode 108. A surge current branch circuit is configured by the semiconductor element 100 for surge protection connected in parallel to the LED 112.
JP 2002-185049 A

ところで最近、LEDの輝度向上に対する要請が高まっており、この要請を満たすために、複数のLEDを封入したLEDパッケージが提案されている。しかしながら、サージ保護用半導体素子を、複数のLEDと共に封入したLEDパッケージは未だ提案されていない。   Recently, there is an increasing demand for improving the brightness of LEDs, and in order to satisfy this demand, an LED package in which a plurality of LEDs are enclosed has been proposed. However, an LED package in which a semiconductor element for surge protection is enclosed with a plurality of LEDs has not been proposed yet.

例えばLEDパッケージ内に、図10(a)に示すサージ保護用半導体素子100とLED112とを複数個封入する場合、LEDパッケージの小型化は困難である。そこで、本願発明者は、LEDパッケージの小型化を図るために、複数個のLEDを搭載可能なフリップチップ型のサージ保護用半導体素子を開発することを検討した。その際に、以下に説明する課題が生じることになった。   For example, when a plurality of surge protection semiconductor elements 100 and LEDs 112 shown in FIG. 10A are enclosed in an LED package, it is difficult to reduce the size of the LED package. Therefore, the present inventor has studied to develop a flip-chip type surge protection semiconductor element on which a plurality of LEDs can be mounted in order to reduce the size of the LED package. At that time, the following problems have arisen.

LEDパッケージ(光源)の輝度変化は等方的であることが望ましく、そのためには、LEDパッケージ内の各LEDの輝度をほぼ同じにする必要がある。LEDの輝度は、LEDに供給される電流値に比例して決まる。   It is desirable that the luminance change of the LED package (light source) is isotropic, and for this purpose, the luminance of each LED in the LED package needs to be substantially the same. The brightness of the LED is determined in proportion to the current value supplied to the LED.

LEDを並列接続した場合には、各LEDの抵抗値に応じて電流値が決まるので、製造誤差による各LEDの抵抗値のバラツキによって、LEDの輝度にバラツキが生じることになる。よって、LEDを並列接続する場合には、各LEDの抵抗値のバラツキを補正する周辺回路を設けて、各LEDの輝度を均一にする必要がある。その場合には、周辺回路が煩雑になるため、LEDパッケージの小型化は困難になる。   When the LEDs are connected in parallel, the current value is determined according to the resistance value of each LED, so that the brightness of the LED varies due to the variation in the resistance value of each LED due to manufacturing errors. Therefore, when LEDs are connected in parallel, it is necessary to provide a peripheral circuit for correcting variations in resistance values of the LEDs to make the brightness of the LEDs uniform. In that case, since the peripheral circuit becomes complicated, it is difficult to reduce the size of the LED package.

一方、LEDを直列接続した場合には、各LEDに供給される電流値が一定になるため、輝度調整のために抵抗値を調整する必要がない。よって、LEDを直列接続すれば、パッケージ内の各LEDの輝度を均一にして、かつ、周辺回路を簡素化することが可能になる。   On the other hand, when the LEDs are connected in series, the current value supplied to each LED is constant, so there is no need to adjust the resistance value for brightness adjustment. Therefore, if the LEDs are connected in series, the brightness of each LED in the package can be made uniform and the peripheral circuit can be simplified.

ただし、図10(a)に示す従来のサージ保護用半導体素子を単に複数個並べて一つのサージ保護用半導体素子を構成した場合には、図11および図12にLEDパッケージの予想図およびその回路図を示すように、裏面電極108が共用されるため、LED112a,112bを直列接続することができない。   However, when a single surge protection semiconductor element is configured by simply arranging a plurality of conventional surge protection semiconductor elements shown in FIG. 10A, FIG. 11 and FIG. As shown, since the back electrode 108 is shared, the LEDs 112a and 112b cannot be connected in series.

それ故に本発明の目的は、複数個のLEDを直列接続して搭載できるサージ保護用半導体素子を提供することにある。   Therefore, an object of the present invention is to provide a semiconductor device for surge protection capable of mounting a plurality of LEDs connected in series.

本発明に係るサージ保護用半導体素子は、サージから保護すべき素子を並列接続して使用するツェナーダイオードを備えたサージ保護用半導体素子であって、第1導電型の半導体基板と、ツェナーダイオードをそれぞれに含む複数のサージ保護用回路部と、半導体基板の裏面に形成した裏面電極とを備え、各サージ保護用回路部は、半導体基板の表面から内部に形成した第2導電型領域と、第2導電型領域の表面から内部に形成した第1導電型領域と、第1導電型領域の一部と第2導電型領域の一部とを露出する絶縁膜と、絶縁膜から露出した第1導電型領域に形成した第1の表面電極と、絶縁膜から露出した第2導電型領域に形成した第2の表面電極とを有する。   A semiconductor device for surge protection according to the present invention is a semiconductor device for surge protection provided with a Zener diode that is used by connecting elements to be protected from surge in parallel, and includes a semiconductor substrate of a first conductivity type, and a Zener diode. A plurality of surge protection circuit portions included in the semiconductor substrate, and a back electrode formed on the back surface of the semiconductor substrate, each surge protection circuit portion including a second conductivity type region formed inside from the surface of the semiconductor substrate; A first conductivity type region formed inside from the surface of the two conductivity type region, an insulating film exposing a part of the first conductivity type region and a part of the second conductivity type region, and a first exposed from the insulating film. It has the 1st surface electrode formed in the conductivity type area | region, and the 2nd surface electrode formed in the 2nd conductivity type area | region exposed from the insulating film.

第1導電型領域と第2導電型領域とでなるツェナーダイオードの降伏電圧の大きさは、通常使用時における保護すべき素子の降下電圧よりも大きく、保護すべき素子の耐電圧未満になっていればよい。   The magnitude of the breakdown voltage of the Zener diode composed of the first conductivity type region and the second conductivity type region is larger than the voltage drop of the element to be protected during normal use and less than the withstand voltage of the element to be protected. Just do it.

より具体的には、ツェナーダイオードの降伏電圧が、3〜50Vになっていればよい。   More specifically, it is sufficient that the breakdown voltage of the Zener diode is 3 to 50V.

また、第2導電型領域と半導体基板とでなる分離用ダイオードの降伏電圧が、通常使用時における各保護すべき素子の降下電圧の和よりも高くなっていればよい。   In addition, the breakdown voltage of the isolation diode composed of the second conductivity type region and the semiconductor substrate may be higher than the sum of the drop voltages of the elements to be protected during normal use.

より具体的には、分離用ダイオードの降伏電圧は、10V以上であればよい。   More specifically, the breakdown voltage of the separation diode may be 10 V or more.

また、本発明に係るサージ保護用半導体素子は、サージ保護用回路部の第1の表面電極と、別のサージ保護用回路部の第2の表面電極とを接続することによって、全てのサージ保護用回路部を直列接続する配線をさらに備えていてもよい。   In addition, the surge protection semiconductor device according to the present invention provides all surge protection by connecting the first surface electrode of the surge protection circuit section and the second surface electrode of another surge protection circuit section. You may further provide the wiring which connects the circuit part for a series.

本発明に係るサージ保護用半導体素子の製造方法は、サージから保護すべき素子を並列接続するツェナーダイオードを備えたサージ保護用半導体素子の製造方法であって、第1導電型の半導体基板の表面から内部に複数の第2導電型領域を形成する工程と、各第2導電型領域の表面から内部に第1導電型領域を形成する工程と、第1導電型領域の一部と第2導電型領域の一部とを露出する絶縁膜を形成する工程と、絶縁膜から露出した第1導電型領域と第2導電型領域とに、第1および第2の表面電極を形成する工程と、半導体基板の裏面に裏面電極を形成する工程とを備える。   A method for manufacturing a semiconductor device for surge protection according to the present invention is a method for manufacturing a semiconductor device for surge protection provided with a Zener diode for connecting elements to be protected from surge in parallel, and the surface of a semiconductor substrate of a first conductivity type A step of forming a plurality of second conductivity type regions from the inside, a step of forming the first conductivity type region from the surface of each second conductivity type region, a part of the first conductivity type region and the second conductivity Forming an insulating film exposing a part of the mold region, forming first and second surface electrodes in the first conductive type region and the second conductive type region exposed from the insulating film, Forming a back electrode on the back surface of the semiconductor substrate.

本発明に係るサージ保護用半導体素子によれば、1つのLEDに対してそれぞれ個別にチップ状のサージ保護用半導体素子を接続する場合よりも、実装面の省面積化が可能になり、また周辺回路も簡素化できる。よって、本発明に係るサージ保護用半導体素子を用いれば、より小型のLEDパッケージを実現することができる。   According to the semiconductor device for surge protection according to the present invention, the mounting surface area can be reduced as compared with the case where a chip-like semiconductor device for surge protection is individually connected to one LED. The circuit can also be simplified. Therefore, if the semiconductor element for surge protection according to the present invention is used, a smaller LED package can be realized.

本実施形態に係るサージ保護用半導体素子は、LEDを直列接続でき、かつ、各LEDに対して各1つのサージ保護用回路部を並列接続できる構成になっている。LEDを直列接続した場合、各LEDに供給される電流値が等しくなるために、各LEDの輝度が均一になる。よって、この半導体素子を用いれば、輝度変化が等方的なLEDパッケージを実現することができる。   The semiconductor element for surge protection according to the present embodiment has a configuration in which LEDs can be connected in series and one surge protection circuit unit can be connected in parallel to each LED. When the LEDs are connected in series, the current values supplied to the LEDs are equal, so that the brightness of the LEDs is uniform. Therefore, if this semiconductor element is used, an LED package in which the luminance change is isotropic can be realized.

また、本発明に係るサージ保護用半導体素子は、分離用ダイオードを備えているために、各サージ保護用回路部を、電気的に分離された素子として個別に取り扱うことができる。よって、本発明に係るサージ保護用半導体素子を用いれば、これを搭載する回路の設計自由度が高くなる。   Moreover, since the semiconductor element for surge protection according to the present invention includes the isolation diode, each surge protection circuit unit can be individually handled as an electrically isolated element. Therefore, if the semiconductor element for surge protection according to the present invention is used, the degree of freedom in designing a circuit on which it is mounted is increased.

表面電極間を接続する配線を設けておけば、電極間を接続する手間を要しない。また、目視によって第1の表面電極と第2の表面電極の極性を区別することができるという利点もある。   If wiring for connecting the surface electrodes is provided, it is not necessary to connect the electrodes. There is also an advantage that the polarities of the first surface electrode and the second surface electrode can be distinguished visually.

(第1の実施形態)
図1(a)および(b)は、本発明の第1の実施形態に係るサージ保護用半導体素子10(以下、単に半導体素子10という)の平面図、および、A−A’線断面図を示している。この半導体素子10は、N型半導体基板2、P型領域3a,3b、N型領域4a,4b、絶縁膜5、アノード電極6a,6b,カソード電極7a,7bおよび、裏面電極8を備えている。
(First embodiment)
1A and 1B are a plan view and a cross-sectional view taken along line AA ′ of a surge protection semiconductor element 10 (hereinafter simply referred to as a semiconductor element 10) according to a first embodiment of the present invention. Show. The semiconductor element 10 includes an N-type semiconductor substrate 2, P-type regions 3a and 3b, N-type regions 4a and 4b, an insulating film 5, anode electrodes 6a and 6b, cathode electrodes 7a and 7b, and a back electrode 8. .

P型領域3a、N型領域4a、アノード電極6aおよびカソード電極7aは、第1のサージ保護用回路部9aを構成している。また、P型領域3b、N型領域4b、アノード電極6bおよびカソード電極7bは、第2のサージ保護用回路部9bを構成している。   The P-type region 3a, the N-type region 4a, the anode electrode 6a, and the cathode electrode 7a constitute a first surge protection circuit portion 9a. Further, the P-type region 3b, the N-type region 4b, the anode electrode 6b, and the cathode electrode 7b constitute a second surge protection circuit portion 9b.

P型領域3a,3bは、N型半導体基板2の表面から内部に形成された、P型不純物濃度が高い領域である。このP型領域3a,3bの深さはd1であり、平面形状は、半径がR1の円形状になっている。N型領域4a,4bは、P型領域3a,3bの表面から内部に形成された、N型不純物濃度が高い領域である。N型領域4a,4bの深さはd2(<d1)であり、その平面形状は、半径がR2(<R1)の円形状になっている。極性の判別を容易にするために、アノード電極6a,6bとカソード電極7a,7bの直径が異なっている。   The P-type regions 3a and 3b are regions formed in the interior from the surface of the N-type semiconductor substrate 2 and having a high P-type impurity concentration. The depths of the P-type regions 3a and 3b are d1, and the planar shape is a circular shape having a radius R1. The N-type regions 4a and 4b are regions having a high N-type impurity concentration formed from the surface of the P-type regions 3a and 3b to the inside. The depths of the N-type regions 4a and 4b are d2 (<d1), and the planar shape thereof is a circular shape having a radius R2 (<R1). In order to easily determine the polarity, the anode electrodes 6a and 6b and the cathode electrodes 7a and 7b have different diameters.

第1および第2のサージ保護用回路部9a,9bにおいて、PN接合されたP型領域3a,3bとN型領域4a,4bとで、後述する回路上のツェナーダイオードD34a,D34bが構成されている(図3参照)。また、PN接合されたP型領域3a,3bとN型半導体基板2とで、後述する回路上の分離用ダイオードD32a,D32bが構成されている(図3参照)。   In the first and second surge protection circuit portions 9a and 9b, PN-junction P-type regions 3a and 3b and N-type regions 4a and 4b constitute zener diodes D34a and D34b on the circuit described later. (See FIG. 3). Further, the PN junction P-type regions 3a and 3b and the N-type semiconductor substrate 2 constitute separation diodes D32a and D32b on a circuit to be described later (see FIG. 3).

図2は、半導体素子10の使用態様の一例であるLEDパッケージ11を示している。図3は、図2の回路図を示している。このLEDパッケージ11は、半導体素子10、LED12a,12b、金属フレーム1a〜1c、および、光透過性樹脂でなる封止部13を備えている。   FIG. 2 shows an LED package 11 which is an example of a usage mode of the semiconductor element 10. FIG. 3 shows a circuit diagram of FIG. The LED package 11 includes a semiconductor element 10, LEDs 12a and 12b, metal frames 1a to 1c, and a sealing portion 13 made of a light transmissive resin.

半導体素子10は、金属フレーム1b上に配置されている。金属フレーム1bは接地されるか、またはフロー状態で使用される。アノード電極6aは金属フレーム1aと、また、カソード電極7bは金属フレーム1cとワイヤで電気的に接続されている。LED12aは、アノード電極6a上に配置されて、そのP側電極がワイヤによってカソード電極7aと電気的に接続されている。また、LED12bは、アノード電極6b上に配置されて、そのP側電極がワイヤによってカソード電極7bと電気的に接続されている。アノード電極6bとカソード電極7aはワイヤによって電気的に接続されている。以上により金属フレーム1a,1c間でのLED12a,12bの直列接続が実現されている。通常使用時には、金属フレーム1a,1c間に、金属フレーム1c側がプラス側になるよう通常電圧が印加される。通常使用時におけるLED12a,12bの順方向降下電圧を、Vfとする。   The semiconductor element 10 is disposed on the metal frame 1b. The metal frame 1b is grounded or used in a flow state. The anode electrode 6a is electrically connected to the metal frame 1a, and the cathode electrode 7b is electrically connected to the metal frame 1c by wires. LED12a is arrange | positioned on the anode electrode 6a, The P side electrode is electrically connected with the cathode electrode 7a by the wire. The LED 12b is disposed on the anode electrode 6b, and its P-side electrode is electrically connected to the cathode electrode 7b by a wire. The anode electrode 6b and the cathode electrode 7a are electrically connected by a wire. As described above, the series connection of the LEDs 12a and 12b between the metal frames 1a and 1c is realized. During normal use, a normal voltage is applied between the metal frames 1a and 1c so that the metal frame 1c side is a plus side. The forward voltage drop of the LEDs 12a and 12b during normal use is defined as Vf.

ツェナーダイオードD34a,D34bは、ツェナー降伏電圧Vz(D34)が次式(1)に示す条件を満たすように設計される。
Vf<Vz(D34)<Vb …(1)
ここで、Vbは、LED12a,12bの耐電圧である。
The Zener diodes D34a and D34b are designed so that the Zener breakdown voltage Vz (D34) satisfies the condition expressed by the following equation (1).
Vf <Vz (D34) <Vb (1)
Here, Vb is a withstand voltage of the LEDs 12a and 12b.

ツェナーダイオードD34a,D34bが、式(1)に示す条件を満たしているために、金属フレーム1a〜1cからサージ電流が侵入した際に、LED12a,12bには耐電圧以上の過電圧が印加されることがなく、また、金属フレーム1a,1c間(アノード電極6aとカソード電極7bとの間)に通常電圧2Vfが印加されたときには、LED12a,12bが発光する。   Since the Zener diodes D34a and D34b satisfy the condition shown in the expression (1), when a surge current enters from the metal frames 1a to 1c, an overvoltage higher than the withstand voltage is applied to the LEDs 12a and 12b. In addition, when the normal voltage 2Vf is applied between the metal frames 1a and 1c (between the anode electrode 6a and the cathode electrode 7b), the LEDs 12a and 12b emit light.

分離用ダイオードD32a,D32bは、金属フレーム1a,1c間に通常電圧2Vfが印加されたときに、アノード電極6aとカソード電極7bとの間の電位差によってP型領域3aとN型半導体基板2との接合部でツェナー降伏が生じないことを条件とする。この条件を満たしていれば、サージ保護用回路部9aとサージ保護用回路部9bとは、電気的に分離された素子として扱うことができる。分離した素子として取り扱うことができれば、回路設計の自由度が高くなるという利点がある。   The separation diodes D32a and D32b are connected to each other between the P-type region 3a and the N-type semiconductor substrate 2 by a potential difference between the anode electrode 6a and the cathode electrode 7b when the normal voltage 2Vf is applied between the metal frames 1a and 1c. The condition is that no zener breakdown occurs at the junction. If this condition is satisfied, the surge protection circuit portion 9a and the surge protection circuit portion 9b can be handled as electrically separated elements. If it can be handled as a separate element, there is an advantage that the degree of freedom in circuit design is increased.

この条件を十分に満たすようにするためには、P型領域3aとN型半導体基板2とのツェナー降伏電圧Vz(D32)が次式(2)を満たすように、P型領域3aおよびN型半導体基板2を設計すればよい。
Vz(D32)>2Vf …(2)
つまり、P型領域3a,3bは、降伏電圧Vz(D32)が、LED12aの降下電圧VfとLED12bの降下電圧Vfとの和(=2Vf)よりも高くなるように設計すればよい。なお、降伏電圧Vz(D32)の値は、P型領域3a,3bおよびN型半導体基板2の不純物濃度を調整することによって調整できる。
In order to satisfy this condition sufficiently, the P-type region 3a and the N-type are set so that the Zener breakdown voltage Vz (D32) between the P-type region 3a and the N-type semiconductor substrate 2 satisfies the following equation (2). The semiconductor substrate 2 may be designed.
Vz (D32)> 2Vf (2)
That is, the P-type regions 3a and 3b may be designed such that the breakdown voltage Vz (D32) is higher than the sum (= 2Vf) of the drop voltage Vf of the LED 12a and the drop voltage Vf of the LED 12b. The value of breakdown voltage Vz (D32) can be adjusted by adjusting the impurity concentrations of P-type regions 3a and 3b and N-type semiconductor substrate 2.

ツェナーダイオードD34a,D34bの降伏電圧と、分離用ダイオードD32a,D32bの降伏電圧とは、LED12a,12bの特性や個数によって決まることになるが、一般的なLEDを用いる場合には、ツェナーダイオードD34a,D34bの降伏電圧が3〜50V程度、分離用ダイオードD32a,D32bの降伏電圧が、10V以上になっていればよい。   The breakdown voltage of the Zener diodes D34a and D34b and the breakdown voltage of the separation diodes D32a and D32b are determined by the characteristics and the number of the LEDs 12a and 12b. It is sufficient that the breakdown voltage of D34b is about 3 to 50V and the breakdown voltages of the separation diodes D32a and D32b are 10V or more.

このような条件を満たす代表的な構造パラメータを挙げると、N型半導体基板2のN型不純物濃度が1013〜1018cm-3、その厚みが100〜400μm、P型領域3a,3bのP型不純物濃度が1018〜1020cm-3、その深さd1が10〜30μm、N型領域4a,4bのN型不純物濃度が1019〜1021cm-3、その深さd2が5〜10μmである。 As representative structural parameters that satisfy such conditions, the N-type semiconductor substrate 2 has an N-type impurity concentration of 10 13 to 10 18 cm −3 , a thickness of 100 to 400 μm, and P in the P-type regions 3a and 3b. The type impurity concentration is 10 18 to 10 20 cm −3 , the depth d 1 is 10 to 30 μm, the N type impurity concentration of the N type regions 4 a and 4 b is 10 19 to 10 21 cm −3 , and the depth d 2 is 5 to 5. 10 μm.

なお、図1では、N型半導体基板2に2つのサージ保護用回路部9a,9bを設けた場合を示しているが、上記の条件を満たしていれば、サージ保護用回路部9a,9bの個数はいくつであってもよい。例えば、N型半導体基板2のN型不純物濃度が1014cm-3、その厚みが150μmであるときに、P型領域3aのP型不純物濃度を1019cm-3、その深さd1を20μmとし、N型領域4aのN型不純物濃度を1021cm-3、その深さd2を5μmとした場合、ツェナーダイオードD34aの降伏電圧が、Vz(D34)=7V、分離用ダイオードD32aの降伏電圧が、Vz(D32)=60Vとなる。よって、LED12aの順方向電圧降下を2Vとした場合には、このサージ保護用回路部9αを30個まで直列接続した場合でも、サージ保護用回路部9αどうしの電気的な分離が可能になる。 Although FIG. 1 shows the case where two surge protection circuit portions 9a and 9b are provided on the N-type semiconductor substrate 2, if the above conditions are satisfied, the surge protection circuit portions 9a and 9b Any number may be used. For example, when the N-type impurity concentration of the N-type semiconductor substrate 2 is 10 14 cm −3 and the thickness thereof is 150 μm, the P-type impurity concentration of the P-type region 3a is 10 19 cm −3 and the depth d1 is 20 μm. When the N-type impurity concentration of the N-type region 4a is 10 21 cm −3 and the depth d2 is 5 μm, the breakdown voltage of the Zener diode D34a is Vz (D34) = 7V, and the breakdown voltage of the isolation diode D32a However, Vz (D32) = 60V. Therefore, when the forward voltage drop of the LED 12a is 2V, even when up to 30 surge protection circuit portions 9α are connected in series, the surge protection circuit portions 9α can be electrically separated.

図2に示すLEDパッケージ11において、サージ電流侵入時の電流経路を、金属フレーム1bがフロー状態にあるときと接地されているときとに分けて説明する。まず、金属フレーム1bがフロー状態にあるときに、金属フレーム1cからサージ電流(+Is)が侵入すると、まず、カソード電極7bで分流されて、一方がLED12bを順方向に、また、他方がツェナーダイオードD34bを逆方向に流れる。これらの電流を足し合わせた電流は、カソード電極7aで再度分流されて、一方がLED12aを順方向に、また、他方がツェナーダイオードD34aを逆方向に流れ、アノード電極6aから金属フレーム1aに流れる。   In the LED package 11 shown in FIG. 2, the current path when the surge current enters will be described separately when the metal frame 1b is in the flow state and when it is grounded. First, when a surge current (+ Is) enters from the metal frame 1c when the metal frame 1b is in the flow state, first, the current is shunted by the cathode electrode 7b, one of which is the LED 12b in the forward direction, and the other is the zener diode. It flows through D34b in the reverse direction. The current obtained by adding these currents is again shunted by the cathode electrode 7a, one of which flows through the LED 12a in the forward direction and the other of which flows through the Zener diode D34a in the reverse direction, and flows from the anode electrode 6a to the metal frame 1a.

LED12a,12bに耐電圧以上の電圧が印加されるときには、ツェナーダイオードD34a,D34bでツェナー降伏が生じるので、LED12a,12bに過電圧が印加されることがない。   When a voltage higher than the withstand voltage is applied to the LEDs 12a and 12b, Zener breakdown occurs in the Zener diodes D34a and D34b, so that no overvoltage is applied to the LEDs 12a and 12b.

また、金属フレーム1aから、サージ電流(+Is)が侵入した場合には、アノード電極6a、P型領域3a、N型領域4a、カソード電極7a、アノード電極6b、P型領域3b、N型領域4b、カソード電極7bを通って、金属フレーム1cに電流が流れる。この場合、サージ電流+Isは、ツェナーダイオードD34a,D34bを順方向に流れることになる。   When surge current (+ Is) enters from the metal frame 1a, the anode electrode 6a, the P-type region 3a, the N-type region 4a, the cathode electrode 7a, the anode electrode 6b, the P-type region 3b, and the N-type region 4b. A current flows through the metal frame 1c through the cathode electrode 7b. In this case, the surge current + Is flows through the Zener diodes D34a and D34b in the forward direction.

また、金属フレーム1bから、サージ電流(+Is)が侵入した場合には、裏面電極8、N型半導体基板2、P型領域3aを通って、アノード電極6aから金属フレーム1aに電流が流れる。また、一部の電流は、P型領域3aから、N型領域4a、カソード電極7a、アノード電極6b、P型領域3b、N型領域4bを通って、カソード電極7bから金属フレーム1cに流れる。   When surge current (+ Is) enters from the metal frame 1b, the current flows from the anode electrode 6a to the metal frame 1a through the back electrode 8, the N-type semiconductor substrate 2, and the P-type region 3a. Further, a part of the current flows from the cathode electrode 7b to the metal frame 1c through the N-type region 4a, the cathode electrode 7a, the anode electrode 6b, the P-type region 3b, and the N-type region 4b from the P-type region 3a.

一方、金属フレーム1bが接地されているときに金属フレーム1cにサージ電流(+Is)が侵入した場合には、カソード電極7b、N型領域4b、P型領域3b、N型半導体基板2および、裏面電極8を通って、金属フレーム1bにサージ電流が流れる。また、金属フレーム1aにサージ電流(+Is)が侵入した場合には、アノード電極6a、P型領域3a、N型半導体基板2および、裏面電極8を通って、金属フレーム1bにサージ電流が逃れる。よって、この場合も、LED12a,12bに耐電圧以上の電圧が印加されることがない。   On the other hand, when a surge current (+ Is) enters the metal frame 1c while the metal frame 1b is grounded, the cathode electrode 7b, the N-type region 4b, the P-type region 3b, the N-type semiconductor substrate 2, and the back surface A surge current flows through the electrode 8 to the metal frame 1b. When a surge current (+ Is) enters the metal frame 1a, the surge current escapes to the metal frame 1b through the anode electrode 6a, the P-type region 3a, the N-type semiconductor substrate 2, and the back electrode 8. Therefore, also in this case, a voltage higher than the withstand voltage is not applied to the LEDs 12a and 12b.

このように、本発明に係る半導体素子10は、いずれの金属フレーム1a〜1cからサージ電流が侵入した場合にも、別の金属フレーム1a〜1cへとサージ電流を逃すことができ、LED12a,12bに耐電圧以上の電圧が印加されることがない。   As described above, the semiconductor element 10 according to the present invention can release the surge current to the other metal frames 1a to 1c when the surge current enters from any of the metal frames 1a to 1c, and the LEDs 12a and 12b. No voltage higher than the withstand voltage is applied.

次に、図4、図5を用いて、半導体素子10の製造方法の一例を説明する。まず、図4(a),(b)に示すように、P型領域3a,3bを、フォトリソグラフィ、不純物ドーピング、不純物拡散によって形成する。より具体的には、まず、シリコンウェーハにリン等のN型不純物がドーピングされたN型半導体基板2の表面に、フォトマスク14を形成する。そして、開口から露出したN型半導体基板2表面からボロン等のP型不純物をドーピングして1200℃程度で熱拡散させて、P型領域3a,3bを形成する。   Next, an example of a method for manufacturing the semiconductor element 10 will be described with reference to FIGS. First, as shown in FIGS. 4A and 4B, P-type regions 3a and 3b are formed by photolithography, impurity doping, and impurity diffusion. More specifically, first, a photomask 14 is formed on the surface of an N-type semiconductor substrate 2 in which an N-type impurity such as phosphorus is doped on a silicon wafer. Then, P-type impurities such as boron are doped from the surface of the N-type semiconductor substrate 2 exposed from the opening and thermally diffused at about 1200 ° C. to form P-type regions 3a and 3b.

次に、図4(c),(d)に示すように、N型領域4a,4bを、フォトリソグラフィ、不純物ドーピング、不純物拡散によって形成する。より具体的には、N型半導体基板2上にフォトマスク15を形成して、開口から露出したP型領域3a,3bの表面からリン等のN型不純物をドーピングして1150℃程度で熱拡散させて、N型領域4a,4bを形成する。   Next, as shown in FIGS. 4C and 4D, N-type regions 4a and 4b are formed by photolithography, impurity doping, and impurity diffusion. More specifically, a photomask 15 is formed on the N-type semiconductor substrate 2, and N-type impurities such as phosphorus are doped from the surfaces of the P-type regions 3a and 3b exposed from the openings, and thermal diffusion is performed at about 1150 ° C. Thus, N-type regions 4a and 4b are formed.

次に、1100℃程度での熱酸化と化学気相成長法(CVD:Chemical Vapor Deposition)を用いて、N型半導体基板2上に絶縁膜5を形成する(図5(e))。そして、絶縁膜5を選択的にエッチングして、P型領域3a,3bの一部表面とN型領域4a,4bの一部表面とを露出するコンタクト窓16a,16bを形成する(図5(f))。なお、絶縁膜5は、N型半導体基板2表面のうち、周辺部を露出するように形成してもよいし、周辺部も覆うようにしておいてもよい。図5(f)に示すように、N型半導体基板2表面のうち、周辺部を除いて絶縁膜5を形成しておけば、ウェーハからチップに切断する際に、絶縁膜5に掛かるストレスを低減することができる。   Next, an insulating film 5 is formed on the N-type semiconductor substrate 2 using thermal oxidation at about 1100 ° C. and chemical vapor deposition (CVD) (FIG. 5E). Then, the insulating film 5 is selectively etched to form contact windows 16a and 16b exposing the partial surfaces of the P-type regions 3a and 3b and the partial surfaces of the N-type regions 4a and 4b (FIG. 5 ( f)). The insulating film 5 may be formed so as to expose the peripheral portion of the surface of the N-type semiconductor substrate 2 or may cover the peripheral portion. As shown in FIG. 5 (f), if the insulating film 5 is formed excluding the peripheral portion of the surface of the N-type semiconductor substrate 2, the stress applied to the insulating film 5 is reduced when the wafer is cut into chips. Can be reduced.

次に、絶縁膜5上にアルミニウム等の導電率の高い材料をスパッタリングして金属膜を形成する。そして、マスクを用いたドライエッチングによって選択的に金属膜を除去して、アノード電極6a,6bおよび、カソード電極7a,7bを形成する(図5(g))。   Next, a metal film is formed on the insulating film 5 by sputtering a material having high conductivity such as aluminum. Then, the metal film is selectively removed by dry etching using a mask to form anode electrodes 6a and 6b and cathode electrodes 7a and 7b (FIG. 5G).

最後に、N型半導体基板2の裏面に、チタン、金、銀、ニッケル等または、これらを含む金属を蒸着して、多層または単層の裏面電極8を形成する(図5(h))。   Finally, titanium, gold, silver, nickel, or a metal containing these is vapor-deposited on the back surface of the N-type semiconductor substrate 2 to form a multilayer or single-layer back electrode 8 (FIG. 5 (h)).

本実施形態に係る半導体素子10は、複数のLEDを配置できるフリップチップ型のサージ保護用半導体素子である。この半導体素子10によれば、1つのLEDに対してそれぞれ個別にチップ状のサージ保護用半導体素子を接続する場合よりも、実装面の省面積化が可能になり、また周辺回路も簡素化できる。よって、本発明に係るサージ保護用半導体素子を用いれば、より小型のLEDパッケージを実現することができる。   The semiconductor element 10 according to the present embodiment is a flip chip type surge protection semiconductor element in which a plurality of LEDs can be arranged. According to this semiconductor element 10, the mounting surface area can be reduced and the peripheral circuit can be simplified as compared with the case where a chip-like surge protection semiconductor element is individually connected to one LED. . Therefore, if the semiconductor element for surge protection according to the present invention is used, a smaller LED package can be realized.

本実施形態に係る半導体素子10は、LED12a,12bが直列接続され、かつ、各LED12a,12bに対して各1つのサージ保護用回路部9a,9bを並列接続できる構成になっている。LED12a,12bを直列接続した場合、各LED12a,12bに供給される電流値が等しくなるために、各LEDの輝度が均一になる。よって、この半導体素子10を用いれば、輝度変化が等方的なLEDパッケージを実現することができる。   The semiconductor element 10 according to the present embodiment has a configuration in which the LEDs 12a and 12b are connected in series, and each one of the surge protection circuit portions 9a and 9b can be connected in parallel to the LEDs 12a and 12b. When the LEDs 12a and 12b are connected in series, the current values supplied to the LEDs 12a and 12b are equal, so that the brightness of each LED is uniform. Therefore, if this semiconductor element 10 is used, an LED package in which the luminance change is isotropic can be realized.

また、本実施形態に係る半導体素子10は、分離用ダイオードD32a,D32bを備えているために、サージ保護用回路部9aとLED12aとでなる組(サージ保護用回路部/保護対象物対)と、サージ保護用回路部9bとLED12bとでなる組とを、電気的に分離された素子として個別に取り扱うことができる。よって、本発明に係る半導体素子10を用いれば、これを搭載する回路の設計自由度が高くなる。   In addition, since the semiconductor element 10 according to the present embodiment includes the separation diodes D32a and D32b, a set of the surge protection circuit unit 9a and the LED 12a (surge protection circuit unit / protection target pair) The combination of the surge protection circuit portion 9b and the LED 12b can be individually handled as an electrically separated element. Therefore, if the semiconductor element 10 according to the present invention is used, the degree of freedom in designing a circuit on which the semiconductor element 10 is mounted increases.

なお、カソード電極7a,7bとアノード電極6a,6bとの間に接続される保護すべき素子は、LED以外の素子であってもよい。また、上記実施形態では、N型半導体基板2に、P型領域3a,3bおよびN型領域4a,4bを設けた場合を説明したが、各部の導電型を逆にした場合にも本発明は有効である。その場合には、N型半導体基板2の代わりにP型半導体基板を用い、例えばリンをドーピングして1200℃程度で熱拡散させることによって、P型領域3a,3bの代わりとなるN型領域を形成すればよい。そして、形成したN型領域内にボロンをドーピングして1150℃程度で熱拡散させることによって、N型領域4a,4bの代わりとなるP型領域を形成するようにすればよい。   The element to be protected connected between the cathode electrodes 7a and 7b and the anode electrodes 6a and 6b may be an element other than the LED. In the above embodiment, the case where the P-type regions 3a and 3b and the N-type regions 4a and 4b are provided in the N-type semiconductor substrate 2 has been described. However, the present invention also applies to the case where the conductivity type of each part is reversed. It is valid. In that case, a P-type semiconductor substrate is used in place of the N-type semiconductor substrate 2, and, for example, phosphorus is doped and thermally diffused at about 1200 ° C. What is necessary is just to form. Then, boron may be doped into the formed N-type region and thermally diffused at about 1150 ° C. to form a P-type region instead of the N-type regions 4a and 4b.

(第2の実施形態)
図6(a),(b)は、本発明の第2の実施形態に係るサージ保護用半導体素子20(以下、半導体素子20という)の断面図および、N型半導体基板2の平面図を示している。半導体素子20は、N型半導体基板2、P型領域3a〜3c、N型領域4a〜4c、絶縁膜5、カソード電極7a〜7c、アノード電極6a〜6c、および、裏面電極8を備えている。N型半導体基板2には、3個のサージ保護用回路部9a〜9cが設けられている。本実施形態では、第1の実施形態で説明した構成要素には同じ参照符号を付して説明を省略する。
(Second Embodiment)
6A and 6B are a cross-sectional view of a surge protection semiconductor element 20 (hereinafter referred to as a semiconductor element 20) and a plan view of the N-type semiconductor substrate 2 according to the second embodiment of the present invention. ing. The semiconductor element 20 includes an N-type semiconductor substrate 2, P-type regions 3a to 3c, N-type regions 4a to 4c, an insulating film 5, cathode electrodes 7a to 7c, anode electrodes 6a to 6c, and a back electrode 8. . The N-type semiconductor substrate 2 is provided with three surge protection circuit portions 9a to 9c. In this embodiment, the same reference numerals are given to the components described in the first embodiment, and the description thereof will be omitted.

本実施形態に係る半導体素子20において、カソード電極7aとアノード電極6b、および、カソード電極7bとアノード電極6cは、配線22a,22bによって電気的に接続されている。配線22a,22bは、カソード電極7a〜7cおよびアノード電極6a〜6cを形成する工程で同時に形成すればよい。   In the semiconductor element 20 according to this embodiment, the cathode electrode 7a and the anode electrode 6b, and the cathode electrode 7b and the anode electrode 6c are electrically connected by wirings 22a and 22b. The wires 22a and 22b may be formed simultaneously in the step of forming the cathode electrodes 7a to 7c and the anode electrodes 6a to 6c.

図7は、この半導体素子20の使用態様の一例であるLEDパッケージ21を示している。また、図8は、図7の回路図を示している。半導体素子20は、金属フレーム1b上に配置されている。そして、アノード電極6aが金属フレーム1aと、また、カソード電極7cが金属フレーム1cとワイヤで電気的に接続されている。そしてアノード電極6aとカソード電極7aとの間、アノード電極6bとカソード電極7bとの間、アノード電極6cとカソード電極7cとの間には、それぞれLED12a〜12cが電気的に接続されている。これによりLED12a〜12cの直列接続が実現されている。半導体素子20には予め配線22a,22bが設けられているために、電極間をワイヤで接続する手間を要しない。   FIG. 7 shows an LED package 21 which is an example of a usage mode of the semiconductor element 20. FIG. 8 shows a circuit diagram of FIG. The semiconductor element 20 is disposed on the metal frame 1b. The anode electrode 6a is electrically connected to the metal frame 1a, and the cathode electrode 7c is electrically connected to the metal frame 1c by wires. The LEDs 12a to 12c are electrically connected between the anode electrode 6a and the cathode electrode 7a, between the anode electrode 6b and the cathode electrode 7b, and between the anode electrode 6c and the cathode electrode 7c, respectively. Thereby, series connection of LED12a-12c is implement | achieved. Since the semiconductor element 20 is provided with the wirings 22a and 22b in advance, there is no need to connect the electrodes with wires.

なお、半導体素子20は3つのサージ保護用回路部9a〜9cを備えているが、N型半導体基板2に設けられるサージ保護用回路部9α(αはa,b…)の個数は、2個以上であればいくつであってもよい。   Although the semiconductor element 20 includes three surge protection circuit portions 9a to 9c, the number of surge protection circuit portions 9α (α is a, b...) Provided on the N-type semiconductor substrate 2 is two. Any number is possible as long as it is above.

例えば図9は、9個のサージ保護用回路部9a〜9iを備えたサージ保護用半導体素子の平面図の一例を示している。このサージ保護用半導体素子には、LEDを行列(3×3)に配置して直列接続することができる。図9において、サージ保護用回路部9αのカソード電極7αと、その隣に位置するサージ保護用回路部9β(βはa,b…であって、β≠α)のアノード電極6βとは、配線22αで接続されており、これにより9個のサージ保護用回路部9αが直列接続されている。   For example, FIG. 9 shows an example of a plan view of a surge protection semiconductor element including nine surge protection circuit portions 9a to 9i. LEDs can be arranged in a matrix (3 × 3) and connected in series to this semiconductor element for surge protection. In FIG. 9, the cathode electrode 7α of the surge protection circuit section 9α and the anode electrode 6β of the surge protection circuit section 9β (β is a, b... Nine surge protection circuit portions 9α are connected in series.

図9等に示しているように、極性によって電極の大きさを変えていれば、アノード電極6a〜6iとカソード電極7a〜7iとを目視によって区別し易いが、それに加えて、配線22a〜22iが形成されていると、LED(図示せず)を設置する位置を容易に判断できるようになる。つまり、配線22a〜22iによって接続されていない電極間にLEDを配置すれば良いので、特にサージ保護用回路部9αが多数形成されている場合には、予め配線を形成しておくと便利である。   As shown in FIG. 9 and the like, the anode electrodes 6a to 6i and the cathode electrodes 7a to 7i can be easily visually distinguished if the size of the electrodes is changed depending on the polarity, but in addition, the wirings 22a to 22i If it is formed, the position where the LED (not shown) is installed can be easily determined. That is, since it is sufficient to arrange the LEDs between the electrodes that are not connected by the wirings 22a to 22i, it is convenient to form wirings in advance, especially when a large number of surge protection circuit portions 9α are formed. .

本発明に係るサージ保護用半導体素子は、複数のLEDをESD等のサージから保護するサージ保護用半導体素子として有用である。   The semiconductor element for surge protection according to the present invention is useful as a semiconductor element for surge protection that protects a plurality of LEDs from surges such as ESD.

(a)は、本発明の第1の実施形態に係るサージ保護用半導体素子の平面図、(b)は、(a)のA−A’線断面図(A) is a top view of the semiconductor element for surge protection which concerns on the 1st Embodiment of this invention, (b) is the sectional view on the A-A 'line of (a). 図1のサージ保護用半導体素子を用いたLEDパッケージの一例を示す図The figure which shows an example of the LED package using the semiconductor element for surge protection of FIG. 図2に示す半導体パッケージの回路図Circuit diagram of the semiconductor package shown in FIG. (a)〜(d)は、図1のサージ保護用半導体素子の製造方法を説明するための図(A)-(d) is a figure for demonstrating the manufacturing method of the semiconductor element for surge protection of FIG. (e)〜(f)は、図4の続図(E)-(f) is a continuation figure of FIG. (a)は、本発明の第2の実施形態に係るサージ保護用半導体素子の平面、(b)は、(a)のB−B’線断面図(A) is the plane of the semiconductor element for surge protection which concerns on the 2nd Embodiment of this invention, (b) is the B-B 'sectional view taken on the line of (a). 図6のサージ保護用半導体素子を用いたLEDパッケージの一例を示す図The figure which shows an example of the LED package using the semiconductor element for surge protection of FIG. 図7に示す半導体パッケージの回路図Circuit diagram of the semiconductor package shown in FIG. 9個のサージ保護用回路部を備えたサージ保護用半導体素子の平面図Plan view of a semiconductor device for surge protection provided with nine surge protection circuit sections (a)は、従来のLEDパッケージを示す図、(b)は、その回路図(A) is a figure which shows the conventional LED package, (b) is the circuit diagram. 従来のサージ保護用半導体素子を用いたLEDパッケージの予想図Expected view of LED package using conventional semiconductor device for surge protection 図11の回路図Circuit diagram of FIG.

符号の説明Explanation of symbols

1a〜1c 金属フレーム
2 N型半導体基板
3 P型領域
4 N型領域
5 絶縁膜
6a〜6i アノード電極
7a〜7i カソード電極
8 裏面電極
9a〜9c サージ保護用回路部
10 サージ保護用半導体素子
11 LEDパッケージ
13 封止部
12a〜12c LED
20 サージ保護用半導体素子
22a〜22i 配線
100 サージ保護用半導体素子
101a,101b 金属フレーム
102 N型半導体基板
103 P型領域
105 絶縁膜
106 カソード電極
107 アノード電極
108 裏面電極
120 LED

DESCRIPTION OF SYMBOLS 1a-1c Metal frame 2 N type semiconductor substrate 3 P type area | region 4 N type area | region 5 Insulating film 6a-6i Anode electrode 7a-7i Cathode electrode 8 Back surface electrodes 9a-9c Surge protection circuit part 10 Surge protection semiconductor element 11 LED Package 13 Sealing part 12a-12c LED
20 Surge protection semiconductor elements 22a to 22i Wiring 100 Surge protection semiconductor elements 101a and 101b Metal frame 102 N-type semiconductor substrate 103 P-type region 105 Insulating film 106 Cathode electrode 107 Anode electrode 108 Back electrode 120 LED

Claims (7)

サージから保護すべき素子を並列接続して使用するツェナーダイオードを備えたサージ保護用半導体素子であって、
第1導電型の半導体基板と、
前記ツェナーダイオードをそれぞれに含む複数のサージ保護用回路部と、
前記半導体基板の裏面に形成した裏面電極とを備え、
前記各サージ保護用回路部は、
前記半導体基板の表面から内部に形成した第2導電型領域と、
前記第2導電型領域の表面から内部に形成した第1導電型領域と、
前記第1導電型領域の一部と前記第2導電型領域の一部とを露出する絶縁膜と、
前記絶縁膜から露出した前記第1導電型領域に形成した第1の表面電極と、
前記絶縁膜から露出した前記第2導電型領域に形成した第2の表面電極とを有する、サージ保護用半導体素子。
A semiconductor device for surge protection provided with a Zener diode that is used by connecting in parallel elements to be protected from surge,
A first conductivity type semiconductor substrate;
A plurality of surge protection circuit units each including the Zener diode;
A back electrode formed on the back surface of the semiconductor substrate,
Each of the circuit portions for surge protection is
A second conductivity type region formed inside from the surface of the semiconductor substrate;
A first conductivity type region formed inside from the surface of the second conductivity type region;
An insulating film exposing a part of the first conductivity type region and a part of the second conductivity type region;
A first surface electrode formed in the first conductivity type region exposed from the insulating film;
And a second surface electrode formed in the second conductivity type region exposed from the insulating film.
前記第1導電型領域と前記第2導電型領域とでなる前記ツェナーダイオードの降伏電圧の大きさが、通常使用時における前記保護すべき素子の降下電圧よりも大きく、当該保護すべき素子の耐電圧未満であることを特徴とする、請求項1に記載のサージ保護用半導体素子。   The breakdown voltage of the Zener diode composed of the first conductivity type region and the second conductivity type region is larger than the voltage drop of the element to be protected during normal use, and the resistance of the element to be protected is 2. The semiconductor element for surge protection according to claim 1, wherein the semiconductor element is less than a voltage. 前記ツェナーダイオードの降伏電圧が、3〜50Vであることを特徴とする、請求項2に記載のサージ保護用半導体素子。   The semiconductor device for surge protection according to claim 2, wherein a breakdown voltage of the Zener diode is 3 to 50V. 前記第2導電型領域と前記半導体基板とでなる分離用ダイオードの降伏電圧が、通常使用時における前記各保護すべき素子の降下電圧の和よりも高いことを特徴とする、請求項1に記載のサージ保護用半導体素子。   The breakdown voltage of the isolation diode composed of the second conductivity type region and the semiconductor substrate is higher than the sum of the drop voltages of the elements to be protected during normal use. Surge protection semiconductor element. 前記分離用ダイオードの降伏電圧が、10V以上であることを特徴とする、請求項4に記載のサージ保護用半導体素子。   5. The semiconductor device for surge protection according to claim 4, wherein a breakdown voltage of the isolation diode is 10 V or more. 前記サージ保護用回路部の前記第1の表面電極と、別の前記サージ保護用回路部の前記第2の表面電極とを接続することによって、全てのサージ保護用回路部を直列接続する配線をさらに備えた、請求項1に記載のサージ保護用半導体素子。   By connecting the first surface electrode of the circuit portion for surge protection and the second surface electrode of another circuit portion for surge protection, wiring for connecting all the circuit portions for surge protection in series The semiconductor device for surge protection according to claim 1, further comprising: サージから保護すべき素子を並列接続するツェナーダイオードを備えたサージ保護用半導体素子の製造方法であって、
第1導電型の半導体基板の表面から内部に複数の第2導電型領域を形成する工程と、
前記各第2導電型領域の表面から内部に第1導電型領域を形成する工程と、
前記第1導電型領域の一部と前記第2導電型領域の一部とを露出する絶縁膜を形成する工程と、
前記絶縁膜から露出した前記第1導電型領域と前記第2導電型領域とに、第1および第2の表面電極を形成する工程と、
前記半導体基板の裏面に裏面電極を形成する工程とを備えたサージ保護用半導体素子の製造方法。
A method for manufacturing a semiconductor device for surge protection comprising a Zener diode for connecting elements to be protected from surge in parallel,
Forming a plurality of second conductivity type regions inside from the surface of the first conductivity type semiconductor substrate;
Forming a first conductivity type region from the surface of each second conductivity type region to the inside;
Forming an insulating film exposing a part of the first conductivity type region and a part of the second conductivity type region;
Forming first and second surface electrodes in the first conductivity type region and the second conductivity type region exposed from the insulating film;
And a step of forming a back electrode on the back surface of the semiconductor substrate.
JP2005046481A 2005-02-23 2005-02-23 Semiconductor element for surge protection, and its manufacturing method Pending JP2006237104A (en)

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