JP2006226792A - Pattern defect inspection method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To accurately adjust the defect inspection sensitivity of a circuit pattern formed on a semiconductor wafer. <P>SOLUTION: A pattern for defect inspection formed of the circuit pattern and a produced defect of a predetermined dimension is formed on the semiconductor wafer, the pattern for defect inspection is detected, prior to the defect inspection of the circuit pattern, and the inspection sensitivity is adjusted, based on the inspection result. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a pattern defect inspection method, and more particularly to a defect inspection method for a circuit pattern formed on a semiconductor wafer.

  In the manufacture of semiconductor ICs, a plurality of types of photomasks having various types of circuit patterns such as diffusion layer patterns and wiring layer patterns are used, and circuit patterns of each photomask are formed using photolithography technology and dry etching technology. The process of transferring and transferring on the semiconductor wafer in a predetermined order is repeated. In these patterning steps, if a mismatch occurs between the circuit pattern of the photomask and the circuit pattern actually formed on the semiconductor wafer, the mismatched portion acts as a defect and causes a malfunction of the semiconductor IC. The pattern mismatch often occurs due to pinholes or deposits caused by foreign matter mixed in during the pattern formation process, but it is difficult to completely remove these foreign substances from the pattern formation process. Defects are inevitable. Therefore, it is necessary to appropriately perform a pattern defect inspection after the pattern forming process to remove defective products.

  When pattern defects are inspected, when a repeated pattern is formed on the same chip like a memory cell, a repeated pattern comparison method for comparing the same patterns separated by this repeated interval, formed at a position separated on the semiconductor wafer. A chip comparison method for comparing patterns at the same location of two chips is used. In the repeated pattern comparison method, the pattern to be compared is located at a relatively close position, so that the inspection accuracy is high, but the inspection is limited to the repeated pattern. On the other hand, the chip comparison method can inspect all patterns on the chip, but since the patterns to be compared are separated, the inspection accuracy is easily affected by the difference in the pattern dimensions and pattern overlay accuracy of the chips. Lower than the repeated pattern comparison method.

  FIG. 7 is a block diagram showing a pattern defect inspection apparatus. In the figure, a semiconductor wafer 11 to be inspected is fixed to an XY stage 12, and the XY stage 12 scans the surface of the semiconductor wafer 11 in the X and Y directions by a stage control unit 21. Above the semiconductor wafer 11, an illumination optical system composed of an illumination light source 13, a half mirror 15, and an objective lens 14 and a CCD image sensor 16 are arranged, and light emitted from the illumination light source 13 is reflected by the half mirror 15. After being focused by the objective lens 14, the light enters the semiconductor wafer 11. Then, the reflected light is taken into the CCD image sensor 16 through the objective lens 14 and the half mirror 15. The reflected light captured by the CCD image sensor 16 is converted into a digital signal of, for example, 256 gradations and sent to the inspection control unit 17.

  The inspection control unit 17 performs image processing on the digital signal sent from the CCD image sensor 16, inspection condition setting unit 19 for setting inspection conditions, image display unit 20 for displaying inspection results on a map, and XY stage 12. It comprises a stage control unit 21 for controlling the above. When comparing the digital signals of the pattern in the image processing unit 18, the digital signal delayed by the distance or the repetition interval between the two chips by the delay memory is compared depending on whether the repetitive pattern comparison method or the chip comparison method is used. Is done. Then, it is determined whether or not the pattern mismatch amount exceeds a predetermined threshold value in a predetermined pixel unit, and when it exceeds, it is determined as a defect, and the position coordinates of the defective portion are displayed on the image display unit 19. Here, the pattern mismatch amount is, for example, an amount indicated by a difference between digital signals represented by 256 gradations.

  If the size and the amount of mismatch of the pattern do not affect the operation of the semiconductor IC, they do not substantially act as defects. Therefore, in the pattern defect inspection, the inspection condition setting unit 20 notifies the image processing unit 18 of the size of the mismatched portion and the allowable range of the mismatched amount in advance, and the defect is detected only when the detected mismatched amount exceeds the allowable range. I will consider it. Here, the threshold value indicating the allowable range determines the inspection sensitivity in the pattern defect inspection, and is specifically determined by the pixel size and the digital signal difference described above.

  The detected defect location is displayed as a defect map on the semiconductor wafer 11 by the image display unit 20. FIGS. 8A and 8B are diagrams showing an example of a defect map of a semiconductor wafer. Chips 22 are arranged on the semiconductor wafer 11 in a matrix. FIG. 8A shows a case where the inspection sensitivity is set lower than the appropriate value, and FIG. 8B shows a case where the inspection sensitivity is set higher than the appropriate value. Is shown.

  Here, if the genuine defect to be detected is at the position indicated by a white mark in FIG. 8A, only the white mark is detected as a defect if the inspection sensitivity is properly set, and the white mark and the black mark are detected. The positions of the marks must match. However, when the inspection sensitivity is set lower than the appropriate value as shown in FIG. 8A, many white marks that are genuine defects are overlooked without being detected. On the other hand, when the inspection sensitivity is set higher than the appropriate value as seen in FIG. 8B, the operation of the semiconductor IC, such as the minute unevenness at the edge of the circuit pattern and the roughness of the pattern surface, is affected. Even those that do not exist will be detected as defects. In FIG. 8 (b), since there are too many defective portions detected, only the defective portions detected by scanning the chip on the first row arranged on the semiconductor wafer are indicated by black marks for the sake of simplicity. The defective part of the chip | tip arrange | positioned below is abbreviate | omitted.

  As described above, if the inspection sensitivity is lowered more than necessary, a genuine defect is overlooked and the yield of the semiconductor IC is lowered. Conversely, if the inspection sensitivity is too high, even a non-original defect is regarded as a defect and processed. Therefore, it takes a lot of time to correct in a later process. Therefore, in pattern defect inspection, it is required to detect only genuine defects indicated by white marks in FIG. 8A by setting appropriate inspection sensitivity. However, pixels and digital signals that determine inspection sensitivity are required. There are an unlimited number of combinations of differences, and the experience and intuition of the inspection operator are required to set the inspection sensitivity to an appropriate value.

Therefore, prior to defect inspection of a semiconductor wafer on which a circuit pattern is formed, a method of adjusting the inspection sensitivity by creating a pseudo-defect wafer having a built-in defect of a predetermined size and inspecting the pseudo-defect wafer is proposed. However, the inspection sensitivity is influenced not only by the planar size of the defect but also by the height from the surface of the semiconductor wafer. Therefore, a method has been proposed in which simulated defect wafers in which various types of simulated defects having different heights from the surface of the semiconductor wafer and in-plane sizes are used for adjustment of inspection sensitivity (Patent Document 1).
JP 2001-337047 A

  However, since the optical inspection method described above uses the reflected light of the light irradiated to the pattern, the detection accuracy is also affected by the material and thickness of the conductive film and insulating film constituting the pattern, the surface condition, etc. The However, in the conventional simulated defect wafer, the pattern material and the surface state are different from the circuit pattern on the semiconductor wafer which is actually a product. As a result, even if the inspection sensitivity is adjusted using the simulated defective wafer, there is a problem that the inspection sensitivity is shifted when inspecting the circuit pattern on the semiconductor wafer that is actually a product.

  Accordingly, it is an object to accurately adjust the defect inspection sensitivity of a circuit pattern formed on a semiconductor wafer.

  The present invention forms a defect inspection pattern consisting of a built-in defect of a predetermined dimension together with a circuit pattern on a semiconductor wafer, detects the defect inspection pattern prior to the defect inspection of the circuit pattern, and based on the detection result The main feature is to adjust the inspection sensitivity.

  Since the defect inspection pattern in the present invention is formed at the same time as the circuit pattern on the semiconductor wafer, the pattern thickness, material, surface condition, etc. are exactly the same as the circuit pattern of the chip as the product. Therefore, there is an advantage that the defect inspection sensitivity for the circuit pattern can be accurately adjusted by detecting the defect inspection pattern and adjusting the sensitivity based on the result.

(Example 1)
In the present invention, a circuit pattern and a defect inspection pattern are formed on a chip basis on each photomask having different types of circuit patterns. Then, the circuit pattern of each photomask is transferred to a semiconductor wafer in a predetermined order using a known photolithography technique and etching technique.

  FIG. 1 is a plan view showing a semiconductor wafer onto which a circuit pattern and a defect inspection pattern are transferred using a photomask. On a chip 2 arranged in a matrix on the semiconductor wafer 1, a circuit pattern 3 and a defect inspection pattern 4 are formed as seen in the enlarged view shown on the right side of the figure. For example, the defect inspection pattern 4 may be formed in a scribe line region. Examples of the circuit pattern 3 include a chip diffusion layer pattern and a wiring layer pattern.

  2a and 4b shown in FIG. 2 show examples of the defect inspection pattern 4. FIG. The defect inspection pattern 4a is composed of 10 line / space patterns formed by repeating five 100 nm wide lines. A part of the lines constituting the line / space pattern is 10 nm in order from the left. , 20 nm... The defect inspection pattern 4b is formed by arranging line patterns having widths of 10 nm, 20 nm,.

  After the circuit pattern 3 and the defect inspection pattern 4 are transferred onto the semiconductor wafer 1, the semiconductor wafer is set in the defect inspection apparatus shown in FIG. First, prior to the defect inspection for the circuit pattern 3, the defect inspection pattern 4 is inspected. When the defect inspection pattern 4a shown in FIG. 2 is formed as the defect inspection pattern 4, the defect inspection is performed between a line partially shifted in the same line / space pattern and a line positioned next to the line. The comparison is performed, and whether or not there is a defect is determined based on whether or not the difference between the two compared lines has been detected. When the defect inspection pattern 4b shown in FIG. 2 is used, the presence / absence of a defect is determined based on whether or not each line having a different width has been detected.

  FIG. 3 shows an example of a defect map on the chip 2 obtained by the defect inspection performed on the defect inspection pattern 4a. In the figure, black marks indicate positions where defects are detected on the chip 2, and formation positions of the circuit pattern 3 and the defect inspection pattern 4 a are indicated by dotted lines. From the figure, it can be seen that only the 10 lines / space patterns constituting the defect inspection pattern 4a having a line with a shift amount of 50 nm or more are detected as defects. Therefore, when the defect inspection is subsequently performed on the circuit pattern, the inspection sensitivity does not change because the circuit pattern 3 has the same material and height from the semiconductor wafer surface as the defect inspection pattern 4a. Inspection shows that defects of 50 nm or more in the circuit pattern are reliably detected.

  Although the inspection sensitivity of the pattern defect inspection apparatus can be accurately known by the above method, the following method is used to adjust the pattern defect inspection apparatus to a desired inspection sensitivity.

  First, as shown in FIG. 1, defect inspection patterns are formed on a plurality of chips 2 formed in a semiconductor wafer 1. Here, it is assumed that the defect inspection pattern 4a shown in FIG. 2 is formed for eight of the 80 chips formed in 8 rows and 10 columns on the semiconductor wafer 1. Then, after setting the semiconductor wafer in the pattern defect inspection apparatus shown in FIG. 7, the inspection condition setting unit 19 performs defect inspection on the defect inspection patterns of the eight chips while changing the inspection sensitivity.

  FIG. 4 shows the shift amount, the detected number, and the detection rate of the defect inspection pattern 4a for eight chips when the inspection sensitivity is set to 25 (arbitrary unit). Here, the shift amount is an amount indicating the shift width of a part of the line / space pattern shown in FIG. 2, the detected number is the number of chips in which the line / space pattern having a predetermined shift amount is detected as a defect, and the detection rate. Is an amount indicating the ratio of the number of chips in which a defect is detected to the number of inspected chips. Similarly, FIG. 5 shows the shift amount of detected defects, the number of detections, and the detection rate for eight chips when the inspection sensitivity is changed from 25 to 30 (arbitrary unit). 4 and 5, when attention is paid to a built-in defect having a shift amount of, for example, 40 nm, it can be seen that when the inspection sensitivity is 25, the detection rate is 75%, and when the sensitivity is 30, the detection rate is 50%.

  FIG. 6 is a plot of the relationship between inspection sensitivity and detection rate for a built-in defect with a shift amount of 40 nm. In order to obtain a detection rate of 100% for a defect having a size of 40 nm by connecting and extending the points indicating the detection rates at the inspection sensitivities of 25 and 30 with straight lines from FIG. It can be seen that the adjustment is necessary.

  Since the defect inspection sensitivity with respect to the circuit pattern formed on the semiconductor wafer can be adjusted quickly and accurately, it is effective in improving the reliability of the semiconductor IC.

The figure which shows the semiconductor wafer which concerns on the Example of this invention. The figure which shows the example of the pattern for a defect inspection. The figure which shows the defect map on a chip | tip. The figure which shows the result of a pattern defect inspection (the 1). The figure which shows the result of a pattern defect inspection (the 2). The figure explaining the adjustment method of inspection sensitivity. The block diagram which shows a pattern defect inspection apparatus. The figure which shows the defect map on the semiconductor wafer which concerns on a prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 11 Semiconductor wafer 2, 22 Chip 3 Circuit pattern 4, 4a, 4b Defect inspection pattern 12 XY stage 13 Illumination light source 14 Objective lens 15 Mirror 16 CCD image sensor 17 Inspection control part 18 Image processing part 19 Inspection condition setting part 20 Image display unit 21 Stage control unit

Claims (4)

  A defect inspection pattern consisting of a built-in defect of a predetermined dimension is formed on a semiconductor wafer together with a circuit pattern, the defect inspection pattern is detected prior to the defect inspection of the circuit pattern, and the inspection sensitivity is determined based on the detection result. A pattern defect inspection method characterized by performing adjustment.   2. The pattern defect inspection method according to claim 1, wherein the built-in defect is formed by shifting a part of a pattern repeatedly appearing on the semiconductor wafer by a predetermined distance.   2. The pattern defect inspection method according to claim 1, wherein the built-in defect includes a plurality of repetitive patterns obtained by shifting a part of a pattern repeatedly appearing on the semiconductor wafer by different distances stepwise.   The pattern defect inspection method according to claim 1, wherein the built-in defect includes a plurality of patterns having different dimensions in stages.

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