JP2006222149A - Semiconductor module - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor module wherein upper and lower arms are paired and which has high heat dissipation as well as reduced parasitic inductance. <P>SOLUTION: The semiconductor module 100 has a structure wherein a semiconductor element is pinched by a pair of metallic electrodes. An intermediate connection is provided between the upper and lower arms to electrically connect them. In addition, the upper arm is provided with an external terminal section for a power supply positive terminal on the same side surface as a side surface to be bonded with the intermediate connection. The lower arm is provided with an external terminal section for a power supply negative terminal on the same side surface as a side surface to be bonded with the intermediate connection. Furthermore, the external terminal of the power supply positive terminal is arranged face to face with that of the power supply negative terminal, so that they are overlapped when viewed in the direction of thickness of the semiconductor module. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor module formed by combining a plurality of semiconductor elements (power MOSFET, IGBT, etc.). More specifically, the present invention relates to a semiconductor module that is used for power control and includes a pair of an upper arm and a lower arm.

  Conventionally, as a semiconductor module for power control, a semiconductor module in which an upper arm and a lower arm are paired is used. As shown in FIG. 17, this semiconductor module is connected in an antiparallel manner to an upper arm 10 composed of an IGBT element 11 and a diode element 12 connected in antiparallel to the IGBT element 11, an IGBT element 21, and an IGBT element 21. The upper arm 10 and the lower arm 20 are connected in series. A known inverter circuit is configured by combining a plurality of such semiconductor modules.

In general, when a semiconductor module is applied to a power IC for high withstand voltage and large current, heat generated from the element during use is large. Therefore, high heat dissipation is required. As an example of a configuration that solves this problem, for example, Patent Document 1 proposes a semiconductor device having a double-sided heat dissipation structure in which a plurality of semiconductor elements are sandwiched between substrates having high thermal conductivity on both sides of the elements.
JP-A-10-56131

  However, the conventional semiconductor module described above has the following problems. That is, in the semiconductor module in which the upper arm and the lower arm are paired, the parasitic inductance of the wiring portion is large. Specifically, in FIG. 17, L1 (inductance between the P terminal and the collector of the upper arm 10), L2 (inductance between the emitter of the upper arm 10 and the connection point), L3 (connection point and lower arm). 20), and L4 (inductance between the emitter of the lower arm 20 and the N terminal) has parasitic inductance. As the parasitic inductance L increases, the surge voltage increases (surge voltage = parasitic inductance L × current change rate dI / dt). Therefore, in the semiconductor module applied to the power converter for high withstand voltage and large current, it is particularly required to reduce the parasitic inductance L.

  Specifically, to reduce the parasitic inductance L, it is conceivable to shorten the length of the wiring portion or increase the cross-sectional area of the wiring. However, since the size of the semiconductor module itself increases due to the wiring arrangement and the like, there is a limit to changing the physical size.

  Therefore, for example, as in the semiconductor device disclosed in Patent Document 1, the external wiring terminals of the front and back substrates are arranged so as to extend in the same direction from the same side surface of the semiconductor module, thereby reducing the parasitic inductance. Has been proposed (see FIG. 18). That is, it is disclosed that the inductance is reduced by utilizing the mutual inductance between the external wiring terminals P and N through which currents in opposite directions flow.

  However, in the semiconductor device of Patent Document 1, although the external wiring terminals P and N are opposed to each other, the distance between them is wide. Further, since the external wiring terminals are arranged in parallel in the surface direction of the substrate, the facing area is small. Therefore, the effect of reducing internal inductance due to mutual inductance cannot be expected. Even if the external wiring terminals P and N face each other and the parasitic inductances L1 and L4 of the external wiring terminal portion can be reduced to some extent, the other portions, for example, the inductances L2 and L3 of the internal terminals are reduced. It is not possible. For this reason, the inductance reduction effect can hardly be expected.

  The present invention has been made to solve the problems of the conventional semiconductor device described above. That is, an object of the present invention is to provide a semiconductor module in which an upper arm and a lower arm are a set, and has a high heat dissipation property and a reduced parasitic inductance.

  A semiconductor module for solving this problem includes a first semiconductor element group constituting an upper arm part and a second semiconductor element group constituting a lower arm part. The first semiconductor element group and the second semiconductor A semiconductor module having an element group arranged in the same plane, the first metal electrode located on one side of the first semiconductor element group, and the other side of the first semiconductor element group, A second metal electrode opposed to the first metal electrode across one semiconductor element group; a third metal electrode located on one side of the second semiconductor element group and electrically connected to the second metal electrode; , A fourth metal electrode which is located on the other surface side of the second semiconductor element group and faces the third metal electrode across the second semiconductor element group, and one end portion of which is the lower arm of the second metal electrode The other end is the upper metal electrode of the third metal electrode. A plate-like shape that is joined to a portion opposed to the first metal portion and electrically connected to the second metal electrode and the third metal electrode, and a portion of the first metal electrode opposite to the lower arm portion. And a flat negative electrode side extraction terminal joined to a portion of the fourth metal electrode facing the upper arm portion.

  That is, the semiconductor module of the present invention is a set of an upper arm having a first semiconductor element group and a lower arm having a second semiconductor element group. In the semiconductor module of the present invention, the first semiconductor element group is sandwiched between the flat plate-like first metal electrode and the second metal electrode, and the second semiconductor element group is sandwiched between the plate-like third metal electrode and the fourth metal electrode. It is out. That is, the semiconductor element group is sandwiched between a pair of plate-like metal electrodes that also function as a heat radiating plate, and heat is radiated from two directions, the upper surface and the lower surface.

  In the semiconductor module of the present invention, the first semiconductor element group and the second semiconductor element group are arranged in the same plane. That is, the upper arm portion and the lower arm portion are arranged in parallel in the same plane. Furthermore, the semiconductor module of the present invention includes an intermediate connection portion that electrically connects the second metal electrode and the third metal electrode between the upper arm portion and the lower arm portion. And the positive electrode side extraction terminal is joined to the site | part facing the lower arm part among 1st metal electrodes, and the negative electrode side extraction terminal is joined to the site | part facing the upper arm part among 4th metal electrodes. By arranging the intermediate connection portion and the power supply terminal of each arm portion in this way, the upper arm portion has a main current flowing through the first metal electrode and a main current flowing through the second metal electrode as compared with the conventional terminal arrangement. The opposing component of increases more. On the other hand, in the lower arm portion, the opposing component of the main current flowing through the third metal electrode and the main current flowing through the fourth metal electrode is further increased. Therefore, even if it is an internal terminal part, the reduction effect of the parasitic inductance by a mutual inductance is acquired, and the reduction of the parasitic inductance as the whole semiconductor module is achieved.

  Note that the fact that the main currents face each other or the directions of the main currents are opposite does not mean that the directions are strictly different by 180 degrees. That is, the difference may be within a range where reduction of inductance due to mutual inductance can be expected. Specifically, if more than half of the current component in the opposite direction is within a range of 180 ° ± 60 °, which is expected as a reduction effect, the effect can be expected.

  Further, in the semiconductor module of the present invention, the power supply terminal of each arm portion is provided at a portion facing the other arm portion. That is, the power supply terminal of each arm part is located between both arm parts. On the other hand, an intermediate connection portion that electrically connects the upper arm and the lower arm is also located between the arm portions. For this reason, the power supply output terminal and the intermediate terminal portion are arranged close to each other. Therefore, it is possible to reduce the inductance of the power supply extraction terminal and the inductance of the intermediate terminal portion located inside the semiconductor module.

  In addition, the semiconductor module of the present invention includes a semiconductor element (transistor element region and diode element region) constituting the first semiconductor element group and a semiconductor element (transistor element area) constituting the second semiconductor element group as viewed from the electrode surface. And the diode element region) are more preferably arranged on the same straight line. With such an arrangement, it is possible to reliably make the directions of currents flowing through the metal electrodes facing each other across the semiconductor element face each other. Therefore, the parasitic inductance of the internal terminal portion can be reliably reduced.

  In the semiconductor module of the present invention, it is better that the positive electrode side extraction terminal and the negative electrode side extraction terminal are opposed to each other. That is, in the semiconductor module of the present invention, the flat positive electrode side extraction terminal and the flat negative electrode side extraction terminal face each other so as to be overlapped in the thickness direction. For this reason, the distance between the power supply terminals is short and the mutual inductance of both terminals is large. Since the main currents flowing through both terminals are opposite to each other, the parasitic inductance of the external terminal portion is greatly reduced.

  According to the present invention, high heat dissipation is ensured by sandwiching the semiconductor element between the metal electrodes to form a double-sided heat dissipation structure. In addition, according to the present invention, a portion of the wiring constituting the semiconductor module, in which the direction of the main current is opposite, is provided in a wide range. Therefore, parasitic inductance can be reduced by mutual inductance. Therefore, a semiconductor module in which the upper arm and the lower arm are combined as one set and having a high heat dissipation property while reducing the parasitic inductance is realized.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments embodying the present invention will be described below in detail with reference to the accompanying drawings. In the following embodiment, the present invention is applied to a power module (semiconductor module) used in an inverter device.

  FIG. 1 shows an equivalent circuit of the semiconductor module 100 of this embodiment. As shown in FIG. 1, the semiconductor module 100 is connected in an antiparallel manner to an upper arm 10 including an IGBT element 11 and a diode element 12 connected in antiparallel to the IGBT element 11, an IGBT element 21, and an IGBT element 21. The upper arm 10 and the lower arm 20 are connected in series. That is, the semiconductor module 100 has a structure in which the upper arm 10 and the lower arm 20 are a set.

  In this semiconductor module 100, each IGBT element is turned on and off by inputting a control signal to the gate terminal of each IGBT element. Thereby, the power supplied to the motor to be controlled is controlled.

  Next, a specific structure of the semiconductor module 100 will be described. FIG. 2 shows the appearance of the semiconductor module 100 as viewed from the top and right sides. 3 shows an AA section of FIG. 2 and a DD section of FIG. 4, FIG. 4 shows a BB section of FIG. 3, and FIG. 5 shows a CC section of FIG. In each figure, the arrow in each metal electrode means the direction of the main current flow.

  As shown in FIGS. 2 to 5, the semiconductor module 100 has a structure in which the upper arm 10 and the lower arm 20 are juxtaposed in the same plane. The upper arm 10 includes an IGBT element 11 and a diode element 12, and has a structure in which both semiconductor elements are sandwiched between flat metal electrodes 13 and 14. The lower arm 20 includes an IGBT element 21 and a diode element 22, and has a structure in which both semiconductor elements are sandwiched between flat metal electrodes 23 and 24. That is, in the upper arm 10, the metal electrodes 13 and 14 face each other with the semiconductor elements 11 and 12 therebetween. On the other hand, in the lower arm 20, the metal electrodes 23 and 24 face each other with the semiconductor elements 21 and 22 interposed therebetween. In both arms, the semiconductor element and the metal electrode are joined by solder or a conductive adhesive. Therefore, in the semiconductor module 100, a current flows in the vertical direction in FIG.

  Further, the metal electrode 13 of the upper arm 10 and the metal electrode 23 of the lower arm 20 are arranged in the same plane. The metal electrode 14 and the metal electrode 24 are also arranged in the same plane. Furthermore, the IGBT element 11 and the diode element 12 of the upper arm 10 and the IGBT element 21 and the diode element 22 of the lower arm 20 are also arranged in the same plane, more specifically in the same straight line.

  In the semiconductor module 100, the gaps between the metal electrodes are filled with a resin (for example, epoxy resin) 6. That is, the upper arm 10 and the lower arm 20 are integrated by being molded with the resin 6.

  Moreover, the semiconductor module 100 has a positive electrode side extraction terminal 1, a negative electrode side extraction terminal 2, and an intermediate extraction terminal 3 as external terminal portions. Each terminal is a flat metal terminal and protrudes from the side surface of the semiconductor module 100. As other external terminals, a gate electrode terminal 15 for the upper arm 10 and a gate electrode terminal 25 for the lower arm 20 are provided.

  Specifically, the side surface of the positive electrode extraction terminal 1 is joined to the side surface of the metal electrode 13 that faces the lower arm 20. That is, the positive electrode side extraction terminal 1 is located between the upper arm 10 and the lower arm 20 and is integrated with the metal electrode 13 (hereinafter, the positive electrode side extraction terminal 1 and the metal electrode 13 that is an internal wiring are connected to each other). The integrated part is called “power supply + terminal”). Further, the side surface of the negative electrode side extraction terminal 2 is joined to the side surface of the metal electrode 24 facing the upper arm 10. That is, the negative electrode side extraction terminal 2 is located between the upper arm 10 and the lower arm 20 in the same manner as the positive electrode side extraction terminal 1, and is integrated with the metal electrode 24 (hereinafter referred to as the negative electrode side extraction terminal 2 and the internal portion). A portion where the metal electrode 24 that is the wiring is integrated is referred to as a “power supply-terminal”). Furthermore, the positive electrode side extraction terminal 1 and the negative electrode side extraction terminal 2 protrude in the same direction from the same side surface of the semiconductor module 100, and the planes thereof face each other. That is, when viewed from the upper surface of the semiconductor module 100, the positive electrode side extraction terminal 1 and the negative electrode side extraction terminal 2 are arranged to overlap each other.

  Further, the side surface of the intermediate extraction terminal 3 is joined to the side surface of the metal electrode 14 other than the side facing the lower arm 20. That is, the intermediate extraction terminal 3 is located on the upper arm 10 side and away from the positive electrode extraction terminal 1 and is integrated with the metal electrode 14. The intermediate extraction terminal 3 may be bonded to the metal electrode 23. In this case, the intermediate extraction terminal 3 is joined to the side surface of the metal electrode 23 other than the side facing the upper arm 10.

  The gate electrode terminal 15 is electrically connected to the gate electrode portion of the IGBT element 11 through a bonding wire. On the other hand, the gate electrode 25 is electrically connected to the gate electrode portion of the IGBT element 25 through a bonding wire.

  In addition, the semiconductor module 100 includes an intermediate connection portion 4 that electrically connects both arms at a position between the upper arm 10 and the lower arm 20. Specifically, the intermediate connection portion 4 faces the upper arm 10 among the side surfaces of the metal electrode 14 of the upper arm 10 facing the lower arm 20 and the side surface of the metal electrode 23 of the lower arm 20. The two metal electrodes are electrically connected to each other. That is, the metal electrode 14 and the metal electrode 23 are integrated via the intermediate connection portion 4 (hereinafter, the portion where the metal electrodes 13 and 23 and the intermediate connection portion 4 as internal wiring are integrated is referred to as “intermediate terminal”. ”).

  That is, the positive electrode side extraction terminal 1 and the negative electrode side extraction terminal 2 and the intermediate connection portion 4 are both located between the upper arm 10 and the lower arm 20. Therefore, both are close to each other, and are opposed to each other when viewed from the upper surface side of the semiconductor module 100.

  Further, Cu, Cu-based alloy, Al, Al-based alloy is used for each external terminal and each metal electrode. By sandwiching each semiconductor element with these metals, heat generated from each semiconductor element is dissipated from both the upper surface and the lower surface. That is, each metal electrode and each metal terminal also function as a heat sink, and perform heat radiation in two directions, the upper surface and the lower surface. Therefore, the semiconductor module 100 has high heat dissipation.

  Next, the flow of the main current in the semiconductor module 100 will be described with reference to FIG. The arrows in FIG. 6 indicate the direction of current flow, and IP1, IQ1, IP2, IU, IN1, IQ2, and IN2 represent currents, respectively, and the same symbols in the circuit diagram of FIG. It is synonymous.

  When the IGBT element 11 of the upper arm 10 is on and the IGBT element 21 of the lower arm 20 is off, a current flows from the positive terminal 1 of the power source + terminal toward the internal terminal (IP1). Then, a current flows through the IGBT element 11 (IQ1) toward the intermediate extraction terminal 3 of the intermediate terminal (IP2, IU).

  On the other hand, when the IGBT element 11 of the upper arm 10 is off and the IGBT element 21 of the lower arm 20 is on, a current flows from the intermediate extraction terminal 3 of the intermediate terminal toward the internal terminal portion (IN2). Then, it passes through the intermediate connection part (IN2) and further passes through the IGBT element 21 (IQ2). Then, a current flows from the IGBT element 21 toward the negative output terminal 2 of the power source terminal (IN1).

  Next, a simulation result of mutual inductance between conductors will be described. In this simulation, conductor A and conductor B are prepared as shown in FIG. 7, and are arranged in parallel in the thickness direction so that the planes of both conductors face each other. Each of the conductors A and B has a size of width 8 mm × length 50 mm × thickness 1 mm, and the self-inductance of each conductor is 30 nH. FIG. 8 shows the relationship between the mutual inductance and the distance between the conductors A and B arranged in this way. As shown in the graph of FIG. 8, it can be seen that the smaller the distance between the conductors A and B, the larger the mutual inductance value.

  Specifically, the distance between the conductor A and the conductor B is set to 1 mm, and reverse currents are simultaneously supplied to the conductors. In that case, a negative mutual inductance of 25 nH is generated in each conductor. This mutual inductance reduces the self-inductance of each conductor, resulting in an inductance of each conductor of 5 nH. That is, in the configuration of this simulation, it can be seen that the inductance of each conductor is reduced to 1/6 by setting the distance between the conductor A and the conductor B to 1 mm and simultaneously flowing reverse currents.

  Next, the inductance reduction effect in the semiconductor device 100 of this embodiment will be examined. In order to reduce the inductance by using the mutual inductance, it is necessary to arrange the conductors having the same amount of current change and the opposite directions of the current in proximity to each other. Therefore, changes in current during switching are shown in FIGS. FIG. 9 shows the current change at the moment when IU> 0, the upper arm is turned from ON to OFF, and the lower arm is turned from OFF to ON. FIG. 10 shows the current change at the moment when IU <0, the upper arm is turned from ON to OFF, and the lower arm is turned from OFF to ON. FIG. 11 shows the current change at the moment when IU> 0, the upper arm is turned from OFF to ON, and the lower arm is turned from ON to OFF. FIG. 12 shows the current change at the moment when IU <0, the upper arm is turned from OFF to ON, and the lower arm is turned from ON to OFF.

  As shown in FIG. 9, when IU> 0, the upper arm is turned from ON to OFF, and the lower arm is turned from OFF to ON, the current (IP1, IQ1, IP2) of the upper arm instantaneously decreases. The rate of change is negative. On the other hand, even if the IGBT element of the upper arm is turned off, the current IU continues to flow, so the negative current (IN2, ID2, IN1) flowing through the lower arm increases. For this reason, the current change rate is similarly negative. At this time, since no current flows through the diode element of the upper arm and the IGBT element of the lower arm, ID1 and IQ2 remain 0. As a result, it can be seen that (IP1, IQ1, IP2) and (IN2, ID2, IN1) are preferably arranged to face each other.

  Similarly, in the case shown in FIG. 10, since the upper arm is turned from ON to OFF, the current (IP1, ID1, IP2) of the upper arm decreases. Therefore, the current change rate becomes a positive value. On the other hand, since the lower arm is turned from OFF to ON, the positive current (IN2, IQ2, IN1) increases. Therefore, the current change rate is also a positive value. Therefore, it can be seen that (IN2, IQ2, IN1) and (IP1, ID1, IP2) are preferably arranged to face each other.

  In the case shown in FIG. 11, since the lower arm is turned from ON to OFF, the current (IN2, ID2, IN1) of the lower arm decreases. Therefore, the current change rate becomes a positive value. On the other hand, in the upper arm, the positive current (IP1, IQ1, IP2) increases because it is turned from OFF to ON. Therefore, the current change rate is also a positive value. Therefore, it can be seen that (IP1, IQ1, IP2) and (IN2, ID2, IN1) are preferably arranged to face each other.

  In the case shown in FIG. 12, since the lower arm is turned from ON to OFF, the current (IN2, IQ2, IN1) of the lower arm decreases. Therefore, the current change rate becomes a negative value. On the other hand, since the upper arm is turned from OFF to ON, negative currents (IP1, ID1, IP2) increase. For this reason, the current change rate is also negative. Therefore, it can be seen that (IN2, IQ2, IN1) and (IP1, ID1, IP2) are preferably arranged to face each other.

  That is, it can be seen that in order to use the mutual inductance in all cases shown in FIGS. 9 to 12, it is preferable that the part where IP1 and IP2 flow is opposite to the part where IN1 and IN2 flow.

  Therefore, in the semiconductor module 100 of the present embodiment, the effect of reducing the parasitic inductance due to the mutual inductance can be expected particularly at the following four locations. The first part is a portion where the positive electrode side extraction terminal 1 of the power source + terminal and the negative electrode side extraction terminal 2 of the power source terminal are opposed to each other ((1) in FIG. 6). That is, the positive electrode side extraction terminal 1 and the negative electrode side extraction terminal 2 are arranged to face each other, and IP1 and IN1 flowing through them are opposite to each other. Therefore, the parasitic inductance (inductances L1 and L4) can be reduced.

  The second part is a part where the vicinity of the take-out part of the metal electrode 13 of the power source + terminal and the intermediate connection part 4 of the intermediate terminal face each other ((2) in FIG. 6). That is, since the metal electrode 13 through which the current IP1 flows and the intermediate connection portion 4 through which the current IN2 flows are arranged to face each other, parasitic inductance (inductances L1 and L3) can be reduced.

  The third place is a portion where the intermediate connection portion 4 of the intermediate terminal and the vicinity of the take-out portion of the metal electrode 24 of the power source-terminal face each other ((3) in FIG. 6). That is, since the intermediate connection portion 4 through which the current IN2 flows and the metal electrode 24 through which the current IN1 flows are disposed to face each other, parasitic inductance (inductances L3 and L4) can be reduced.

  The fourth part is a part where the metal electrode part 23 of the intermediate terminal and the metal electrode 24 of the power source-terminal face each other ((4) in FIG. 6). That is, since the metal electrode 23 through which the current IN2 flows and the metal electrode 24 through which the current IN1 flows are arranged to face each other, parasitic inductance (inductances L3 and L4) can be reduced.

  On the other hand, in the semiconductor device shown in Patent Document 1 (conventional form), a current flows as shown in FIG. In this semiconductor device, the external terminal portions are certainly facing each other ((1 ′) in FIG. 13). However, the distance between the external terminals is large and the mutual inductance is small. Therefore, reduction of parasitic inductance due to mutual inductance cannot be expected. As for the internal terminal portions, the direction of the current flowing in the intermediate terminal and the direction of the current flowing in the other terminals intersect at an angle close to orthogonal ((2 ') in FIG. 13). Therefore, reduction of parasitic inductance due to mutual inductance cannot be expected.

  As described in detail above, the semiconductor module 100 of this embodiment has a structure in which the upper arm portion 10 and the lower arm portion 20 are a set, and the semiconductor elements constituting each arm are sandwiched between a pair of metal electrodes. I am going to do that. That is, it has a double-sided heat dissipation structure and has high heat dissipation. Further, between the upper arm 10 and the lower arm 20, an intermediate connection portion 4 that electrically connects both arms is provided. Further, in the upper arm 10, the positive electrode side extraction terminal 1 is provided on the same side surface as the side surface joined to the intermediate connection portion 4. In the lower arm 20, the negative electrode side extraction terminal 2 is provided on the same side surface as the side surface joined to the intermediate connection portion 4. For this reason, among the metal electrodes, there are many opposing components of the main current in the region near the portion where the power supply terminal is joined and the portion where the intermediate connection portion 4 is joined. Therefore, it is possible to reduce the parasitic inductance in those areas. Therefore, a semiconductor module in which the upper arm and the lower arm are combined as one set and having a high heat dissipation property and a reduction in parasitic inductance is realized.

  Further, in the semiconductor module 100, the positive electrode side extraction terminal 1 and the negative electrode side extraction terminal 2 which are external terminal portions are opposed to each other on their planes. That is, when viewed from the top surface of the semiconductor module, the positive electrode side extraction terminal 1 and the negative electrode side extraction terminal 2 are superposed. Therefore, the distance between both terminals is narrow and the mutual inductance value is large. Therefore, the effect of reducing inductance is great.

  Note that this embodiment is merely an example, and does not limit the present invention. Therefore, the present invention can naturally be improved and modified in various ways without departing from the gist thereof. For example, the arrangement of the semiconductor elements is not limited to the embodiment. In other words, the arrangement may be such that the direction of the current flowing in the opposing metal electrode is opposite.

  Further, the number of IGBT elements and diode elements constituting each arm is not limited to one. That is, as shown in FIGS. 14 and 15, a plurality of IGBT elements and diode elements may be arranged on one arm. FIG. 16 shows an equivalent circuit of the semiconductor module shown in FIGS.

It is a figure which shows the equivalent circuit of the semiconductor module concerning embodiment. It is a figure which shows the external appearance seen from the upper surface and side surface of the semiconductor module concerning embodiment. It is a figure which shows the AA cross section of the semiconductor module shown in FIG. It is a figure which shows the BB cross section of the semiconductor module shown in FIG. It is a figure which shows CC cross section of the semiconductor module shown in FIG. It is a figure which shows arrangement | positioning of a semiconductor element, and the flow of main current of the semiconductor module concerning embodiment. It is a figure which shows arrangement | positioning of the conductors A and B concerning a simulation. It is a graph which shows the relationship between the mutual inductance in the arrangement | positioning shown in FIG. 7, and the distance between conductors. It is a figure which shows the change of the electric current at the time of switching (IU> 0, upper arm ON to OFF, lower arm OFF to ON). It is a figure which shows the change of the electric current at the time of switching (IU <0, upper arm ON to OFF, lower arm OFF to ON). It is a figure which shows the change of the electric current at the time of switching (IU> 0, upper arm OFF to ON, lower arm ON to OFF). It is a figure which shows the change of the electric current at the time of switching (IU <0, upper arm OFF to ON, lower arm ON to OFF). It is a figure which shows arrangement | positioning of a semiconductor element, and the flow of main current of the semiconductor module concerning the conventional form. It is FIG. (1) which shows the application example of arrangement | positioning of a semiconductor element. It is FIG. (2) which shows the application example of arrangement | positioning of a semiconductor element. It is a figure which shows the equivalent circuit of the semiconductor module concerning an application example. It is a figure which shows the equivalent circuit of the semiconductor module with which the upper arm and the lower arm became one set. It is a perspective view which shows the external appearance of the semiconductor module concerning the conventional form.

Explanation of symbols

1 Positive side extraction terminal (Positive side extraction terminal)
2 Negative side extraction terminal (Negative side extraction terminal)
3 Intermediate extraction terminal 4 Intermediate connection (intermediate connection)
6 Resin 10 Upper arm (upper arm)
11 IGBT element (first semiconductor element group)
12 Diode element (first semiconductor element group)
13 Metal electrode (first metal electrode)
14 Metal electrode (second metal electrode)
15 Gate electrode terminal 20 Lower arm (lower arm)
21 IGBT element (second semiconductor element group)
22 Diode element (second semiconductor element group)
23 Metal electrode (third metal electrode)
24 Metal electrode (4th metal electrode)
25 Gate electrode terminal 100 Semiconductor module (semiconductor module)

Claims (5)

A semiconductor comprising a first semiconductor element group constituting an upper arm part and a second semiconductor element group constituting a lower arm part, wherein the first semiconductor element group and the second semiconductor element group are arranged in the same plane In the module,
A first metal electrode located on one surface side of the first semiconductor element group;
A second metal electrode located on the other surface side of the first semiconductor element group and facing the first metal electrode across the first semiconductor element group;
A third metal electrode located on one surface side of the second semiconductor element group and electrically connected to the second metal electrode;
A fourth metal electrode positioned on the other surface side of the second semiconductor element group and facing the third metal electrode across the second semiconductor element group;
One end is joined to a part of the second metal electrode facing the lower arm part, and the other end is joined to a part of the third metal electrode facing the upper arm part, An intermediate connection portion for electrically connecting the second metal electrode and the third metal electrode;
A plate-like positive electrode side extraction terminal joined to a portion of the first metal electrode facing the lower arm portion;
A semiconductor module comprising: a flat-plate-like negative electrode side extraction terminal joined to a portion of the fourth metal electrode facing the upper arm portion. The semiconductor module according to claim 1,
The first semiconductor element group is arranged such that the direction of the main current flowing through the first metal electrode is substantially opposite to the direction of the main current flowing through the second metal electrode, and the main current flowing through the third metal electrode is 2. The semiconductor module according to claim 1, wherein the second semiconductor element group is disposed so that a direction is substantially opposite to a direction of a main current flowing through the fourth metal electrode. In the semiconductor module according to claim 1 or 2,
A semiconductor module, wherein a semiconductor element constituting the first semiconductor element group and a semiconductor element constituting the second semiconductor element group are arranged on the same straight line when viewed from the electrode surface. In the semiconductor module according to any one of claims 1 to 3,
The semiconductor module according to claim 1, wherein the positive electrode side extraction terminal and the negative electrode side extraction terminal are opposed to each other. A semiconductor comprising a first semiconductor element group constituting an upper arm part and a second semiconductor element group constituting a lower arm part, wherein the first semiconductor element group and the second semiconductor element group are arranged in the same plane In the module,
A first metal electrode located on one surface side of the first semiconductor element group;
A second metal electrode located on the other surface side of the first semiconductor element group and facing the first metal electrode across the first semiconductor element group;
A third metal electrode located on one surface side of the second semiconductor element group and electrically connected to the second metal electrode;
A fourth metal electrode positioned on the other surface side of the second semiconductor element group and facing the third metal electrode across the second semiconductor element group;
A plate-like positive electrode side extraction terminal electrically connected to the first metal electrode;
A flat negative electrode side extraction terminal electrically connected to the fourth metal electrode,
The semiconductor module according to claim 1, wherein the positive electrode side extraction terminal and the negative electrode side extraction terminal are opposed to each other.

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