JP2006210692A - Group iii nitride compound semiconductor light emitting device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve characteristics of a light emitting device by preventing generation of misfit dislocation and edge dislocation and raising crystallinity. <P>SOLUTION: A region changes its composition for relaxing a lattice constant of a barrier layer 41 and a well layer 43. The region is provided by using a ternary or binary compound of a group III nitride compound semiconductor between clad layers 3, 5 or the barrier layer 41 and the well layer 43, or in a junction to the well layer 43 inside the clad layers 3, 5 or the barrier layer 41. For example, the composition is changed in the order of AlGaN to GaN to InGaN. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a group III nitride compound semiconductor light emitting device having a quantum well structure.

Conventionally, a group III nitride compound semiconductor light-emitting device uses a multiple quantum well (MQW) structure in which layers having different band gap energies are alternately stacked at a predetermined period. For example, a multiple quantum in which a well layer made of In _0.2 Ga _0.8 N with a thickness of 2.5 nm and a barrier layer made of In _0.05 Ga _0.95 N or GaN with a thickness of 5 nm are alternately stacked. There are blue light emitting diodes (LEDs) and green LEDs having a well (MQW) structure and a single quantum well (SQW) structure having a single well layer with a thickness of about 3 nm. Recently, a near-ultraviolet LED having a light emission wavelength of about 380 nm and a 405 nm blue-violet laser diode (LD) have been proposed. It has become. In general, in a heterojunction including the above structure, the occurrence of dislocations due to lattice mismatch at the heterojunction surface causes problems such as a reduction in luminous intensity, a decrease in output due to a decrease in output and deterioration in a light emitting element. The group III nitride compound semiconductor also has a similar problem due to a difference in lattice constant as shown in FIG. In particular, in recent LEDs in the near ultraviolet region of about 380 nm and 405 nm blue-violet LD, since AlGaN is used for the barrier layer, the occurrence of dislocation has become remarkable.

On the other hand, means for solving the above-described problem of lattice mismatch related to the group III nitride compound semiconductor light-emitting device is disclosed in the following publicly known documents.
Japanese Patent Laid-Open No. 64-17484 JP-A-11-26812 JP 2001-230447 A

According to Patent Document 1, only the relaxation of lattice mismatch is premised, and in both Example 1 and Example 2, a ternary InGaN light-emitting layer is formed as a current injection layer (cladding layer) of a single quaternary AlInGaN layer. ). However, quaternary AlInGaN with good crystallinity has not been realized, and even if improved in terms of relaxation of lattice mismatch, it has the most important characteristics as a light emitting element with light emission intensity and output intensity. It cannot be.
According to Patent Document 2, the In composition of the well layer, which is a light emitting layer, is made to be substantially the same at the interface with the barrier layer and continuously changed so as to be maximized at the substantially central portion in the thickness direction. It has a structure. However, a change in the composition of the well layer is not preferable because a plurality of levels are formed in the well layer, and as a result, a large number of emission levels, that is, a large number of emission wavelengths are generated. In general, since the well layer is very thin, it is difficult to change the composition in the well layer.
Further, according to Patent Document 3, in order to alleviate lattice mismatch between the substrate and the n-contact layer, between the aluminum nitride (AlN) that is the buffer layer and the gallium nitride (GaN) layer that is the n-contact layer. In this structure, an AlGaN layer is inserted and the Al composition is changed stepwise. However, there is no disclosure or suggestion as to whether or how this structure can be applied to the light emitting layer.
Therefore, in view of the above problems, an object of the present invention relates to a group III nitride compound semiconductor light-emitting device having a quantum well structure, which suppresses the occurrence of misfit dislocations in the vicinity of the interface of the well layer and is caused by misfit dislocations. An object of the present invention is to realize a group III nitride compound semiconductor light emitting device in which the occurrence of edge dislocations is prevented, the crystallinity is enhanced, and at the same time, the device characteristics (emission intensity, output intensity and life) are further improved.

In order to solve the above-mentioned problem, according to the means of claim 1, it is a group III nitride compound semiconductor light emitting device having a quantum well structure, and a layer and a well layer formed above and below the well layer And a region where the lattice constant of the layer formed above and below the well layer is changed so as to approach the lattice constant of the well layer. By adopting this structure, it is possible to suppress the occurrence of misfit dislocations in the vicinity of the interface of the well layer and at the same time to suppress the generation of multiple levels in the well layer. Can be improved.

In order to solve the above-mentioned problem, according to the means described in claim 2, the region is formed in layers formed above and below the well layer. It is possible to continuously change from the layers formed above and below the well layer to the well layer without forming a new layer.
In order to solve the above problems, according to the means described in claim 3, the layers formed above and below the well layer are clad layers. In a single quantum well structure, the layers formed above and below the well layer also act as cladding layers, so the presence of this region suppresses the occurrence of misfit dislocations near the interface of the well layer and at the same time, Since generation of a plurality of levels can be suppressed, the crystallinity can be improved and the device characteristics can be further improved.
In order to solve the above-mentioned problem, according to the means described in claim 4, the layers formed above and below the well layer are barrier layers (barrier layers). Even when applied to a multiple quantum well (MQW) structure, the presence of this region suppresses the generation of misfit dislocations in the vicinity of the interface of the well layer and at the same time suppresses the generation of a plurality of levels in the well layer. The device characteristics can be further improved at the same time as improving the properties.
In order to solve the above problem, according to the means of claim 5, the layers formed above and below the well layer are Al _x Ga _1-x N (0 <x <1), and the well layer is In _y Ga _1-y N (0 ≦ y <1), the region is Al _{x ′} Ga _{1-x ′} N (0 ≦ x ′ <1), and x ′ in the region is from x ′ = x. It is characterized by being changed in the direction of x ′ = 0. By using a ternary group III-nitride semiconductor with good crystallinity and at the interface with the well layer, GaN (Al _{x ′} Ga _1- x′N with the best crystallinity is x ′ = 0. ) Can suppress the generation of misfit dislocations in the vicinity of the interface of the well layer, and can also suppress the generation of a plurality of levels in the well layer. be able to.
In order to solve the above-described problem, according to the means of claim 6, the layers formed above and below the well layer are Al _x Ga _1-x N (0 <x <1), and the well layer is In _y Ga _1-y N (0 <y <1), and the region is In _{y ′} Ga _{1-y ′} N (0 ≦ y ′ <1) and Al _{x ′} Ga _1-x from the well layer side. _“ N” (0 ≦ x ′ <1), and y ′ and x ′ are changed from y to y through y ′ = x ′ = 0 to x from the well layer side. It is characterized by. Ternary system with good crystallinity (AlGaN and InGaN) and GaN with the best crystallinity (x ′ = 0 in Al _{x ′} Ga _{1-x ′} N and _{y ′} = in In _{y ′} Ga _{1-y ′} N 0) can suppress the generation of misfit dislocations in the vicinity of the interface of the well layer and simultaneously suppress the generation of multiple levels in the well layer. Can be made.

The inventions of claims 1 to 6 suppress the occurrence of misfit dislocations in the vicinity of the interface of the well layer, prevent the occurrence of edge dislocations due to misfit dislocations, increase the crystallinity, and at the same time A semiconductor device with improved characteristics (emission intensity, output intensity and life). In particular, by using ternary and binary compositions having good crystallinity, the effect becomes remarkable.

FIG. 2 is a schematic cross-sectional configuration diagram of a light-emitting element 10 made of a group III nitride semiconductor of a type that emits light from the semiconductor layer side formed on the sapphire substrate 1. A buffer layer 2 made of AlN and having a thickness of about 25 nm is provided on the substrate 1, and a high carrier concentration layer 3 made of silicon (Si) -doped GaN and having a thickness of about 4.0 μm is formed thereon. Yes. Then, a barrier layer 41 made of Al _0.1 Ga _0.9 N having a thickness of about 8 nm on the high carrier concentration layer 3 and a thickness of about 1. nm within the barrier layer and in contact with a well layer described later. At 5 nm, the Al composition becomes GaN, and the regions 42 in which the In composition continuously changes and the well layers 43 made of In _0.1 Ga _0.9 N having a thickness of about 3 nm are alternately stacked. The multiple quantum well layer 4 thus formed is formed. The barrier layer 41 is composed of four layers, and the well layer 43 is composed of three layers. On the multiple quantum well layer 4, a clad layer 5 made of p-type Al _0.4 Ga _0.6 N and having a thickness of about 20 nm is formed. Further, a contact layer 6 made of p-type GaN and having a thickness of about 100 nm is formed on the cladding layer 5. In this embodiment, the film thickness of the region 42 is 1.5 nm, but the film thickness of the region 42 is preferably in the range of 1/40 to 3/8 of the film thickness of the barrier layer. If the thickness of the region 42 is too thick, a plurality of quantum levels based on the material composition of the barrier layer are formed in the well layer, and the same problem as in Patent Document 2 occurs. In addition, if the region 42 is too thin, it becomes difficult to control the temperature up and down and composition described later.
A translucent electrode 7 is formed on the contact layer 6, and an electrode 8 is formed on the high carrier concentration layer 3. On the electrode 7, an electrode 9 for bonding is further formed. The translucent electrode 7 bonded to the contact layer 7 is ITO having a film thickness of about 150 nm. The electrode 8 is made of vanadium (V) having a film thickness of about 20 nm and aluminum (Al) having a film thickness of about 1.8 μm. The electrode 9 is made of about 2.0 μm of gold (Au).
Next, a method for manufacturing the light emitting element 10 will be described. The light emitting device 10 was manufactured by vapor phase growth by metal organic chemical vapor deposition (hereinafter abbreviated as “MOVPE”). The gases used were ammonia (NH ₃ ), carrier gas (H ₂ , N ₂ ), trimethyl gallium (Ga (CH ₃ ) ₃ ) (hereinafter referred to as “TMG”), trimethyl aluminum (Al (CH ₃ ) ₃ (Hereinafter referred to as “TMA”), trimethylindium (In (CH ₃ ) ₃ ) (hereinafter referred to as “TMI”), silane (SiH ₄ ) and cyclopentadienyl magnesium (Mg (C ₂ H ₅ ) ₂ ) (Hereinafter referred to as “CP ₂ Mg”).
(Crystal growth)
First, a single-crystal sapphire substrate 1 having an a-plane cleaned by organic cleaning and heat treatment as a main surface is mounted on a susceptor mounted in a reaction chamber of a MOVPE apparatus. Next, the substrate 1 was baked at a temperature of 1100 ° C. while flowing H ₂ into the reaction chamber at normal pressure. Next, the temperature of the substrate 1 was lowered to 400 ° C., and H ₂ , NH ₃ , and TMA were supplied to form the buffer layer 2 made of AlN with a film thickness of about 25 nm. Next, the temperature of the substrate 1 is maintained at 1150 ° C., H ₂ , NH ₃ , TMG, and silane are supplied, and a high carrier concentration of GaN having a film thickness of about 4.0 μm and an electron concentration of 2 × 10 ¹⁸ / cm ^3. Layer 3 was formed.
After the high carrier concentration layer 3 is formed, N ₂ , NH ₃ , TMA, and TMG are supplied by setting the temperature of the substrate 1 to 900 ° C., and from Al _0.1 Ga _0.9 N having a film thickness of about 5 nm. Next, the supply amount of TMA is decreased while the temperature of the substrate 1 is lowered, and after the supply amount of TMA becomes 0, the supply amount of TMI is increased and the film thickness is about 1.5 nm. Region 42 was formed. This temperature drop is set so that TMI is supplied to form the well layer In _0.1 Ga _0.9 N when the temperature of the substrate 1 reaches 600 ° C. In the present embodiment, a layer made of Al _0.1 Ga _0.9 N having a thickness of about 5 nm and a region 42 having a thickness of about 1.5 nm are used as the first barrier layer 41. Next, N ₂ , NH ₃ , TMG, and TMI were supplied to form an In _0.1 Ga _0.9 N well layer 52 having a thickness of about 3 nm. Next, while the substrate temperature is raised, the supply amounts of N ₂ , NH ₃ , and TMG are constant, the supply amount of TMI is decreased, and after the supply amount of TMI reaches zero, the supply amount of TMA is increased. A region 42 having a thickness of about 1.5 nm was formed. This temperature rise is set so that TMA is supplied to form the next Al _0.1 Ga _0.9 N when the temperature of the substrate 1 reaches 900 ° C. Subsequently, N ₂ , NH ₃ , TMA, and TMG are supplied to form a layer made of Al _0.1 Ga _0.9 N having a film thickness of about 5 nm. Next, the temperature of the substrate 1 is decreased while the temperature of the TMA is decreased. After the supply amount was decreased and the TMA supply amount became zero, the TMI supply amount was increased to form a region 42 having a film thickness of about 1.5 nm. This temperature drop is set so that TMI is supplied to form the well layers In _0.1 a _0.9 N when the temperature of the substrate 1 reaches 600 ° C. Therefore, in the second barrier layer, the barrier layer 41 is a total of 8 nm including a layer made of Al _0.1 Ga _0.9 N having a thickness of about 5 nm and a region 42 having a thickness of two layers of about 1.5 nm. Similarly, the formation of the barrier layer and the well layer is repeated, and after the final well layer is formed, the supply amount of N ₂ , NH ₃ , and TMG is constant while the substrate temperature is raised, and the supply amount of TMI is decreased, After the TMI supply amount became zero, the TMA supply amount was increased to form a region 42 having a film thickness of about 1.5 nm. This temperature rise is set so that TMA is supplied to form the next Al _0.1 Ga _0.9 N when the temperature of the substrate 1 reaches 900 ° C. Subsequently, N ₂ , NH ₃ , TMA, and TMG were supplied to form a layer made of Al _0.1 Ga _0.9 N having a thickness of about 5 nm. Therefore, in the last barrier layer, a total of 5.5 nm barrier layer 41 including a region 42 having a thickness of about 1.5 nm and a layer made of Al _0.1 Ga _0.9 N having a thickness of about 5 nm is obtained. (Figure 3)
Next, the temperature of the substrate 1 was maintained at 1000 ° C., and H ₂ , N ₂ , NH ₃ , TMA, TMG, and CP ₂ Mg were supplied to be doped with 5 × 10 ¹⁹ / cm ³ magnesium (Mg). A clad layer 5 made of p-type Al _0.4 Ga _0.6 N having a thickness of about 20 nm was formed. Next, H ₂ , N ₂ , NH ₃ , TMG, and CP ₂ Mg are supplied, and a contact layer made of p-type GaN having a thickness of about 100 nm doped with 5 × 10 ¹⁹ / cm ³ magnesium (Mg). 6 was formed.
(Formation of electrodes)
Next, an etching mask is formed on the contact layer 6, the etching mask in a predetermined region is removed, and the contact layer 6, the cladding layer 5, the multiple quantum well layer 4, and the high carriers that are not covered with the etching mask. A part of the concentration layer 3 was etched by reactive ion etching using a gas containing chlorine to expose the surface of the high carrier concentration layer 3. Next, with the etching mask left, a photoresist is applied to the entire surface, a window is formed in a predetermined region on the exposed surface of the high carrier concentration layer 3 by photolithography, and vanadium (V) having a film thickness of about 20 nm is formed. An Al electrode 8 having a thickness of about 1.8 μm is formed.
(Formation of translucent electrode)
Next, a photoresist is applied on the surface, and the photoresist is removed from the electrode forming portion on the contact layer 6 by photolithography to form a window to expose the contact layer 6. An ITO film having a thickness of about 150 nm is formed on the exposed contact layer 6. Next, a sample is taken out from the apparatus, ITO deposited on the photoresist is removed by a lift-off method, and a translucent electrode 7 for the contact layer 6 is formed.
(Formation of bonding electrodes)
Next, a photoresist is applied on the surface, and the photoresist is removed from the electrode forming portion on the translucent electrode 7 by photolithography to form a window, and the translucent electrode 8 is exposed. An Au film having a thickness of about 2.0 μm is formed on the exposed translucent electrode 8. Next, a sample is taken out from the apparatus, Au deposited on the photoresist is removed by a lift-off method, and an electrode 9 for bonding is formed.
Thereafter, the sample atmosphere is evacuated with a vacuum pump, O ₂ gas is supplied to a pressure of 3 Pa, and in this state, the atmosphere temperature is set to about 500 ° C. and heated for about 3 minutes, whereby the contact layer 6 and the cladding layer 5 are formed. The p-type resistance was lowered, and the alloying process between the contact layer 6 and the electrode 7 and the alloying process between the high carrier concentration layer 3 and the electrode 8 were performed.
(Embodiment 2)
In the best mode, the composition of the region 42 is changed in the order of AlGaN.fwdarw.GaN.fwdarw.InGaN before the formation of the well layer. However, there is an effect in the case of AlGaN.fwdarw.GaN. In this case, the procedure is as follows. That is, after the high carrier concentration layer 3 is formed, the temperature of the substrate 1 is set to 900 ° C., and N ₂ , NH ₃ , TMA, and TMG are supplied, and Al _0.1 Ga _0.9 N having a thickness of about 5 nm is supplied. Next, the supply amount of TMA was reduced while lowering the temperature of the substrate 1 to form a region 42 having a film thickness of about 1.5 nm. In this temperature decrease, the supply amount of TMA is set so that the supply amount of TMA becomes 0 (zero) when the temperature of the substrate 1 reaches 600 ° C. In the present embodiment, a layer made of Al _0.1 Ga _0.9 N having a thickness of about 5 nm and a region 42 having a thickness of about 1.5 nm are used as the first barrier layer 41. Next, N ₂ , NH ₃ , TMG, and TMI were supplied to form an In _0.1 Ga _0.9 N well layer 52 having a thickness of about 3 nm. Next, the supply amount of N ₂ , NH ₃ , and TMG was constant while the substrate temperature was raised, and the supply amount of TMA was increased to form a region 42 having a film thickness of about 1.5 nm. This temperature rise is set so that TMA is supplied to form the next Al _0.1 Ga _0.9 N when the temperature of the substrate 1 reaches 900 ° C. Subsequently, N ₂ , NH ₃ , TMA, and TMG are supplied to form a layer made of Al _0.1 Ga _0.9 N having a film thickness of about 5 nm. Next, the temperature of the substrate 1 is decreased while the temperature of the TMA is decreased. The supply amount was reduced to form a region 42 having a film thickness of about 1.5 nm. In this temperature decrease, the supply amount of TMA is set so that the supply amount of TMA becomes 0 (zero) when the temperature of the substrate 1 reaches 600 ° C. Therefore, in the second barrier layer, the barrier layer 41 is a total of 8 nm including a layer made of Al _0.1 Ga _0.9 N having a thickness of about 5 nm and a region 42 having a thickness of two layers of about 1.5 nm. Similarly, after the formation of the barrier layer and the well layer is repeated and the final well layer is formed, the supply amount of N ₂ , NH ₃ , and TMG is constant while the substrate temperature is raised, and the supply amount of TMA is increased, A region 42 having a thickness of about 1.5 nm was formed. This temperature rise is set so that TMA is supplied to form the next Al _0.1 Ga _0.9 N when the temperature of the substrate 1 reaches 900 ° C. Subsequently, N ₂ , NH ₃ , TMA, and TMG were supplied to form a layer made of Al _0.1 Ga _0.9 N having a thickness of about 5 nm. Therefore, in the last barrier layer, a total of 5.5 nm barrier layer 41 including a region 42 having a thickness of about 1.5 nm and a layer made of Al _0.1 Ga _0.9 N having a thickness of about 5 nm is obtained.

(result)
As a result of the above-described embodiment, when the composition of the region 42 is changed in the order of AlGaN → GaN → InGaN, the luminous intensity is about 15%, and when the composition is changed in the order of AlGaN → GaN, the luminous intensity is 10%. The degree of improvement was seen. In both cases, there was no change in the emission spectrum compared to the case without the region 42. In addition, although the said Example was related with the multiple quantum well structure, it is the same also in a single quantum well structure. In this case, instead of the barrier layer, the lattice constant of the layers formed above and below the well layer is changed in the cladding layer or in the vicinity of the junction with the well layer separately from the cladding layer so as to approach the lattice constant of the well layer. A region formed as described above may be provided. Also, a region formed near the junction with the well layer so that the lattice constant of the layers formed above and below the well layer changes so as to approach the lattice constant of the well layer is provided separately from the barrier layer. However, it is clear that the same effect can be achieved. Furthermore, although the said Example is a case where it has a barrier layer on the upper and lower sides of a well layer, MQW structure which starts from a well layer, or MQW structure where a barrier layer exists only on one side (well layer / barrier layer /... / Well layer / barrier layer / cladding layer, etc.) have the same effect.

It is the figure which showed the relationship between the material composition and lattice constant in a group III nitride compound semiconductor. It is the schematic diagram which showed the structure of the group 3 nitride type compound semiconductor light-emitting device in the best form for implementing invention. It is the figure which showed the relationship between the material which comprises the barrier layer 41 (including area | region 42) and the well layer 43, and a lattice constant in the best form for implementing invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Sapphire substrate 2 AlN buffer layer 3 High carrier concentration layer 5 Cladding layer 6 Contact layer 7 Translucent electrode 8 n electrode 9 Bonding electrode 10 Light emitting element 41 Barrier layer 42 The lattice constant changes so as to approach the lattice constant of the well layer Region 43 formed as a well layer

Claims (6)

A group III nitride compound semiconductor light emitting device having a quantum well structure, wherein a lattice constant of a layer formed above and below the well layer is in the vicinity of a junction between the layer formed above and below the well layer and the well layer. A group III nitride compound semiconductor light emitting device comprising a region formed so as to be changed so as to approach the lattice constant of the well layer. 2. The group III nitride compound semiconductor light-emitting element according to claim 1, wherein the region is formed in layers formed above and below the well layer. 3. The group III nitride compound semiconductor light-emitting element according to claim 1, wherein the layers formed above and below the well layer are clad layers. 4. 3. The group III nitride compound semiconductor light emitting device according to claim 1, wherein the layers formed above and below the well layer are barrier layers (barrier layers). 4. The layers formed above and below the well layer are Al _x Ga _1-x N (0 <x <1), the well layer is In _y Ga _1-y N (0 ≦ y <1), and the region is Al _{x ′} Ga _{1-x ′} N (0 ≦ x ′ <1), wherein x ′ in the region is formed to change from x ′ = x to x ′ = 0. The group III nitride compound semiconductor light-emitting device according to claim 1. The layers formed above and below the well layer are Al _x Ga _1-x N (0 <x <1), the well layer is In _y Ga _1-y N (0 <y <1), and the region Is formed of In _{y ′} Ga _{1-y ′} N (0 ≦ y ′ <1) and Al _{x ′} Ga _{1-x ′} N (0 ≦ x ′ <1) from the well layer side, and further y ′ and x 5. The third group according to claim 1, wherein 'is formed so as to change from y to y through y' = x '= 0 from the well layer side. Nitride compound semiconductor light emitting device.

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