JP2006203252A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can prevent deterioration of a ferroelectric film in a capacitor when forming an insulation film covering the capacitor. <P>SOLUTION: The semiconductor device comprises a first insulation film 9 formed above a silicon substrate (semiconductor substrate) 1; a capacitor Q in which a lower electrode 11a, a dielectric film 12a, and an upper electrode 13a are formed in turn on the first insulation film 9; a first capacitor protection insulation film 14 covering the dielectric film 12a and the upper electrode 13a; a second capacitor protection insulation film 16 formed on the first capacitor protection insulation film 14; and a second insulation film 17 formed on the second capacitor protection insulation film 16. A carbon content of the second capacitor protection insulation film 16 is more than a carbon content of the second insulation film 17. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a nonvolatile memory (FeRAM: Ferroelectric Random Access Memory) using a ferroelectric material for a dielectric film of a capacitor.

  In FeRAM, the cell area is expected to be further reduced in the future due to the demand for higher integration. When such reduction is performed, the interval between adjacent capacitors is also reduced, and the wiring interval is also reduced accordingly. In general, an insulating film is embedded between capacitors and wirings. However, as the degree of integration increases as described above, as the insulating film, a film with good embedding property in which a cavity (also referred to as a void) is not formed between capacitors must be used.

  As such an insulating film having good embedding properties, a film formed by a high density plasma chemical vapor deposition (HDPCVD) method is conventionally known.

  An insulating film formed by the HDPCVD method can be seen, for example, in FIG. 1 of JP-A-2001-210798. In that publication, it is disclosed in paragraph number 0042 that HDP oxide can be used as the insulating film 134 covering the capacitor of FIG.

  Similarly, Japanese Patent Laid-Open No. 2001-230382 discloses that HDP oxide can be used as the insulating film 408 covering the capacitor of FIG.

By the way, SiH ₄ is usually used as a film forming gas in the HDPCVD method, and during the film formation, the SiH ₄ is decomposed to generate hydrogen, and the ferroelectric film of the capacitor is exposed to the hydrogen.

  However, if the ferroelectric film is exposed to a reducing substance such as hydrogen, its ferroelectric characteristics are deteriorated. Therefore, some measures are required to prevent it.

In a normal plasma CVD method other than the HDPCVD method, a structure in which a capacitor is covered with an insulating film made of a metal oxide, for example, an alumina (Al ₂ O ₃ ) film is known as a method for isolating a ferroelectric film from hydrogen. ing. Such a structure is disclosed in Japanese Patent Application No. 11-215600, Japanese Patent Application Laid-Open No. 2001-44375, Japanese Patent Application Laid-Open No. Hei 6-290984, and Japanese Patent No. 3056773.

  However, in the HDPCVD method, this alumina film is not sufficient to block hydrogen, and it has been made clear by the present inventor that the ferroelectric film can be deteriorated by hydrogen.

  An object of the present invention is to provide a semiconductor device capable of preventing deterioration of a ferroelectric film in a capacitor when an insulating film covering the capacitor is formed.

  The above-described problems include a first insulating film formed above a semiconductor substrate, a capacitor formed by sequentially forming a lower electrode, a dielectric film, and an upper electrode on the first insulating film, the dielectric film, A first capacitor protective insulating film covering the upper electrode; a second capacitor protective insulating film formed on the first capacitor protective insulating film; and a second insulating film formed on the second capacitor protective insulating film. The semiconductor device is characterized in that the carbon content of the second capacitor protective insulating film is higher than the carbon content of the second insulating film.

  Next, the operation of the present invention will be described.

  According to the present invention, the first capacitor protection insulating film covering the capacitor dielectric film and the upper electrode is formed. Then, a second capacitor protective insulating film is formed on the first capacitor protective insulating film without applying a bias voltage to the semiconductor substrate, and then a second insulating film is formed with a bias voltage applied.

  By forming the second insulating film in a state where a bias voltage is applied, for example, an electric field is concentrated on the shoulder portion of the capacitor, and sputtered ions are attracted to the shoulder portion by the electric field. As a result, film deposition and sputtering are simultaneously performed on the shoulder portion, thereby preventing the film from being thickly formed on the shoulder portion. As a result, the film thickness on the side surfaces of the capacitors is made uniform, and a second insulating film with good embedding property is formed between the capacitors having a high aspect ratio. Since the embedding property is good, even if the integration is advanced and the interval between the capacitors is narrowed, a cavity is not formed in the second insulating film therebetween.

  Moreover, even if the second insulating film is formed in a state where a bias voltage is applied, the collision energy is absorbed by the second capacitor protective insulating film, and the movement speed of the sputtered ions and other ions is reduced. . As a result, ions can be blocked by the lower first capacitor protection insulating film, and the capacitor dielectric film is prevented from being deteriorated by the ions.

  Furthermore, since the second capacitor protective insulating film is formed without applying a bias voltage to the semiconductor substrate, it is possible to prevent the capacitor dielectric film from being deteriorated during the film formation.

  Similarly, by forming the first capacitor protective insulating film without applying a bias voltage to the semiconductor substrate, it is possible to prevent the capacitor dielectric film from being deteriorated during the film formation.

Further, by forming the second capacitor protective insulating film by chemical vapor deposition using a reactive gas containing TEOS, the coverage of the second capacitor protective insulating film is improved. It is absorbed evenly at the top and side of the. Moreover, since TEOS is less likely to generate reducing hydrogen than SiH ₄ , there is no possibility of degrading the capacitor due to hydrogen.

In this case, when the second insulating film is formed by chemical vapor deposition using a reaction gas containing any of SiH ₄ , Si ₂ H ₆ , Si ₃ H ₈ and SiCl ₄ , the second capacitor protective insulating film is formed. The carbon content of is greater than that of the second insulating film.

  The first capacitor protective insulating film includes two layers: a lower protective insulating film that covers the capacitor dielectric film and the upper electrode, and an upper protective insulating film formed on the lower protective insulating film and the first insulating film. A layer structure is preferable. According to this, since the capacitor and the first insulating film are continuously covered with the upper protective insulating film, a reducing substance such as hydrogen is prevented from entering the capacitor dielectric film through the first insulating film. Can be removed.

  Furthermore, when a plurality of capacitors are formed, the total film thickness of the first capacitor protective insulating film and the second capacitor protective insulating film is set to be equal to or less than half of the minimum interval between the plurality of upper electrodes. A cavity is not formed, and the space between the capacitors is filled with a second insulating film as desired.

  Further, the thickness of the second insulating film is set to be thicker than the total thickness of the lower electrode, the capacitor dielectric film, and the capacitor upper electrode, and smaller than the total thickness obtained by adding 1 μm. Is preferred. According to this, the gap between the capacitors is filled with the second insulating film while suppressing the deterioration of the capacitor dielectric film due to the ions generated when the second insulating film is formed.

  When the surface of the second insulating film is polished and flattened, a third insulating film is formed on the surface before polishing, and the second and third insulating films are polished so that the polishing film thickness is increased. The film thickness distribution after polishing becomes uniform.

  According to the present invention, the first capacitor protection insulating film is formed to cover the capacitor dielectric film and the upper electrode. Then, a second capacitor protective insulating film is formed on the first capacitor protective insulating film without applying a bias voltage to the semiconductor substrate, and then a second insulating film is formed with a bias voltage applied.

  According to this, the second insulating film with good embedding can be formed, and damage to the capacitor dielectric film due to the ions generated when the second insulating film is formed is caused by the second capacitor protective insulating film. Can be reduced.

  In addition, by forming the first capacitor protection insulating film without applying a bias voltage to the semiconductor substrate, it is possible to prevent the capacitor dielectric film from being deteriorated during the film formation.

Furthermore, by forming the second capacitor protective insulating film by a chemical vapor deposition method using a reaction gas containing TEOS, the coverage of the second capacitor protective insulating film can be improved, and the ions that collide are The upper part and the side part can absorb evenly. Moreover, since TEOS is less likely to generate reducing hydrogen than SiH ₄ , there is no possibility of degrading the capacitor due to hydrogen.

  In addition, when the first capacitor protective insulating film has a two-layer structure of the lower protective insulating film and the upper protective insulating film, it is difficult for a reducing substance such as hydrogen to enter the capacitor dielectric film.

  Furthermore, when a plurality of capacitors are formed, the total film thickness of the first capacitor protective insulating film and the second capacitor protective insulating film is set to be equal to or less than half of the minimum interval between the plurality of upper electrodes. The space between the capacitors can be filled with the second insulating film as desired without forming a cavity.

  Further, the film thickness of the second insulating film is set to be thicker than the total film thickness of the lower electrode, the capacitor dielectric film, and the capacitor upper electrode, and to a film thickness obtained by adding 1 μm to the total film thickness. Thus, the gap between the capacitors can be filled with the second insulating film while minimizing damage to the capacitor dielectric film.

  Further, when the surface of the second insulating film is polished and flattened, a third insulating film is formed on the surface before polishing, and the second and third insulating films are polished to increase the polishing film thickness. The film thickness distribution after polishing can be made uniform.

  Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

(First embodiment)
1 to 10 are sectional views showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention in the order of steps.

  First, steps required until a sectional structure shown in FIG.

  As shown in FIG. 1, an element isolation insulating film 2 is formed on the surface of an n-type or p-type silicon (semiconductor) substrate 1 by a LOCOS (Local Oxidation of Silicon) method. As the element isolation insulating film 2, an STI (Shallow Trench Isolation) method may be adopted in addition to the LOCOS method.

  After such an element isolation insulating film 2 is formed, a p-type impurity and an n-type impurity are selectively introduced into a predetermined active region (transistor formation region) of the silicon substrate 1 to form a p-well 3a and an n-well 3b. Form.

  Thereafter, the active region surface of the silicon substrate 1 is thermally oxidized to form a silicon oxide film as the gate insulating film 5.

  Next, an amorphous or polycrystalline silicon film is formed on the entire upper surface of the silicon substrate 1, and an n-type impurity is ion-implanted into the silicon film on the p-well 3a and a p-type impurity is ion-implanted into the silicon film on the n-well 3b. Reduce the resistance of the film. Thereafter, the silicon film is patterned into a predetermined shape by photolithography to form gate electrodes 6a and 6b. The gate electrodes 6a and 6b are arranged substantially parallel to each other and constitute a part of the word line WL.

  Next, an n-type impurity is ion-implanted into the p-well 3a on both sides of the gate electrodes 6a and 6b to form an n-type impurity diffusion region 4a that becomes the source / drain of the n-channel MOS transistor. Subsequently, a p-type impurity is ion-implanted into the n-well 3b to form a p-type impurity diffusion region 4b serving as a source / drain of a p-channel MOS transistor (not shown).

Subsequently, after an insulating film is formed on the entire surface of the silicon substrate 1, the insulating film is etched back to leave the side wall insulating film 10 only on both sides of the gate electrodes 6a and 6b. As the insulating film, silicon oxide (SiO ₂ ) is formed by, eg, CVD (chemical vapor deposition).

  Further, by using the gate electrodes 6a and 6b and the sidewall insulating film 10 as a mask, n-type impurity ions are implanted again into the p-well 3a, thereby forming the n-type impurity diffusion region 4a in an LDD (Lightly Doped Drain) structure. Further, by implanting p-type impurity ions again into the n-well 3b, the p-type impurity diffusion region 4b also has an LDD structure.

  Note that n-type impurities and p-type impurities are separated using a resist pattern (not shown).

  As described above, an n-type MOSFET is formed by the p-well 3a, the gate electrodes 6a and 6b, the n-type impurity regions 4a on both sides thereof, and the like. The n-type well 3b, the p-type impurity diffusion region 4b, the gate electrode (not shown), and the like constitute a p-type MOSFET (not shown).

  Next, after forming a refractory metal film such as Ti (titanium) or Co (cobalt) film on the entire surface, the refractory metal film is heated to form an n-type impurity diffusion region 4a and a p-type impurity diffusion region 4b. Refractory metal silicide layers 8a and 8b are formed on the surfaces of the layers. Thereafter, the unreacted refractory metal film is removed by wet etching.

Next, a silicon oxynitride (SiON) film having a thickness of about 200 nm is formed as a cover insulating film 7 on the entire surface of the silicon substrate 1 by plasma CVD. Further, silicon oxide (SiO ₂ ) is grown on the cover insulating film 7 to a thickness of about 1.0 μm as the first interlayer insulating film (first insulating film) 9 by plasma CVD using TEOS (tetraethoxy silane) gas. To do.

  Subsequently, the first interlayer insulating film 9 is polished by a chemical mechanical polishing (CMP) method to flatten the surface.

  Next, steps required until a structure shown in FIG.

  First, a titanium (Ti) film and a platinum (Pt) film are sequentially formed on the first interlayer insulating film 9 by DC sputtering, and these films are used as the first conductive film 11. In this case, the thickness of the Ti film is about 10 to 30 nm, for example, 20 nm, and the thickness of the Pt film is about 100 to 300 nm, for example, 175 nm. The Ti film serves to improve the adhesion between the Pt film and the first interlayer insulating film 9 and to improve the crystallinity of the Pt film.

Note that a film of iridium, ruthenium, ruthenium oxide, ruthenium oxide strontium (SrRuO ₃ ), or the like may be formed as the first conductive film 11.

Then, by _{sputtering, PZT (Pb (Zr 1-} x Ti x) O 3) film thickness of 100~300nm on the first conductive film 11, for example, is formed in 240 nm, which ferroelectric film 12 is used.

  Subsequently, the silicon substrate 1 is placed in an oxygen atmosphere, and a rapid thermal annealing (RTA: Rapid Thermal Annealing) is performed on the PZT film constituting the ferroelectric film 12 under conditions of, for example, 725 ° C., 20 seconds, and a temperature rising rate of 125 ° C./sec. ) To crystallize the PZT film.

As a method for forming the ferroelectric film 12, in addition to the above sputtering method, there are a spin-on method, a sol-gel method, a MOD (Metal Organi Deposition) method, and an MOCVD method. In addition to PZT, the material constituting the ferroelectric film 12 is PLZT (Lead Lanthanum Zirconate Titanate: (Pb _{1-3x / 2} La _x ) (Zr _1-y ) in which lanthanum (La) is added to PZT. Ti _y ) O ₃ ), and PZT materials such as PLCSZT in which lanthanum (La), calcium (Ca) and strontium (Sr) are added to PZT, and SrBi ₂ (Ta _x Nb) of bismuth (Bi) materials. _1-x ) ₂ O ₉ (where 0 <x ≦ 1), Bi ₄ Ti ₂ O _{12 and the} like.

After the ferroelectric film 12 as described above is formed, an iridium oxide (IrO _x ) film is formed as a second conductive film 13 thereon by a sputtering method to a thickness of 100 to 300 nm, for example, 200 nm. As the second conductive film 13, a platinum (Pt) film or a ruthenium strontium oxide (SRO) film may be formed by sputtering.

  Next, steps required until a structure shown in FIG.

  First, a capacitor upper electrode-shaped resist pattern (not shown) is formed on the second conductive film 13, and then the second conductive film 13 is patterned using the resist pattern as an etching mask. The conductive film 13 is used as the capacitor upper electrode 13a.

  Then, after removing the resist pattern, the ferroelectric film 12 is annealed in an oxygen atmosphere at a temperature of 650 ° C. for 60 minutes. This annealing is performed to recover the damage that has entered the ferroelectric film 12 during sputtering and etching.

  In addition, the top view in this case is as FIG. 11, and FIG.2 (b) above is equivalent to II sectional drawing of FIG.

  Subsequently, as shown in FIG. 3A, a resist pattern (not shown) is formed on the capacitor upper electrode 13a, and the ferroelectric film 12 is patterned using the resist pattern as an etching mask. The remaining ferroelectric film 12 is used as a capacitor dielectric film 12a. Then, after removing the resist pattern, the capacitor dielectric film 12a is annealed in an oxygen atmosphere at a temperature of 650 ° C. for 60 minutes.

  In addition, the top view in this case is as FIG. 12, and FIG. 3A above corresponds to the II cross-sectional view of FIG.

Next, as shown in FIG. 3B, alumina (Al ₂ O ₃ ) is formed at a room temperature to a thickness of 50 nm by sputtering as a lower protective insulating film 14a covering the capacitor dielectric film 12a and the capacitor upper electrode 13a. Form below. The lower protective insulating film 14a is formed to protect the capacitor dielectric film 12a that is easily reduced from a reducing substance such as hydrogen and block hydrogen from entering the inside.

  By the way, when the lower protective insulating film 14a is formed, if a bias voltage is applied to the silicon substrate 1, the target atoms are drawn into the silicon substrate 1 at a high speed by the bias, whereby the capacitor dielectric film 12a is formed. There is a risk of deterioration. Therefore, it is preferable not to apply a bias voltage to the silicon substrate 1 when forming the lower protective insulating film 14a. In the present invention, since the bias voltage is not applied, the above inconvenience does not occur.

  Note that as the lower protective insulating film 14a, a PLZT film, a PZT film, a titanium oxide film, an aluminum nitride film, a silicon nitride film, or a silicon nitride oxide film may be formed.

  Next, steps required until a structure shown in FIG.

  First, the capacitor dielectric film 12a under the lower protective insulating film 14a is subjected to rapid thermal processing (RTA) under conditions of 700 ° C. for 60 seconds and a temperature rising rate of 125 ° C./sec in an oxygen atmosphere to improve the film quality. .

  Next, a resist (not shown) is applied on the lower protective insulating film 14a, exposed and developed, and left to cover the capacitor upper electrode 13a and the capacitor dielectric film 12a. Then, using the resist as an etching mask, the lower protective insulating film 14a and the first conductive film 11 are patterned. As a result, the lower protective insulating film 14a remains on the capacitor upper electrode 13a and the capacitor dielectric film 12a. Then, the first conductive film 11 remaining by this patterning is used as the capacitor lower electrode 11a. The lower protective insulating film 14a and the first conductive film 11 are etched by dry etching using chlorine as an etching gas.

  As a result, the capacitor Q formed by sequentially laminating the lower electrode 11a, the capacitor dielectric film 12a, and the upper electrode 13a is formed on the first interlayer insulating film 9.

  Note that the plan view in this case is as shown in FIG. 13, and FIG. 4A corresponds to the II cross-sectional view of FIG. However, in FIG. 13, the lower protective insulating film 14a is omitted.

Next, as shown in FIG. 4 (b), alumina (Al ₂ O ₃ ) is deposited to a thickness of 20 nm on the first interlayer insulating film 9 and the lower protective insulating film 14a by sputtering as the upper protective insulating film 14b. It is formed at room temperature.

  The upper protective insulating film 14b constitutes the first capacitor protective insulating film 14 together with the lower protective insulating film 14a. By forming the first capacitor protection insulating film 14 with such a two-layer structure, the film thickness can be increased, and hydrogen is less likely to enter the dielectric film 12a. Further, the upper protective insulating film 14b continuously covers the capacitor Q and the first interlayer insulating film 9, so that a reducing substance such as hydrogen enters the capacitor Q from the outside via the first interlayer insulating film 9. Is prevented.

  Similarly to the case of the upper protective insulating film 14a, the bias voltage is not applied to the silicon substrate 1 when the lower protective insulating film 14b is formed, thereby preventing the capacitor dielectric film 12a from being deteriorated by the target atoms. it can.

  Next, steps required until a structure shown in FIG.

  First, the silicon substrate 1 is placed in the chamber 50 of the plasma CVD apparatus shown in FIG. The substrate mounting table 51 on which the silicon substrate 1 is mounted is grounded, while the gas dispersion plate 53 is connected to a high frequency power source 54 and applied with high frequency power.

Next, film formation is performed under the following conditions.
・ TEOS gas flow rate: 460sccm
・ He (TEOS carrier gas) flow rate ・ ・ ・ 480sccm
・ O ₂ flow rate: 700sccm
・ Pressure: 9.0 Torr
・ Frequency of the high frequency power supply 54. 13.56 MHz
・ Power of high frequency power supply 54 ... 400W
・ Deposition temperature: 390 ℃
As a result, as shown in FIG. 5A, silicon oxide (SiO ₂ ) having a thickness of 100 nm is formed on the first capacitor protection insulating film 14 as the second capacitor protection insulating film 16.

  When the second capacitor protection insulating film 16 is formed, no bias voltage is applied to the silicon substrate 1 because the substrate mounting table 51 (see FIG. 17) is grounded. Accordingly, since the plasmad reaction gas is not drawn into the silicon substrate 1 by the bias voltage, there is no possibility that the capacitor dielectric film 12a is deteriorated by the reaction gas.

Thereafter, the second capacitor protection insulating film 16 is heated at a temperature of 350 ° C. in a vacuum chamber (not shown), thereby releasing the surface and internal water to the outside. After such dehydration treatment, the second capacitor protection insulating film 16 is exposed to N ₂ O plasma to improve the film quality along with dehydration. Thereby, the deterioration of the capacitor due to heating and water in a later process is prevented.

Such dehydration treatment and plasma treatment may be performed in the same chamber (not shown). In the chamber, a support electrode on which the silicon substrate 1 is placed and a counter electrode facing the support electrode are arranged, and a high frequency power source can be connected to the counter electrode. Then, with the N ₂ O gas introduced into the chamber, first, the insulating film is dehydrated without applying a high-frequency power to the counter electrode, and then the electrode is applied with the high-frequency power applied to the counter electrode. N ₂ O plasma is generated between them to perform N ₂ O plasma treatment of the insulating film. In this case, the frequency of the high frequency power source is 13.56 MHz, and the power is 300 W. The flow rate of N ₂ O is 700 sccm.

Note that N ₂ O plasma is preferably used in the plasma treatment subsequent to the dehydration treatment, but NO plasma, N ₂ plasma, or the like may be used, and this is the same in the steps described later.

  Incidentally, the film thickness of the second capacitor protection insulating film 16 is not arbitrary and is preferably set as shown in FIG.

  19A and 19B, when a plurality of capacitors Q are formed, the minimum interval among the intervals between the upper electrodes 13a is B, and the first capacitor protection insulating film 14 and the second capacitor protection insulation are used. The total film thickness with the film 16 is A.

  At this time, if A and B do not satisfy the relationship A <(B / 2) (FIG. 19B), a cavity is formed between the capacitors Q, and the cavity is filled with an insulating film in a later step. It is not preferable because it cannot be done.

  On the other hand, in the present invention, as shown in FIG. 19 (a), the above relation A <(B / 2) is satisfied, so that no cavity is formed between the capacitors Q. An insulating film can be embedded as desired. This advantage can also be obtained in a second embodiment described later.

  Next, steps required until a structure shown in FIG.

First, the silicon substrate 1 is placed in the chamber 60 of the HDPCVD (High Density Plasma CVD) apparatus shown in FIG. In general, the HDPCVD method refers to a CVD method performed in a plasma atmosphere having a plasma density of about 1 × 10 ¹¹ to 1 × 10 ¹³ cm ⁻³ . This plasma density is higher than the plasma density (about 1 × 10 ⁹ to 1 × 10 ¹⁰ cm ⁻³ ) in a normal plasma CVD method in which the second capacitor protective insulating film 16 is formed. Further, in the HDPCVD method, film formation is performed under a low pressure of about 1 mTorr to 7 mTorr in order to lengthen the mean free path of ions. This pressure is lower than the pressure of the normal plasma CVD method (about 2 to 10 Torr).

  In the HDPCVD method, a first high frequency power source 64 is connected to a coil 63 provided above the chamber 60, and a second high frequency power source 62 is connected to the substrate mounting table 61. The coil 63 is wound in a plane parallel to the main surface of the silicon substrate 1, and a cross section thereof is shown in the drawing.

  By applying a high frequency power source to the substrate mounting table 61 as described above, a bias voltage is applied to the silicon substrate 1, so that the plasmad reaction gas is drawn into the silicon substrate 1. Among such reactive gases, in addition to those that contribute to film deposition, there are those that sputter the deposited film. By this sputtering action, film deposition and sputtering are simultaneously performed on the shoulder portion of the capacitor, thereby preventing the film from being formed thick on the shoulder portion. As a result, the film thickness on the side surface of the capacitor is made uniform, and a second insulating film with good embedding can be formed between the capacitors with a high aspect ratio.

Using such an HDPCVD method, film formation is performed under the following conditions.
・ SiH ₄ flow rate: 69sccm
・ O ₂ flow rate: 300sccm
・ Ar flow rate: 300sccm
・ Pressure: 6.2 mTorr
・ Frequency of the first high-frequency power supply 64 ... 13.56 MHz
・ Power of first high frequency power supply 64... 3000 W
・ Frequency of the second high-frequency power source 62 ... 2 MHz
-Power of the second high frequency power supply 62 ... 1200W
・ Film formation temperature: 250 ℃
As a result, as shown in FIG. 5B, silicon oxide (SiO ₂ ) having a thickness of about 800 nm is formed as the second interlayer insulating film 17 on the second capacitor protection insulating film 16 with good embeddability. Since the embedding property is good, even if the integration is advanced and the interval between the capacitors Q is narrowed, a cavity is not formed in the second interlayer insulating film 17 therebetween.

Instead of SiH ₄ described above, a silane-based gas such as Si ₂ H ₆ or Si ₃ H ₈ or a chlorine-containing gas such as SiCl ₄ may be used.

Further, if necessary, the second interlayer insulating film 17 may contain F fluorine, P (phosphorus), B (boron), or the like. In that case, in addition to the above silane-based gas, C ₂ F ₆ , B ₂ H ₆ , B (OCH ₃ ) ₃ , B (OC ₂ H ₅ ) ₃ , or PH ₃ may be added to the reaction gas. Good.

  The same applies to the second embodiment described later.

As described above, since a bias voltage is applied to the substrate in the HDPCVD method, it is considered that hydrogen ions H ⁺ dissociated from SiH ₄ are drawn into the silicon substrate 1. Therefore, it is considered that the capacitor dielectric film 12a is likely to be deteriorated by hydrogen ions H ^{+ as} compared with the plasma CVD method in which no bias voltage is applied to the substrate.

  And it is thought that the imprint characteristic of a capacitor deteriorates by the deterioration of the capacitor dielectric film 12a. Deterioration of imprint characteristics means that after writing a signal (for example, “1”) in a capacitor and leaving it for a certain period of time, the reverse signal (for example, “0”) is written to the capacitor. The problem is that the reverse signal cannot be read out. That is, the reverse signal is imprinted on the capacitor, making it difficult to write the reverse signal.

  In order to confirm the influence of such a bias voltage, the inventor of the present application conducted the following experiment. In this experiment, the deterioration of each imprint characteristic was compared between when the second interlayer insulating film 17 was formed by HDPCVD and when it was formed by plasma CVD without applying a bias voltage. In the plasma CVD method, a reactive gas containing TEOS was used. The second capacitor protection insulating film 16 was not formed, and the second interlayer insulating film 17 was formed directly on the first capacitor protection insulating film 14.

The result is shown in FIG. In FIG. 20, Q3 ₍₈₈₎ (μC / cm ² ) on the left vertical axis indicates that a reverse signal is written in two pairs of capacitors of a two-transistor / 2-capacitor type and then baked at 150 ° C. for 88 hours. It represents the difference in polarization charge amount. The Q3 rate on the right side represents the deterioration rate of the capacitor after e time (e = natural logarithm). That is, the larger the value of Q3 _{(88) and} the smaller the absolute value of the Q3 rate, the better the imprint characteristics.

  As shown in FIG. 20, the imprint characteristic is the best when no bias voltage is applied (plasma TEOS). When HDPCVD is used, the imprint characteristics are deteriorated. In particular, as the bias voltage (the high frequency voltage applied to the substrate mounting table 61 (see FIG. 18)) is increased, the imprint characteristics are deteriorated.

  As a result, it is clear that when the bias voltage is applied and the second interlayer insulating film 17 is formed, the capacitor Q is deteriorated as compared with the case where the bias voltage is not applied. Moreover, as shown in the figure, it has been clarified that the deterioration of the capacitor Q is more serious as the bias voltage is larger.

By the way, it is considered that the first capacitor protection insulating film 14 made of alumina alone (see FIG. 5B) cannot sufficiently block the hydrogen ions H ⁺ and deteriorate the capacitor dielectric film 12a.

On the other hand, in the present invention, since the second capacitor protective insulating film 16 is further formed on the first capacitor protective insulating film 14, the collision energy of hydrogen ions H ⁺ is absorbed by the second capacitor protective insulating film 16. , Its movement speed becomes slow. As a result, hydrogen ions H ⁺ can be blocked by the lower first capacitor protection insulating film 14, and the capacitor dielectric film 12 a can be prevented from being deteriorated by the hydrogen ions H ⁺ .

In addition, since the second capacitor protective insulating film 16 formed using TEOS has good coverage, the colliding hydrogen ions H ⁺ can be evenly absorbed by the upper and side portions of the capacitor Q.

Furthermore, since TEOS is less likely to generate reducing hydrogen than SiH ₄ , there is no risk of degrading capacitor Q due to hydrogen.

  If necessary, the second interlayer insulating film 17 may be subjected to plasma treatment. The conditions are the same as those of the second capacitor protection insulating film 16 and are omitted.

Incidentally, since the second interlayer insulating film 17 is formed for the purpose of embedding the space between the capacitors Q, it is not necessary to form it unnecessarily thick. If it is formed too thick, the film formation time becomes long. Therefore, even if the second capacitor protection insulating film 16 is formed, the capacitor dielectric film 12a becomes hydrogen ions H ⁺ or sputtered ions. There is a risk of being exposed to damage for a long time. Therefore, the film thickness of the second interlayer insulating film 17 is thicker than the height of the capacitor Q, which is about 600 nm (≈total film thickness of the lower electrode 11a, the capacitor dielectric film 12a, and the upper electrode 13a). Is preferably set to be thinner than the film thickness (= 1600 nm) obtained by adding 1 μm to the film thickness. With such a film thickness, the gap between the capacitors Q can be filled with the second interlayer insulating film 17 while minimizing damage to the capacitor dielectric film 12a.

Next, as shown in FIG. 6A, silicon oxide (SiO ₂ ) having a thickness of about 700 nm is formed on the second interlayer insulating film 17 as the third insulating film 18. This third insulating film 18 is formed by the plasma CVD apparatus shown in FIG. 17, and the film forming conditions are as follows.
・ TEOS gas flow rate: 460sccm
・ He (TEOS carrier gas) flow rate 480sccm
・ O ₂ flow rate: 700sccm
・ Pressure: 9.0 Torr
・ Frequency of the high frequency power supply 54. 13.56 MHz
・ Power of high frequency power supply 54 ... 400W
・ Deposition temperature: 390 ℃
Next, as shown in FIG. 6B, the second interlayer insulating film 17 and the third insulating film 18 are polished by the CMP method, and the surfaces thereof are planarized. The planarization is performed until the thickness of the second interlayer insulating film 17 on the upper electrode 13a reaches 200 nm.

  At this time, since the third insulating film 18 is formed, the polishing film thickness can be increased, and thereby the film thickness distribution after polishing can be made uniform.

Moisture in the slurry used for planarization by this CMP method and moisture in the cleaning liquid used for subsequent cleaning adhere to the surface of the second interlayer insulating film 17 and are absorbed therein. Therefore, the second interlayer insulating film 17 is exposed to N ₂ O plasma to improve film quality along with dehydration. Thereby, the deterioration of the capacitor due to heating and water in a later process is prevented.

  Next, as shown in FIG. 7A, a resist 19 is applied on the second interlayer insulating film 17, exposed and developed, and a hole forming window is formed on each of the impurity diffusion regions 4a and 4b. 19a to 19d are formed.

Subsequently, the second interlayer insulating film 17, the second capacitor protective insulating film 16, the upper protective insulating film 14b, the first interlayer insulating film 9, and the cover insulating film 7 are dry-etched to form the upper surfaces of the impurity diffusion regions 4a and 4b. Contact holes 17a to 17d are formed in the substrate. At this time, when etching the second interlayer insulating film 17, the second capacitor protective insulating film 16, the upper protective insulating film 14b, and the first interlayer insulating film 9, for example, a mixture of Ar, C ₄ F ₈ , and O ₂ A gas is used as an etching gas. When the cover insulating film 7 made of silicon oxynitride is etched, a gas obtained by adding CF ₄ to the above mixed gas is used as an etching gas.

  The contact holes 17a to 17d have a tapered shape with a wide top and a narrow bottom, and the diameter at the center in the depth direction is about 0.5 μm.

  The plan view in this case is as shown in FIG. 14, and FIG. 7A corresponds to the II cross-sectional view of FIG.

Next, after removing the resist 19, as shown in FIG. 7B, a titanium (Ti) film is formed on the second interlayer insulating film 17 and the inner surfaces of the contact holes 17a to 17d by a sputtering method to a thickness of 20 nm. A (TiN) film is formed to a thickness of 50 nm, and these films serve as a glue film 20. Further, a tungsten film 21 is formed on the glue film 20 by a CVD method using a mixed gas of tungsten fluoride gas (WF ₆ ), argon, and hydrogen. Note that silane (SiH ₄ ) gas is also used at the initial growth stage of the tungsten film 21. The tungsten film 21 has a thickness that completely fills the contact holes 17a to 17d, for example, about 500 nm on the second interlayer insulating film 17.

  Since the contact holes 17a to 17d each have a tapered shape, it is difficult for a cavity to be formed in the tungsten film 21 embedded therein.

  Next, as shown in FIG. 8A, the tungsten film 21 and the glue film 20 on the second interlayer insulating film 17 are removed by the CMP method, and are left only in the contact holes 17a to 17d. Thereby, the tungsten film 21 and the glue film 20 in the contact holes 17a to 17d are used as the plugs 21a to 21d. Here, if etching back is used instead of the CMP method, different etching gases are required for etching the tungsten film 21 and the etching of the glue film 20, so that it takes time to manage the etching.

Thereafter, a vacuum chamber (not shown) is used to remove moisture adhering to the surface of the second interlayer insulating film 17 and penetrating into the second interlayer insulating film 17 in steps such as a cleaning process after the contact holes 17a to 17d are formed and a cleaning process after the CMP. ), The second interlayer insulating film 17 is heated at a temperature of 390 ° C. to release water to the outside. After such dehydration treatment, annealing for improving the film quality by exposing the second interlayer insulating film 17 to N ₂ plasma is performed for 2 minutes, for example. Here, instead of the N ₂ O plasma, it was used the N ₂ plasma, and to prevent the etching of the tungsten film 21 in the contact hole 17a to 17d, not only to prevent the deterioration of the capacitor by dehydration This is to prevent the film constituting the capacitor Q from being peeled off due to thermal stress. The peeling of the film occurs due to a difference in thermal stress from the surrounding film.

Subsequently, as shown in FIG. 8B, a SiON film having a thickness of, for example, 100 nm is formed on the second interlayer insulating film 17 and the plugs 21a to 21d by plasma CVD. This SiON film is formed using a mixed gas of silane (SiH ₄ ) and N ₂ O, and is used as an antioxidant insulating film 22 for preventing the oxidation of the plugs 21a to 21d.

  Next, as shown in FIG. 9A, the antioxidant insulating film 22, the second interlayer insulating film 17, the second capacitor protective insulating film 16, and the first capacitor protective insulating film 14 are patterned by photolithography. Contact holes 17e to 17g reaching the upper electrode 13a of the capacitor Q are formed.

  Thereafter, the capacitor dielectric film 12a is annealed in an oxygen atmosphere at 550 ° C. for 60 minutes to improve the film quality of the dielectric film 12a. In this case, the plugs 21 a to 21 d are prevented from being oxidized by the antioxidant insulating film 22.

  The plan view in this case is as shown in FIG. 15, and FIG. 9A corresponds to the II cross-sectional view of FIG. As shown in FIG. 15, on the lower electrode 11a, lower electrode contact holes 17h to 17j are formed simultaneously with the contact holes 17e to 17g.

  Thereafter, as shown in FIG. 9B, the SiON antioxidant insulating film 22 is dry-etched using a CF-based gas.

  Next, the surfaces of the plugs 21a to 21d and the upper electrode 13a are etched by about 10 nm by RF etching to expose the clean surfaces. Thereafter, as shown in FIG. 10, a conductive film having a four-layer structure containing aluminum is formed on the second interlayer insulating film 17, the plugs 21a to 21d, and the contact holes 17e to 17g of the capacitor Q by a sputtering method. The conductive film is, in order from the bottom, a titanium nitride film with a thickness of 50 nm, a copper-containing (0.5%) aluminum film with a thickness of 500 nm, a titanium film with a thickness of 5 nm, and a titanium nitride film with a thickness of 100 nm.

  Then, the conductive film is patterned by photolithography to form conductive contact pads 23b and first-layer metal wirings 23a and 23c to 23d as shown in FIG. Among these, the first-layer metal wirings 23a and 23c to 23d are electrically connected to the upper electrode 13a through the contact holes 17e to 17g.

  The plan view in this case is as shown in FIG. 16, and the above FIG. 10 corresponds to the II cross-sectional view of FIG.

  As shown in FIG. 16, the conductive film is also formed in the lower electrode contact holes 17h to 17j, and becomes first layer metal wirings 23e to 23g electrically connected therewith.

  Thereafter, an insulating film (not shown) is formed to cover the conductive contact pad 23b, the first-layer metal wirings 23a, 23c to 20d, and the second interlayer insulating film 17. Then, the insulating film is patterned by photolithography to form a contact hole on the conductive contact pad 23b, and a plug having a two-layer structure of a TiN film and a tungsten film is formed therein. Thereafter, a second layer metal wiring electrically connected to the plug is formed on the insulating film.

  In the above embodiment, as shown in FIG. 5B, after forming the first capacitor protection insulating film 14 covering the capacitor Q, the second capacitor protection insulating film 16 is further formed thereon, A second interlayer insulating film 17 is formed thereon by HDPCVD.

In this way, hydrogen ions H ⁺ and sputtered ions generated by the HDPCVD method are absorbed by the second capacitor protective insulating film 16 and the movement speed is reduced, so that the first capacitor below The protective insulating film 14 can block the ions, and the capacitor dielectric film 12a can be prevented from being deteriorated by the ions.

  FIG. 21 is a graph showing the results of an experiment conducted to confirm the effect of the second capacitor protection insulating film 16.

  This experiment was performed on n chips in which the above-described steps were performed to integrate chips on a wafer and no defects occurred during the steps. Then, data (“0”, “1”, etc.) was written into the capacitor in the chip, and then the wafer was baked at 150 ° C. Next, data was read from the capacitor under the worst conditions for guaranteeing FeRAM operation (for example, minimum power supply voltage 4.5 V, temperature 85 ° C.), and it was checked whether it was the same as the data written first. After that, data opposite to the data just read (that is, “0” and “1” are reversed) is written, and it is checked whether or not the data can be read correctly. In this flow, if an error occurs in any of the two readings, the chip is determined to be “defective”, and the number of “defective” chips is set to m.

   The vertical axis in FIG. 21 represents the wafer retention yield defined by (m / n) × 100. Retention refers to the ability to keep data for a long time without breaking it. The horizontal axis in FIG. 21 represents the accumulated time of baking.

  In this experiment, the thickness of the second capacitor protection insulating film 16 was set to 100 nm. For comparison, a case was also examined in which the second interlayer insulating film 17 was formed directly on the first capacitor protective insulating film 14 made of alumina by the HDPCVD method without forming the second capacitor protective insulating film 16. .

  As shown in FIG. 21, in the absence of the second capacitor insulating film 16, the yield deteriorates immediately after baking.

  On the other hand, when the second capacitor insulating film 16 is formed, the yield does not deteriorate even if baking is performed for 1000 hours, and a value close to approximately 100% is maintained.

  From this result, when the second interlayer insulating film 17 is formed by the HDPCVD method, the single-layer first capacitor protective insulating film 14 alone cannot prevent the process damage to the capacitor Q, and the second capacitor is further formed thereon. It can be seen that the damage to the capacitor Q is effectively reduced by forming the insulating film 16.

(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

  22 to 27 are cross-sectional views showing manufacturing steps of the semiconductor device according to the second embodiment of the present invention.

  In the second embodiment, the first embodiment is applied to a stack type FeRAM.

  First, steps required until a sectional structure shown in FIG.

As shown in FIG. 22A, after an element isolation trench is formed around the transistor formation region of the n-type or p-type silicon (semiconductor) substrate 71 by photolithography, oxidation is performed in the element isolation trench. Silicon (SiO ₂ ) is embedded, and an element isolation insulating film 72 having an STI structure is formed. Note that an insulating film formed by the LOCOS method may be employed as the element isolation insulating film.

  Subsequently, a p-type impurity is introduced into the transistor formation region of the silicon substrate 71 to form a p-well 71a. Further, the surface of the transistor formation region of the silicon substrate 71 is thermally oxidized to form a silicon oxide film that becomes the gate insulating film 73.

  Next, an amorphous or polycrystalline silicon film and a tungsten silicide film are sequentially formed on the entire upper surface of the silicon substrate 71, and the silicon film and the tungsten silicide film are patterned by a photolithography method to form gate electrodes 74a and 74b. Form.

  Two gate electrodes 74a and 74b are formed in parallel on one p-well 71a, and these gate electrodes 4a and 4b constitute a part of the word line WL.

  Next, n-type impurities are ion-implanted on both sides of the gate electrodes 74a and 74b in the p-well 71a to form first to third n-type impurity diffusion regions 75a to 75c serving as source / drain.

Further, after an insulating film, for example, a silicon oxide (SiO ₂ ) film is formed on the entire surface of the silicon substrate 71 by the CVD method, the insulating film is etched back and left as side wall insulating films 76 on both sides of the gate electrodes 74a and 74b. .

  Subsequently, n-type impurities are ion-implanted again into the first to third n-type impurity diffusion regions 75a to 75c using the gate electrodes 74a and 74b and the side wall insulating film 76 as a mask, so that the first to first n-type impurities are ion-implanted. 3 n-type impurity diffusion regions 75a to 75c have an LDD structure.

  Note that the first n-type impurity diffusion region 75a between the two gate electrodes 74a and 74b in one transistor formation region is electrically connected to the bit line, and the second and third regions on both end sides of the transistor formation region. N-type impurity diffusion regions 75b and 75c are electrically connected to the lower electrode of the capacitor.

Through the above steps, two MOS transistors T ₁ and T ₂ having gate electrodes 74a and 74b and n-type impurity diffusion regions 75a to 75c having an LDD structure are formed in the p well 71a.

Next, a silicon oxynitride (SiON) film having a thickness of about 200 nm is formed on the entire surface of the silicon substrate 71 by plasma CVD as a cover insulating film 77 covering the MOS transistors T ₁ and T ₂ . Thereafter, silicon oxide (SiO ₂ ) having a thickness of about 1.0 μm is formed on the cover insulating film 77 as a first interlayer insulating film 78 by plasma CVD using TEOS gas.

  Subsequently, as a densification process of the first interlayer insulating film 78, the first interlayer insulating film 78 is heat-treated at a temperature of 700 ° C. for 30 minutes, for example, in a normal-pressure nitrogen atmosphere. Thereafter, the upper surface of the first interlayer insulating film 78 is planarized by a chemical mechanical polishing (CMP) method.

  Next, steps required until a structure shown in FIG.

First, the cover insulating film 77 and the first interlayer insulating film 78 are patterned by photolithography to form a first contact hole 78a having a depth reaching the first impurity diffusion region 75a. Thereafter, a titanium (Ti) film having a thickness of 30 nm and a titanium nitride (TiN) film having a thickness of 50 nm are sequentially formed as a glue film on the upper surface of the first interlayer insulating film 78 and the inner surface of the contact hole 78a by a sputtering method. Further, a tungsten (W) film is grown on the TiN film by a CVD method using WF ₆ to completely fill the first contact hole 78a.

  Subsequently, the W film, the TiN film, and the Ti film are polished by a CMP method and removed from the upper surface of the first interlayer insulating film 78. The tungsten film, TiN film, and Ti film left in the first contact hole 78 a are used as the first plug 79.

Thereafter, as shown in FIG. 22 (c), an antioxidant insulating film 80a made of silicon nitride (Si ₃ N ₄ ) having a thickness of 100 nm and a film thickness are formed on the first interlayer insulating film 78 and the first plug 79. A base insulating film 80b made of 100 nm of SiO ₂ is sequentially formed by a plasma CVD method. The SiO ₂ film is grown by plasma CVD using TEOS. The anti-oxidation insulating film 80a is formed in order to prevent the plug 79 from being abnormally oxidized during the heat treatment by annealing or the like later and causing a contact failure, and the film thickness is desirably set to 70 nm or more, for example.

  The first insulating film 94 is constituted by the first interlayer insulating film 78, the antioxidant insulating film 80a, and the base insulating film 80b.

  Next, by using the resist pattern (not shown), the first insulating film 94 is etched as shown in FIG. 23A, so that the second impurity diffusion regions 75b and 75c are exposed to the second regions. Then, third contact holes 78b and 78c are formed.

  Further, a Ti film having a thickness of 30 nm and a TiN film having a thickness of 50 nm are sequentially formed as a glue film on the upper surface of the base insulating film 80b and the inner surfaces of the second and third contact holes 78b and 78c by sputtering. Further, a W film is grown on the TiN film by the CVD method to completely fill the second and third contact holes 78b and 78c.

  Subsequently, as shown in FIG. 23B, the W film, the TiN film, and the Ti film are polished by the CMP method and removed from the upper surface of the base insulating film 80b. As a result, the tungsten film, TiN film, and Ti film remaining in the second and third contact holes 78b and 78c are defined as second and third plugs 81a and 81b, respectively.

  Next, steps required until a structure shown in FIG.

  First, an iridium (Ir) film 82 of, eg, a 200 nm-thickness is formed on the second and third plugs 81a, 81b and the base insulating film 80b by sputtering. Further, a platinum oxide (PtO) film 83 having a film thickness of 23 nm, for example, is formed on the iridium film 82 by sputtering. Subsequently, a platinum (Pt) film 84 of, eg, a 50 nm-thickness is formed on the platinum oxide film 83 by sputtering.

  The Ir film 82, the PtO film 83, and the Pt film 84 serve as a first conductive film 85 having a multilayer structure. Note that the base insulating film 80b is annealed before or after the first conductive film 85 is formed, for example, to prevent film peeling. As an annealing method, for example, RTA heated at 600 to 750 ° C. in an argon atmosphere is employed.

Next, a PZT film of, eg, a 100 nm-thickness is formed as a ferroelectric film 86 on the first conductive film 85 by sputtering. Other methods for forming the ferroelectric film 86 include the MOD method, the MOCVD (organometallic CVD) method, and the sol-gel method. As the material of the ferroelectric film 86, in addition to PZT, other PZT-based materials such as PLCSZT and PLZT, and bismuth (Bi) -based material SrBi ₂ (Ta _x Nb _1-x ) ₂ O ₉ (However, 0 <x ≦ 1), Bi ₄ Ti ₂ O ₁₂ or the like may be used.

  Subsequently, the ferroelectric film 86 is crystallized by annealing in an oxygen atmosphere. As the annealing, for example, the first step is a substrate temperature of 600 ° C. for 90 seconds in a mixed gas atmosphere of argon and oxygen, and the second step is a substrate temperature of 750 ° C. for 60 seconds in an oxygen atmosphere. RTA processing is adopted.

Further, on the ferroelectric film 86, for example, iridium oxide (IrO ₂ ) having a film thickness of 200 nm is formed as the second conductive film 87 by sputtering. The growth condition of the iridium oxide film is that the sputtering power is 1 kW, and argon and oxygen are allowed to flow in the growth atmosphere.

Thereafter, a TiN film 88a and a SiO ₂ film 88b are sequentially formed as a hard mask 88 on the second conductive film 87. The SiO ₂ film 88b is formed by plasma CVD using TEOS gas as a silicon source. The hard mask 88 is patterned by photolithography so as to have a capacitor planar shape above the second and third plugs 81a and 81b.

  Next, as shown in FIG. 24A, the second conductive film 87, the ferroelectric film 86, and the first conductive film 85 in a region not covered with the hard mask 88 are sequentially etched and patterned. In this case, the ferroelectric film 86 is etched by a sputtering reaction in an atmosphere containing chlorine and argon. The second conductive film 87 and the first conductive film 85 are etched by a sputter reaction in a bromine (Br2) -introduced atmosphere.

  As described above, the lower electrode 85a of the capacitor Q made of the first conductive film 85, the dielectric film 86a of the capacitor Q made of the ferroelectric film 86, and the second conductive film 87 are formed on the antioxidant insulating film 80b. The upper electrode 87a of the capacitor Q is formed. In one transistor formation region, one lower electrode 85a is electrically connected to the second impurity diffusion region 75b via the second plug 81a, and another lower electrode 85a is connected via the third plug 81b. The third impurity diffusion region 75c is electrically connected. Thereafter, the hard mask 88 is removed.

  Subsequently, recovery annealing is performed to recover damage to the ferroelectric film 86 due to etching. In this case, the recovery annealing is performed, for example, in an oxygen atmosphere at a substrate temperature of 650 ° C. for 60 minutes.

Next, as shown in FIG. 24B, after a 50 nm-thickness alumina (Al ₂ O ₃ ) is formed on the base insulating film 80b as a first capacitor protective insulating film 89 covering the capacitor Q by sputtering, Capacitor Q is annealed in an atmosphere at 650 ° C. for 60 minutes. The first capacitor protection insulating film 89 protects the capacitor Q from process damage.

Next, the silicon substrate 1 is placed in the above-described plasma CVD apparatus (see FIG. 17), and film formation is performed under the following conditions.
・ TEOS gas flow rate: 460sccm
・ He (TEOS carrier gas) flow rate 480sccm
・ O ₂ flow rate: 700sccm
・ Pressure: 9.0 Torr
・ Frequency of the high frequency power supply 54. 13.56 MHz
・ Power of high frequency power supply 54 ... 400W
・ Deposition temperature: 390 ℃
As a result, as shown in FIG. 25A, silicon oxide (SiO ₂ ) having a thickness of 100 nm is formed on the first capacitor protective insulating film 89 as the second capacitor protective insulating film 95.

  If necessary, dehydration treatment and plasma treatment may be performed on the second capacitor protection insulating film 95. The conditions are the same as in the first embodiment, and are omitted.

Next, as shown in FIG. 25B, silicon oxide (SiO ₂ ) having a thickness of about 800 nm is formed as the second interlayer insulating film (second insulating film) 90 by the above-described HDPCVD method. 95. The second interlayer insulating film 90 is formed in the HDPCVD apparatus of FIG. 18 described in the first embodiment, and the film forming conditions are as follows.
・ SiH ₄ flow rate: 69sccm
・ O ₂ flow rate: 300sccm
・ Ar flow rate: 300sccm
・ Pressure: 6.2 Torr
・ Frequency of the first high-frequency power supply 64 ... 13.56 MHz
・ Power of first high frequency power supply 64... 3000 W
・ Frequency of the second high-frequency power source 62 ... 2 MHz
-Power of the second high frequency power supply 62 ... 1200W
・ Film formation temperature: 250 ℃
When the second interlayer insulating film 90 is formed by the HDPCVD method, the second capacitor protective insulating film 95 is formed under the second interlayer insulating film 90, so that the collision energy of hydrogen ions H ⁺ and sputtered ions generated during the film formation is formed. Is absorbed there. Therefore, the first capacitor protection insulating film 89 in the lower layer can block the ions, and the capacitor dielectric film 86a can be prevented from being deteriorated by the ions.

In addition, since the second capacitor protective insulating film 95 formed using TEOS has good coverage, the colliding hydrogen ions H ⁺ can be evenly absorbed by the upper and side portions of the capacitor.

Furthermore, since TEOS is less likely to generate reducing hydrogen than SiH ₄ , there is no risk of degrading capacitor Q due to hydrogen.

  If necessary, the second interlayer insulating film 90 may be subjected to plasma treatment. The conditions are the same as in the first embodiment, and are omitted.

Thereafter, silicon oxide (SiO ₂ ) having a thickness of about 700 nm is formed on the second interlayer insulating film 90 as the third insulating film 96. Since the film forming conditions are the same as those in the first embodiment, the description is omitted.

  Next, as shown in FIG. 26A, the second interlayer insulating film 90 and the third insulating film 96 are polished by the CMP method, and the surfaces thereof are planarized. The planarization is performed until the thickness of the second interlayer insulating film 90 on the upper electrode 87a reaches 300 nm.

  At this time, by forming the third insulating film 95, the polishing film thickness can be increased, and thereby the film thickness distribution after polishing can be made uniform.

  Next, using a resist mask (not shown), as shown in FIG. 26B, the second interlayer insulating film 90, the second capacitor protective insulating film 95, the first capacitor protective insulating film 89, the antioxidant insulating film A hole 90a is formed on the first plug 79 by etching the 80a and the base insulating film 80b.

  Next, a Ti film having a thickness of 30 nm and a TiN film having a thickness of 50 nm are sequentially formed as a glue film in the hole 90a and on the second interlayer insulating film 90 by a sputtering method. Further, a W film is grown on the glue film by the CVD method and the hole 90a is completely filled.

  Subsequently, the W film, the TiN film, and the Ti film are polished by a CMP method and removed from the upper surface of the second interlayer insulating film 90. Then, as shown in FIG. 27A, the tungsten film and the glue film remaining in the hole 90 a are used as the fourth plug 91. The fourth plug 91 is electrically connected to the first impurity diffusion region 75a through the first plug 79.

  Next, steps required until a structure shown in FIG.

  First, a SiON film is formed as a second antioxidant insulating film (not shown) on the fourth plug 91 and the second interlayer insulating film 90 by the CVD method. Further, the second anti-oxidation insulating film (not shown), the second interlayer insulating film 90, the second capacitor protective insulating film 95, and the first capacitor protective insulating film 89 are patterned by photolithography to form the upper electrode of the capacitor Q. A contact hole 90b reaching 87a is formed.

  Capacitor Q damaged by forming contact hole 90b is recovered by annealing. The annealing is performed, for example, in an oxygen atmosphere at a substrate temperature of 550 ° C. for 60 minutes.

  Thereafter, the antioxidant insulating film formed on the second interlayer insulating film 90 is removed by etch back, and the surface of the fourth plug 91 is exposed.

  Next, a multilayer metal film is formed in the contact hole 90 b on the upper electrode 87 a of the capacitor Q and on the second interlayer insulating film 90. Thereafter, by patterning the multilayer metal film, a first-layer metal wiring 91a electrically connected to the upper electrode 87a via the contact hole 90b and a conductive contact pad 91b connected to the fourth plug 91 are formed. .

  Further, a third interlayer insulating film 92 is formed on the second interlayer insulating film 90, the first layer metal wiring 91a, and the conductive contact pad 91b. Subsequently, the third interlayer insulating film 92 is patterned to form a hole 92a on the conductive contact pad 91b, and a fifth plug 93 made of a TiN film and a W film is formed in the hole 92a in order from the bottom.

  Thereafter, although not particularly shown, a second layer wiring including a bit line is formed on the third interlayer insulating film 92. The bit line is electrically connected to the first impurity diffusion region 75a through the fifth plug 93, the conductive contact pad 91b, the fourth plug 91, and the first plug 79. Subsequently, an insulating film or the like covering the second wiring layer is formed, but details thereof are omitted.

  In addition, the top view in this case is as FIG. 28, FIG.27 (b) above is equivalent to the II sectional view taken on the line of FIG. FIG. 29 is a sectional view taken along line II-II in FIG.

  As described above, also in this embodiment, since the second capacitor protective insulating film 95 is formed, the capacitor dielectric film 86a is damaged when the second interlayer insulating film 90 is formed by the HDPCVD method. Can be prevented.

  The features of the present invention are added below.

(Additional remark 1) The 1st insulating film formed above the semiconductor substrate,
A capacitor formed by sequentially forming a lower electrode, a dielectric film, and an upper electrode on the first insulating film;
A first capacitor protective insulating film covering the dielectric film and the upper electrode;
A second capacitor protective insulating film formed on the first capacitor protective insulating film;
A second insulating film formed on the second capacitor protective insulating film,
The semiconductor device according to claim 1, wherein a carbon content of the second capacitor protection insulating film is larger than a carbon content of the second insulating film.

  (Supplementary note 2) The semiconductor device according to supplementary note 1, wherein the second capacitor protection insulating film is a silicon oxide film.

  (Supplementary Note 3) The semiconductor device according to Supplementary Note 1 or 2, wherein the second insulating film is a silicon oxide film.

  (Additional remark 4) The said 1st capacitor protective insulating film consists of any one of an alumina, PLZT, PZT, a titanium oxide, an aluminum nitride, a silicon nitride, and a silicon nitride oxide. The semiconductor device described.

  (Supplementary note 5) The semiconductor device according to any one of supplementary notes 1 to 4, wherein the dielectric film is made of any one of a PZT material and a bismuth material.

(Appendix 6) A hole reaching the upper electrode is formed in the first capacitor protective insulating film, the second capacitor protective insulating film, and the second insulating film,
6. The semiconductor device according to any one of appendix 1 to appendix 5, wherein a wiring electrically connected to the upper electrode through the hole is formed on the second insulating film.

(Appendix 7) A step of forming a first insulating film above the semiconductor substrate;
Forming a first conductive film, a ferroelectric film, and a second conductive film in order on the first insulating film;
Patterning the second conductive film to form an upper electrode of a capacitor;
Patterning the ferroelectric film to form a capacitor dielectric film;
Patterning the first conductive film to form a lower electrode of a capacitor;
Forming a first capacitor protective insulating film covering the dielectric film and the upper electrode;
Forming a second capacitor protective insulating film covering the first capacitor protective insulating film by chemical vapor deposition without applying a bias voltage to the semiconductor substrate;
Forming a second insulating film on the second capacitor protective insulating film by a chemical vapor deposition method in a state where a bias voltage is applied to the semiconductor substrate. .

  (Supplementary note 8) The method of manufacturing a semiconductor device according to supplementary note 7, wherein the step of forming the first capacitor protection insulating film is performed in a state where a bias voltage is not applied to the semiconductor substrate.

  (Additional remark 9) The process of forming the said 2nd capacitor protective insulating film is performed in the pressure higher than the process of forming a said 2nd insulating film, The semiconductor device of Additional remark 7 or Additional remark 8 characterized by the above-mentioned Production method.

  (Supplementary note 10) The plasma density in the step of forming the second capacitor protective insulating film is lower than the plasma density in the step of forming the second insulating film, according to any one of supplementary notes 7 to 9, A method for manufacturing a semiconductor device.

  (Additional remark 11) The process of forming the said 2nd capacitor protective insulating film is performed by the chemical vapor deposition method using the reactive gas containing TEOS, The additional remark 7 thru | or Additional remark 10 characterized by the above-mentioned. A method for manufacturing a semiconductor device.

(Supplementary Note 12) forming said second insulating film is performed by _{SiH 4, Si 2 H 6,} Si 3 H 8 and a chemical vapor deposition method using a reaction gas containing any of SiCl ₄ 12. A method for manufacturing a semiconductor device according to any one of appendix 7 to appendix 11, wherein:

  (Additional remark 13) The process of forming the said 2nd insulating film adds the gas containing any of a fluorine, phosphorus, and boron to the said reaction gas, The manufacturing method of the semiconductor device of Additional remark 12 characterized by the above-mentioned.

  (Additional remark 14) The process of forming the said 2nd capacitor protective insulating film has the process of heating and dehydrating the said 2nd capacitor protective insulating film, The additional remark 7 thru | or the additional remark 13 characterized by the above-mentioned A method for manufacturing a semiconductor device.

  (Supplementary Note 15) The step of forming the second capacitor protective insulating film includes a step of improving the film quality by exposing the second capacitor protective insulating film to a plasma atmosphere containing N (nitrogen). The manufacturing method of the semiconductor device as described in any one of thru | or appendix 14.

  (Additional remark 16) The process of forming the said 2nd insulating film has the process of exposing a said 2nd insulating film to the plasma atmosphere containing N (nitrogen), and improving the film quality The manufacturing method of the semiconductor device as described in any one.

(Supplementary Note 17) The step of forming the first capacitor protective insulating film includes:
Forming a lower protective insulating film covering the dielectric film and the upper electrode on the first conductive film;
Patterning the lower protective insulating film to leave at least on the dielectric film and the upper electrode;
Forming an upper protective insulating film on the first insulating film and the lower protective insulating film, and applying the upper protective film and the lower protective film as the first capacitor protective insulating film. A method of manufacturing a semiconductor device according to any one of appendix 7 to appendix 16, wherein

  (Supplementary Note 18) A plurality of the capacitors are formed, and a total film thickness of the first capacitor protective insulating film and the second capacitor protective insulating film is not more than half of a minimum interval between the plurality of upper electrodes. 18. A method for manufacturing a semiconductor device according to any one of appendix 7 to appendix 17.

  (Additional remark 19) The film thickness of the said 2nd insulating film is thicker than the total film thickness of the said lower electrode, the said dielectric material film, and the said capacitor upper electrode, and from the film thickness which added 1 micrometer to the said total film thickness 19. The method for manufacturing a semiconductor device according to any one of appendix 7 to appendix 18, wherein the semiconductor device is thin.

(Supplementary Note 20) The step of forming the second insulating film includes:
Forming a third insulating film on the second insulating film;
20. The method for manufacturing a semiconductor device according to any one of appendixes 7 to 19, further comprising a step of polishing the second insulating film and the third insulating film to planarize a surface.

It is sectional drawing (the 1) which shows the manufacturing process of FeRAM which is the semiconductor device which concerns on the 1st Embodiment of this invention. FIG. 6 is a cross-sectional view (No. 2) showing the manufacturing process of the FeRAM which is the semiconductor device according to the first embodiment of the invention. It is sectional drawing (the 3) which shows the manufacturing process of FeRAM which is the semiconductor device which concerns on the 1st Embodiment of this invention. FIG. 6 is a sectional view (No. 4) showing a manufacturing step of the FeRAM which is the semiconductor device according to the first embodiment of the invention. It is sectional drawing (the 5) which shows the manufacturing process of FeRAM which is the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing (the 6) which shows the manufacturing process of FeRAM which is the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing (the 7) which shows the manufacturing process of FeRAM which is the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing (the 8) which shows the manufacturing process of FeRAM which is the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing (the 9) which shows the manufacturing process of FeRAM which is the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing (the 10) which shows the manufacturing process of FeRAM which is a semiconductor device which concerns on the 1st Embodiment of this invention. FIG. 2B is a plan view of the semiconductor device according to the first embodiment of the present invention shown in FIG. 3A is a plan view of the semiconductor device according to the first embodiment of the present invention shown in FIG. FIG. 4A is a plan view of the semiconductor device according to the first embodiment of the present invention shown in FIG. FIG. 7A is a plan view of the semiconductor device according to the first embodiment of the present invention shown in FIG. FIG. 10A is a plan view of the semiconductor device according to the first embodiment of the present invention shown in FIG. FIG. 11 is a plan view of the semiconductor device according to the first embodiment of the present invention shown in FIG. 10. It is a block diagram of the plasma CVD apparatus used for the manufacturing process of the semiconductor device which concerns on each embodiment of this invention. It is a block diagram of the HDPCVD apparatus used for the manufacturing process of the semiconductor device which concerns on each embodiment of this invention. It is sectional drawing for demonstrating the conditions which the film thickness of a 2nd capacitor insulating film should satisfy in the manufacturing process of the semiconductor device which concerns on each embodiment of this invention. In the manufacturing process of the semiconductor device according to the first embodiment of the present invention, the damage received by the capacitor Q between when the bias voltage is applied and the second insulating film is formed and when the bias voltage is not applied. It is a graph shown about the difference. 4 is a graph showing a difference in damage received by a capacitor Q when a second capacitor protection insulating film is formed and when it is not formed in the manufacturing process of the semiconductor device according to the first embodiment of the present invention. It is sectional drawing (the 1) which shows the manufacturing process of FeRAM which is a semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing (the 2) which shows the manufacturing process of FeRAM which is a semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing (the 3) which shows the manufacturing process of FeRAM which is a semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing (the 4) which shows the manufacturing process of FeRAM which is a semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing (the 5) which shows the manufacturing process of FeRAM which is a semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing (the 6) which shows the manufacturing process of FeRAM which is a semiconductor device which concerns on the 2nd Embodiment of this invention. FIG. 27B is a plan view of the semiconductor device according to the second embodiment of the present invention shown in FIG. It is the II-II sectional view taken on the line of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,71 ... Silicon substrate (semiconductor substrate) 2, 72 ... Element isolation insulating film, 3a, 3b, 71a ... Well, 4a, 4b, 75a-75c ... Impurity diffusion region, 5, 73: Gate insulating film, 6a, 6b, 74a, 74b ... Gate electrode, 7, 77 ... Cover insulating film, 8a, 8b ... refractory metal silicide layer, 9 ... First layer Insulating film (first insulating film) 10, 76 ... sidewall insulating film, 11, 85 ... first conductive film, 11a, 85a ... lower electrode, 12, 86 ... ferroelectric film, 12a, 86a, capacitor dielectric film, 13, 87, second conductive film, 13a, 87a, upper electrode, 14, 89, first capacitor protective insulating film, 14a, lower layer protection Insulating film, 14b ... upper protective insulating film, 16, 95 ... second capacitor 17, 90..., Second interlayer insulating film (second insulating film), 17 a to 17 g, 78 a to 78 c, 90 b... Contact hole, 17 h to 17 j. 18, 96 ... third insulating film, 19 ... resist, 19a-19d ... hole forming window, 20 ... glue film, 21 ... tungsten film, 21a-21d, 79, 81a, 81b, 91, 93 ... plug, 22, 80a ... antioxidation insulating film, 23a, 23c-23g, 91a ... first layer metal wiring, 23b ... conductive contact pad, 50, 60 ... -Chamber, 51, 61 ... Substrate mounting table, 53, 63 ... Gas dispersion plate, 54, 64 ... High frequency power source, 62 ... Low frequency power source, 78 ... First interlayer insulating film, 90a, 92a ... Lumpur, 92 ... third interlayer insulating film, 94 ... first insulating film.

Claims (1)

A first insulating film formed above the semiconductor substrate;
A capacitor formed by sequentially forming a lower electrode, a dielectric film, and an upper electrode on the first insulating film;
A first capacitor protective insulating film covering the dielectric film and the upper electrode;
A second capacitor protective insulating film formed on the first capacitor protective insulating film;
A second insulating film formed on the second capacitor protective insulating film,
The semiconductor device according to claim 1, wherein a carbon content of the second capacitor protection insulating film is larger than a carbon content of the second insulating film.

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